drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c

   1 /* Copyright Altera Corporation (C) 2016. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License, version 2,
   5  * as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  14  *
  15  * Author: Tien Hock Loh <thloh@altera.com>
  16  */
  17
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_net.h>
  22 #include <linux/phy.h>
  23 #include <linux/regmap.h>
  24 #include <linux/reset.h>
  25 #include <linux/stmmac.h>
  26
  27 #include "stmmac.h"
  28 #include "stmmac_platform.h"
  29 #include "altr_tse_pcs.h"
  30
  31 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII        0
  32 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII           BIT(1)
  33 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII            BIT(2)
  34 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH                2
  35 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK                 GENMASK(1, 0)
  36
  37 #define TSE_PCS_CONTROL_AN_EN_MASK                      BIT(12)
  38 #define TSE_PCS_CONTROL_REG                             0x00
  39 #define TSE_PCS_CONTROL_RESTART_AN_MASK                 BIT(9)
  40 #define TSE_PCS_IF_MODE_REG                             0x28
  41 #define TSE_PCS_LINK_TIMER_0_REG                        0x24
  42 #define TSE_PCS_LINK_TIMER_1_REG                        0x26
  43 #define TSE_PCS_SIZE                                    0x40
  44 #define TSE_PCS_STATUS_AN_COMPLETED_MASK                BIT(5)
  45 #define TSE_PCS_STATUS_LINK_MASK                        0x0004
  46 #define TSE_PCS_STATUS_REG                              0x02
  47 #define TSE_PCS_SGMII_SPEED_1000                        BIT(3)
  48 #define TSE_PCS_SGMII_SPEED_100                         BIT(2)
  49 #define TSE_PCS_SGMII_SPEED_10                          0x0
  50 #define TSE_PCS_SW_RST_MASK                             0x8000
  51 #define TSE_PCS_PARTNER_ABILITY_REG                     0x0A
  52 #define TSE_PCS_PARTNER_DUPLEX_FULL                     0x1000
  53 #define TSE_PCS_PARTNER_DUPLEX_HALF                     0x0000
  54 #define TSE_PCS_PARTNER_DUPLEX_MASK                     0x1000
  55 #define TSE_PCS_PARTNER_SPEED_MASK                      GENMASK(11, 10)
  56 #define TSE_PCS_PARTNER_SPEED_1000                      BIT(11)
  57 #define TSE_PCS_PARTNER_SPEED_100                       BIT(10)
  58 #define TSE_PCS_PARTNER_SPEED_10                        0x0000
  59 #define TSE_PCS_PARTNER_SPEED_1000                      BIT(11)
  60 #define TSE_PCS_PARTNER_SPEED_100                       BIT(10)
  61 #define TSE_PCS_PARTNER_SPEED_10                        0x0000
  62 #define TSE_PCS_SGMII_SPEED_MASK                        GENMASK(3, 2)
  63 #define TSE_PCS_SGMII_LINK_TIMER_0                      0x0D40
  64 #define TSE_PCS_SGMII_LINK_TIMER_1                      0x0003
  65 #define TSE_PCS_SW_RESET_TIMEOUT                        100
  66 #define TSE_PCS_USE_SGMII_AN_MASK                       BIT(2)
  67 #define TSE_PCS_USE_SGMII_ENA                           BIT(1)
  68
  69 #define SGMII_ADAPTER_CTRL_REG                          0x00
  70 #define SGMII_ADAPTER_DISABLE                           0x0001
  71 #define SGMII_ADAPTER_ENABLE                            0x0000
  72
  73 #define AUTONEGO_LINK_TIMER                             20
  74
  75 static int tse_pcs_reset(void __iomem *base, struct tse_pcs *pcs)
  76 {
  77         int counter = 0;
  78         u16 val;
  79
  80         val = readw(base + TSE_PCS_CONTROL_REG);
  81         val |= TSE_PCS_SW_RST_MASK;
  82         writew(val, base + TSE_PCS_CONTROL_REG);
  83
  84         while (counter < TSE_PCS_SW_RESET_TIMEOUT) {
  85                 val = readw(base + TSE_PCS_CONTROL_REG);
  86                 val &= TSE_PCS_SW_RST_MASK;
  87                 if (val == 0)
  88                         break;
  89                 counter++;
  90                 udelay(1);
  91         }
  92         if (counter >= TSE_PCS_SW_RESET_TIMEOUT) {
  93                 dev_err(pcs->dev, "PCS could not get out of sw reset\n");
  94                 return -ETIMEDOUT;
  95         }
  96
  97         return 0;
  98 }
  99
 100 int tse_pcs_init(void __iomem *base, struct tse_pcs *pcs)
 101 {
 102         int ret = 0;
 103
 104         writew(TSE_PCS_USE_SGMII_ENA, base + TSE_PCS_IF_MODE_REG);
 105
 106         writew(TSE_PCS_SGMII_LINK_TIMER_0, base + TSE_PCS_LINK_TIMER_0_REG);
 107         writew(TSE_PCS_SGMII_LINK_TIMER_1, base + TSE_PCS_LINK_TIMER_1_REG);
 108
 109         ret = tse_pcs_reset(base, pcs);
 110         if (ret == 0)
 111                 writew(SGMII_ADAPTER_ENABLE,
 112                        pcs->sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
 113
 114         return ret;
 115 }
 116
 117 static void pcs_link_timer_callback(unsigned long data)
 118 {
 119         u16 val = 0;
 120         struct tse_pcs *pcs = (struct tse_pcs *)data;
 121         void __iomem *tse_pcs_base = pcs->tse_pcs_base;
 122         void __iomem *sgmii_adapter_base = pcs->sgmii_adapter_base;
 123
 124         val = readw(tse_pcs_base + TSE_PCS_STATUS_REG);
 125         val &= TSE_PCS_STATUS_LINK_MASK;
 126
 127         if (val != 0) {
 128                 dev_dbg(pcs->dev, "Adapter: Link is established\n");
 129                 writew(SGMII_ADAPTER_ENABLE,
 130                        sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
 131         } else {
 132                 mod_timer(&pcs->aneg_link_timer, jiffies +
 133                           msecs_to_jiffies(AUTONEGO_LINK_TIMER));
 134         }
 135 }
 136
 137 static void auto_nego_timer_callback(unsigned long data)
 138 {
 139         u16 val = 0;
 140         u16 speed = 0;
 141         u16 duplex = 0;
 142         struct tse_pcs *pcs = (struct tse_pcs *)data;
 143         void __iomem *tse_pcs_base = pcs->tse_pcs_base;
 144         void __iomem *sgmii_adapter_base = pcs->sgmii_adapter_base;
 145
 146         val = readw(tse_pcs_base + TSE_PCS_STATUS_REG);
 147         val &= TSE_PCS_STATUS_AN_COMPLETED_MASK;
 148
 149         if (val != 0) {
 150                 dev_dbg(pcs->dev, "Adapter: Auto Negotiation is completed\n");
 151                 val = readw(tse_pcs_base + TSE_PCS_PARTNER_ABILITY_REG);
 152                 speed = val & TSE_PCS_PARTNER_SPEED_MASK;
 153                 duplex = val & TSE_PCS_PARTNER_DUPLEX_MASK;
 154
 155                 if (speed == TSE_PCS_PARTNER_SPEED_10 &&
 156                     duplex == TSE_PCS_PARTNER_DUPLEX_FULL)
 157                         dev_dbg(pcs->dev,
 158                                 "Adapter: Link Partner is Up - 10/Full\n");
 159                 else if (speed == TSE_PCS_PARTNER_SPEED_100 &&
 160                          duplex == TSE_PCS_PARTNER_DUPLEX_FULL)
 161                         dev_dbg(pcs->dev,
 162                                 "Adapter: Link Partner is Up - 100/Full\n");
 163                 else if (speed == TSE_PCS_PARTNER_SPEED_1000 &&
 164                          duplex == TSE_PCS_PARTNER_DUPLEX_FULL)
 165                         dev_dbg(pcs->dev,
 166                                 "Adapter: Link Partner is Up - 1000/Full\n");
 167                 else if (speed == TSE_PCS_PARTNER_SPEED_10 &&
 168                          duplex == TSE_PCS_PARTNER_DUPLEX_HALF)
 169                         dev_err(pcs->dev,
 170                                 "Adapter does not support Half Duplex\n");
 171                 else if (speed == TSE_PCS_PARTNER_SPEED_100 &&
 172                          duplex == TSE_PCS_PARTNER_DUPLEX_HALF)
 173                         dev_err(pcs->dev,
 174                                 "Adapter does not support Half Duplex\n");
 175                 else if (speed == TSE_PCS_PARTNER_SPEED_1000 &&
 176                          duplex == TSE_PCS_PARTNER_DUPLEX_HALF)
 177                         dev_err(pcs->dev,
 178                                 "Adapter does not support Half Duplex\n");
 179                 else
 180                         dev_err(pcs->dev,
 181                                 "Adapter: Invalid Partner Speed and Duplex\n");
 182
 183                 if (duplex == TSE_PCS_PARTNER_DUPLEX_FULL &&
 184                     (speed == TSE_PCS_PARTNER_SPEED_10 ||
 185                      speed == TSE_PCS_PARTNER_SPEED_100 ||
 186                      speed == TSE_PCS_PARTNER_SPEED_1000))
 187                         writew(SGMII_ADAPTER_ENABLE,
 188                                sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
 189         } else {
 190                 val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);
 191                 val |= TSE_PCS_CONTROL_RESTART_AN_MASK;
 192                 writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG);
 193
 194                 tse_pcs_reset(tse_pcs_base, pcs);
 195                 mod_timer(&pcs->aneg_link_timer, jiffies +
 196                           msecs_to_jiffies(AUTONEGO_LINK_TIMER));
 197         }
 198 }
 199
 200 static void aneg_link_timer_callback(unsigned long data)
 201 {
 202         struct tse_pcs *pcs = (struct tse_pcs *)data;
 203
 204         if (pcs->autoneg == AUTONEG_ENABLE)
 205                 auto_nego_timer_callback(data);
 206         else if (pcs->autoneg == AUTONEG_DISABLE)
 207                 pcs_link_timer_callback(data);
 208 }
 209
 210 void tse_pcs_fix_mac_speed(struct tse_pcs *pcs, struct phy_device *phy_dev,
 211                            unsigned int speed)
 212 {
 213         void __iomem *tse_pcs_base = pcs->tse_pcs_base;
 214         void __iomem *sgmii_adapter_base = pcs->sgmii_adapter_base;
 215         u32 val;
 216
 217         writew(SGMII_ADAPTER_ENABLE,
 218                sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
 219
 220         pcs->autoneg = phy_dev->autoneg;
 221
 222         if (phy_dev->autoneg == AUTONEG_ENABLE) {
 223                 val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);
 224                 val |= TSE_PCS_CONTROL_AN_EN_MASK;
 225                 writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG);
 226
 227                 val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG);
 228                 val |= TSE_PCS_USE_SGMII_AN_MASK;
 229                 writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG);
 230
 231                 val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);
 232                 val |= TSE_PCS_CONTROL_RESTART_AN_MASK;
 233
 234                 tse_pcs_reset(tse_pcs_base, pcs);
 235
 236                 setup_timer(&pcs->aneg_link_timer,
 237                             aneg_link_timer_callback, (unsigned long)pcs);
 238                 mod_timer(&pcs->aneg_link_timer, jiffies +
 239                           msecs_to_jiffies(AUTONEGO_LINK_TIMER));
 240         } else if (phy_dev->autoneg == AUTONEG_DISABLE) {
 241                 val = readw(tse_pcs_base + TSE_PCS_CONTROL_REG);
 242                 val &= ~TSE_PCS_CONTROL_AN_EN_MASK;
 243                 writew(val, tse_pcs_base + TSE_PCS_CONTROL_REG);
 244
 245                 val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG);
 246                 val &= ~TSE_PCS_USE_SGMII_AN_MASK;
 247                 writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG);
 248
 249                 val = readw(tse_pcs_base + TSE_PCS_IF_MODE_REG);
 250                 val &= ~TSE_PCS_SGMII_SPEED_MASK;
 251
 252                 switch (speed) {
 253                 case 1000:
 254                         val |= TSE_PCS_SGMII_SPEED_1000;
 255                         break;
 256                 case 100:
 257                         val |= TSE_PCS_SGMII_SPEED_100;
 258                         break;
 259                 case 10:
 260                         val |= TSE_PCS_SGMII_SPEED_10;
 261                         break;
 262                 default:
 263                         return;
 264                 }
 265                 writew(val, tse_pcs_base + TSE_PCS_IF_MODE_REG);
 266
 267                 tse_pcs_reset(tse_pcs_base, pcs);
 268
 269                 setup_timer(&pcs->aneg_link_timer,
 270                             aneg_link_timer_callback, (unsigned long)pcs);
 271                 mod_timer(&pcs->aneg_link_timer, jiffies +
 272                           msecs_to_jiffies(AUTONEGO_LINK_TIMER));
 273         }
 274 }