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[deliverable/linux.git] / drivers / net / ethernet / stmicro / stmmac / common.h
1 /*******************************************************************************
2 STMMAC Common Header File
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
24
25 #ifndef __COMMON_H__
26 #define __COMMON_H__
27
28 #include <linux/etherdevice.h>
29 #include <linux/netdevice.h>
30 #include <linux/stmmac.h>
31 #include <linux/phy.h>
32 #include <linux/module.h>
33 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
34 #define STMMAC_VLAN_TAG_USED
35 #include <linux/if_vlan.h>
36 #endif
37
38 #include "descs.h"
39 #include "mmc.h"
40
41 /* Synopsys Core versions */
42 #define DWMAC_CORE_3_40 0x34
43 #define DWMAC_CORE_3_50 0x35
44 #define DWMAC_CORE_4_00 0x40
45 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */
46
47 #define DMA_TX_SIZE 512
48 #define DMA_RX_SIZE 512
49 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
50
51 #undef FRAME_FILTER_DEBUG
52 /* #define FRAME_FILTER_DEBUG */
53
54 /* Extra statistic and debug information exposed by ethtool */
55 struct stmmac_extra_stats {
56 /* Transmit errors */
57 unsigned long tx_underflow ____cacheline_aligned;
58 unsigned long tx_carrier;
59 unsigned long tx_losscarrier;
60 unsigned long vlan_tag;
61 unsigned long tx_deferred;
62 unsigned long tx_vlan;
63 unsigned long tx_jabber;
64 unsigned long tx_frame_flushed;
65 unsigned long tx_payload_error;
66 unsigned long tx_ip_header_error;
67 /* Receive errors */
68 unsigned long rx_desc;
69 unsigned long sa_filter_fail;
70 unsigned long overflow_error;
71 unsigned long ipc_csum_error;
72 unsigned long rx_collision;
73 unsigned long rx_crc;
74 unsigned long dribbling_bit;
75 unsigned long rx_length;
76 unsigned long rx_mii;
77 unsigned long rx_multicast;
78 unsigned long rx_gmac_overflow;
79 unsigned long rx_watchdog;
80 unsigned long da_rx_filter_fail;
81 unsigned long sa_rx_filter_fail;
82 unsigned long rx_missed_cntr;
83 unsigned long rx_overflow_cntr;
84 unsigned long rx_vlan;
85 /* Tx/Rx IRQ error info */
86 unsigned long tx_undeflow_irq;
87 unsigned long tx_process_stopped_irq;
88 unsigned long tx_jabber_irq;
89 unsigned long rx_overflow_irq;
90 unsigned long rx_buf_unav_irq;
91 unsigned long rx_process_stopped_irq;
92 unsigned long rx_watchdog_irq;
93 unsigned long tx_early_irq;
94 unsigned long fatal_bus_error_irq;
95 /* Tx/Rx IRQ Events */
96 unsigned long rx_early_irq;
97 unsigned long threshold;
98 unsigned long tx_pkt_n;
99 unsigned long rx_pkt_n;
100 unsigned long normal_irq_n;
101 unsigned long rx_normal_irq_n;
102 unsigned long napi_poll;
103 unsigned long tx_normal_irq_n;
104 unsigned long tx_clean;
105 unsigned long tx_set_ic_bit;
106 unsigned long irq_receive_pmt_irq_n;
107 /* MMC info */
108 unsigned long mmc_tx_irq_n;
109 unsigned long mmc_rx_irq_n;
110 unsigned long mmc_rx_csum_offload_irq_n;
111 /* EEE */
112 unsigned long irq_tx_path_in_lpi_mode_n;
113 unsigned long irq_tx_path_exit_lpi_mode_n;
114 unsigned long irq_rx_path_in_lpi_mode_n;
115 unsigned long irq_rx_path_exit_lpi_mode_n;
116 unsigned long phy_eee_wakeup_error_n;
117 /* Extended RDES status */
118 unsigned long ip_hdr_err;
119 unsigned long ip_payload_err;
120 unsigned long ip_csum_bypassed;
121 unsigned long ipv4_pkt_rcvd;
122 unsigned long ipv6_pkt_rcvd;
123 unsigned long rx_msg_type_ext_no_ptp;
124 unsigned long rx_msg_type_sync;
125 unsigned long rx_msg_type_follow_up;
126 unsigned long rx_msg_type_delay_req;
127 unsigned long rx_msg_type_delay_resp;
128 unsigned long rx_msg_type_pdelay_req;
129 unsigned long rx_msg_type_pdelay_resp;
130 unsigned long rx_msg_type_pdelay_follow_up;
131 unsigned long ptp_frame_type;
132 unsigned long ptp_ver;
133 unsigned long timestamp_dropped;
134 unsigned long av_pkt_rcvd;
135 unsigned long av_tagged_pkt_rcvd;
136 unsigned long vlan_tag_priority_val;
137 unsigned long l3_filter_match;
138 unsigned long l4_filter_match;
139 unsigned long l3_l4_filter_no_match;
140 /* PCS */
141 unsigned long irq_pcs_ane_n;
142 unsigned long irq_pcs_link_n;
143 unsigned long irq_rgmii_n;
144 unsigned long pcs_link;
145 unsigned long pcs_duplex;
146 unsigned long pcs_speed;
147 /* debug register */
148 unsigned long mtl_tx_status_fifo_full;
149 unsigned long mtl_tx_fifo_not_empty;
150 unsigned long mmtl_fifo_ctrl;
151 unsigned long mtl_tx_fifo_read_ctrl_write;
152 unsigned long mtl_tx_fifo_read_ctrl_wait;
153 unsigned long mtl_tx_fifo_read_ctrl_read;
154 unsigned long mtl_tx_fifo_read_ctrl_idle;
155 unsigned long mac_tx_in_pause;
156 unsigned long mac_tx_frame_ctrl_xfer;
157 unsigned long mac_tx_frame_ctrl_idle;
158 unsigned long mac_tx_frame_ctrl_wait;
159 unsigned long mac_tx_frame_ctrl_pause;
160 unsigned long mac_gmii_tx_proto_engine;
161 unsigned long mtl_rx_fifo_fill_level_full;
162 unsigned long mtl_rx_fifo_fill_above_thresh;
163 unsigned long mtl_rx_fifo_fill_below_thresh;
164 unsigned long mtl_rx_fifo_fill_level_empty;
165 unsigned long mtl_rx_fifo_read_ctrl_flush;
166 unsigned long mtl_rx_fifo_read_ctrl_read_data;
167 unsigned long mtl_rx_fifo_read_ctrl_status;
168 unsigned long mtl_rx_fifo_read_ctrl_idle;
169 unsigned long mtl_rx_fifo_ctrl_active;
170 unsigned long mac_rx_frame_ctrl_fifo;
171 unsigned long mac_gmii_rx_proto_engine;
172 /* TSO */
173 unsigned long tx_tso_frames;
174 unsigned long tx_tso_nfrags;
175 };
176
177 /* CSR Frequency Access Defines*/
178 #define CSR_F_35M 35000000
179 #define CSR_F_60M 60000000
180 #define CSR_F_100M 100000000
181 #define CSR_F_150M 150000000
182 #define CSR_F_250M 250000000
183 #define CSR_F_300M 300000000
184
185 #define MAC_CSR_H_FRQ_MASK 0x20
186
187 #define HASH_TABLE_SIZE 64
188 #define PAUSE_TIME 0xffff
189
190 /* Flow Control defines */
191 #define FLOW_OFF 0
192 #define FLOW_RX 1
193 #define FLOW_TX 2
194 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
195
196 /* PCS defines */
197 #define STMMAC_PCS_RGMII (1 << 0)
198 #define STMMAC_PCS_SGMII (1 << 1)
199 #define STMMAC_PCS_TBI (1 << 2)
200 #define STMMAC_PCS_RTBI (1 << 3)
201
202 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
203
204 /* DAM HW feature register fields */
205 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
206 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
207 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
208 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
209 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
210 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
211 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
212 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
213 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
214 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
215 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
216 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
217 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
218 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
219 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
220 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
221 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
222 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
223 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
224 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
225 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
226 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
227 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
228 /* Timestamping with Internal System Time */
229 #define DMA_HW_FEAT_INTTSEN 0x02000000
230 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
231 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
232 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
233 #define DEFAULT_DMA_PBL 8
234
235 /* PCS status and mask defines */
236 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
237 #define PCS_LINK_IRQ BIT(1) /* PCS Link */
238 #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
239
240 /* Max/Min RI Watchdog Timer count value */
241 #define MAX_DMA_RIWT 0xff
242 #define MIN_DMA_RIWT 0x20
243 /* Tx coalesce parameters */
244 #define STMMAC_COAL_TX_TIMER 40000
245 #define STMMAC_MAX_COAL_TX_TICK 100000
246 #define STMMAC_TX_MAX_FRAMES 256
247 #define STMMAC_TX_FRAMES 64
248
249 /* Rx IPC status */
250 enum rx_frame_status {
251 good_frame = 0x0,
252 discard_frame = 0x1,
253 csum_none = 0x2,
254 llc_snap = 0x4,
255 dma_own = 0x8,
256 rx_not_ls = 0x10,
257 };
258
259 /* Tx status */
260 enum tx_frame_status {
261 tx_done = 0x0,
262 tx_not_ls = 0x1,
263 tx_err = 0x2,
264 tx_dma_own = 0x4,
265 };
266
267 enum dma_irq_status {
268 tx_hard_error = 0x1,
269 tx_hard_error_bump_tc = 0x2,
270 handle_rx = 0x4,
271 handle_tx = 0x8,
272 };
273
274 /* EEE and LPI defines */
275 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
276 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
277 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
278 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
279
280 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
281
282 /* Physical Coding Sublayer */
283 struct rgmii_adv {
284 unsigned int pause;
285 unsigned int duplex;
286 unsigned int lp_pause;
287 unsigned int lp_duplex;
288 };
289
290 #define STMMAC_PCS_PAUSE 1
291 #define STMMAC_PCS_ASYM_PAUSE 2
292
293 /* DMA HW capabilities */
294 struct dma_features {
295 unsigned int mbps_10_100;
296 unsigned int mbps_1000;
297 unsigned int half_duplex;
298 unsigned int hash_filter;
299 unsigned int multi_addr;
300 unsigned int pcs;
301 unsigned int sma_mdio;
302 unsigned int pmt_remote_wake_up;
303 unsigned int pmt_magic_frame;
304 unsigned int rmon;
305 /* IEEE 1588-2002 */
306 unsigned int time_stamp;
307 /* IEEE 1588-2008 */
308 unsigned int atime_stamp;
309 /* 802.3az - Energy-Efficient Ethernet (EEE) */
310 unsigned int eee;
311 unsigned int av;
312 unsigned int tsoen;
313 /* TX and RX csum */
314 unsigned int tx_coe;
315 unsigned int rx_coe;
316 unsigned int rx_coe_type1;
317 unsigned int rx_coe_type2;
318 unsigned int rxfifo_over_2048;
319 /* TX and RX number of channels */
320 unsigned int number_rx_channel;
321 unsigned int number_tx_channel;
322 /* Alternate (enhanced) DESC mode */
323 unsigned int enh_desc;
324 };
325
326 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
327 #define BUF_SIZE_16KiB 16384
328 #define BUF_SIZE_8KiB 8192
329 #define BUF_SIZE_4KiB 4096
330 #define BUF_SIZE_2KiB 2048
331
332 /* Power Down and WOL */
333 #define PMT_NOT_SUPPORTED 0
334 #define PMT_SUPPORTED 1
335
336 /* Common MAC defines */
337 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
338 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
339 #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
340
341 /* Default LPI timers */
342 #define STMMAC_DEFAULT_LIT_LS 0x3E8
343 #define STMMAC_DEFAULT_TWT_LS 0x1E
344
345 #define STMMAC_CHAIN_MODE 0x1
346 #define STMMAC_RING_MODE 0x2
347
348 #define JUMBO_LEN 9000
349
350 /* Descriptors helpers */
351 struct stmmac_desc_ops {
352 /* DMA RX descriptor ring initialization */
353 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
354 int end);
355 /* DMA TX descriptor ring initialization */
356 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
357
358 /* Invoked by the xmit function to prepare the tx descriptor */
359 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
360 bool csum_flag, int mode, bool tx_own,
361 bool ls);
362 void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
363 int len2, bool tx_own, bool ls,
364 unsigned int tcphdrlen,
365 unsigned int tcppayloadlen);
366 /* Set/get the owner of the descriptor */
367 void (*set_tx_owner) (struct dma_desc *p);
368 int (*get_tx_owner) (struct dma_desc *p);
369 /* Clean the tx descriptor as soon as the tx irq is received */
370 void (*release_tx_desc) (struct dma_desc *p, int mode);
371 /* Clear interrupt on tx frame completion. When this bit is
372 * set an interrupt happens as soon as the frame is transmitted */
373 void (*set_tx_ic)(struct dma_desc *p);
374 /* Last tx segment reports the transmit status */
375 int (*get_tx_ls) (struct dma_desc *p);
376 /* Return the transmit status looking at the TDES1 */
377 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
378 struct dma_desc *p, void __iomem *ioaddr);
379 /* Get the buffer size from the descriptor */
380 int (*get_tx_len) (struct dma_desc *p);
381 /* Handle extra events on specific interrupts hw dependent */
382 void (*set_rx_owner) (struct dma_desc *p);
383 /* Get the receive frame size */
384 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
385 /* Return the reception status looking at the RDES1 */
386 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
387 struct dma_desc *p);
388 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
389 struct dma_extended_desc *p);
390 /* Set tx timestamp enable bit */
391 void (*enable_tx_timestamp) (struct dma_desc *p);
392 /* get tx timestamp status */
393 int (*get_tx_timestamp_status) (struct dma_desc *p);
394 /* get timestamp value */
395 u64(*get_timestamp) (void *desc, u32 ats);
396 /* get rx timestamp status */
397 int (*get_rx_timestamp_status) (void *desc, u32 ats);
398 /* Display ring */
399 void (*display_ring)(void *head, unsigned int size, bool rx);
400 /* set MSS via context descriptor */
401 void (*set_mss)(struct dma_desc *p, unsigned int mss);
402 };
403
404 extern const struct stmmac_desc_ops enh_desc_ops;
405 extern const struct stmmac_desc_ops ndesc_ops;
406
407 /* Specific DMA helpers */
408 struct stmmac_dma_ops {
409 /* DMA core initialization */
410 int (*reset)(void __iomem *ioaddr);
411 void (*init)(void __iomem *ioaddr, int pbl, int fb, int mb,
412 int aal, u32 dma_tx, u32 dma_rx, int atds);
413 /* Configure the AXI Bus Mode Register */
414 void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
415 /* Dump DMA registers */
416 void (*dump_regs) (void __iomem *ioaddr);
417 /* Set tx/rx threshold in the csr6 register
418 * An invalid value enables the store-and-forward mode */
419 void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
420 int rxfifosz);
421 /* To track extra statistic (if supported) */
422 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
423 void __iomem *ioaddr);
424 void (*enable_dma_transmission) (void __iomem *ioaddr);
425 void (*enable_dma_irq) (void __iomem *ioaddr);
426 void (*disable_dma_irq) (void __iomem *ioaddr);
427 void (*start_tx) (void __iomem *ioaddr);
428 void (*stop_tx) (void __iomem *ioaddr);
429 void (*start_rx) (void __iomem *ioaddr);
430 void (*stop_rx) (void __iomem *ioaddr);
431 int (*dma_interrupt) (void __iomem *ioaddr,
432 struct stmmac_extra_stats *x);
433 /* If supported then get the optional core features */
434 void (*get_hw_feature)(void __iomem *ioaddr,
435 struct dma_features *dma_cap);
436 /* Program the HW RX Watchdog */
437 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
438 void (*set_tx_ring_len)(void __iomem *ioaddr, u32 len);
439 void (*set_rx_ring_len)(void __iomem *ioaddr, u32 len);
440 void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
441 void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
442 void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);
443 };
444
445 struct mac_device_info;
446
447 /* Helpers to program the MAC core */
448 struct stmmac_ops {
449 /* MAC core initialization */
450 void (*core_init)(struct mac_device_info *hw, int mtu);
451 /* Enable and verify that the IPC module is supported */
452 int (*rx_ipc)(struct mac_device_info *hw);
453 /* Dump MAC registers */
454 void (*dump_regs)(struct mac_device_info *hw);
455 /* Handle extra events on specific interrupts hw dependent */
456 int (*host_irq_status)(struct mac_device_info *hw,
457 struct stmmac_extra_stats *x);
458 /* Multicast filter setting */
459 void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
460 /* Flow control setting */
461 void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
462 unsigned int fc, unsigned int pause_time);
463 /* Set power management mode (e.g. magic frame) */
464 void (*pmt)(struct mac_device_info *hw, unsigned long mode);
465 /* Set/Get Unicast MAC addresses */
466 void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
467 unsigned int reg_n);
468 void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
469 unsigned int reg_n);
470 void (*set_eee_mode)(struct mac_device_info *hw);
471 void (*reset_eee_mode)(struct mac_device_info *hw);
472 void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
473 void (*set_eee_pls)(struct mac_device_info *hw, int link);
474 void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x);
475 /* PCS calls */
476 void (*pcs_ctrl_ane)(void __iomem *ioaddr, bool ane, bool srgmi_ral,
477 bool loopback);
478 void (*pcs_rane)(void __iomem *ioaddr, bool restart);
479 void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);
480 };
481
482 /* PTP and HW Timer helpers */
483 struct stmmac_hwtimestamp {
484 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
485 u32 (*config_sub_second_increment) (void __iomem *ioaddr, u32 clk_rate);
486 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
487 int (*config_addend) (void __iomem *ioaddr, u32 addend);
488 int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
489 int add_sub);
490 u64(*get_systime) (void __iomem *ioaddr);
491 };
492
493 extern const struct stmmac_hwtimestamp stmmac_ptp;
494 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
495
496 struct mac_link {
497 int port;
498 int duplex;
499 int speed;
500 };
501
502 struct mii_regs {
503 unsigned int addr; /* MII Address */
504 unsigned int data; /* MII Data */
505 };
506
507 /* Helpers to manage the descriptors for chain and ring modes */
508 struct stmmac_mode_ops {
509 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
510 unsigned int extend_desc);
511 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
512 int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);
513 int (*set_16kib_bfsize)(int mtu);
514 void (*init_desc3)(struct dma_desc *p);
515 void (*refill_desc3) (void *priv, struct dma_desc *p);
516 void (*clean_desc3) (void *priv, struct dma_desc *p);
517 };
518
519 struct mac_device_info {
520 const struct stmmac_ops *mac;
521 const struct stmmac_desc_ops *desc;
522 const struct stmmac_dma_ops *dma;
523 const struct stmmac_mode_ops *mode;
524 const struct stmmac_hwtimestamp *ptp;
525 struct mii_regs mii; /* MII register Addresses */
526 struct mac_link link;
527 void __iomem *pcsr; /* vpointer to device CSRs */
528 int multicast_filter_bins;
529 int unicast_filter_entries;
530 int mcast_bits_log2;
531 unsigned int rx_csum;
532 unsigned int pcs;
533 unsigned int pmt;
534 };
535
536 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
537 int perfect_uc_entries,
538 int *synopsys_id);
539 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id);
540 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
541 int perfect_uc_entries, int *synopsys_id);
542
543 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
544 unsigned int high, unsigned int low);
545 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
546 unsigned int high, unsigned int low);
547 void stmmac_set_mac(void __iomem *ioaddr, bool enable);
548
549 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
550 unsigned int high, unsigned int low);
551 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
552 unsigned int high, unsigned int low);
553 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
554
555 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
556
557 extern const struct stmmac_mode_ops ring_mode_ops;
558 extern const struct stmmac_mode_ops chain_mode_ops;
559 extern const struct stmmac_desc_ops dwmac4_desc_ops;
560
561 /**
562 * stmmac_get_synopsys_id - return the SYINID.
563 * @priv: driver private structure
564 * Description: this simple function is to decode and return the SYINID
565 * starting from the HW core register.
566 */
567 static inline u32 stmmac_get_synopsys_id(u32 hwid)
568 {
569 /* Check Synopsys Id (not available on old chips) */
570 if (likely(hwid)) {
571 u32 uid = ((hwid & 0x0000ff00) >> 8);
572 u32 synid = (hwid & 0x000000ff);
573
574 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
575 uid, synid);
576
577 return synid;
578 }
579 return 0;
580 }
581 #endif /* __COMMON_H__ */
Linux kernel - Deliverables
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