drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

   1 /* Copyright Altera Corporation (C) 2014. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License, version 2,
   5  * as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  14  *
  15  * Adopted from dwmac-sti.c
  16  */
  17
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/of_net.h>
  22 #include <linux/phy.h>
  23 #include <linux/regmap.h>
  24 #include <linux/reset.h>
  25 #include <linux/stmmac.h>
  26
  27 #include "stmmac.h"
  28 #include "stmmac_platform.h"
  29
  30 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
  31 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
  32 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
  33 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
  34 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
  35 #define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010
  36
  37 #define EMAC_SPLITTER_CTRL_REG                  0x0
  38 #define EMAC_SPLITTER_CTRL_SPEED_MASK           0x3
  39 #define EMAC_SPLITTER_CTRL_SPEED_10             0x2
  40 #define EMAC_SPLITTER_CTRL_SPEED_100            0x3
  41 #define EMAC_SPLITTER_CTRL_SPEED_1000           0x0
  42
  43 struct socfpga_dwmac {
  44         int     interface;
  45         u32     reg_offset;
  46         u32     reg_shift;
  47         struct  device *dev;
  48         struct regmap *sys_mgr_base_addr;
  49         struct reset_control *stmmac_rst;
  50         void __iomem *splitter_base;
  51         bool f2h_ptp_ref_clk;
  52 };
  53
  54 static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
  55 {
  56         struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv;
  57         void __iomem *splitter_base = dwmac->splitter_base;
  58         u32 val;
  59
  60         if (!splitter_base)
  61                 return;
  62
  63         val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
  64         val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;
  65
  66         switch (speed) {
  67         case 1000:
  68                 val |= EMAC_SPLITTER_CTRL_SPEED_1000;
  69                 break;
  70         case 100:
  71                 val |= EMAC_SPLITTER_CTRL_SPEED_100;
  72                 break;
  73         case 10:
  74                 val |= EMAC_SPLITTER_CTRL_SPEED_10;
  75                 break;
  76         default:
  77                 return;
  78         }
  79
  80         writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
  81 }
  82
  83 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
  84 {
  85         struct device_node *np = dev->of_node;
  86         struct regmap *sys_mgr_base_addr;
  87         u32 reg_offset, reg_shift;
  88         int ret;
  89         struct device_node *np_splitter;
  90         struct resource res_splitter;
  91
  92         dwmac->stmmac_rst = devm_reset_control_get(dev,
  93                                                   STMMAC_RESOURCE_NAME);
  94         if (IS_ERR(dwmac->stmmac_rst)) {
  95                 dev_info(dev, "Could not get reset control!\n");
  96                 if (PTR_ERR(dwmac->stmmac_rst) == -EPROBE_DEFER)
  97                         return -EPROBE_DEFER;
  98                 dwmac->stmmac_rst = NULL;
  99         }
 100
 101         dwmac->interface = of_get_phy_mode(np);
 102
 103         sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
 104         if (IS_ERR(sys_mgr_base_addr)) {
 105                 dev_info(dev, "No sysmgr-syscon node found\n");
 106                 return PTR_ERR(sys_mgr_base_addr);
 107         }
 108
 109         ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
 110         if (ret) {
 111                 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
 112                 return -EINVAL;
 113         }
 114
 115         ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift);
 116         if (ret) {
 117                 dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
 118                 return -EINVAL;
 119         }
 120
 121         dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");
 122
 123         np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
 124         if (np_splitter) {
 125                 if (of_address_to_resource(np_splitter, 0, &res_splitter)) {
 126                         dev_info(dev, "Missing emac splitter address\n");
 127                         return -EINVAL;
 128                 }
 129
 130                 dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
 131                 if (IS_ERR(dwmac->splitter_base)) {
 132                         dev_info(dev, "Failed to mapping emac splitter\n");
 133                         return PTR_ERR(dwmac->splitter_base);
 134                 }
 135         }
 136
 137         dwmac->reg_offset = reg_offset;
 138         dwmac->reg_shift = reg_shift;
 139         dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
 140         dwmac->dev = dev;
 141
 142         return 0;
 143 }
 144
 145 static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac)
 146 {
 147         struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
 148         int phymode = dwmac->interface;
 149         u32 reg_offset = dwmac->reg_offset;
 150         u32 reg_shift = dwmac->reg_shift;
 151         u32 ctrl, val;
 152
 153         switch (phymode) {
 154         case PHY_INTERFACE_MODE_RGMII:
 155         case PHY_INTERFACE_MODE_RGMII_ID:
 156                 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
 157                 break;
 158         case PHY_INTERFACE_MODE_MII:
 159         case PHY_INTERFACE_MODE_GMII:
 160                 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
 161                 break;
 162         default:
 163                 dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
 164                 return -EINVAL;
 165         }
 166
 167         /* Overwrite val to GMII if splitter core is enabled. The phymode here
 168          * is the actual phy mode on phy hardware, but phy interface from
 169          * EMAC core is GMII.
 170          */
 171         if (dwmac->splitter_base)
 172                 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
 173
 174         regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
 175         ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
 176         ctrl |= val << reg_shift;
 177
 178         if (dwmac->f2h_ptp_ref_clk)
 179                 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
 180         else
 181                 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2));
 182
 183         regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
 184         return 0;
 185 }
 186
 187 static void socfpga_dwmac_exit(struct platform_device *pdev, void *priv)
 188 {
 189         struct socfpga_dwmac    *dwmac = priv;
 190
 191         /* On socfpga platform exit, assert and hold reset to the
 192          * enet controller - the default state after a hard reset.
 193          */
 194         if (dwmac->stmmac_rst)
 195                 reset_control_assert(dwmac->stmmac_rst);
 196 }
 197
 198 static int socfpga_dwmac_init(struct platform_device *pdev, void *priv)
 199 {
 200         struct socfpga_dwmac    *dwmac = priv;
 201         struct net_device *ndev = platform_get_drvdata(pdev);
 202         struct stmmac_priv *stpriv = NULL;
 203         int ret = 0;
 204
 205         if (ndev)
 206                 stpriv = netdev_priv(ndev);
 207
 208         /* Assert reset to the enet controller before changing the phy mode */
 209         if (dwmac->stmmac_rst)
 210                 reset_control_assert(dwmac->stmmac_rst);
 211
 212         /* Setup the phy mode in the system manager registers according to
 213          * devicetree configuration
 214          */
 215         ret = socfpga_dwmac_setup(dwmac);
 216
 217         /* Deassert reset for the phy configuration to be sampled by
 218          * the enet controller, and operation to start in requested mode
 219          */
 220         if (dwmac->stmmac_rst)
 221                 reset_control_deassert(dwmac->stmmac_rst);
 222
 223         /* Before the enet controller is suspended, the phy is suspended.
 224          * This causes the phy clock to be gated. The enet controller is
 225          * resumed before the phy, so the clock is still gated "off" when
 226          * the enet controller is resumed. This code makes sure the phy
 227          * is "resumed" before reinitializing the enet controller since
 228          * the enet controller depends on an active phy clock to complete
 229          * a DMA reset. A DMA reset will "time out" if executed
 230          * with no phy clock input on the Synopsys enet controller.
 231          * Verified through Synopsys Case #8000711656.
 232          *
 233          * Note that the phy clock is also gated when the phy is isolated.
 234          * Phy "suspend" and "isolate" controls are located in phy basic
 235          * control register 0, and can be modified by the phy driver
 236          * framework.
 237          */
 238         if (stpriv && stpriv->phydev)
 239                 phy_resume(stpriv->phydev);
 240
 241         return ret;
 242 }
 243
 244 static int socfpga_dwmac_probe(struct platform_device *pdev)
 245 {
 246         struct plat_stmmacenet_data *plat_dat;
 247         struct stmmac_resources stmmac_res;
 248         struct device           *dev = &pdev->dev;
 249         int                     ret;
 250         struct socfpga_dwmac    *dwmac;
 251
 252         ret = stmmac_get_platform_resources(pdev, &stmmac_res);
 253         if (ret)
 254                 return ret;
 255
 256         plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
 257         if (IS_ERR(plat_dat))
 258                 return PTR_ERR(plat_dat);
 259
 260         dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
 261         if (!dwmac)
 262                 return -ENOMEM;
 263
 264         ret = socfpga_dwmac_parse_data(dwmac, dev);
 265         if (ret) {
 266                 dev_err(dev, "Unable to parse OF data\n");
 267                 return ret;
 268         }
 269
 270         ret = socfpga_dwmac_setup(dwmac);
 271         if (ret) {
 272                 dev_err(dev, "couldn't setup SoC glue (%d)\n", ret);
 273                 return ret;
 274         }
 275
 276         plat_dat->bsp_priv = dwmac;
 277         plat_dat->init = socfpga_dwmac_init;
 278         plat_dat->exit = socfpga_dwmac_exit;
 279         plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
 280
 281         ret = socfpga_dwmac_init(pdev, plat_dat->bsp_priv);
 282         if (ret)
 283                 return ret;
 284
 285         return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
 286 }
 287
 288 static const struct of_device_id socfpga_dwmac_match[] = {
 289         { .compatible = "altr,socfpga-stmmac" },
 290         { }
 291 };
 292 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
 293
 294 static struct platform_driver socfpga_dwmac_driver = {
 295         .probe  = socfpga_dwmac_probe,
 296         .remove = stmmac_pltfr_remove,
 297         .driver = {
 298                 .name           = "socfpga-dwmac",
 299                 .pm             = &stmmac_pltfr_pm_ops,
 300                 .of_match_table = socfpga_dwmac_match,
 301         },
 302 };
 303 module_platform_driver(socfpga_dwmac_driver);
 304
 305 MODULE_LICENSE("GPL v2");