drivers/net/ethernet/stmicro/stmmac/dwmac1000.h

   1 /*******************************************************************************
   2   Copyright (C) 2007-2009  STMicroelectronics Ltd
   3
   4   This program is free software; you can redistribute it and/or modify it
   5   under the terms and conditions of the GNU General Public License,
   6   version 2, as published by the Free Software Foundation.
   7
   8   This program is distributed in the hope it will be useful, but WITHOUT
   9   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11   more details.
  12
  13   You should have received a copy of the GNU General Public License along with
  14   this program; if not, write to the Free Software Foundation, Inc.,
  15   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16
  17   The full GNU General Public License is included in this distribution in
  18   the file called "COPYING".
  19
  20   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  21 *******************************************************************************/
  22
  23 #include <linux/phy.h>
  24 #include "common.h"
  25
  26 #define GMAC_CONTROL            0x00000000      /* Configuration */
  27 #define GMAC_FRAME_FILTER       0x00000004      /* Frame Filter */
  28 #define GMAC_HASH_HIGH          0x00000008      /* Multicast Hash Table High */
  29 #define GMAC_HASH_LOW           0x0000000c      /* Multicast Hash Table Low */
  30 #define GMAC_MII_ADDR           0x00000010      /* MII Address */
  31 #define GMAC_MII_DATA           0x00000014      /* MII Data */
  32 #define GMAC_FLOW_CTRL          0x00000018      /* Flow Control */
  33 #define GMAC_VLAN_TAG           0x0000001c      /* VLAN Tag */
  34 #define GMAC_VERSION            0x00000020      /* GMAC CORE Version */
  35 #define GMAC_WAKEUP_FILTER      0x00000028      /* Wake-up Frame Filter */
  36
  37 #define GMAC_INT_STATUS         0x00000038      /* interrupt status register */
  38 enum dwmac1000_irq_status {
  39         lpiis_irq = 0x400,
  40         time_stamp_irq = 0x0200,
  41         mmc_rx_csum_offload_irq = 0x0080,
  42         mmc_tx_irq = 0x0040,
  43         mmc_rx_irq = 0x0020,
  44         mmc_irq = 0x0010,
  45         pmt_irq = 0x0008,
  46         pcs_ane_irq = 0x0004,
  47         pcs_link_irq = 0x0002,
  48         rgmii_irq = 0x0001,
  49 };
  50 #define GMAC_INT_MASK           0x0000003c      /* interrupt mask register */
  51
  52 /* PMT Control and Status */
  53 #define GMAC_PMT                0x0000002c
  54 enum power_event {
  55         pointer_reset = 0x80000000,
  56         global_unicast = 0x00000200,
  57         wake_up_rx_frame = 0x00000040,
  58         magic_frame = 0x00000020,
  59         wake_up_frame_en = 0x00000004,
  60         magic_pkt_en = 0x00000002,
  61         power_down = 0x00000001,
  62 };
  63
  64 /* Energy Efficient Ethernet (EEE)
  65  *
  66  * LPI status, timer and control register offset
  67  */
  68 #define LPI_CTRL_STATUS 0x0030
  69 #define LPI_TIMER_CTRL  0x0034
  70
  71 /* LPI control and status defines */
  72 #define LPI_CTRL_STATUS_LPITXA  0x00080000      /* Enable LPI TX Automate */
  73 #define LPI_CTRL_STATUS_PLSEN   0x00040000      /* Enable PHY Link Status */
  74 #define LPI_CTRL_STATUS_PLS     0x00020000      /* PHY Link Status */
  75 #define LPI_CTRL_STATUS_LPIEN   0x00010000      /* LPI Enable */
  76 #define LPI_CTRL_STATUS_RLPIST  0x00000200      /* Receive LPI state */
  77 #define LPI_CTRL_STATUS_TLPIST  0x00000100      /* Transmit LPI state */
  78 #define LPI_CTRL_STATUS_RLPIEX  0x00000008      /* Receive LPI Exit */
  79 #define LPI_CTRL_STATUS_RLPIEN  0x00000004      /* Receive LPI Entry */
  80 #define LPI_CTRL_STATUS_TLPIEX  0x00000002      /* Transmit LPI Exit */
  81 #define LPI_CTRL_STATUS_TLPIEN  0x00000001      /* Transmit LPI Entry */
  82
  83 /* GMAC HW ADDR regs */
  84 #define GMAC_ADDR_HIGH(reg)     (((reg > 15) ? 0x00000800 : 0x00000040) + \
  85                                 (reg * 8))
  86 #define GMAC_ADDR_LOW(reg)      (((reg > 15) ? 0x00000804 : 0x00000044) + \
  87                                 (reg * 8))
  88 #define GMAC_MAX_PERFECT_ADDRESSES      32
  89
  90 #define GMAC_AN_CTRL    0x000000c0      /* AN control */
  91 #define GMAC_AN_STATUS  0x000000c4      /* AN status */
  92 #define GMAC_ANE_ADV    0x000000c8      /* Auto-Neg. Advertisement */
  93 #define GMAC_ANE_LINK   0x000000cc      /* Auto-Neg. link partener ability */
  94 #define GMAC_ANE_EXP    0x000000d0      /* ANE expansion */
  95 #define GMAC_TBI        0x000000d4      /* TBI extend status */
  96 #define GMAC_GMII_STATUS 0x000000d8     /* S/R-GMII status */
  97
  98 /* GMAC Configuration defines */
  99 #define GMAC_CONTROL_TC 0x01000000      /* Transmit Conf. in RGMII/SGMII */
 100 #define GMAC_CONTROL_WD 0x00800000      /* Disable Watchdog on receive */
 101 #define GMAC_CONTROL_JD 0x00400000      /* Jabber disable */
 102 #define GMAC_CONTROL_BE 0x00200000      /* Frame Burst Enable */
 103 #define GMAC_CONTROL_JE 0x00100000      /* Jumbo frame */
 104 enum inter_frame_gap {
 105         GMAC_CONTROL_IFG_88 = 0x00040000,
 106         GMAC_CONTROL_IFG_80 = 0x00020000,
 107         GMAC_CONTROL_IFG_40 = 0x000e0000,
 108 };
 109 #define GMAC_CONTROL_DCRS       0x00010000 /* Disable carrier sense during tx */
 110 #define GMAC_CONTROL_PS         0x00008000 /* Port Select 0:GMI 1:MII */
 111 #define GMAC_CONTROL_FES        0x00004000 /* Speed 0:10 1:100 */
 112 #define GMAC_CONTROL_DO         0x00002000 /* Disable Rx Own */
 113 #define GMAC_CONTROL_LM         0x00001000 /* Loop-back mode */
 114 #define GMAC_CONTROL_DM         0x00000800 /* Duplex Mode */
 115 #define GMAC_CONTROL_IPC        0x00000400 /* Checksum Offload */
 116 #define GMAC_CONTROL_DR         0x00000200 /* Disable Retry */
 117 #define GMAC_CONTROL_LUD        0x00000100 /* Link up/down */
 118 #define GMAC_CONTROL_ACS        0x00000080 /* Automatic Pad/FCS Stripping */
 119 #define GMAC_CONTROL_DC         0x00000010 /* Deferral Check */
 120 #define GMAC_CONTROL_TE         0x00000008 /* Transmitter Enable */
 121 #define GMAC_CONTROL_RE         0x00000004 /* Receiver Enable */
 122
 123 #define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \
 124                         GMAC_CONTROL_JE | GMAC_CONTROL_BE)
 125
 126 /* GMAC Frame Filter defines */
 127 #define GMAC_FRAME_FILTER_PR    0x00000001      /* Promiscuous Mode */
 128 #define GMAC_FRAME_FILTER_HUC   0x00000002      /* Hash Unicast */
 129 #define GMAC_FRAME_FILTER_HMC   0x00000004      /* Hash Multicast */
 130 #define GMAC_FRAME_FILTER_DAIF  0x00000008      /* DA Inverse Filtering */
 131 #define GMAC_FRAME_FILTER_PM    0x00000010      /* Pass all multicast */
 132 #define GMAC_FRAME_FILTER_DBF   0x00000020      /* Disable Broadcast frames */
 133 #define GMAC_FRAME_FILTER_SAIF  0x00000100      /* Inverse Filtering */
 134 #define GMAC_FRAME_FILTER_SAF   0x00000200      /* Source Address Filter */
 135 #define GMAC_FRAME_FILTER_HPF   0x00000400      /* Hash or perfect Filter */
 136 #define GMAC_FRAME_FILTER_RA    0x80000000      /* Receive all mode */
 137 /* GMII ADDR  defines */
 138 #define GMAC_MII_ADDR_WRITE     0x00000002      /* MII Write */
 139 #define GMAC_MII_ADDR_BUSY      0x00000001      /* MII Busy */
 140 /* GMAC FLOW CTRL defines */
 141 #define GMAC_FLOW_CTRL_PT_MASK  0xffff0000      /* Pause Time Mask */
 142 #define GMAC_FLOW_CTRL_PT_SHIFT 16
 143 #define GMAC_FLOW_CTRL_RFE      0x00000004      /* Rx Flow Control Enable */
 144 #define GMAC_FLOW_CTRL_TFE      0x00000002      /* Tx Flow Control Enable */
 145 #define GMAC_FLOW_CTRL_FCB_BPA  0x00000001      /* Flow Control Busy ... */
 146
 147 /*--- DMA BLOCK defines ---*/
 148 /* DMA Bus Mode register defines */
 149 #define DMA_BUS_MODE_SFT_RESET  0x00000001      /* Software Reset */
 150 #define DMA_BUS_MODE_DA         0x00000002      /* Arbitration scheme */
 151 #define DMA_BUS_MODE_DSL_MASK   0x0000007c      /* Descriptor Skip Length */
 152 #define DMA_BUS_MODE_DSL_SHIFT  2       /*   (in DWORDS)      */
 153 /* Programmable burst length (passed thorugh platform)*/
 154 #define DMA_BUS_MODE_PBL_MASK   0x00003f00      /* Programmable Burst Len */
 155 #define DMA_BUS_MODE_PBL_SHIFT  8
 156
 157 enum rx_tx_priority_ratio {
 158         double_ratio = 0x00004000,      /*2:1 */
 159         triple_ratio = 0x00008000,      /*3:1 */
 160         quadruple_ratio = 0x0000c000,   /*4:1 */
 161 };
 162
 163 #define DMA_BUS_MODE_FB         0x00010000      /* Fixed burst */
 164 #define DMA_BUS_MODE_MB         0x04000000      /* Mixed burst */
 165 #define DMA_BUS_MODE_RPBL_MASK  0x003e0000      /* Rx-Programmable Burst Len */
 166 #define DMA_BUS_MODE_RPBL_SHIFT 17
 167 #define DMA_BUS_MODE_USP        0x00800000
 168 #define DMA_BUS_MODE_PBL        0x01000000
 169 #define DMA_BUS_MODE_AAL        0x02000000
 170
 171 /* DMA CRS Control and Status Register Mapping */
 172 #define DMA_HOST_TX_DESC          0x00001048    /* Current Host Tx descriptor */
 173 #define DMA_HOST_RX_DESC          0x0000104c    /* Current Host Rx descriptor */
 174 /*  DMA Bus Mode register defines */
 175 #define DMA_BUS_PR_RATIO_MASK     0x0000c000    /* Rx/Tx priority ratio */
 176 #define DMA_BUS_PR_RATIO_SHIFT    14
 177 #define DMA_BUS_FB                0x00010000    /* Fixed Burst */
 178
 179 /* DMA operation mode defines (start/stop tx/rx are placed in common header)*/
 180 #define DMA_CONTROL_DT          0x04000000 /* Disable Drop TCP/IP csum error */
 181 #define DMA_CONTROL_RSF         0x02000000 /* Receive Store and Forward */
 182 #define DMA_CONTROL_DFF         0x01000000 /* Disaable flushing */
 183 /* Threshold for Activating the FC */
 184 enum rfa {
 185         act_full_minus_1 = 0x00800000,
 186         act_full_minus_2 = 0x00800200,
 187         act_full_minus_3 = 0x00800400,
 188         act_full_minus_4 = 0x00800600,
 189 };
 190 /* Threshold for Deactivating the FC */
 191 enum rfd {
 192         deac_full_minus_1 = 0x00400000,
 193         deac_full_minus_2 = 0x00400800,
 194         deac_full_minus_3 = 0x00401000,
 195         deac_full_minus_4 = 0x00401800,
 196 };
 197 #define DMA_CONTROL_TSF         0x00200000 /* Transmit  Store and Forward */
 198
 199 enum ttc_control {
 200         DMA_CONTROL_TTC_64 = 0x00000000,
 201         DMA_CONTROL_TTC_128 = 0x00004000,
 202         DMA_CONTROL_TTC_192 = 0x00008000,
 203         DMA_CONTROL_TTC_256 = 0x0000c000,
 204         DMA_CONTROL_TTC_40 = 0x00010000,
 205         DMA_CONTROL_TTC_32 = 0x00014000,
 206         DMA_CONTROL_TTC_24 = 0x00018000,
 207         DMA_CONTROL_TTC_16 = 0x0001c000,
 208 };
 209 #define DMA_CONTROL_TC_TX_MASK  0xfffe3fff
 210
 211 #define DMA_CONTROL_EFC         0x00000100
 212 #define DMA_CONTROL_FEF         0x00000080
 213 #define DMA_CONTROL_FUF         0x00000040
 214
 215 enum rtc_control {
 216         DMA_CONTROL_RTC_64 = 0x00000000,
 217         DMA_CONTROL_RTC_32 = 0x00000008,
 218         DMA_CONTROL_RTC_96 = 0x00000010,
 219         DMA_CONTROL_RTC_128 = 0x00000018,
 220 };
 221 #define DMA_CONTROL_TC_RX_MASK  0xffffffe7
 222
 223 #define DMA_CONTROL_OSF 0x00000004      /* Operate on second frame */
 224
 225 /* MMC registers offset */
 226 #define GMAC_MMC_CTRL      0x100
 227 #define GMAC_MMC_RX_INTR   0x104
 228 #define GMAC_MMC_TX_INTR   0x108
 229 #define GMAC_MMC_RX_CSUM_OFFLOAD   0x208
 230
 231 /* Synopsys Core versions */
 232 #define DWMAC_CORE_3_40 34
 233
 234 extern const struct stmmac_dma_ops dwmac1000_dma_ops;