1 /*******************************************************************************
2 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
3 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
6 This only implements the mac core functions for this chip.
8 Copyright (C) 2007-2009 STMicroelectronics Ltd
10 This program is free software; you can redistribute it and/or modify it
11 under the terms and conditions of the GNU General Public License,
12 version 2, as published by the Free Software Foundation.
14 This program is distributed in the hope it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 You should have received a copy of the GNU General Public License along with
20 this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
23 The full GNU General Public License is included in this distribution in
24 the file called "COPYING".
26 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
27 *******************************************************************************/
29 #include <linux/crc32.h>
30 #include <linux/slab.h>
31 #include <linux/ethtool.h>
33 #include "stmmac_pcs.h"
34 #include "dwmac1000.h"
36 static void dwmac1000_core_init(struct mac_device_info
*hw
, int mtu
)
38 void __iomem
*ioaddr
= hw
->pcsr
;
39 u32 value
= readl(ioaddr
+ GMAC_CONTROL
);
41 /* Configure GMAC core */
42 value
|= GMAC_CORE_INIT
;
45 value
|= GMAC_CONTROL_2K
;
47 value
|= GMAC_CONTROL_JE
;
50 value
|= GMAC_CONTROL_TE
;
52 if (hw
->ps
== SPEED_1000
) {
53 value
&= ~GMAC_CONTROL_PS
;
55 value
|= GMAC_CONTROL_PS
;
57 if (hw
->ps
== SPEED_10
)
58 value
&= ~GMAC_CONTROL_FES
;
60 value
|= GMAC_CONTROL_FES
;
64 writel(value
, ioaddr
+ GMAC_CONTROL
);
66 /* Mask GMAC interrupts */
67 value
= GMAC_INT_DEFAULT_MASK
;
70 value
&= ~GMAC_INT_DISABLE_PMT
;
72 value
&= ~GMAC_INT_DISABLE_PCS
;
74 writel(value
, ioaddr
+ GMAC_INT_MASK
);
76 #ifdef STMMAC_VLAN_TAG_USED
77 /* Tag detection without filtering */
78 writel(0x0, ioaddr
+ GMAC_VLAN_TAG
);
82 static int dwmac1000_rx_ipc_enable(struct mac_device_info
*hw
)
84 void __iomem
*ioaddr
= hw
->pcsr
;
85 u32 value
= readl(ioaddr
+ GMAC_CONTROL
);
88 value
|= GMAC_CONTROL_IPC
;
90 value
&= ~GMAC_CONTROL_IPC
;
92 writel(value
, ioaddr
+ GMAC_CONTROL
);
94 value
= readl(ioaddr
+ GMAC_CONTROL
);
96 return !!(value
& GMAC_CONTROL_IPC
);
99 static void dwmac1000_dump_regs(struct mac_device_info
*hw
)
101 void __iomem
*ioaddr
= hw
->pcsr
;
103 pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr
);
105 for (i
= 0; i
< 55; i
++) {
107 pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i
,
108 offset
, readl(ioaddr
+ offset
));
112 static void dwmac1000_set_umac_addr(struct mac_device_info
*hw
,
116 void __iomem
*ioaddr
= hw
->pcsr
;
117 stmmac_set_mac_addr(ioaddr
, addr
, GMAC_ADDR_HIGH(reg_n
),
118 GMAC_ADDR_LOW(reg_n
));
121 static void dwmac1000_get_umac_addr(struct mac_device_info
*hw
,
125 void __iomem
*ioaddr
= hw
->pcsr
;
126 stmmac_get_mac_addr(ioaddr
, addr
, GMAC_ADDR_HIGH(reg_n
),
127 GMAC_ADDR_LOW(reg_n
));
130 static void dwmac1000_set_mchash(void __iomem
*ioaddr
, u32
*mcfilterbits
,
133 int numhashregs
, regs
;
135 switch (mcbitslog2
) {
137 writel(mcfilterbits
[0], ioaddr
+ GMAC_HASH_LOW
);
138 writel(mcfilterbits
[1], ioaddr
+ GMAC_HASH_HIGH
);
148 pr_debug("STMMAC: err in setting mulitcast filter\n");
152 for (regs
= 0; regs
< numhashregs
; regs
++)
153 writel(mcfilterbits
[regs
],
154 ioaddr
+ GMAC_EXTHASH_BASE
+ regs
* 4);
157 static void dwmac1000_set_filter(struct mac_device_info
*hw
,
158 struct net_device
*dev
)
160 void __iomem
*ioaddr
= (void __iomem
*)dev
->base_addr
;
161 unsigned int value
= 0;
162 unsigned int perfect_addr_number
= hw
->unicast_filter_entries
;
164 int mcbitslog2
= hw
->mcast_bits_log2
;
166 pr_debug("%s: # mcasts %d, # unicast %d\n", __func__
,
167 netdev_mc_count(dev
), netdev_uc_count(dev
));
169 memset(mc_filter
, 0, sizeof(mc_filter
));
171 if (dev
->flags
& IFF_PROMISC
) {
172 value
= GMAC_FRAME_FILTER_PR
;
173 } else if (dev
->flags
& IFF_ALLMULTI
) {
174 value
= GMAC_FRAME_FILTER_PM
; /* pass all multi */
175 } else if (!netdev_mc_empty(dev
)) {
176 struct netdev_hw_addr
*ha
;
178 /* Hash filter for multicast */
179 value
= GMAC_FRAME_FILTER_HMC
;
181 netdev_for_each_mc_addr(ha
, dev
) {
182 /* The upper n bits of the calculated CRC are used to
183 * index the contents of the hash table. The number of
184 * bits used depends on the hardware configuration
185 * selected at core configuration time.
187 int bit_nr
= bitrev32(~crc32_le(~0, ha
->addr
,
190 /* The most significant bit determines the register to
191 * use (H/L) while the other 5 bits determine the bit
192 * within the register.
194 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
198 dwmac1000_set_mchash(ioaddr
, mc_filter
, mcbitslog2
);
200 /* Handle multiple unicast addresses (perfect filtering) */
201 if (netdev_uc_count(dev
) > perfect_addr_number
)
202 /* Switch to promiscuous mode if more than unicast
203 * addresses are requested than supported by hardware.
205 value
|= GMAC_FRAME_FILTER_PR
;
208 struct netdev_hw_addr
*ha
;
210 netdev_for_each_uc_addr(ha
, dev
) {
211 stmmac_set_mac_addr(ioaddr
, ha
->addr
,
218 #ifdef FRAME_FILTER_DEBUG
219 /* Enable Receive all mode (to debug filtering_fail errors) */
220 value
|= GMAC_FRAME_FILTER_RA
;
222 writel(value
, ioaddr
+ GMAC_FRAME_FILTER
);
226 static void dwmac1000_flow_ctrl(struct mac_device_info
*hw
, unsigned int duplex
,
227 unsigned int fc
, unsigned int pause_time
)
229 void __iomem
*ioaddr
= hw
->pcsr
;
230 /* Set flow such that DZPQ in Mac Register 6 is 0,
231 * and unicast pause detect is enabled.
233 unsigned int flow
= GMAC_FLOW_CTRL_UP
;
235 pr_debug("GMAC Flow-Control:\n");
237 pr_debug("\tReceive Flow-Control ON\n");
238 flow
|= GMAC_FLOW_CTRL_RFE
;
241 pr_debug("\tTransmit Flow-Control ON\n");
242 flow
|= GMAC_FLOW_CTRL_TFE
;
246 pr_debug("\tduplex mode: PAUSE %d\n", pause_time
);
247 flow
|= (pause_time
<< GMAC_FLOW_CTRL_PT_SHIFT
);
250 writel(flow
, ioaddr
+ GMAC_FLOW_CTRL
);
253 static void dwmac1000_pmt(struct mac_device_info
*hw
, unsigned long mode
)
255 void __iomem
*ioaddr
= hw
->pcsr
;
256 unsigned int pmt
= 0;
258 if (mode
& WAKE_MAGIC
) {
259 pr_debug("GMAC: WOL Magic frame\n");
260 pmt
|= power_down
| magic_pkt_en
;
262 if (mode
& WAKE_UCAST
) {
263 pr_debug("GMAC: WOL on global unicast\n");
264 pmt
|= global_unicast
;
267 writel(pmt
, ioaddr
+ GMAC_PMT
);
270 /* RGMII or SMII interface */
271 static void dwmac1000_rgsmii(void __iomem
*ioaddr
, struct stmmac_extra_stats
*x
)
275 status
= readl(ioaddr
+ GMAC_RGSMIIIS
);
278 /* Check the link status */
279 if (status
& GMAC_RGSMIIIS_LNKSTS
) {
284 speed_value
= ((status
& GMAC_RGSMIIIS_SPEED
) >>
285 GMAC_RGSMIIIS_SPEED_SHIFT
);
286 if (speed_value
== GMAC_RGSMIIIS_SPEED_125
)
287 x
->pcs_speed
= SPEED_1000
;
288 else if (speed_value
== GMAC_RGSMIIIS_SPEED_25
)
289 x
->pcs_speed
= SPEED_100
;
291 x
->pcs_speed
= SPEED_10
;
293 x
->pcs_duplex
= (status
& GMAC_RGSMIIIS_LNKMOD_MASK
);
295 pr_info("Link is Up - %d/%s\n", (int)x
->pcs_speed
,
296 x
->pcs_duplex
? "Full" : "Half");
299 pr_info("Link is Down\n");
303 static int dwmac1000_irq_status(struct mac_device_info
*hw
,
304 struct stmmac_extra_stats
*x
)
306 void __iomem
*ioaddr
= hw
->pcsr
;
307 u32 intr_status
= readl(ioaddr
+ GMAC_INT_STATUS
);
310 /* Not used events (e.g. MMC interrupts) are not handled. */
311 if ((intr_status
& GMAC_INT_STATUS_MMCTIS
))
313 if (unlikely(intr_status
& GMAC_INT_STATUS_MMCRIS
))
315 if (unlikely(intr_status
& GMAC_INT_STATUS_MMCCSUM
))
316 x
->mmc_rx_csum_offload_irq_n
++;
317 if (unlikely(intr_status
& GMAC_INT_DISABLE_PMT
)) {
318 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
319 readl(ioaddr
+ GMAC_PMT
);
320 x
->irq_receive_pmt_irq_n
++;
323 /* MAC tx/rx EEE LPI entry/exit interrupts */
324 if (intr_status
& GMAC_INT_STATUS_LPIIS
) {
325 /* Clean LPI interrupt by reading the Reg 12 */
326 ret
= readl(ioaddr
+ LPI_CTRL_STATUS
);
328 if (ret
& LPI_CTRL_STATUS_TLPIEN
)
329 x
->irq_tx_path_in_lpi_mode_n
++;
330 if (ret
& LPI_CTRL_STATUS_TLPIEX
)
331 x
->irq_tx_path_exit_lpi_mode_n
++;
332 if (ret
& LPI_CTRL_STATUS_RLPIEN
)
333 x
->irq_rx_path_in_lpi_mode_n
++;
334 if (ret
& LPI_CTRL_STATUS_RLPIEX
)
335 x
->irq_rx_path_exit_lpi_mode_n
++;
338 dwmac_pcs_isr(ioaddr
, GMAC_PCS_BASE
, intr_status
, x
);
340 if (intr_status
& PCS_RGSMIIIS_IRQ
)
341 dwmac1000_rgsmii(ioaddr
, x
);
346 static void dwmac1000_set_eee_mode(struct mac_device_info
*hw
)
348 void __iomem
*ioaddr
= hw
->pcsr
;
351 /* Enable the link status receive on RGMII, SGMII ore SMII
352 * receive path and instruct the transmit to enter in LPI
355 value
= readl(ioaddr
+ LPI_CTRL_STATUS
);
356 value
|= LPI_CTRL_STATUS_LPIEN
| LPI_CTRL_STATUS_LPITXA
;
357 writel(value
, ioaddr
+ LPI_CTRL_STATUS
);
360 static void dwmac1000_reset_eee_mode(struct mac_device_info
*hw
)
362 void __iomem
*ioaddr
= hw
->pcsr
;
365 value
= readl(ioaddr
+ LPI_CTRL_STATUS
);
366 value
&= ~(LPI_CTRL_STATUS_LPIEN
| LPI_CTRL_STATUS_LPITXA
);
367 writel(value
, ioaddr
+ LPI_CTRL_STATUS
);
370 static void dwmac1000_set_eee_pls(struct mac_device_info
*hw
, int link
)
372 void __iomem
*ioaddr
= hw
->pcsr
;
375 value
= readl(ioaddr
+ LPI_CTRL_STATUS
);
378 value
|= LPI_CTRL_STATUS_PLS
;
380 value
&= ~LPI_CTRL_STATUS_PLS
;
382 writel(value
, ioaddr
+ LPI_CTRL_STATUS
);
385 static void dwmac1000_set_eee_timer(struct mac_device_info
*hw
, int ls
, int tw
)
387 void __iomem
*ioaddr
= hw
->pcsr
;
388 int value
= ((tw
& 0xffff)) | ((ls
& 0x7ff) << 16);
390 /* Program the timers in the LPI timer control register:
391 * LS: minimum time (ms) for which the link
392 * status from PHY should be ok before transmitting
394 * TW: minimum time (us) for which the core waits
395 * after it has stopped transmitting the LPI pattern.
397 writel(value
, ioaddr
+ LPI_TIMER_CTRL
);
400 static void dwmac1000_ctrl_ane(void __iomem
*ioaddr
, bool ane
, bool srgmi_ral
,
403 dwmac_ctrl_ane(ioaddr
, GMAC_PCS_BASE
, ane
, srgmi_ral
, loopback
);
406 static void dwmac1000_rane(void __iomem
*ioaddr
, bool restart
)
408 dwmac_rane(ioaddr
, GMAC_PCS_BASE
, restart
);
411 static void dwmac1000_get_adv_lp(void __iomem
*ioaddr
, struct rgmii_adv
*adv
)
413 dwmac_get_adv_lp(ioaddr
, GMAC_PCS_BASE
, adv
);
416 static void dwmac1000_debug(void __iomem
*ioaddr
, struct stmmac_extra_stats
*x
)
418 u32 value
= readl(ioaddr
+ GMAC_DEBUG
);
420 if (value
& GMAC_DEBUG_TXSTSFSTS
)
421 x
->mtl_tx_status_fifo_full
++;
422 if (value
& GMAC_DEBUG_TXFSTS
)
423 x
->mtl_tx_fifo_not_empty
++;
424 if (value
& GMAC_DEBUG_TWCSTS
)
426 if (value
& GMAC_DEBUG_TRCSTS_MASK
) {
427 u32 trcsts
= (value
& GMAC_DEBUG_TRCSTS_MASK
)
428 >> GMAC_DEBUG_TRCSTS_SHIFT
;
429 if (trcsts
== GMAC_DEBUG_TRCSTS_WRITE
)
430 x
->mtl_tx_fifo_read_ctrl_write
++;
431 else if (trcsts
== GMAC_DEBUG_TRCSTS_TXW
)
432 x
->mtl_tx_fifo_read_ctrl_wait
++;
433 else if (trcsts
== GMAC_DEBUG_TRCSTS_READ
)
434 x
->mtl_tx_fifo_read_ctrl_read
++;
436 x
->mtl_tx_fifo_read_ctrl_idle
++;
438 if (value
& GMAC_DEBUG_TXPAUSED
)
439 x
->mac_tx_in_pause
++;
440 if (value
& GMAC_DEBUG_TFCSTS_MASK
) {
441 u32 tfcsts
= (value
& GMAC_DEBUG_TFCSTS_MASK
)
442 >> GMAC_DEBUG_TFCSTS_SHIFT
;
444 if (tfcsts
== GMAC_DEBUG_TFCSTS_XFER
)
445 x
->mac_tx_frame_ctrl_xfer
++;
446 else if (tfcsts
== GMAC_DEBUG_TFCSTS_GEN_PAUSE
)
447 x
->mac_tx_frame_ctrl_pause
++;
448 else if (tfcsts
== GMAC_DEBUG_TFCSTS_WAIT
)
449 x
->mac_tx_frame_ctrl_wait
++;
451 x
->mac_tx_frame_ctrl_idle
++;
453 if (value
& GMAC_DEBUG_TPESTS
)
454 x
->mac_gmii_tx_proto_engine
++;
455 if (value
& GMAC_DEBUG_RXFSTS_MASK
) {
456 u32 rxfsts
= (value
& GMAC_DEBUG_RXFSTS_MASK
)
457 >> GMAC_DEBUG_RRCSTS_SHIFT
;
459 if (rxfsts
== GMAC_DEBUG_RXFSTS_FULL
)
460 x
->mtl_rx_fifo_fill_level_full
++;
461 else if (rxfsts
== GMAC_DEBUG_RXFSTS_AT
)
462 x
->mtl_rx_fifo_fill_above_thresh
++;
463 else if (rxfsts
== GMAC_DEBUG_RXFSTS_BT
)
464 x
->mtl_rx_fifo_fill_below_thresh
++;
466 x
->mtl_rx_fifo_fill_level_empty
++;
468 if (value
& GMAC_DEBUG_RRCSTS_MASK
) {
469 u32 rrcsts
= (value
& GMAC_DEBUG_RRCSTS_MASK
) >>
470 GMAC_DEBUG_RRCSTS_SHIFT
;
472 if (rrcsts
== GMAC_DEBUG_RRCSTS_FLUSH
)
473 x
->mtl_rx_fifo_read_ctrl_flush
++;
474 else if (rrcsts
== GMAC_DEBUG_RRCSTS_RSTAT
)
475 x
->mtl_rx_fifo_read_ctrl_read_data
++;
476 else if (rrcsts
== GMAC_DEBUG_RRCSTS_RDATA
)
477 x
->mtl_rx_fifo_read_ctrl_status
++;
479 x
->mtl_rx_fifo_read_ctrl_idle
++;
481 if (value
& GMAC_DEBUG_RWCSTS
)
482 x
->mtl_rx_fifo_ctrl_active
++;
483 if (value
& GMAC_DEBUG_RFCFCSTS_MASK
)
484 x
->mac_rx_frame_ctrl_fifo
= (value
& GMAC_DEBUG_RFCFCSTS_MASK
)
485 >> GMAC_DEBUG_RFCFCSTS_SHIFT
;
486 if (value
& GMAC_DEBUG_RPESTS
)
487 x
->mac_gmii_rx_proto_engine
++;
490 static const struct stmmac_ops dwmac1000_ops
= {
491 .core_init
= dwmac1000_core_init
,
492 .rx_ipc
= dwmac1000_rx_ipc_enable
,
493 .dump_regs
= dwmac1000_dump_regs
,
494 .host_irq_status
= dwmac1000_irq_status
,
495 .set_filter
= dwmac1000_set_filter
,
496 .flow_ctrl
= dwmac1000_flow_ctrl
,
497 .pmt
= dwmac1000_pmt
,
498 .set_umac_addr
= dwmac1000_set_umac_addr
,
499 .get_umac_addr
= dwmac1000_get_umac_addr
,
500 .set_eee_mode
= dwmac1000_set_eee_mode
,
501 .reset_eee_mode
= dwmac1000_reset_eee_mode
,
502 .set_eee_timer
= dwmac1000_set_eee_timer
,
503 .set_eee_pls
= dwmac1000_set_eee_pls
,
504 .debug
= dwmac1000_debug
,
505 .pcs_ctrl_ane
= dwmac1000_ctrl_ane
,
506 .pcs_rane
= dwmac1000_rane
,
507 .pcs_get_adv_lp
= dwmac1000_get_adv_lp
,
510 struct mac_device_info
*dwmac1000_setup(void __iomem
*ioaddr
, int mcbins
,
511 int perfect_uc_entries
,
514 struct mac_device_info
*mac
;
515 u32 hwid
= readl(ioaddr
+ GMAC_VERSION
);
517 mac
= kzalloc(sizeof(const struct mac_device_info
), GFP_KERNEL
);
522 mac
->multicast_filter_bins
= mcbins
;
523 mac
->unicast_filter_entries
= perfect_uc_entries
;
524 mac
->mcast_bits_log2
= 0;
526 if (mac
->multicast_filter_bins
)
527 mac
->mcast_bits_log2
= ilog2(mac
->multicast_filter_bins
);
529 mac
->mac
= &dwmac1000_ops
;
530 mac
->dma
= &dwmac1000_dma_ops
;
532 mac
->link
.port
= GMAC_CONTROL_PS
;
533 mac
->link
.duplex
= GMAC_CONTROL_DM
;
534 mac
->link
.speed
= GMAC_CONTROL_FES
;
535 mac
->mii
.addr
= GMAC_MII_ADDR
;
536 mac
->mii
.data
= GMAC_MII_DATA
;
538 /* Get and dump the chip ID */
539 *synopsys_id
= stmmac_get_synopsys_id(hwid
);