1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #include <linux/pinctrl/consumer.h>
47 #ifdef CONFIG_DEBUG_FS
48 #include <linux/debugfs.h>
49 #include <linux/seq_file.h>
50 #endif /* CONFIG_DEBUG_FS */
51 #include <linux/net_tstamp.h>
52 #include "stmmac_ptp.h"
54 #include <linux/reset.h>
55 #include <linux/of_mdio.h>
56 #include "dwmac1000.h"
58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
60 /* Module parameters */
62 static int watchdog
= TX_TIMEO
;
63 module_param(watchdog
, int, S_IRUGO
| S_IWUSR
);
64 MODULE_PARM_DESC(watchdog
, "Transmit timeout in milliseconds (default 5s)");
66 static int debug
= -1;
67 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
68 MODULE_PARM_DESC(debug
, "Message Level (-1: default, 0: no output, 16: all)");
70 static int phyaddr
= -1;
71 module_param(phyaddr
, int, S_IRUGO
);
72 MODULE_PARM_DESC(phyaddr
, "Physical device address");
74 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
76 static int flow_ctrl
= FLOW_OFF
;
77 module_param(flow_ctrl
, int, S_IRUGO
| S_IWUSR
);
78 MODULE_PARM_DESC(flow_ctrl
, "Flow control ability [on/off]");
80 static int pause
= PAUSE_TIME
;
81 module_param(pause
, int, S_IRUGO
| S_IWUSR
);
82 MODULE_PARM_DESC(pause
, "Flow Control Pause Time");
85 static int tc
= TC_DEFAULT
;
86 module_param(tc
, int, S_IRUGO
| S_IWUSR
);
87 MODULE_PARM_DESC(tc
, "DMA threshold control value");
89 #define DEFAULT_BUFSIZE 1536
90 static int buf_sz
= DEFAULT_BUFSIZE
;
91 module_param(buf_sz
, int, S_IRUGO
| S_IWUSR
);
92 MODULE_PARM_DESC(buf_sz
, "DMA buffer size");
94 static const u32 default_msg_level
= (NETIF_MSG_DRV
| NETIF_MSG_PROBE
|
95 NETIF_MSG_LINK
| NETIF_MSG_IFUP
|
96 NETIF_MSG_IFDOWN
| NETIF_MSG_TIMER
);
98 #define STMMAC_DEFAULT_LPI_TIMER 1000
99 static int eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
100 module_param(eee_timer
, int, S_IRUGO
| S_IWUSR
);
101 MODULE_PARM_DESC(eee_timer
, "LPI tx expiration time in msec");
102 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
104 /* By default the driver will use the ring mode to manage tx and rx descriptors
105 * but passing this value so user can force to use the chain instead of the ring
107 static unsigned int chain_mode
;
108 module_param(chain_mode
, int, S_IRUGO
);
109 MODULE_PARM_DESC(chain_mode
, "To use chain instead of ring mode");
111 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
);
113 #ifdef CONFIG_DEBUG_FS
114 static int stmmac_init_fs(struct net_device
*dev
);
115 static void stmmac_exit_fs(struct net_device
*dev
);
118 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
121 * stmmac_verify_args - verify the driver parameters.
122 * Description: it checks the driver parameters and set a default in case of
125 static void stmmac_verify_args(void)
127 if (unlikely(watchdog
< 0))
129 if (unlikely((buf_sz
< DEFAULT_BUFSIZE
) || (buf_sz
> BUF_SIZE_16KiB
)))
130 buf_sz
= DEFAULT_BUFSIZE
;
131 if (unlikely(flow_ctrl
> 1))
132 flow_ctrl
= FLOW_AUTO
;
133 else if (likely(flow_ctrl
< 0))
134 flow_ctrl
= FLOW_OFF
;
135 if (unlikely((pause
< 0) || (pause
> 0xffff)))
138 eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
142 * stmmac_clk_csr_set - dynamically set the MDC clock
143 * @priv: driver private structure
144 * Description: this is to dynamically set the MDC clock according to the csr
147 * If a specific clk_csr value is passed from the platform
148 * this means that the CSR Clock Range selection cannot be
149 * changed at run-time and it is fixed (as reported in the driver
150 * documentation). Viceversa the driver will try to set the MDC
151 * clock dynamically according to the actual clock input.
153 static void stmmac_clk_csr_set(struct stmmac_priv
*priv
)
157 clk_rate
= clk_get_rate(priv
->stmmac_clk
);
159 /* Platform provided default clk_csr would be assumed valid
160 * for all other cases except for the below mentioned ones.
161 * For values higher than the IEEE 802.3 specified frequency
162 * we can not estimate the proper divider as it is not known
163 * the frequency of clk_csr_i. So we do not change the default
166 if (!(priv
->clk_csr
& MAC_CSR_H_FRQ_MASK
)) {
167 if (clk_rate
< CSR_F_35M
)
168 priv
->clk_csr
= STMMAC_CSR_20_35M
;
169 else if ((clk_rate
>= CSR_F_35M
) && (clk_rate
< CSR_F_60M
))
170 priv
->clk_csr
= STMMAC_CSR_35_60M
;
171 else if ((clk_rate
>= CSR_F_60M
) && (clk_rate
< CSR_F_100M
))
172 priv
->clk_csr
= STMMAC_CSR_60_100M
;
173 else if ((clk_rate
>= CSR_F_100M
) && (clk_rate
< CSR_F_150M
))
174 priv
->clk_csr
= STMMAC_CSR_100_150M
;
175 else if ((clk_rate
>= CSR_F_150M
) && (clk_rate
< CSR_F_250M
))
176 priv
->clk_csr
= STMMAC_CSR_150_250M
;
177 else if ((clk_rate
>= CSR_F_250M
) && (clk_rate
< CSR_F_300M
))
178 priv
->clk_csr
= STMMAC_CSR_250_300M
;
182 static void print_pkt(unsigned char *buf
, int len
)
184 pr_debug("len = %d byte, buf addr: 0x%p\n", len
, buf
);
185 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
, buf
, len
);
188 static inline u32
stmmac_tx_avail(struct stmmac_priv
*priv
)
192 if (priv
->dirty_tx
> priv
->cur_tx
)
193 avail
= priv
->dirty_tx
- priv
->cur_tx
- 1;
195 avail
= DMA_TX_SIZE
- priv
->cur_tx
+ priv
->dirty_tx
- 1;
200 static inline u32
stmmac_rx_dirty(struct stmmac_priv
*priv
)
204 if (priv
->dirty_rx
<= priv
->cur_rx
)
205 dirty
= priv
->cur_rx
- priv
->dirty_rx
;
207 dirty
= DMA_RX_SIZE
- priv
->dirty_rx
+ priv
->cur_rx
;
213 * stmmac_hw_fix_mac_speed - callback for speed selection
214 * @priv: driver private structure
215 * Description: on some platforms (e.g. ST), some HW system configuraton
216 * registers have to be set according to the link speed negotiated.
218 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv
*priv
)
220 struct phy_device
*phydev
= priv
->phydev
;
222 if (likely(priv
->plat
->fix_mac_speed
))
223 priv
->plat
->fix_mac_speed(priv
->plat
->bsp_priv
, phydev
->speed
);
227 * stmmac_enable_eee_mode - check and enter in LPI mode
228 * @priv: driver private structure
229 * Description: this function is to verify and enter in LPI mode in case of
232 static void stmmac_enable_eee_mode(struct stmmac_priv
*priv
)
234 /* Check and enter in LPI mode */
235 if ((priv
->dirty_tx
== priv
->cur_tx
) &&
236 (priv
->tx_path_in_lpi_mode
== false))
237 priv
->hw
->mac
->set_eee_mode(priv
->hw
);
241 * stmmac_disable_eee_mode - disable and exit from LPI mode
242 * @priv: driver private structure
243 * Description: this function is to exit and disable EEE in case of
244 * LPI state is true. This is called by the xmit.
246 void stmmac_disable_eee_mode(struct stmmac_priv
*priv
)
248 priv
->hw
->mac
->reset_eee_mode(priv
->hw
);
249 del_timer_sync(&priv
->eee_ctrl_timer
);
250 priv
->tx_path_in_lpi_mode
= false;
254 * stmmac_eee_ctrl_timer - EEE TX SW timer.
257 * if there is no data transfer and if we are not in LPI state,
258 * then MAC Transmitter can be moved to LPI state.
260 static void stmmac_eee_ctrl_timer(unsigned long arg
)
262 struct stmmac_priv
*priv
= (struct stmmac_priv
*)arg
;
264 stmmac_enable_eee_mode(priv
);
265 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
269 * stmmac_eee_init - init EEE
270 * @priv: driver private structure
272 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
273 * can also manage EEE, this function enable the LPI state and start related
276 bool stmmac_eee_init(struct stmmac_priv
*priv
)
278 char *phy_bus_name
= priv
->plat
->phy_bus_name
;
282 /* Using PCS we cannot dial with the phy registers at this stage
283 * so we do not support extra feature like EEE.
285 if ((priv
->pcs
== STMMAC_PCS_RGMII
) || (priv
->pcs
== STMMAC_PCS_TBI
) ||
286 (priv
->pcs
== STMMAC_PCS_RTBI
))
289 /* Never init EEE in case of a switch is attached */
290 if (phy_bus_name
&& (!strcmp(phy_bus_name
, "fixed")))
293 /* MAC core supports the EEE feature. */
294 if (priv
->dma_cap
.eee
) {
295 int tx_lpi_timer
= priv
->tx_lpi_timer
;
297 /* Check if the PHY supports EEE */
298 if (phy_init_eee(priv
->phydev
, 1)) {
299 /* To manage at run-time if the EEE cannot be supported
300 * anymore (for example because the lp caps have been
302 * In that case the driver disable own timers.
304 spin_lock_irqsave(&priv
->lock
, flags
);
305 if (priv
->eee_active
) {
306 pr_debug("stmmac: disable EEE\n");
307 del_timer_sync(&priv
->eee_ctrl_timer
);
308 priv
->hw
->mac
->set_eee_timer(priv
->hw
, 0,
311 priv
->eee_active
= 0;
312 spin_unlock_irqrestore(&priv
->lock
, flags
);
315 /* Activate the EEE and start timers */
316 spin_lock_irqsave(&priv
->lock
, flags
);
317 if (!priv
->eee_active
) {
318 priv
->eee_active
= 1;
319 setup_timer(&priv
->eee_ctrl_timer
,
320 stmmac_eee_ctrl_timer
,
321 (unsigned long)priv
);
322 mod_timer(&priv
->eee_ctrl_timer
,
323 STMMAC_LPI_T(eee_timer
));
325 priv
->hw
->mac
->set_eee_timer(priv
->hw
,
326 STMMAC_DEFAULT_LIT_LS
,
329 /* Set HW EEE according to the speed */
330 priv
->hw
->mac
->set_eee_pls(priv
->hw
, priv
->phydev
->link
);
333 spin_unlock_irqrestore(&priv
->lock
, flags
);
335 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
341 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
342 * @priv: driver private structure
343 * @entry : descriptor index to be used.
344 * @skb : the socket buffer
346 * This function will read timestamp from the descriptor & pass it to stack.
347 * and also perform some sanity checks.
349 static void stmmac_get_tx_hwtstamp(struct stmmac_priv
*priv
,
350 unsigned int entry
, struct sk_buff
*skb
)
352 struct skb_shared_hwtstamps shhwtstamp
;
356 if (!priv
->hwts_tx_en
)
359 /* exit if skb doesn't support hw tstamp */
360 if (likely(!skb
|| !(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)))
364 desc
= (priv
->dma_etx
+ entry
);
366 desc
= (priv
->dma_tx
+ entry
);
368 /* check tx tstamp status */
369 if (!priv
->hw
->desc
->get_tx_timestamp_status((struct dma_desc
*)desc
))
372 /* get the valid tstamp */
373 ns
= priv
->hw
->desc
->get_timestamp(desc
, priv
->adv_ts
);
375 memset(&shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
376 shhwtstamp
.hwtstamp
= ns_to_ktime(ns
);
377 /* pass tstamp to stack */
378 skb_tstamp_tx(skb
, &shhwtstamp
);
383 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
384 * @priv: driver private structure
385 * @entry : descriptor index to be used.
386 * @skb : the socket buffer
388 * This function will read received packet's timestamp from the descriptor
389 * and pass it to stack. It also perform some sanity checks.
391 static void stmmac_get_rx_hwtstamp(struct stmmac_priv
*priv
,
392 unsigned int entry
, struct sk_buff
*skb
)
394 struct skb_shared_hwtstamps
*shhwtstamp
= NULL
;
398 if (!priv
->hwts_rx_en
)
402 desc
= (priv
->dma_erx
+ entry
);
404 desc
= (priv
->dma_rx
+ entry
);
406 /* exit if rx tstamp is not valid */
407 if (!priv
->hw
->desc
->get_rx_timestamp_status(desc
, priv
->adv_ts
))
410 /* get valid tstamp */
411 ns
= priv
->hw
->desc
->get_timestamp(desc
, priv
->adv_ts
);
412 shhwtstamp
= skb_hwtstamps(skb
);
413 memset(shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
414 shhwtstamp
->hwtstamp
= ns_to_ktime(ns
);
418 * stmmac_hwtstamp_ioctl - control hardware timestamping.
419 * @dev: device pointer.
420 * @ifr: An IOCTL specefic structure, that can contain a pointer to
421 * a proprietary structure used to pass information to the driver.
423 * This function configures the MAC to enable/disable both outgoing(TX)
424 * and incoming(RX) packets time stamping based on user input.
426 * 0 on success and an appropriate -ve integer on failure.
428 static int stmmac_hwtstamp_ioctl(struct net_device
*dev
, struct ifreq
*ifr
)
430 struct stmmac_priv
*priv
= netdev_priv(dev
);
431 struct hwtstamp_config config
;
432 struct timespec64 now
;
436 u32 ptp_over_ipv4_udp
= 0;
437 u32 ptp_over_ipv6_udp
= 0;
438 u32 ptp_over_ethernet
= 0;
439 u32 snap_type_sel
= 0;
440 u32 ts_master_en
= 0;
445 if (!(priv
->dma_cap
.time_stamp
|| priv
->adv_ts
)) {
446 netdev_alert(priv
->dev
, "No support for HW time stamping\n");
447 priv
->hwts_tx_en
= 0;
448 priv
->hwts_rx_en
= 0;
453 if (copy_from_user(&config
, ifr
->ifr_data
,
454 sizeof(struct hwtstamp_config
)))
457 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
458 __func__
, config
.flags
, config
.tx_type
, config
.rx_filter
);
460 /* reserved for future extensions */
464 if (config
.tx_type
!= HWTSTAMP_TX_OFF
&&
465 config
.tx_type
!= HWTSTAMP_TX_ON
)
469 switch (config
.rx_filter
) {
470 case HWTSTAMP_FILTER_NONE
:
471 /* time stamp no incoming packet at all */
472 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
475 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
476 /* PTP v1, UDP, any kind of event packet */
477 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
478 /* take time stamp for all event messages */
479 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
481 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
482 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
485 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
486 /* PTP v1, UDP, Sync packet */
487 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_SYNC
;
488 /* take time stamp for SYNC messages only */
489 ts_event_en
= PTP_TCR_TSEVNTENA
;
491 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
492 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
495 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
496 /* PTP v1, UDP, Delay_req packet */
497 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
;
498 /* take time stamp for Delay_Req messages only */
499 ts_master_en
= PTP_TCR_TSMSTRENA
;
500 ts_event_en
= PTP_TCR_TSEVNTENA
;
502 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
503 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
506 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
507 /* PTP v2, UDP, any kind of event packet */
508 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_EVENT
;
509 ptp_v2
= PTP_TCR_TSVER2ENA
;
510 /* take time stamp for all event messages */
511 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
513 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
514 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
517 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
518 /* PTP v2, UDP, Sync packet */
519 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_SYNC
;
520 ptp_v2
= PTP_TCR_TSVER2ENA
;
521 /* take time stamp for SYNC messages only */
522 ts_event_en
= PTP_TCR_TSEVNTENA
;
524 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
525 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
528 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
529 /* PTP v2, UDP, Delay_req packet */
530 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
;
531 ptp_v2
= PTP_TCR_TSVER2ENA
;
532 /* take time stamp for Delay_Req messages only */
533 ts_master_en
= PTP_TCR_TSMSTRENA
;
534 ts_event_en
= PTP_TCR_TSEVNTENA
;
536 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
537 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
540 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
541 /* PTP v2/802.AS1 any layer, any kind of event packet */
542 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
543 ptp_v2
= PTP_TCR_TSVER2ENA
;
544 /* take time stamp for all event messages */
545 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
547 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
548 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
549 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
552 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
553 /* PTP v2/802.AS1, any layer, Sync packet */
554 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_SYNC
;
555 ptp_v2
= PTP_TCR_TSVER2ENA
;
556 /* take time stamp for SYNC messages only */
557 ts_event_en
= PTP_TCR_TSEVNTENA
;
559 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
560 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
561 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
564 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
565 /* PTP v2/802.AS1, any layer, Delay_req packet */
566 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
;
567 ptp_v2
= PTP_TCR_TSVER2ENA
;
568 /* take time stamp for Delay_Req messages only */
569 ts_master_en
= PTP_TCR_TSMSTRENA
;
570 ts_event_en
= PTP_TCR_TSEVNTENA
;
572 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
573 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
574 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
577 case HWTSTAMP_FILTER_ALL
:
578 /* time stamp any incoming packet */
579 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
580 tstamp_all
= PTP_TCR_TSENALL
;
587 switch (config
.rx_filter
) {
588 case HWTSTAMP_FILTER_NONE
:
589 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
592 /* PTP v1, UDP, any kind of event packet */
593 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
597 priv
->hwts_rx_en
= ((config
.rx_filter
== HWTSTAMP_FILTER_NONE
) ? 0 : 1);
598 priv
->hwts_tx_en
= config
.tx_type
== HWTSTAMP_TX_ON
;
600 if (!priv
->hwts_tx_en
&& !priv
->hwts_rx_en
)
601 priv
->hw
->ptp
->config_hw_tstamping(priv
->ioaddr
, 0);
603 value
= (PTP_TCR_TSENA
| PTP_TCR_TSCFUPDT
| PTP_TCR_TSCTRLSSR
|
604 tstamp_all
| ptp_v2
| ptp_over_ethernet
|
605 ptp_over_ipv6_udp
| ptp_over_ipv4_udp
| ts_event_en
|
606 ts_master_en
| snap_type_sel
);
607 priv
->hw
->ptp
->config_hw_tstamping(priv
->ioaddr
, value
);
609 /* program Sub Second Increment reg */
610 sec_inc
= priv
->hw
->ptp
->config_sub_second_increment(
611 priv
->ioaddr
, priv
->clk_ptp_rate
);
612 temp
= div_u64(1000000000ULL, sec_inc
);
614 /* calculate default added value:
616 * addend = (2^32)/freq_div_ratio;
617 * where, freq_div_ratio = 1e9ns/sec_inc
619 temp
= (u64
)(temp
<< 32);
620 priv
->default_addend
= div_u64(temp
, priv
->clk_ptp_rate
);
621 priv
->hw
->ptp
->config_addend(priv
->ioaddr
,
622 priv
->default_addend
);
624 /* initialize system time */
625 ktime_get_real_ts64(&now
);
627 /* lower 32 bits of tv_sec are safe until y2106 */
628 priv
->hw
->ptp
->init_systime(priv
->ioaddr
, (u32
)now
.tv_sec
,
632 return copy_to_user(ifr
->ifr_data
, &config
,
633 sizeof(struct hwtstamp_config
)) ? -EFAULT
: 0;
637 * stmmac_init_ptp - init PTP
638 * @priv: driver private structure
639 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
640 * This is done by looking at the HW cap. register.
641 * This function also registers the ptp driver.
643 static int stmmac_init_ptp(struct stmmac_priv
*priv
)
645 if (!(priv
->dma_cap
.time_stamp
|| priv
->dma_cap
.atime_stamp
))
648 /* Fall-back to main clock in case of no PTP ref is passed */
649 priv
->clk_ptp_ref
= devm_clk_get(priv
->device
, "clk_ptp_ref");
650 if (IS_ERR(priv
->clk_ptp_ref
)) {
651 priv
->clk_ptp_rate
= clk_get_rate(priv
->stmmac_clk
);
652 priv
->clk_ptp_ref
= NULL
;
654 clk_prepare_enable(priv
->clk_ptp_ref
);
655 priv
->clk_ptp_rate
= clk_get_rate(priv
->clk_ptp_ref
);
659 if (priv
->dma_cap
.atime_stamp
&& priv
->extend_desc
)
662 if (netif_msg_hw(priv
) && priv
->dma_cap
.time_stamp
)
663 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
665 if (netif_msg_hw(priv
) && priv
->adv_ts
)
666 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
668 priv
->hw
->ptp
= &stmmac_ptp
;
669 priv
->hwts_tx_en
= 0;
670 priv
->hwts_rx_en
= 0;
672 return stmmac_ptp_register(priv
);
675 static void stmmac_release_ptp(struct stmmac_priv
*priv
)
677 if (priv
->clk_ptp_ref
)
678 clk_disable_unprepare(priv
->clk_ptp_ref
);
679 stmmac_ptp_unregister(priv
);
683 * stmmac_adjust_link - adjusts the link parameters
684 * @dev: net device structure
685 * Description: this is the helper called by the physical abstraction layer
686 * drivers to communicate the phy link status. According the speed and duplex
687 * this driver can invoke registered glue-logic as well.
688 * It also invoke the eee initialization because it could happen when switch
689 * on different networks (that are eee capable).
691 static void stmmac_adjust_link(struct net_device
*dev
)
693 struct stmmac_priv
*priv
= netdev_priv(dev
);
694 struct phy_device
*phydev
= priv
->phydev
;
697 unsigned int fc
= priv
->flow_ctrl
, pause_time
= priv
->pause
;
702 spin_lock_irqsave(&priv
->lock
, flags
);
705 u32 ctrl
= readl(priv
->ioaddr
+ MAC_CTRL_REG
);
707 /* Now we make sure that we can be in full duplex mode.
708 * If not, we operate in half-duplex mode. */
709 if (phydev
->duplex
!= priv
->oldduplex
) {
711 if (!(phydev
->duplex
))
712 ctrl
&= ~priv
->hw
->link
.duplex
;
714 ctrl
|= priv
->hw
->link
.duplex
;
715 priv
->oldduplex
= phydev
->duplex
;
717 /* Flow Control operation */
719 priv
->hw
->mac
->flow_ctrl(priv
->hw
, phydev
->duplex
,
722 if (phydev
->speed
!= priv
->speed
) {
724 switch (phydev
->speed
) {
726 if (likely(priv
->plat
->has_gmac
))
727 ctrl
&= ~priv
->hw
->link
.port
;
728 stmmac_hw_fix_mac_speed(priv
);
732 if (priv
->plat
->has_gmac
) {
733 ctrl
|= priv
->hw
->link
.port
;
734 if (phydev
->speed
== SPEED_100
) {
735 ctrl
|= priv
->hw
->link
.speed
;
737 ctrl
&= ~(priv
->hw
->link
.speed
);
740 ctrl
&= ~priv
->hw
->link
.port
;
742 stmmac_hw_fix_mac_speed(priv
);
745 if (netif_msg_link(priv
))
746 pr_warn("%s: Speed (%d) not 10/100\n",
747 dev
->name
, phydev
->speed
);
751 priv
->speed
= phydev
->speed
;
754 writel(ctrl
, priv
->ioaddr
+ MAC_CTRL_REG
);
756 if (!priv
->oldlink
) {
760 } else if (priv
->oldlink
) {
764 priv
->oldduplex
= -1;
767 if (new_state
&& netif_msg_link(priv
))
768 phy_print_status(phydev
);
770 spin_unlock_irqrestore(&priv
->lock
, flags
);
772 /* At this stage, it could be needed to setup the EEE or adjust some
773 * MAC related HW registers.
775 priv
->eee_enabled
= stmmac_eee_init(priv
);
779 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
780 * @priv: driver private structure
781 * Description: this is to verify if the HW supports the PCS.
782 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
783 * configured for the TBI, RTBI, or SGMII PHY interface.
785 static void stmmac_check_pcs_mode(struct stmmac_priv
*priv
)
787 int interface
= priv
->plat
->interface
;
789 if (priv
->dma_cap
.pcs
) {
790 if ((interface
== PHY_INTERFACE_MODE_RGMII
) ||
791 (interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
792 (interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
793 (interface
== PHY_INTERFACE_MODE_RGMII_TXID
)) {
794 pr_debug("STMMAC: PCS RGMII support enable\n");
795 priv
->pcs
= STMMAC_PCS_RGMII
;
796 } else if (interface
== PHY_INTERFACE_MODE_SGMII
) {
797 pr_debug("STMMAC: PCS SGMII support enable\n");
798 priv
->pcs
= STMMAC_PCS_SGMII
;
804 * stmmac_init_phy - PHY initialization
805 * @dev: net device structure
806 * Description: it initializes the driver's PHY state, and attaches the PHY
811 static int stmmac_init_phy(struct net_device
*dev
)
813 struct stmmac_priv
*priv
= netdev_priv(dev
);
814 struct phy_device
*phydev
;
815 char phy_id_fmt
[MII_BUS_ID_SIZE
+ 3];
816 char bus_id
[MII_BUS_ID_SIZE
];
817 int interface
= priv
->plat
->interface
;
818 int max_speed
= priv
->plat
->max_speed
;
821 priv
->oldduplex
= -1;
823 if (priv
->plat
->phy_node
) {
824 phydev
= of_phy_connect(dev
, priv
->plat
->phy_node
,
825 &stmmac_adjust_link
, 0, interface
);
827 if (priv
->plat
->phy_bus_name
)
828 snprintf(bus_id
, MII_BUS_ID_SIZE
, "%s-%x",
829 priv
->plat
->phy_bus_name
, priv
->plat
->bus_id
);
831 snprintf(bus_id
, MII_BUS_ID_SIZE
, "stmmac-%x",
834 snprintf(phy_id_fmt
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
, bus_id
,
835 priv
->plat
->phy_addr
);
836 pr_debug("stmmac_init_phy: trying to attach to %s\n",
839 phydev
= phy_connect(dev
, phy_id_fmt
, &stmmac_adjust_link
,
843 if (IS_ERR_OR_NULL(phydev
)) {
844 pr_err("%s: Could not attach to PHY\n", dev
->name
);
848 return PTR_ERR(phydev
);
851 /* Stop Advertising 1000BASE Capability if interface is not GMII */
852 if ((interface
== PHY_INTERFACE_MODE_MII
) ||
853 (interface
== PHY_INTERFACE_MODE_RMII
) ||
854 (max_speed
< 1000 && max_speed
> 0))
855 phydev
->advertising
&= ~(SUPPORTED_1000baseT_Half
|
856 SUPPORTED_1000baseT_Full
);
859 * Broken HW is sometimes missing the pull-up resistor on the
860 * MDIO line, which results in reads to non-existent devices returning
861 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
863 * Note: phydev->phy_id is the result of reading the UID PHY registers.
865 if (!priv
->plat
->phy_node
&& phydev
->phy_id
== 0) {
866 phy_disconnect(phydev
);
870 /* If attached to a switch, there is no reason to poll phy handler */
871 if (priv
->plat
->phy_bus_name
)
872 if (!strcmp(priv
->plat
->phy_bus_name
, "fixed"))
873 phydev
->irq
= PHY_IGNORE_INTERRUPT
;
875 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
876 " Link = %d\n", dev
->name
, phydev
->phy_id
, phydev
->link
);
878 priv
->phydev
= phydev
;
884 * stmmac_display_ring - display ring
885 * @head: pointer to the head of the ring passed.
886 * @size: size of the ring.
887 * @extend_desc: to verify if extended descriptors are used.
888 * Description: display the control/status and buffer descriptors.
890 static void stmmac_display_ring(void *head
, int size
, int extend_desc
)
893 struct dma_extended_desc
*ep
= (struct dma_extended_desc
*)head
;
894 struct dma_desc
*p
= (struct dma_desc
*)head
;
896 for (i
= 0; i
< size
; i
++) {
900 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
901 i
, (unsigned int)virt_to_phys(ep
),
902 (unsigned int)x
, (unsigned int)(x
>> 32),
903 ep
->basic
.des2
, ep
->basic
.des3
);
907 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
908 i
, (unsigned int)virt_to_phys(p
),
909 (unsigned int)x
, (unsigned int)(x
>> 32),
917 static void stmmac_display_rings(struct stmmac_priv
*priv
)
919 if (priv
->extend_desc
) {
920 pr_info("Extended RX descriptor ring:\n");
921 stmmac_display_ring((void *)priv
->dma_erx
, DMA_RX_SIZE
, 1);
922 pr_info("Extended TX descriptor ring:\n");
923 stmmac_display_ring((void *)priv
->dma_etx
, DMA_TX_SIZE
, 1);
925 pr_info("RX descriptor ring:\n");
926 stmmac_display_ring((void *)priv
->dma_rx
, DMA_RX_SIZE
, 0);
927 pr_info("TX descriptor ring:\n");
928 stmmac_display_ring((void *)priv
->dma_tx
, DMA_TX_SIZE
, 0);
932 static int stmmac_set_bfsize(int mtu
, int bufsize
)
936 if (mtu
>= BUF_SIZE_4KiB
)
938 else if (mtu
>= BUF_SIZE_2KiB
)
940 else if (mtu
> DEFAULT_BUFSIZE
)
943 ret
= DEFAULT_BUFSIZE
;
949 * stmmac_clear_descriptors - clear descriptors
950 * @priv: driver private structure
951 * Description: this function is called to clear the tx and rx descriptors
952 * in case of both basic and extended descriptors are used.
954 static void stmmac_clear_descriptors(struct stmmac_priv
*priv
)
958 /* Clear the Rx/Tx descriptors */
959 for (i
= 0; i
< DMA_RX_SIZE
; i
++)
960 if (priv
->extend_desc
)
961 priv
->hw
->desc
->init_rx_desc(&priv
->dma_erx
[i
].basic
,
962 priv
->use_riwt
, priv
->mode
,
963 (i
== DMA_RX_SIZE
- 1));
965 priv
->hw
->desc
->init_rx_desc(&priv
->dma_rx
[i
],
966 priv
->use_riwt
, priv
->mode
,
967 (i
== DMA_RX_SIZE
- 1));
968 for (i
= 0; i
< DMA_TX_SIZE
; i
++)
969 if (priv
->extend_desc
)
970 priv
->hw
->desc
->init_tx_desc(&priv
->dma_etx
[i
].basic
,
972 (i
== DMA_TX_SIZE
- 1));
974 priv
->hw
->desc
->init_tx_desc(&priv
->dma_tx
[i
],
976 (i
== DMA_TX_SIZE
- 1));
980 * stmmac_init_rx_buffers - init the RX descriptor buffer.
981 * @priv: driver private structure
982 * @p: descriptor pointer
983 * @i: descriptor index
985 * Description: this function is called to allocate a receive buffer, perform
986 * the DMA mapping and init the descriptor.
988 static int stmmac_init_rx_buffers(struct stmmac_priv
*priv
, struct dma_desc
*p
,
993 skb
= __netdev_alloc_skb_ip_align(priv
->dev
, priv
->dma_buf_sz
, flags
);
995 pr_err("%s: Rx init fails; skb is NULL\n", __func__
);
998 priv
->rx_skbuff
[i
] = skb
;
999 priv
->rx_skbuff_dma
[i
] = dma_map_single(priv
->device
, skb
->data
,
1002 if (dma_mapping_error(priv
->device
, priv
->rx_skbuff_dma
[i
])) {
1003 pr_err("%s: DMA mapping error\n", __func__
);
1004 dev_kfree_skb_any(skb
);
1008 p
->des2
= priv
->rx_skbuff_dma
[i
];
1010 if ((priv
->hw
->mode
->init_desc3
) &&
1011 (priv
->dma_buf_sz
== BUF_SIZE_16KiB
))
1012 priv
->hw
->mode
->init_desc3(p
);
1017 static void stmmac_free_rx_buffers(struct stmmac_priv
*priv
, int i
)
1019 if (priv
->rx_skbuff
[i
]) {
1020 dma_unmap_single(priv
->device
, priv
->rx_skbuff_dma
[i
],
1021 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
1022 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
1024 priv
->rx_skbuff
[i
] = NULL
;
1028 * init_dma_desc_rings - init the RX/TX descriptor rings
1029 * @dev: net device structure
1031 * Description: this function initializes the DMA RX/TX descriptors
1032 * and allocates the socket buffers. It suppors the chained and ring
1035 static int init_dma_desc_rings(struct net_device
*dev
, gfp_t flags
)
1038 struct stmmac_priv
*priv
= netdev_priv(dev
);
1039 unsigned int bfsize
= 0;
1042 if (priv
->hw
->mode
->set_16kib_bfsize
)
1043 bfsize
= priv
->hw
->mode
->set_16kib_bfsize(dev
->mtu
);
1045 if (bfsize
< BUF_SIZE_16KiB
)
1046 bfsize
= stmmac_set_bfsize(dev
->mtu
, priv
->dma_buf_sz
);
1048 priv
->dma_buf_sz
= bfsize
;
1050 if (netif_msg_probe(priv
)) {
1051 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__
,
1052 (u32
) priv
->dma_rx_phy
, (u32
) priv
->dma_tx_phy
);
1054 /* RX INITIALIZATION */
1055 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1057 for (i
= 0; i
< DMA_RX_SIZE
; i
++) {
1059 if (priv
->extend_desc
)
1060 p
= &((priv
->dma_erx
+ i
)->basic
);
1062 p
= priv
->dma_rx
+ i
;
1064 ret
= stmmac_init_rx_buffers(priv
, p
, i
, flags
);
1066 goto err_init_rx_buffers
;
1068 if (netif_msg_probe(priv
))
1069 pr_debug("[%p]\t[%p]\t[%x]\n", priv
->rx_skbuff
[i
],
1070 priv
->rx_skbuff
[i
]->data
,
1071 (unsigned int)priv
->rx_skbuff_dma
[i
]);
1074 priv
->dirty_rx
= (unsigned int)(i
- DMA_RX_SIZE
);
1077 /* Setup the chained descriptor addresses */
1078 if (priv
->mode
== STMMAC_CHAIN_MODE
) {
1079 if (priv
->extend_desc
) {
1080 priv
->hw
->mode
->init(priv
->dma_erx
, priv
->dma_rx_phy
,
1082 priv
->hw
->mode
->init(priv
->dma_etx
, priv
->dma_tx_phy
,
1085 priv
->hw
->mode
->init(priv
->dma_rx
, priv
->dma_rx_phy
,
1087 priv
->hw
->mode
->init(priv
->dma_tx
, priv
->dma_tx_phy
,
1092 /* TX INITIALIZATION */
1093 for (i
= 0; i
< DMA_TX_SIZE
; i
++) {
1095 if (priv
->extend_desc
)
1096 p
= &((priv
->dma_etx
+ i
)->basic
);
1098 p
= priv
->dma_tx
+ i
;
1100 priv
->tx_skbuff_dma
[i
].buf
= 0;
1101 priv
->tx_skbuff_dma
[i
].map_as_page
= false;
1102 priv
->tx_skbuff_dma
[i
].len
= 0;
1103 priv
->tx_skbuff_dma
[i
].last_segment
= false;
1104 priv
->tx_skbuff
[i
] = NULL
;
1109 netdev_reset_queue(priv
->dev
);
1111 stmmac_clear_descriptors(priv
);
1113 if (netif_msg_hw(priv
))
1114 stmmac_display_rings(priv
);
1117 err_init_rx_buffers
:
1119 stmmac_free_rx_buffers(priv
, i
);
1123 static void dma_free_rx_skbufs(struct stmmac_priv
*priv
)
1127 for (i
= 0; i
< DMA_RX_SIZE
; i
++)
1128 stmmac_free_rx_buffers(priv
, i
);
1131 static void dma_free_tx_skbufs(struct stmmac_priv
*priv
)
1135 for (i
= 0; i
< DMA_TX_SIZE
; i
++) {
1138 if (priv
->extend_desc
)
1139 p
= &((priv
->dma_etx
+ i
)->basic
);
1141 p
= priv
->dma_tx
+ i
;
1143 if (priv
->tx_skbuff_dma
[i
].buf
) {
1144 if (priv
->tx_skbuff_dma
[i
].map_as_page
)
1145 dma_unmap_page(priv
->device
,
1146 priv
->tx_skbuff_dma
[i
].buf
,
1147 priv
->tx_skbuff_dma
[i
].len
,
1150 dma_unmap_single(priv
->device
,
1151 priv
->tx_skbuff_dma
[i
].buf
,
1152 priv
->tx_skbuff_dma
[i
].len
,
1156 if (priv
->tx_skbuff
[i
] != NULL
) {
1157 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
1158 priv
->tx_skbuff
[i
] = NULL
;
1159 priv
->tx_skbuff_dma
[i
].buf
= 0;
1160 priv
->tx_skbuff_dma
[i
].map_as_page
= false;
1166 * alloc_dma_desc_resources - alloc TX/RX resources.
1167 * @priv: private structure
1168 * Description: according to which descriptor can be used (extend or basic)
1169 * this function allocates the resources for TX and RX paths. In case of
1170 * reception, for example, it pre-allocated the RX socket buffer in order to
1171 * allow zero-copy mechanism.
1173 static int alloc_dma_desc_resources(struct stmmac_priv
*priv
)
1177 priv
->rx_skbuff_dma
= kmalloc_array(DMA_RX_SIZE
, sizeof(dma_addr_t
),
1179 if (!priv
->rx_skbuff_dma
)
1182 priv
->rx_skbuff
= kmalloc_array(DMA_RX_SIZE
, sizeof(struct sk_buff
*),
1184 if (!priv
->rx_skbuff
)
1187 priv
->tx_skbuff_dma
= kmalloc_array(DMA_TX_SIZE
,
1188 sizeof(*priv
->tx_skbuff_dma
),
1190 if (!priv
->tx_skbuff_dma
)
1191 goto err_tx_skbuff_dma
;
1193 priv
->tx_skbuff
= kmalloc_array(DMA_TX_SIZE
, sizeof(struct sk_buff
*),
1195 if (!priv
->tx_skbuff
)
1198 if (priv
->extend_desc
) {
1199 priv
->dma_erx
= dma_zalloc_coherent(priv
->device
, DMA_RX_SIZE
*
1207 priv
->dma_etx
= dma_zalloc_coherent(priv
->device
, DMA_TX_SIZE
*
1212 if (!priv
->dma_etx
) {
1213 dma_free_coherent(priv
->device
, DMA_RX_SIZE
*
1214 sizeof(struct dma_extended_desc
),
1215 priv
->dma_erx
, priv
->dma_rx_phy
);
1219 priv
->dma_rx
= dma_zalloc_coherent(priv
->device
, DMA_RX_SIZE
*
1220 sizeof(struct dma_desc
),
1226 priv
->dma_tx
= dma_zalloc_coherent(priv
->device
, DMA_TX_SIZE
*
1227 sizeof(struct dma_desc
),
1230 if (!priv
->dma_tx
) {
1231 dma_free_coherent(priv
->device
, DMA_RX_SIZE
*
1232 sizeof(struct dma_desc
),
1233 priv
->dma_rx
, priv
->dma_rx_phy
);
1241 kfree(priv
->tx_skbuff
);
1243 kfree(priv
->tx_skbuff_dma
);
1245 kfree(priv
->rx_skbuff
);
1247 kfree(priv
->rx_skbuff_dma
);
1251 static void free_dma_desc_resources(struct stmmac_priv
*priv
)
1253 /* Release the DMA TX/RX socket buffers */
1254 dma_free_rx_skbufs(priv
);
1255 dma_free_tx_skbufs(priv
);
1257 /* Free DMA regions of consistent memory previously allocated */
1258 if (!priv
->extend_desc
) {
1259 dma_free_coherent(priv
->device
,
1260 DMA_TX_SIZE
* sizeof(struct dma_desc
),
1261 priv
->dma_tx
, priv
->dma_tx_phy
);
1262 dma_free_coherent(priv
->device
,
1263 DMA_RX_SIZE
* sizeof(struct dma_desc
),
1264 priv
->dma_rx
, priv
->dma_rx_phy
);
1266 dma_free_coherent(priv
->device
, DMA_TX_SIZE
*
1267 sizeof(struct dma_extended_desc
),
1268 priv
->dma_etx
, priv
->dma_tx_phy
);
1269 dma_free_coherent(priv
->device
, DMA_RX_SIZE
*
1270 sizeof(struct dma_extended_desc
),
1271 priv
->dma_erx
, priv
->dma_rx_phy
);
1273 kfree(priv
->rx_skbuff_dma
);
1274 kfree(priv
->rx_skbuff
);
1275 kfree(priv
->tx_skbuff_dma
);
1276 kfree(priv
->tx_skbuff
);
1280 * stmmac_dma_operation_mode - HW DMA operation mode
1281 * @priv: driver private structure
1282 * Description: it is used for configuring the DMA operation mode register in
1283 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1285 static void stmmac_dma_operation_mode(struct stmmac_priv
*priv
)
1287 int rxfifosz
= priv
->plat
->rx_fifo_size
;
1289 if (priv
->plat
->force_thresh_dma_mode
)
1290 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, tc
, rxfifosz
);
1291 else if (priv
->plat
->force_sf_dma_mode
|| priv
->plat
->tx_coe
) {
1293 * In case of GMAC, SF mode can be enabled
1294 * to perform the TX COE in HW. This depends on:
1295 * 1) TX COE if actually supported
1296 * 2) There is no bugged Jumbo frame support
1297 * that needs to not insert csum in the TDES.
1299 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, SF_DMA_MODE
, SF_DMA_MODE
,
1301 priv
->xstats
.threshold
= SF_DMA_MODE
;
1303 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, SF_DMA_MODE
,
1308 * stmmac_tx_clean - to manage the transmission completion
1309 * @priv: driver private structure
1310 * Description: it reclaims the transmit resources after transmission completes.
1312 static void stmmac_tx_clean(struct stmmac_priv
*priv
)
1314 unsigned int bytes_compl
= 0, pkts_compl
= 0;
1315 unsigned int entry
= priv
->dirty_tx
;
1317 spin_lock(&priv
->tx_lock
);
1319 priv
->xstats
.tx_clean
++;
1321 while (entry
!= priv
->cur_tx
) {
1322 struct sk_buff
*skb
= priv
->tx_skbuff
[entry
];
1326 if (priv
->extend_desc
)
1327 p
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
1329 p
= priv
->dma_tx
+ entry
;
1331 status
= priv
->hw
->desc
->tx_status(&priv
->dev
->stats
,
1334 /* Check if the descriptor is owned by the DMA */
1335 if (unlikely(status
& tx_dma_own
))
1338 /* Just consider the last segment and ...*/
1339 if (likely(!(status
& tx_not_ls
))) {
1340 /* ... verify the status error condition */
1341 if (unlikely(status
& tx_err
)) {
1342 priv
->dev
->stats
.tx_errors
++;
1344 priv
->dev
->stats
.tx_packets
++;
1345 priv
->xstats
.tx_pkt_n
++;
1347 stmmac_get_tx_hwtstamp(priv
, entry
, skb
);
1350 if (likely(priv
->tx_skbuff_dma
[entry
].buf
)) {
1351 if (priv
->tx_skbuff_dma
[entry
].map_as_page
)
1352 dma_unmap_page(priv
->device
,
1353 priv
->tx_skbuff_dma
[entry
].buf
,
1354 priv
->tx_skbuff_dma
[entry
].len
,
1357 dma_unmap_single(priv
->device
,
1358 priv
->tx_skbuff_dma
[entry
].buf
,
1359 priv
->tx_skbuff_dma
[entry
].len
,
1361 priv
->tx_skbuff_dma
[entry
].buf
= 0;
1362 priv
->tx_skbuff_dma
[entry
].map_as_page
= false;
1364 priv
->hw
->mode
->clean_desc3(priv
, p
);
1365 priv
->tx_skbuff_dma
[entry
].last_segment
= false;
1366 priv
->tx_skbuff_dma
[entry
].is_jumbo
= false;
1368 if (likely(skb
!= NULL
)) {
1370 bytes_compl
+= skb
->len
;
1371 dev_consume_skb_any(skb
);
1372 priv
->tx_skbuff
[entry
] = NULL
;
1375 priv
->hw
->desc
->release_tx_desc(p
, priv
->mode
);
1377 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
1379 priv
->dirty_tx
= entry
;
1381 netdev_completed_queue(priv
->dev
, pkts_compl
, bytes_compl
);
1383 if (unlikely(netif_queue_stopped(priv
->dev
) &&
1384 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH
)) {
1385 netif_tx_lock(priv
->dev
);
1386 if (netif_queue_stopped(priv
->dev
) &&
1387 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH
) {
1388 if (netif_msg_tx_done(priv
))
1389 pr_debug("%s: restart transmit\n", __func__
);
1390 netif_wake_queue(priv
->dev
);
1392 netif_tx_unlock(priv
->dev
);
1395 if ((priv
->eee_enabled
) && (!priv
->tx_path_in_lpi_mode
)) {
1396 stmmac_enable_eee_mode(priv
);
1397 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
1399 spin_unlock(&priv
->tx_lock
);
1402 static inline void stmmac_enable_dma_irq(struct stmmac_priv
*priv
)
1404 priv
->hw
->dma
->enable_dma_irq(priv
->ioaddr
);
1407 static inline void stmmac_disable_dma_irq(struct stmmac_priv
*priv
)
1409 priv
->hw
->dma
->disable_dma_irq(priv
->ioaddr
);
1413 * stmmac_tx_err - to manage the tx error
1414 * @priv: driver private structure
1415 * Description: it cleans the descriptors and restarts the transmission
1416 * in case of transmission errors.
1418 static void stmmac_tx_err(struct stmmac_priv
*priv
)
1421 netif_stop_queue(priv
->dev
);
1423 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1424 dma_free_tx_skbufs(priv
);
1425 for (i
= 0; i
< DMA_TX_SIZE
; i
++)
1426 if (priv
->extend_desc
)
1427 priv
->hw
->desc
->init_tx_desc(&priv
->dma_etx
[i
].basic
,
1429 (i
== DMA_TX_SIZE
- 1));
1431 priv
->hw
->desc
->init_tx_desc(&priv
->dma_tx
[i
],
1433 (i
== DMA_TX_SIZE
- 1));
1436 netdev_reset_queue(priv
->dev
);
1437 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1439 priv
->dev
->stats
.tx_errors
++;
1440 netif_wake_queue(priv
->dev
);
1444 * stmmac_dma_interrupt - DMA ISR
1445 * @priv: driver private structure
1446 * Description: this is the DMA ISR. It is called by the main ISR.
1447 * It calls the dwmac dma routine and schedule poll method in case of some
1450 static void stmmac_dma_interrupt(struct stmmac_priv
*priv
)
1453 int rxfifosz
= priv
->plat
->rx_fifo_size
;
1455 status
= priv
->hw
->dma
->dma_interrupt(priv
->ioaddr
, &priv
->xstats
);
1456 if (likely((status
& handle_rx
)) || (status
& handle_tx
)) {
1457 if (likely(napi_schedule_prep(&priv
->napi
))) {
1458 stmmac_disable_dma_irq(priv
);
1459 __napi_schedule(&priv
->napi
);
1462 if (unlikely(status
& tx_hard_error_bump_tc
)) {
1463 /* Try to bump up the dma threshold on this failure */
1464 if (unlikely(priv
->xstats
.threshold
!= SF_DMA_MODE
) &&
1467 if (priv
->plat
->force_thresh_dma_mode
)
1468 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, tc
,
1471 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
,
1472 SF_DMA_MODE
, rxfifosz
);
1473 priv
->xstats
.threshold
= tc
;
1475 } else if (unlikely(status
== tx_hard_error
))
1476 stmmac_tx_err(priv
);
1480 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1481 * @priv: driver private structure
1482 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1484 static void stmmac_mmc_setup(struct stmmac_priv
*priv
)
1486 unsigned int mode
= MMC_CNTRL_RESET_ON_READ
| MMC_CNTRL_COUNTER_RESET
|
1487 MMC_CNTRL_PRESET
| MMC_CNTRL_FULL_HALF_PRESET
;
1489 dwmac_mmc_intr_all_mask(priv
->ioaddr
);
1491 if (priv
->dma_cap
.rmon
) {
1492 dwmac_mmc_ctrl(priv
->ioaddr
, mode
);
1493 memset(&priv
->mmc
, 0, sizeof(struct stmmac_counters
));
1495 pr_info(" No MAC Management Counters available\n");
1499 * stmmac_get_synopsys_id - return the SYINID.
1500 * @priv: driver private structure
1501 * Description: this simple function is to decode and return the SYINID
1502 * starting from the HW core register.
1504 static u32
stmmac_get_synopsys_id(struct stmmac_priv
*priv
)
1506 u32 hwid
= priv
->hw
->synopsys_uid
;
1508 /* Check Synopsys Id (not available on old chips) */
1510 u32 uid
= ((hwid
& 0x0000ff00) >> 8);
1511 u32 synid
= (hwid
& 0x000000ff);
1513 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1522 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1523 * @priv: driver private structure
1524 * Description: select the Enhanced/Alternate or Normal descriptors.
1525 * In case of Enhanced/Alternate, it checks if the extended descriptors are
1526 * supported by the HW capability register.
1528 static void stmmac_selec_desc_mode(struct stmmac_priv
*priv
)
1530 if (priv
->plat
->enh_desc
) {
1531 pr_info(" Enhanced/Alternate descriptors\n");
1533 /* GMAC older than 3.50 has no extended descriptors */
1534 if (priv
->synopsys_id
>= DWMAC_CORE_3_50
) {
1535 pr_info("\tEnabled extended descriptors\n");
1536 priv
->extend_desc
= 1;
1538 pr_warn("Extended descriptors not supported\n");
1540 priv
->hw
->desc
= &enh_desc_ops
;
1542 pr_info(" Normal descriptors\n");
1543 priv
->hw
->desc
= &ndesc_ops
;
1548 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1549 * @priv: driver private structure
1551 * new GMAC chip generations have a new register to indicate the
1552 * presence of the optional feature/functions.
1553 * This can be also used to override the value passed through the
1554 * platform and necessary for old MAC10/100 and GMAC chips.
1556 static int stmmac_get_hw_features(struct stmmac_priv
*priv
)
1560 if (priv
->hw
->dma
->get_hw_feature
) {
1561 hw_cap
= priv
->hw
->dma
->get_hw_feature(priv
->ioaddr
);
1563 priv
->dma_cap
.mbps_10_100
= (hw_cap
& DMA_HW_FEAT_MIISEL
);
1564 priv
->dma_cap
.mbps_1000
= (hw_cap
& DMA_HW_FEAT_GMIISEL
) >> 1;
1565 priv
->dma_cap
.half_duplex
= (hw_cap
& DMA_HW_FEAT_HDSEL
) >> 2;
1566 priv
->dma_cap
.hash_filter
= (hw_cap
& DMA_HW_FEAT_HASHSEL
) >> 4;
1567 priv
->dma_cap
.multi_addr
= (hw_cap
& DMA_HW_FEAT_ADDMAC
) >> 5;
1568 priv
->dma_cap
.pcs
= (hw_cap
& DMA_HW_FEAT_PCSSEL
) >> 6;
1569 priv
->dma_cap
.sma_mdio
= (hw_cap
& DMA_HW_FEAT_SMASEL
) >> 8;
1570 priv
->dma_cap
.pmt_remote_wake_up
=
1571 (hw_cap
& DMA_HW_FEAT_RWKSEL
) >> 9;
1572 priv
->dma_cap
.pmt_magic_frame
=
1573 (hw_cap
& DMA_HW_FEAT_MGKSEL
) >> 10;
1575 priv
->dma_cap
.rmon
= (hw_cap
& DMA_HW_FEAT_MMCSEL
) >> 11;
1576 /* IEEE 1588-2002 */
1577 priv
->dma_cap
.time_stamp
=
1578 (hw_cap
& DMA_HW_FEAT_TSVER1SEL
) >> 12;
1579 /* IEEE 1588-2008 */
1580 priv
->dma_cap
.atime_stamp
=
1581 (hw_cap
& DMA_HW_FEAT_TSVER2SEL
) >> 13;
1582 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1583 priv
->dma_cap
.eee
= (hw_cap
& DMA_HW_FEAT_EEESEL
) >> 14;
1584 priv
->dma_cap
.av
= (hw_cap
& DMA_HW_FEAT_AVSEL
) >> 15;
1585 /* TX and RX csum */
1586 priv
->dma_cap
.tx_coe
= (hw_cap
& DMA_HW_FEAT_TXCOESEL
) >> 16;
1587 priv
->dma_cap
.rx_coe_type1
=
1588 (hw_cap
& DMA_HW_FEAT_RXTYP1COE
) >> 17;
1589 priv
->dma_cap
.rx_coe_type2
=
1590 (hw_cap
& DMA_HW_FEAT_RXTYP2COE
) >> 18;
1591 priv
->dma_cap
.rxfifo_over_2048
=
1592 (hw_cap
& DMA_HW_FEAT_RXFIFOSIZE
) >> 19;
1593 /* TX and RX number of channels */
1594 priv
->dma_cap
.number_rx_channel
=
1595 (hw_cap
& DMA_HW_FEAT_RXCHCNT
) >> 20;
1596 priv
->dma_cap
.number_tx_channel
=
1597 (hw_cap
& DMA_HW_FEAT_TXCHCNT
) >> 22;
1598 /* Alternate (enhanced) DESC mode */
1599 priv
->dma_cap
.enh_desc
= (hw_cap
& DMA_HW_FEAT_ENHDESSEL
) >> 24;
1606 * stmmac_check_ether_addr - check if the MAC addr is valid
1607 * @priv: driver private structure
1609 * it is to verify if the MAC address is valid, in case of failures it
1610 * generates a random MAC address
1612 static void stmmac_check_ether_addr(struct stmmac_priv
*priv
)
1614 if (!is_valid_ether_addr(priv
->dev
->dev_addr
)) {
1615 priv
->hw
->mac
->get_umac_addr(priv
->hw
,
1616 priv
->dev
->dev_addr
, 0);
1617 if (!is_valid_ether_addr(priv
->dev
->dev_addr
))
1618 eth_hw_addr_random(priv
->dev
);
1619 pr_info("%s: device MAC address %pM\n", priv
->dev
->name
,
1620 priv
->dev
->dev_addr
);
1625 * stmmac_init_dma_engine - DMA init.
1626 * @priv: driver private structure
1628 * It inits the DMA invoking the specific MAC/GMAC callback.
1629 * Some DMA parameters can be passed from the platform;
1630 * in case of these are not passed a default is kept for the MAC or GMAC.
1632 static int stmmac_init_dma_engine(struct stmmac_priv
*priv
)
1634 int pbl
= DEFAULT_DMA_PBL
, fixed_burst
= 0, aal
= 0;
1635 int mixed_burst
= 0;
1639 if (priv
->plat
->dma_cfg
) {
1640 pbl
= priv
->plat
->dma_cfg
->pbl
;
1641 fixed_burst
= priv
->plat
->dma_cfg
->fixed_burst
;
1642 mixed_burst
= priv
->plat
->dma_cfg
->mixed_burst
;
1643 aal
= priv
->plat
->dma_cfg
->aal
;
1646 if (priv
->extend_desc
&& (priv
->mode
== STMMAC_RING_MODE
))
1649 ret
= priv
->hw
->dma
->reset(priv
->ioaddr
);
1651 dev_err(priv
->device
, "Failed to reset the dma\n");
1655 priv
->hw
->dma
->init(priv
->ioaddr
, pbl
, fixed_burst
, mixed_burst
,
1656 aal
, priv
->dma_tx_phy
, priv
->dma_rx_phy
, atds
);
1658 if ((priv
->synopsys_id
>= DWMAC_CORE_3_50
) &&
1659 (priv
->plat
->axi
&& priv
->hw
->dma
->axi
))
1660 priv
->hw
->dma
->axi(priv
->ioaddr
, priv
->plat
->axi
);
1666 * stmmac_tx_timer - mitigation sw timer for tx.
1667 * @data: data pointer
1669 * This is the timer handler to directly invoke the stmmac_tx_clean.
1671 static void stmmac_tx_timer(unsigned long data
)
1673 struct stmmac_priv
*priv
= (struct stmmac_priv
*)data
;
1675 stmmac_tx_clean(priv
);
1679 * stmmac_init_tx_coalesce - init tx mitigation options.
1680 * @priv: driver private structure
1682 * This inits the transmit coalesce parameters: i.e. timer rate,
1683 * timer handler and default threshold used for enabling the
1684 * interrupt on completion bit.
1686 static void stmmac_init_tx_coalesce(struct stmmac_priv
*priv
)
1688 priv
->tx_coal_frames
= STMMAC_TX_FRAMES
;
1689 priv
->tx_coal_timer
= STMMAC_COAL_TX_TIMER
;
1690 init_timer(&priv
->txtimer
);
1691 priv
->txtimer
.expires
= STMMAC_COAL_TIMER(priv
->tx_coal_timer
);
1692 priv
->txtimer
.data
= (unsigned long)priv
;
1693 priv
->txtimer
.function
= stmmac_tx_timer
;
1694 add_timer(&priv
->txtimer
);
1698 * stmmac_hw_setup - setup mac in a usable state.
1699 * @dev : pointer to the device structure.
1701 * this is the main function to setup the HW in a usable state because the
1702 * dma engine is reset, the core registers are configured (e.g. AXI,
1703 * Checksum features, timers). The DMA is ready to start receiving and
1706 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1709 static int stmmac_hw_setup(struct net_device
*dev
, bool init_ptp
)
1711 struct stmmac_priv
*priv
= netdev_priv(dev
);
1714 /* DMA initialization and SW reset */
1715 ret
= stmmac_init_dma_engine(priv
);
1717 pr_err("%s: DMA engine initialization failed\n", __func__
);
1721 /* Copy the MAC addr into the HW */
1722 priv
->hw
->mac
->set_umac_addr(priv
->hw
, dev
->dev_addr
, 0);
1724 /* If required, perform hw setup of the bus. */
1725 if (priv
->plat
->bus_setup
)
1726 priv
->plat
->bus_setup(priv
->ioaddr
);
1728 /* Initialize the MAC Core */
1729 priv
->hw
->mac
->core_init(priv
->hw
, dev
->mtu
);
1731 ret
= priv
->hw
->mac
->rx_ipc(priv
->hw
);
1733 pr_warn(" RX IPC Checksum Offload disabled\n");
1734 priv
->plat
->rx_coe
= STMMAC_RX_COE_NONE
;
1735 priv
->hw
->rx_csum
= 0;
1738 /* Enable the MAC Rx/Tx */
1739 stmmac_set_mac(priv
->ioaddr
, true);
1741 /* Set the HW DMA mode and the COE */
1742 stmmac_dma_operation_mode(priv
);
1744 stmmac_mmc_setup(priv
);
1747 ret
= stmmac_init_ptp(priv
);
1748 if (ret
&& ret
!= -EOPNOTSUPP
)
1749 pr_warn("%s: failed PTP initialisation\n", __func__
);
1752 #ifdef CONFIG_DEBUG_FS
1753 ret
= stmmac_init_fs(dev
);
1755 pr_warn("%s: failed debugFS registration\n", __func__
);
1757 /* Start the ball rolling... */
1758 pr_debug("%s: DMA RX/TX processes started...\n", dev
->name
);
1759 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1760 priv
->hw
->dma
->start_rx(priv
->ioaddr
);
1762 /* Dump DMA/MAC registers */
1763 if (netif_msg_hw(priv
)) {
1764 priv
->hw
->mac
->dump_regs(priv
->hw
);
1765 priv
->hw
->dma
->dump_regs(priv
->ioaddr
);
1767 priv
->tx_lpi_timer
= STMMAC_DEFAULT_TWT_LS
;
1769 if ((priv
->use_riwt
) && (priv
->hw
->dma
->rx_watchdog
)) {
1770 priv
->rx_riwt
= MAX_DMA_RIWT
;
1771 priv
->hw
->dma
->rx_watchdog(priv
->ioaddr
, MAX_DMA_RIWT
);
1774 if (priv
->pcs
&& priv
->hw
->mac
->ctrl_ane
)
1775 priv
->hw
->mac
->ctrl_ane(priv
->hw
, 0);
1781 * stmmac_open - open entry point of the driver
1782 * @dev : pointer to the device structure.
1784 * This function is the open entry point of the driver.
1786 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1789 static int stmmac_open(struct net_device
*dev
)
1791 struct stmmac_priv
*priv
= netdev_priv(dev
);
1794 stmmac_check_ether_addr(priv
);
1796 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
1797 priv
->pcs
!= STMMAC_PCS_RTBI
) {
1798 ret
= stmmac_init_phy(dev
);
1800 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1806 /* Extra statistics */
1807 memset(&priv
->xstats
, 0, sizeof(struct stmmac_extra_stats
));
1808 priv
->xstats
.threshold
= tc
;
1810 priv
->dma_buf_sz
= STMMAC_ALIGN(buf_sz
);
1812 ret
= alloc_dma_desc_resources(priv
);
1814 pr_err("%s: DMA descriptors allocation failed\n", __func__
);
1815 goto dma_desc_error
;
1818 ret
= init_dma_desc_rings(dev
, GFP_KERNEL
);
1820 pr_err("%s: DMA descriptors initialization failed\n", __func__
);
1824 ret
= stmmac_hw_setup(dev
, true);
1826 pr_err("%s: Hw setup failed\n", __func__
);
1830 stmmac_init_tx_coalesce(priv
);
1833 phy_start(priv
->phydev
);
1835 /* Request the IRQ lines */
1836 ret
= request_irq(dev
->irq
, stmmac_interrupt
,
1837 IRQF_SHARED
, dev
->name
, dev
);
1838 if (unlikely(ret
< 0)) {
1839 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1840 __func__
, dev
->irq
, ret
);
1844 /* Request the Wake IRQ in case of another line is used for WoL */
1845 if (priv
->wol_irq
!= dev
->irq
) {
1846 ret
= request_irq(priv
->wol_irq
, stmmac_interrupt
,
1847 IRQF_SHARED
, dev
->name
, dev
);
1848 if (unlikely(ret
< 0)) {
1849 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1850 __func__
, priv
->wol_irq
, ret
);
1855 /* Request the IRQ lines */
1856 if (priv
->lpi_irq
> 0) {
1857 ret
= request_irq(priv
->lpi_irq
, stmmac_interrupt
, IRQF_SHARED
,
1859 if (unlikely(ret
< 0)) {
1860 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1861 __func__
, priv
->lpi_irq
, ret
);
1866 napi_enable(&priv
->napi
);
1867 netif_start_queue(dev
);
1872 if (priv
->wol_irq
!= dev
->irq
)
1873 free_irq(priv
->wol_irq
, dev
);
1875 free_irq(dev
->irq
, dev
);
1878 free_dma_desc_resources(priv
);
1881 phy_disconnect(priv
->phydev
);
1887 * stmmac_release - close entry point of the driver
1888 * @dev : device pointer.
1890 * This is the stop entry point of the driver.
1892 static int stmmac_release(struct net_device
*dev
)
1894 struct stmmac_priv
*priv
= netdev_priv(dev
);
1896 if (priv
->eee_enabled
)
1897 del_timer_sync(&priv
->eee_ctrl_timer
);
1899 /* Stop and disconnect the PHY */
1901 phy_stop(priv
->phydev
);
1902 phy_disconnect(priv
->phydev
);
1903 priv
->phydev
= NULL
;
1906 netif_stop_queue(dev
);
1908 napi_disable(&priv
->napi
);
1910 del_timer_sync(&priv
->txtimer
);
1912 /* Free the IRQ lines */
1913 free_irq(dev
->irq
, dev
);
1914 if (priv
->wol_irq
!= dev
->irq
)
1915 free_irq(priv
->wol_irq
, dev
);
1916 if (priv
->lpi_irq
> 0)
1917 free_irq(priv
->lpi_irq
, dev
);
1919 /* Stop TX/RX DMA and clear the descriptors */
1920 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1921 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
1923 /* Release and free the Rx/Tx resources */
1924 free_dma_desc_resources(priv
);
1926 /* Disable the MAC Rx/Tx */
1927 stmmac_set_mac(priv
->ioaddr
, false);
1929 netif_carrier_off(dev
);
1931 #ifdef CONFIG_DEBUG_FS
1932 stmmac_exit_fs(dev
);
1935 stmmac_release_ptp(priv
);
1941 * stmmac_xmit - Tx entry point of the driver
1942 * @skb : the socket buffer
1943 * @dev : device pointer
1944 * Description : this is the tx entry point of the driver.
1945 * It programs the chain or the ring and supports oversized frames
1948 static netdev_tx_t
stmmac_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1950 struct stmmac_priv
*priv
= netdev_priv(dev
);
1951 unsigned int nopaged_len
= skb_headlen(skb
);
1952 int i
, csum_insertion
= 0, is_jumbo
= 0;
1953 int nfrags
= skb_shinfo(skb
)->nr_frags
;
1954 unsigned int entry
, first_entry
;
1955 struct dma_desc
*desc
, *first
;
1956 unsigned int enh_desc
;
1958 spin_lock(&priv
->tx_lock
);
1960 if (unlikely(stmmac_tx_avail(priv
) < nfrags
+ 1)) {
1961 spin_unlock(&priv
->tx_lock
);
1962 if (!netif_queue_stopped(dev
)) {
1963 netif_stop_queue(dev
);
1964 /* This is a hard error, log it. */
1965 pr_err("%s: Tx Ring full when queue awake\n", __func__
);
1967 return NETDEV_TX_BUSY
;
1970 if (priv
->tx_path_in_lpi_mode
)
1971 stmmac_disable_eee_mode(priv
);
1973 entry
= priv
->cur_tx
;
1974 first_entry
= entry
;
1976 csum_insertion
= (skb
->ip_summed
== CHECKSUM_PARTIAL
);
1978 if (likely(priv
->extend_desc
))
1979 desc
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
1981 desc
= priv
->dma_tx
+ entry
;
1985 priv
->tx_skbuff
[first_entry
] = skb
;
1987 enh_desc
= priv
->plat
->enh_desc
;
1988 /* To program the descriptors according to the size of the frame */
1990 is_jumbo
= priv
->hw
->mode
->is_jumbo_frm(skb
->len
, enh_desc
);
1992 if (unlikely(is_jumbo
)) {
1993 entry
= priv
->hw
->mode
->jumbo_frm(priv
, skb
, csum_insertion
);
1994 if (unlikely(entry
< 0))
1998 for (i
= 0; i
< nfrags
; i
++) {
1999 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2000 int len
= skb_frag_size(frag
);
2001 bool last_segment
= (i
== (nfrags
- 1));
2003 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
2005 if (likely(priv
->extend_desc
))
2006 desc
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
2008 desc
= priv
->dma_tx
+ entry
;
2010 desc
->des2
= skb_frag_dma_map(priv
->device
, frag
, 0, len
,
2012 if (dma_mapping_error(priv
->device
, desc
->des2
))
2013 goto dma_map_err
; /* should reuse desc w/o issues */
2015 priv
->tx_skbuff
[entry
] = NULL
;
2016 priv
->tx_skbuff_dma
[entry
].buf
= desc
->des2
;
2017 priv
->tx_skbuff_dma
[entry
].map_as_page
= true;
2018 priv
->tx_skbuff_dma
[entry
].len
= len
;
2019 priv
->tx_skbuff_dma
[entry
].last_segment
= last_segment
;
2021 /* Prepare the descriptor and set the own bit too */
2022 priv
->hw
->desc
->prepare_tx_desc(desc
, 0, len
, csum_insertion
,
2023 priv
->mode
, 1, last_segment
);
2026 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
2028 priv
->cur_tx
= entry
;
2030 if (netif_msg_pktdata(priv
)) {
2031 pr_debug("%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
2032 __func__
, priv
->cur_tx
, priv
->dirty_tx
, first_entry
,
2033 entry
, first
, nfrags
);
2035 if (priv
->extend_desc
)
2036 stmmac_display_ring((void *)priv
->dma_etx
,
2039 stmmac_display_ring((void *)priv
->dma_tx
,
2042 pr_debug(">>> frame to be transmitted: ");
2043 print_pkt(skb
->data
, skb
->len
);
2046 if (unlikely(stmmac_tx_avail(priv
) <= (MAX_SKB_FRAGS
+ 1))) {
2047 if (netif_msg_hw(priv
))
2048 pr_debug("%s: stop transmitted packets\n", __func__
);
2049 netif_stop_queue(dev
);
2052 dev
->stats
.tx_bytes
+= skb
->len
;
2054 /* According to the coalesce parameter the IC bit for the latest
2055 * segment is reset and the timer re-started to clean the tx status.
2056 * This approach takes care about the fragments: desc is the first
2057 * element in case of no SG.
2059 priv
->tx_count_frames
+= nfrags
+ 1;
2060 if (likely(priv
->tx_coal_frames
> priv
->tx_count_frames
)) {
2061 mod_timer(&priv
->txtimer
,
2062 STMMAC_COAL_TIMER(priv
->tx_coal_timer
));
2064 priv
->tx_count_frames
= 0;
2065 priv
->hw
->desc
->set_tx_ic(desc
);
2066 priv
->xstats
.tx_set_ic_bit
++;
2069 if (!priv
->hwts_tx_en
)
2070 skb_tx_timestamp(skb
);
2072 /* Ready to fill the first descriptor and set the OWN bit w/o any
2073 * problems because all the descriptors are actually ready to be
2074 * passed to the DMA engine.
2076 if (likely(!is_jumbo
)) {
2077 bool last_segment
= (nfrags
== 0);
2079 first
->des2
= dma_map_single(priv
->device
, skb
->data
,
2080 nopaged_len
, DMA_TO_DEVICE
);
2081 if (dma_mapping_error(priv
->device
, first
->des2
))
2084 priv
->tx_skbuff_dma
[first_entry
].buf
= first
->des2
;
2085 priv
->tx_skbuff_dma
[first_entry
].len
= nopaged_len
;
2086 priv
->tx_skbuff_dma
[first_entry
].last_segment
= last_segment
;
2088 if (unlikely((skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) &&
2089 priv
->hwts_tx_en
)) {
2090 /* declare that device is doing timestamping */
2091 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
2092 priv
->hw
->desc
->enable_tx_timestamp(first
);
2095 /* Prepare the first descriptor setting the OWN bit too */
2096 priv
->hw
->desc
->prepare_tx_desc(first
, 1, nopaged_len
,
2097 csum_insertion
, priv
->mode
, 1,
2100 /* The own bit must be the latest setting done when prepare the
2101 * descriptor and then barrier is needed to make sure that
2102 * all is coherent before granting the DMA engine.
2107 netdev_sent_queue(dev
, skb
->len
);
2108 priv
->hw
->dma
->enable_dma_transmission(priv
->ioaddr
);
2110 spin_unlock(&priv
->tx_lock
);
2111 return NETDEV_TX_OK
;
2114 spin_unlock(&priv
->tx_lock
);
2115 dev_err(priv
->device
, "Tx dma map failed\n");
2117 priv
->dev
->stats
.tx_dropped
++;
2118 return NETDEV_TX_OK
;
2121 static void stmmac_rx_vlan(struct net_device
*dev
, struct sk_buff
*skb
)
2123 struct ethhdr
*ehdr
;
2126 if ((dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) ==
2127 NETIF_F_HW_VLAN_CTAG_RX
&&
2128 !__vlan_get_tag(skb
, &vlanid
)) {
2129 /* pop the vlan tag */
2130 ehdr
= (struct ethhdr
*)skb
->data
;
2131 memmove(skb
->data
+ VLAN_HLEN
, ehdr
, ETH_ALEN
* 2);
2132 skb_pull(skb
, VLAN_HLEN
);
2133 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vlanid
);
2139 * stmmac_rx_refill - refill used skb preallocated buffers
2140 * @priv: driver private structure
2141 * Description : this is to reallocate the skb for the reception process
2142 * that is based on zero-copy.
2144 static inline void stmmac_rx_refill(struct stmmac_priv
*priv
)
2146 int bfsize
= priv
->dma_buf_sz
;
2147 unsigned int entry
= priv
->dirty_rx
;
2148 int dirty
= stmmac_rx_dirty(priv
);
2150 while (dirty
-- > 0) {
2153 if (priv
->extend_desc
)
2154 p
= (struct dma_desc
*)(priv
->dma_erx
+ entry
);
2156 p
= priv
->dma_rx
+ entry
;
2158 if (likely(priv
->rx_skbuff
[entry
] == NULL
)) {
2159 struct sk_buff
*skb
;
2161 skb
= netdev_alloc_skb_ip_align(priv
->dev
, bfsize
);
2163 if (unlikely(skb
== NULL
))
2166 priv
->rx_skbuff
[entry
] = skb
;
2167 priv
->rx_skbuff_dma
[entry
] =
2168 dma_map_single(priv
->device
, skb
->data
, bfsize
,
2170 if (dma_mapping_error(priv
->device
,
2171 priv
->rx_skbuff_dma
[entry
])) {
2172 dev_err(priv
->device
, "Rx dma map failed\n");
2176 p
->des2
= priv
->rx_skbuff_dma
[entry
];
2178 priv
->hw
->mode
->refill_desc3(priv
, p
);
2180 if (netif_msg_rx_status(priv
))
2181 pr_debug("\trefill entry #%d\n", entry
);
2184 priv
->hw
->desc
->set_rx_owner(p
);
2187 entry
= STMMAC_GET_ENTRY(entry
, DMA_RX_SIZE
);
2189 priv
->dirty_rx
= entry
;
2193 * stmmac_rx - manage the receive process
2194 * @priv: driver private structure
2195 * @limit: napi bugget.
2196 * Description : this the function called by the napi poll method.
2197 * It gets all the frames inside the ring.
2199 static int stmmac_rx(struct stmmac_priv
*priv
, int limit
)
2201 unsigned int entry
= priv
->cur_rx
;
2202 unsigned int next_entry
;
2203 unsigned int count
= 0;
2204 int coe
= priv
->hw
->rx_csum
;
2206 if (netif_msg_rx_status(priv
)) {
2207 pr_debug("%s: descriptor ring:\n", __func__
);
2208 if (priv
->extend_desc
)
2209 stmmac_display_ring((void *)priv
->dma_erx
,
2212 stmmac_display_ring((void *)priv
->dma_rx
,
2215 while (count
< limit
) {
2219 if (priv
->extend_desc
)
2220 p
= (struct dma_desc
*)(priv
->dma_erx
+ entry
);
2222 p
= priv
->dma_rx
+ entry
;
2224 /* read the status of the incoming frame */
2225 status
= priv
->hw
->desc
->rx_status(&priv
->dev
->stats
,
2227 /* check if managed by the DMA otherwise go ahead */
2228 if (unlikely(status
& dma_own
))
2233 priv
->cur_rx
= STMMAC_GET_ENTRY(priv
->cur_rx
, DMA_RX_SIZE
);
2234 next_entry
= priv
->cur_rx
;
2236 if (priv
->extend_desc
)
2237 prefetch(priv
->dma_erx
+ next_entry
);
2239 prefetch(priv
->dma_rx
+ next_entry
);
2241 if ((priv
->extend_desc
) && (priv
->hw
->desc
->rx_extended_status
))
2242 priv
->hw
->desc
->rx_extended_status(&priv
->dev
->stats
,
2246 if (unlikely(status
== discard_frame
)) {
2247 priv
->dev
->stats
.rx_errors
++;
2248 if (priv
->hwts_rx_en
&& !priv
->extend_desc
) {
2249 /* DESC2 & DESC3 will be overwitten by device
2250 * with timestamp value, hence reinitialize
2251 * them in stmmac_rx_refill() function so that
2252 * device can reuse it.
2254 priv
->rx_skbuff
[entry
] = NULL
;
2255 dma_unmap_single(priv
->device
,
2256 priv
->rx_skbuff_dma
[entry
],
2261 struct sk_buff
*skb
;
2264 frame_len
= priv
->hw
->desc
->get_rx_frame_len(p
, coe
);
2266 /* check if frame_len fits the preallocated memory */
2267 if (frame_len
> priv
->dma_buf_sz
) {
2268 priv
->dev
->stats
.rx_length_errors
++;
2272 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2273 * Type frames (LLC/LLC-SNAP)
2275 if (unlikely(status
!= llc_snap
))
2276 frame_len
-= ETH_FCS_LEN
;
2278 if (netif_msg_rx_status(priv
)) {
2279 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2281 if (frame_len
> ETH_FRAME_LEN
)
2282 pr_debug("\tframe size %d, COE: %d\n",
2285 skb
= priv
->rx_skbuff
[entry
];
2286 if (unlikely(!skb
)) {
2287 pr_err("%s: Inconsistent Rx descriptor chain\n",
2289 priv
->dev
->stats
.rx_dropped
++;
2292 prefetch(skb
->data
- NET_IP_ALIGN
);
2293 priv
->rx_skbuff
[entry
] = NULL
;
2295 stmmac_get_rx_hwtstamp(priv
, entry
, skb
);
2297 skb_put(skb
, frame_len
);
2298 dma_unmap_single(priv
->device
,
2299 priv
->rx_skbuff_dma
[entry
],
2300 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
2302 if (netif_msg_pktdata(priv
)) {
2303 pr_debug("frame received (%dbytes)", frame_len
);
2304 print_pkt(skb
->data
, frame_len
);
2307 stmmac_rx_vlan(priv
->dev
, skb
);
2309 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
2312 skb_checksum_none_assert(skb
);
2314 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2316 napi_gro_receive(&priv
->napi
, skb
);
2318 priv
->dev
->stats
.rx_packets
++;
2319 priv
->dev
->stats
.rx_bytes
+= frame_len
;
2324 stmmac_rx_refill(priv
);
2326 priv
->xstats
.rx_pkt_n
+= count
;
2332 * stmmac_poll - stmmac poll method (NAPI)
2333 * @napi : pointer to the napi structure.
2334 * @budget : maximum number of packets that the current CPU can receive from
2337 * To look at the incoming frames and clear the tx resources.
2339 static int stmmac_poll(struct napi_struct
*napi
, int budget
)
2341 struct stmmac_priv
*priv
= container_of(napi
, struct stmmac_priv
, napi
);
2344 priv
->xstats
.napi_poll
++;
2345 stmmac_tx_clean(priv
);
2347 work_done
= stmmac_rx(priv
, budget
);
2348 if (work_done
< budget
) {
2349 napi_complete(napi
);
2350 stmmac_enable_dma_irq(priv
);
2357 * @dev : Pointer to net device structure
2358 * Description: this function is called when a packet transmission fails to
2359 * complete within a reasonable time. The driver will mark the error in the
2360 * netdev structure and arrange for the device to be reset to a sane state
2361 * in order to transmit a new packet.
2363 static void stmmac_tx_timeout(struct net_device
*dev
)
2365 struct stmmac_priv
*priv
= netdev_priv(dev
);
2367 /* Clear Tx resources and restart transmitting again */
2368 stmmac_tx_err(priv
);
2372 * stmmac_set_rx_mode - entry point for multicast addressing
2373 * @dev : pointer to the device structure
2375 * This function is a driver entry point which gets called by the kernel
2376 * whenever multicast addresses must be enabled/disabled.
2380 static void stmmac_set_rx_mode(struct net_device
*dev
)
2382 struct stmmac_priv
*priv
= netdev_priv(dev
);
2384 priv
->hw
->mac
->set_filter(priv
->hw
, dev
);
2388 * stmmac_change_mtu - entry point to change MTU size for the device.
2389 * @dev : device pointer.
2390 * @new_mtu : the new MTU size for the device.
2391 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2392 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2393 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2395 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2398 static int stmmac_change_mtu(struct net_device
*dev
, int new_mtu
)
2400 struct stmmac_priv
*priv
= netdev_priv(dev
);
2403 if (netif_running(dev
)) {
2404 pr_err("%s: must be stopped to change its MTU\n", dev
->name
);
2408 if (priv
->plat
->enh_desc
)
2409 max_mtu
= JUMBO_LEN
;
2411 max_mtu
= SKB_MAX_HEAD(NET_SKB_PAD
+ NET_IP_ALIGN
);
2413 if (priv
->plat
->maxmtu
< max_mtu
)
2414 max_mtu
= priv
->plat
->maxmtu
;
2416 if ((new_mtu
< 46) || (new_mtu
> max_mtu
)) {
2417 pr_err("%s: invalid MTU, max MTU is: %d\n", dev
->name
, max_mtu
);
2422 netdev_update_features(dev
);
2427 static netdev_features_t
stmmac_fix_features(struct net_device
*dev
,
2428 netdev_features_t features
)
2430 struct stmmac_priv
*priv
= netdev_priv(dev
);
2432 if (priv
->plat
->rx_coe
== STMMAC_RX_COE_NONE
)
2433 features
&= ~NETIF_F_RXCSUM
;
2435 if (!priv
->plat
->tx_coe
)
2436 features
&= ~NETIF_F_CSUM_MASK
;
2438 /* Some GMAC devices have a bugged Jumbo frame support that
2439 * needs to have the Tx COE disabled for oversized frames
2440 * (due to limited buffer sizes). In this case we disable
2441 * the TX csum insertionin the TDES and not use SF.
2443 if (priv
->plat
->bugged_jumbo
&& (dev
->mtu
> ETH_DATA_LEN
))
2444 features
&= ~NETIF_F_CSUM_MASK
;
2449 static int stmmac_set_features(struct net_device
*netdev
,
2450 netdev_features_t features
)
2452 struct stmmac_priv
*priv
= netdev_priv(netdev
);
2454 /* Keep the COE Type in case of csum is supporting */
2455 if (features
& NETIF_F_RXCSUM
)
2456 priv
->hw
->rx_csum
= priv
->plat
->rx_coe
;
2458 priv
->hw
->rx_csum
= 0;
2459 /* No check needed because rx_coe has been set before and it will be
2460 * fixed in case of issue.
2462 priv
->hw
->mac
->rx_ipc(priv
->hw
);
2468 * stmmac_interrupt - main ISR
2469 * @irq: interrupt number.
2470 * @dev_id: to pass the net device pointer.
2471 * Description: this is the main driver interrupt service routine.
2473 * o DMA service routine (to manage incoming frame reception and transmission
2475 * o Core interrupts to manage: remote wake-up, management counter, LPI
2478 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
)
2480 struct net_device
*dev
= (struct net_device
*)dev_id
;
2481 struct stmmac_priv
*priv
= netdev_priv(dev
);
2484 pm_wakeup_event(priv
->device
, 0);
2486 if (unlikely(!dev
)) {
2487 pr_err("%s: invalid dev pointer\n", __func__
);
2491 /* To handle GMAC own interrupts */
2492 if (priv
->plat
->has_gmac
) {
2493 int status
= priv
->hw
->mac
->host_irq_status(priv
->hw
,
2495 if (unlikely(status
)) {
2496 /* For LPI we need to save the tx status */
2497 if (status
& CORE_IRQ_TX_PATH_IN_LPI_MODE
)
2498 priv
->tx_path_in_lpi_mode
= true;
2499 if (status
& CORE_IRQ_TX_PATH_EXIT_LPI_MODE
)
2500 priv
->tx_path_in_lpi_mode
= false;
2504 /* To handle DMA interrupts */
2505 stmmac_dma_interrupt(priv
);
2510 #ifdef CONFIG_NET_POLL_CONTROLLER
2511 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2512 * to allow network I/O with interrupts disabled.
2514 static void stmmac_poll_controller(struct net_device
*dev
)
2516 disable_irq(dev
->irq
);
2517 stmmac_interrupt(dev
->irq
, dev
);
2518 enable_irq(dev
->irq
);
2523 * stmmac_ioctl - Entry point for the Ioctl
2524 * @dev: Device pointer.
2525 * @rq: An IOCTL specefic structure, that can contain a pointer to
2526 * a proprietary structure used to pass information to the driver.
2527 * @cmd: IOCTL command
2529 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2531 static int stmmac_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2533 struct stmmac_priv
*priv
= netdev_priv(dev
);
2534 int ret
= -EOPNOTSUPP
;
2536 if (!netif_running(dev
))
2545 ret
= phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
2548 ret
= stmmac_hwtstamp_ioctl(dev
, rq
);
2557 #ifdef CONFIG_DEBUG_FS
2558 static struct dentry
*stmmac_fs_dir
;
2560 static void sysfs_display_ring(void *head
, int size
, int extend_desc
,
2561 struct seq_file
*seq
)
2564 struct dma_extended_desc
*ep
= (struct dma_extended_desc
*)head
;
2565 struct dma_desc
*p
= (struct dma_desc
*)head
;
2567 for (i
= 0; i
< size
; i
++) {
2571 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2572 i
, (unsigned int)virt_to_phys(ep
),
2573 (unsigned int)x
, (unsigned int)(x
>> 32),
2574 ep
->basic
.des2
, ep
->basic
.des3
);
2578 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2579 i
, (unsigned int)virt_to_phys(ep
),
2580 (unsigned int)x
, (unsigned int)(x
>> 32),
2584 seq_printf(seq
, "\n");
2588 static int stmmac_sysfs_ring_read(struct seq_file
*seq
, void *v
)
2590 struct net_device
*dev
= seq
->private;
2591 struct stmmac_priv
*priv
= netdev_priv(dev
);
2593 if (priv
->extend_desc
) {
2594 seq_printf(seq
, "Extended RX descriptor ring:\n");
2595 sysfs_display_ring((void *)priv
->dma_erx
, DMA_RX_SIZE
, 1, seq
);
2596 seq_printf(seq
, "Extended TX descriptor ring:\n");
2597 sysfs_display_ring((void *)priv
->dma_etx
, DMA_TX_SIZE
, 1, seq
);
2599 seq_printf(seq
, "RX descriptor ring:\n");
2600 sysfs_display_ring((void *)priv
->dma_rx
, DMA_RX_SIZE
, 0, seq
);
2601 seq_printf(seq
, "TX descriptor ring:\n");
2602 sysfs_display_ring((void *)priv
->dma_tx
, DMA_TX_SIZE
, 0, seq
);
2608 static int stmmac_sysfs_ring_open(struct inode
*inode
, struct file
*file
)
2610 return single_open(file
, stmmac_sysfs_ring_read
, inode
->i_private
);
2613 static const struct file_operations stmmac_rings_status_fops
= {
2614 .owner
= THIS_MODULE
,
2615 .open
= stmmac_sysfs_ring_open
,
2617 .llseek
= seq_lseek
,
2618 .release
= single_release
,
2621 static int stmmac_sysfs_dma_cap_read(struct seq_file
*seq
, void *v
)
2623 struct net_device
*dev
= seq
->private;
2624 struct stmmac_priv
*priv
= netdev_priv(dev
);
2626 if (!priv
->hw_cap_support
) {
2627 seq_printf(seq
, "DMA HW features not supported\n");
2631 seq_printf(seq
, "==============================\n");
2632 seq_printf(seq
, "\tDMA HW features\n");
2633 seq_printf(seq
, "==============================\n");
2635 seq_printf(seq
, "\t10/100 Mbps %s\n",
2636 (priv
->dma_cap
.mbps_10_100
) ? "Y" : "N");
2637 seq_printf(seq
, "\t1000 Mbps %s\n",
2638 (priv
->dma_cap
.mbps_1000
) ? "Y" : "N");
2639 seq_printf(seq
, "\tHalf duple %s\n",
2640 (priv
->dma_cap
.half_duplex
) ? "Y" : "N");
2641 seq_printf(seq
, "\tHash Filter: %s\n",
2642 (priv
->dma_cap
.hash_filter
) ? "Y" : "N");
2643 seq_printf(seq
, "\tMultiple MAC address registers: %s\n",
2644 (priv
->dma_cap
.multi_addr
) ? "Y" : "N");
2645 seq_printf(seq
, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2646 (priv
->dma_cap
.pcs
) ? "Y" : "N");
2647 seq_printf(seq
, "\tSMA (MDIO) Interface: %s\n",
2648 (priv
->dma_cap
.sma_mdio
) ? "Y" : "N");
2649 seq_printf(seq
, "\tPMT Remote wake up: %s\n",
2650 (priv
->dma_cap
.pmt_remote_wake_up
) ? "Y" : "N");
2651 seq_printf(seq
, "\tPMT Magic Frame: %s\n",
2652 (priv
->dma_cap
.pmt_magic_frame
) ? "Y" : "N");
2653 seq_printf(seq
, "\tRMON module: %s\n",
2654 (priv
->dma_cap
.rmon
) ? "Y" : "N");
2655 seq_printf(seq
, "\tIEEE 1588-2002 Time Stamp: %s\n",
2656 (priv
->dma_cap
.time_stamp
) ? "Y" : "N");
2657 seq_printf(seq
, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2658 (priv
->dma_cap
.atime_stamp
) ? "Y" : "N");
2659 seq_printf(seq
, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2660 (priv
->dma_cap
.eee
) ? "Y" : "N");
2661 seq_printf(seq
, "\tAV features: %s\n", (priv
->dma_cap
.av
) ? "Y" : "N");
2662 seq_printf(seq
, "\tChecksum Offload in TX: %s\n",
2663 (priv
->dma_cap
.tx_coe
) ? "Y" : "N");
2664 seq_printf(seq
, "\tIP Checksum Offload (type1) in RX: %s\n",
2665 (priv
->dma_cap
.rx_coe_type1
) ? "Y" : "N");
2666 seq_printf(seq
, "\tIP Checksum Offload (type2) in RX: %s\n",
2667 (priv
->dma_cap
.rx_coe_type2
) ? "Y" : "N");
2668 seq_printf(seq
, "\tRXFIFO > 2048bytes: %s\n",
2669 (priv
->dma_cap
.rxfifo_over_2048
) ? "Y" : "N");
2670 seq_printf(seq
, "\tNumber of Additional RX channel: %d\n",
2671 priv
->dma_cap
.number_rx_channel
);
2672 seq_printf(seq
, "\tNumber of Additional TX channel: %d\n",
2673 priv
->dma_cap
.number_tx_channel
);
2674 seq_printf(seq
, "\tEnhanced descriptors: %s\n",
2675 (priv
->dma_cap
.enh_desc
) ? "Y" : "N");
2680 static int stmmac_sysfs_dma_cap_open(struct inode
*inode
, struct file
*file
)
2682 return single_open(file
, stmmac_sysfs_dma_cap_read
, inode
->i_private
);
2685 static const struct file_operations stmmac_dma_cap_fops
= {
2686 .owner
= THIS_MODULE
,
2687 .open
= stmmac_sysfs_dma_cap_open
,
2689 .llseek
= seq_lseek
,
2690 .release
= single_release
,
2693 static int stmmac_init_fs(struct net_device
*dev
)
2695 struct stmmac_priv
*priv
= netdev_priv(dev
);
2697 /* Create per netdev entries */
2698 priv
->dbgfs_dir
= debugfs_create_dir(dev
->name
, stmmac_fs_dir
);
2700 if (!priv
->dbgfs_dir
|| IS_ERR(priv
->dbgfs_dir
)) {
2701 pr_err("ERROR %s/%s, debugfs create directory failed\n",
2702 STMMAC_RESOURCE_NAME
, dev
->name
);
2707 /* Entry to report DMA RX/TX rings */
2708 priv
->dbgfs_rings_status
=
2709 debugfs_create_file("descriptors_status", S_IRUGO
,
2710 priv
->dbgfs_dir
, dev
,
2711 &stmmac_rings_status_fops
);
2713 if (!priv
->dbgfs_rings_status
|| IS_ERR(priv
->dbgfs_rings_status
)) {
2714 pr_info("ERROR creating stmmac ring debugfs file\n");
2715 debugfs_remove_recursive(priv
->dbgfs_dir
);
2720 /* Entry to report the DMA HW features */
2721 priv
->dbgfs_dma_cap
= debugfs_create_file("dma_cap", S_IRUGO
,
2723 dev
, &stmmac_dma_cap_fops
);
2725 if (!priv
->dbgfs_dma_cap
|| IS_ERR(priv
->dbgfs_dma_cap
)) {
2726 pr_info("ERROR creating stmmac MMC debugfs file\n");
2727 debugfs_remove_recursive(priv
->dbgfs_dir
);
2735 static void stmmac_exit_fs(struct net_device
*dev
)
2737 struct stmmac_priv
*priv
= netdev_priv(dev
);
2739 debugfs_remove_recursive(priv
->dbgfs_dir
);
2741 #endif /* CONFIG_DEBUG_FS */
2743 static const struct net_device_ops stmmac_netdev_ops
= {
2744 .ndo_open
= stmmac_open
,
2745 .ndo_start_xmit
= stmmac_xmit
,
2746 .ndo_stop
= stmmac_release
,
2747 .ndo_change_mtu
= stmmac_change_mtu
,
2748 .ndo_fix_features
= stmmac_fix_features
,
2749 .ndo_set_features
= stmmac_set_features
,
2750 .ndo_set_rx_mode
= stmmac_set_rx_mode
,
2751 .ndo_tx_timeout
= stmmac_tx_timeout
,
2752 .ndo_do_ioctl
= stmmac_ioctl
,
2753 #ifdef CONFIG_NET_POLL_CONTROLLER
2754 .ndo_poll_controller
= stmmac_poll_controller
,
2756 .ndo_set_mac_address
= eth_mac_addr
,
2760 * stmmac_hw_init - Init the MAC device
2761 * @priv: driver private structure
2762 * Description: this function is to configure the MAC device according to
2763 * some platform parameters or the HW capability register. It prepares the
2764 * driver to use either ring or chain modes and to setup either enhanced or
2765 * normal descriptors.
2767 static int stmmac_hw_init(struct stmmac_priv
*priv
)
2769 struct mac_device_info
*mac
;
2771 /* Identify the MAC HW device */
2772 if (priv
->plat
->has_gmac
) {
2773 priv
->dev
->priv_flags
|= IFF_UNICAST_FLT
;
2774 mac
= dwmac1000_setup(priv
->ioaddr
,
2775 priv
->plat
->multicast_filter_bins
,
2776 priv
->plat
->unicast_filter_entries
);
2778 mac
= dwmac100_setup(priv
->ioaddr
);
2785 /* Get and dump the chip ID */
2786 priv
->synopsys_id
= stmmac_get_synopsys_id(priv
);
2788 /* To use the chained or ring mode */
2790 priv
->hw
->mode
= &chain_mode_ops
;
2791 pr_info(" Chain mode enabled\n");
2792 priv
->mode
= STMMAC_CHAIN_MODE
;
2794 priv
->hw
->mode
= &ring_mode_ops
;
2795 pr_info(" Ring mode enabled\n");
2796 priv
->mode
= STMMAC_RING_MODE
;
2799 /* Get the HW capability (new GMAC newer than 3.50a) */
2800 priv
->hw_cap_support
= stmmac_get_hw_features(priv
);
2801 if (priv
->hw_cap_support
) {
2802 pr_info(" DMA HW capability register supported");
2804 /* We can override some gmac/dma configuration fields: e.g.
2805 * enh_desc, tx_coe (e.g. that are passed through the
2806 * platform) with the values from the HW capability
2807 * register (if supported).
2809 priv
->plat
->enh_desc
= priv
->dma_cap
.enh_desc
;
2810 priv
->plat
->pmt
= priv
->dma_cap
.pmt_remote_wake_up
;
2812 /* TXCOE doesn't work in thresh DMA mode */
2813 if (priv
->plat
->force_thresh_dma_mode
)
2814 priv
->plat
->tx_coe
= 0;
2816 priv
->plat
->tx_coe
= priv
->dma_cap
.tx_coe
;
2818 if (priv
->dma_cap
.rx_coe_type2
)
2819 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE2
;
2820 else if (priv
->dma_cap
.rx_coe_type1
)
2821 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE1
;
2824 pr_info(" No HW DMA feature register supported");
2826 /* To use alternate (extended) or normal descriptor structures */
2827 stmmac_selec_desc_mode(priv
);
2829 if (priv
->plat
->rx_coe
) {
2830 priv
->hw
->rx_csum
= priv
->plat
->rx_coe
;
2831 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2832 priv
->plat
->rx_coe
);
2834 if (priv
->plat
->tx_coe
)
2835 pr_info(" TX Checksum insertion supported\n");
2837 if (priv
->plat
->pmt
) {
2838 pr_info(" Wake-Up On Lan supported\n");
2839 device_set_wakeup_capable(priv
->device
, 1);
2847 * @device: device pointer
2848 * @plat_dat: platform data pointer
2849 * @res: stmmac resource pointer
2850 * Description: this is the main probe function used to
2851 * call the alloc_etherdev, allocate the priv structure.
2853 * returns 0 on success, otherwise errno.
2855 int stmmac_dvr_probe(struct device
*device
,
2856 struct plat_stmmacenet_data
*plat_dat
,
2857 struct stmmac_resources
*res
)
2860 struct net_device
*ndev
= NULL
;
2861 struct stmmac_priv
*priv
;
2863 ndev
= alloc_etherdev(sizeof(struct stmmac_priv
));
2867 SET_NETDEV_DEV(ndev
, device
);
2869 priv
= netdev_priv(ndev
);
2870 priv
->device
= device
;
2873 stmmac_set_ethtool_ops(ndev
);
2874 priv
->pause
= pause
;
2875 priv
->plat
= plat_dat
;
2876 priv
->ioaddr
= res
->addr
;
2877 priv
->dev
->base_addr
= (unsigned long)res
->addr
;
2879 priv
->dev
->irq
= res
->irq
;
2880 priv
->wol_irq
= res
->wol_irq
;
2881 priv
->lpi_irq
= res
->lpi_irq
;
2884 memcpy(priv
->dev
->dev_addr
, res
->mac
, ETH_ALEN
);
2886 dev_set_drvdata(device
, priv
->dev
);
2888 /* Verify driver arguments */
2889 stmmac_verify_args();
2891 /* Override with kernel parameters if supplied XXX CRS XXX
2892 * this needs to have multiple instances
2894 if ((phyaddr
>= 0) && (phyaddr
<= 31))
2895 priv
->plat
->phy_addr
= phyaddr
;
2897 priv
->stmmac_clk
= devm_clk_get(priv
->device
, STMMAC_RESOURCE_NAME
);
2898 if (IS_ERR(priv
->stmmac_clk
)) {
2899 dev_warn(priv
->device
, "%s: warning: cannot get CSR clock\n",
2901 /* If failed to obtain stmmac_clk and specific clk_csr value
2902 * is NOT passed from the platform, probe fail.
2904 if (!priv
->plat
->clk_csr
) {
2905 ret
= PTR_ERR(priv
->stmmac_clk
);
2908 priv
->stmmac_clk
= NULL
;
2911 clk_prepare_enable(priv
->stmmac_clk
);
2913 priv
->pclk
= devm_clk_get(priv
->device
, "pclk");
2914 if (IS_ERR(priv
->pclk
)) {
2915 if (PTR_ERR(priv
->pclk
) == -EPROBE_DEFER
) {
2916 ret
= -EPROBE_DEFER
;
2917 goto error_pclk_get
;
2921 clk_prepare_enable(priv
->pclk
);
2923 priv
->stmmac_rst
= devm_reset_control_get(priv
->device
,
2924 STMMAC_RESOURCE_NAME
);
2925 if (IS_ERR(priv
->stmmac_rst
)) {
2926 if (PTR_ERR(priv
->stmmac_rst
) == -EPROBE_DEFER
) {
2927 ret
= -EPROBE_DEFER
;
2930 dev_info(priv
->device
, "no reset control found\n");
2931 priv
->stmmac_rst
= NULL
;
2933 if (priv
->stmmac_rst
)
2934 reset_control_deassert(priv
->stmmac_rst
);
2936 /* Init MAC and get the capabilities */
2937 ret
= stmmac_hw_init(priv
);
2941 ndev
->netdev_ops
= &stmmac_netdev_ops
;
2943 ndev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
2945 ndev
->features
|= ndev
->hw_features
| NETIF_F_HIGHDMA
;
2946 ndev
->watchdog_timeo
= msecs_to_jiffies(watchdog
);
2947 #ifdef STMMAC_VLAN_TAG_USED
2948 /* Both mac100 and gmac support receive VLAN tag detection */
2949 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_RX
;
2951 priv
->msg_enable
= netif_msg_init(debug
, default_msg_level
);
2954 priv
->flow_ctrl
= FLOW_AUTO
; /* RX/TX pause on */
2956 /* Rx Watchdog is available in the COREs newer than the 3.40.
2957 * In some case, for example on bugged HW this feature
2958 * has to be disable and this can be done by passing the
2959 * riwt_off field from the platform.
2961 if ((priv
->synopsys_id
>= DWMAC_CORE_3_50
) && (!priv
->plat
->riwt_off
)) {
2963 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2966 netif_napi_add(ndev
, &priv
->napi
, stmmac_poll
, 64);
2968 spin_lock_init(&priv
->lock
);
2969 spin_lock_init(&priv
->tx_lock
);
2971 ret
= register_netdev(ndev
);
2973 pr_err("%s: ERROR %i registering the device\n", __func__
, ret
);
2974 goto error_netdev_register
;
2977 /* If a specific clk_csr value is passed from the platform
2978 * this means that the CSR Clock Range selection cannot be
2979 * changed at run-time and it is fixed. Viceversa the driver'll try to
2980 * set the MDC clock dynamically according to the csr actual
2983 if (!priv
->plat
->clk_csr
)
2984 stmmac_clk_csr_set(priv
);
2986 priv
->clk_csr
= priv
->plat
->clk_csr
;
2988 stmmac_check_pcs_mode(priv
);
2990 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
2991 priv
->pcs
!= STMMAC_PCS_RTBI
) {
2992 /* MDIO bus Registration */
2993 ret
= stmmac_mdio_register(ndev
);
2995 pr_debug("%s: MDIO bus (id: %d) registration failed",
2996 __func__
, priv
->plat
->bus_id
);
2997 goto error_mdio_register
;
3003 error_mdio_register
:
3004 unregister_netdev(ndev
);
3005 error_netdev_register
:
3006 netif_napi_del(&priv
->napi
);
3008 clk_disable_unprepare(priv
->pclk
);
3010 clk_disable_unprepare(priv
->stmmac_clk
);
3016 EXPORT_SYMBOL_GPL(stmmac_dvr_probe
);
3020 * @ndev: net device pointer
3021 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3022 * changes the link status, releases the DMA descriptor rings.
3024 int stmmac_dvr_remove(struct net_device
*ndev
)
3026 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3028 pr_info("%s:\n\tremoving driver", __func__
);
3030 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
3031 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
3033 stmmac_set_mac(priv
->ioaddr
, false);
3034 netif_carrier_off(ndev
);
3035 unregister_netdev(ndev
);
3036 if (priv
->stmmac_rst
)
3037 reset_control_assert(priv
->stmmac_rst
);
3038 clk_disable_unprepare(priv
->pclk
);
3039 clk_disable_unprepare(priv
->stmmac_clk
);
3040 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
3041 priv
->pcs
!= STMMAC_PCS_RTBI
)
3042 stmmac_mdio_unregister(ndev
);
3047 EXPORT_SYMBOL_GPL(stmmac_dvr_remove
);
3050 * stmmac_suspend - suspend callback
3051 * @ndev: net device pointer
3052 * Description: this is the function to suspend the device and it is called
3053 * by the platform driver to stop the network queue, release the resources,
3054 * program the PMT register (for WoL), clean and release driver resources.
3056 int stmmac_suspend(struct net_device
*ndev
)
3058 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3059 unsigned long flags
;
3061 if (!ndev
|| !netif_running(ndev
))
3065 phy_stop(priv
->phydev
);
3067 spin_lock_irqsave(&priv
->lock
, flags
);
3069 netif_device_detach(ndev
);
3070 netif_stop_queue(ndev
);
3072 napi_disable(&priv
->napi
);
3074 /* Stop TX/RX DMA */
3075 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
3076 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
3078 /* Enable Power down mode by programming the PMT regs */
3079 if (device_may_wakeup(priv
->device
)) {
3080 priv
->hw
->mac
->pmt(priv
->hw
, priv
->wolopts
);
3083 stmmac_set_mac(priv
->ioaddr
, false);
3084 pinctrl_pm_select_sleep_state(priv
->device
);
3085 /* Disable clock in case of PWM is off */
3086 clk_disable(priv
->pclk
);
3087 clk_disable(priv
->stmmac_clk
);
3089 spin_unlock_irqrestore(&priv
->lock
, flags
);
3093 priv
->oldduplex
= -1;
3096 EXPORT_SYMBOL_GPL(stmmac_suspend
);
3099 * stmmac_resume - resume callback
3100 * @ndev: net device pointer
3101 * Description: when resume this function is invoked to setup the DMA and CORE
3102 * in a usable state.
3104 int stmmac_resume(struct net_device
*ndev
)
3106 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3107 unsigned long flags
;
3109 if (!netif_running(ndev
))
3112 spin_lock_irqsave(&priv
->lock
, flags
);
3114 /* Power Down bit, into the PM register, is cleared
3115 * automatically as soon as a magic packet or a Wake-up frame
3116 * is received. Anyway, it's better to manually clear
3117 * this bit because it can generate problems while resuming
3118 * from another devices (e.g. serial console).
3120 if (device_may_wakeup(priv
->device
)) {
3121 priv
->hw
->mac
->pmt(priv
->hw
, 0);
3124 pinctrl_pm_select_default_state(priv
->device
);
3125 /* enable the clk prevously disabled */
3126 clk_enable(priv
->stmmac_clk
);
3127 clk_enable(priv
->pclk
);
3128 /* reset the phy so that it's ready */
3130 stmmac_mdio_reset(priv
->mii
);
3133 netif_device_attach(ndev
);
3139 stmmac_clear_descriptors(priv
);
3141 stmmac_hw_setup(ndev
, false);
3142 stmmac_init_tx_coalesce(priv
);
3143 stmmac_set_rx_mode(ndev
);
3145 napi_enable(&priv
->napi
);
3147 netif_start_queue(ndev
);
3149 spin_unlock_irqrestore(&priv
->lock
, flags
);
3152 phy_start(priv
->phydev
);
3156 EXPORT_SYMBOL_GPL(stmmac_resume
);
3159 static int __init
stmmac_cmdline_opt(char *str
)
3165 while ((opt
= strsep(&str
, ",")) != NULL
) {
3166 if (!strncmp(opt
, "debug:", 6)) {
3167 if (kstrtoint(opt
+ 6, 0, &debug
))
3169 } else if (!strncmp(opt
, "phyaddr:", 8)) {
3170 if (kstrtoint(opt
+ 8, 0, &phyaddr
))
3172 } else if (!strncmp(opt
, "buf_sz:", 7)) {
3173 if (kstrtoint(opt
+ 7, 0, &buf_sz
))
3175 } else if (!strncmp(opt
, "tc:", 3)) {
3176 if (kstrtoint(opt
+ 3, 0, &tc
))
3178 } else if (!strncmp(opt
, "watchdog:", 9)) {
3179 if (kstrtoint(opt
+ 9, 0, &watchdog
))
3181 } else if (!strncmp(opt
, "flow_ctrl:", 10)) {
3182 if (kstrtoint(opt
+ 10, 0, &flow_ctrl
))
3184 } else if (!strncmp(opt
, "pause:", 6)) {
3185 if (kstrtoint(opt
+ 6, 0, &pause
))
3187 } else if (!strncmp(opt
, "eee_timer:", 10)) {
3188 if (kstrtoint(opt
+ 10, 0, &eee_timer
))
3190 } else if (!strncmp(opt
, "chain_mode:", 11)) {
3191 if (kstrtoint(opt
+ 11, 0, &chain_mode
))
3198 pr_err("%s: ERROR broken module parameter conversion", __func__
);
3202 __setup("stmmaceth=", stmmac_cmdline_opt
);
3205 static int __init
stmmac_init(void)
3207 #ifdef CONFIG_DEBUG_FS
3208 /* Create debugfs main directory if it doesn't exist yet */
3209 if (!stmmac_fs_dir
) {
3210 stmmac_fs_dir
= debugfs_create_dir(STMMAC_RESOURCE_NAME
, NULL
);
3212 if (!stmmac_fs_dir
|| IS_ERR(stmmac_fs_dir
)) {
3213 pr_err("ERROR %s, debugfs create directory failed\n",
3214 STMMAC_RESOURCE_NAME
);
3224 static void __exit
stmmac_exit(void)
3226 #ifdef CONFIG_DEBUG_FS
3227 debugfs_remove_recursive(stmmac_fs_dir
);
3231 module_init(stmmac_init
)
3232 module_exit(stmmac_exit
)
3234 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3235 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3236 MODULE_LICENSE("GPL");