1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/clk.h>
32 #include <linux/kernel.h>
33 #include <linux/interrupt.h>
35 #include <linux/tcp.h>
36 #include <linux/skbuff.h>
37 #include <linux/ethtool.h>
38 #include <linux/if_ether.h>
39 #include <linux/crc32.h>
40 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/slab.h>
45 #include <linux/prefetch.h>
46 #include <linux/pinctrl/consumer.h>
47 #ifdef CONFIG_DEBUG_FS
48 #include <linux/debugfs.h>
49 #include <linux/seq_file.h>
50 #endif /* CONFIG_DEBUG_FS */
51 #include <linux/net_tstamp.h>
52 #include "stmmac_ptp.h"
54 #include <linux/reset.h>
55 #include <linux/of_mdio.h>
56 #include "dwmac1000.h"
58 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
59 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
61 /* Module parameters */
63 static int watchdog
= TX_TIMEO
;
64 module_param(watchdog
, int, S_IRUGO
| S_IWUSR
);
65 MODULE_PARM_DESC(watchdog
, "Transmit timeout in milliseconds (default 5s)");
67 static int debug
= -1;
68 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
69 MODULE_PARM_DESC(debug
, "Message Level (-1: default, 0: no output, 16: all)");
71 static int phyaddr
= -1;
72 module_param(phyaddr
, int, S_IRUGO
);
73 MODULE_PARM_DESC(phyaddr
, "Physical device address");
75 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
76 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
78 static int flow_ctrl
= FLOW_OFF
;
79 module_param(flow_ctrl
, int, S_IRUGO
| S_IWUSR
);
80 MODULE_PARM_DESC(flow_ctrl
, "Flow control ability [on/off]");
82 static int pause
= PAUSE_TIME
;
83 module_param(pause
, int, S_IRUGO
| S_IWUSR
);
84 MODULE_PARM_DESC(pause
, "Flow Control Pause Time");
87 static int tc
= TC_DEFAULT
;
88 module_param(tc
, int, S_IRUGO
| S_IWUSR
);
89 MODULE_PARM_DESC(tc
, "DMA threshold control value");
91 #define DEFAULT_BUFSIZE 1536
92 static int buf_sz
= DEFAULT_BUFSIZE
;
93 module_param(buf_sz
, int, S_IRUGO
| S_IWUSR
);
94 MODULE_PARM_DESC(buf_sz
, "DMA buffer size");
96 #define STMMAC_RX_COPYBREAK 256
98 static const u32 default_msg_level
= (NETIF_MSG_DRV
| NETIF_MSG_PROBE
|
99 NETIF_MSG_LINK
| NETIF_MSG_IFUP
|
100 NETIF_MSG_IFDOWN
| NETIF_MSG_TIMER
);
102 #define STMMAC_DEFAULT_LPI_TIMER 1000
103 static int eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
104 module_param(eee_timer
, int, S_IRUGO
| S_IWUSR
);
105 MODULE_PARM_DESC(eee_timer
, "LPI tx expiration time in msec");
106 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
108 /* By default the driver will use the ring mode to manage tx and rx descriptors
109 * but passing this value so user can force to use the chain instead of the ring
111 static unsigned int chain_mode
;
112 module_param(chain_mode
, int, S_IRUGO
);
113 MODULE_PARM_DESC(chain_mode
, "To use chain instead of ring mode");
115 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
);
117 #ifdef CONFIG_DEBUG_FS
118 static int stmmac_init_fs(struct net_device
*dev
);
119 static void stmmac_exit_fs(struct net_device
*dev
);
122 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
125 * stmmac_verify_args - verify the driver parameters.
126 * Description: it checks the driver parameters and set a default in case of
129 static void stmmac_verify_args(void)
131 if (unlikely(watchdog
< 0))
133 if (unlikely((buf_sz
< DEFAULT_BUFSIZE
) || (buf_sz
> BUF_SIZE_16KiB
)))
134 buf_sz
= DEFAULT_BUFSIZE
;
135 if (unlikely(flow_ctrl
> 1))
136 flow_ctrl
= FLOW_AUTO
;
137 else if (likely(flow_ctrl
< 0))
138 flow_ctrl
= FLOW_OFF
;
139 if (unlikely((pause
< 0) || (pause
> 0xffff)))
142 eee_timer
= STMMAC_DEFAULT_LPI_TIMER
;
146 * stmmac_clk_csr_set - dynamically set the MDC clock
147 * @priv: driver private structure
148 * Description: this is to dynamically set the MDC clock according to the csr
151 * If a specific clk_csr value is passed from the platform
152 * this means that the CSR Clock Range selection cannot be
153 * changed at run-time and it is fixed (as reported in the driver
154 * documentation). Viceversa the driver will try to set the MDC
155 * clock dynamically according to the actual clock input.
157 static void stmmac_clk_csr_set(struct stmmac_priv
*priv
)
161 clk_rate
= clk_get_rate(priv
->stmmac_clk
);
163 /* Platform provided default clk_csr would be assumed valid
164 * for all other cases except for the below mentioned ones.
165 * For values higher than the IEEE 802.3 specified frequency
166 * we can not estimate the proper divider as it is not known
167 * the frequency of clk_csr_i. So we do not change the default
170 if (!(priv
->clk_csr
& MAC_CSR_H_FRQ_MASK
)) {
171 if (clk_rate
< CSR_F_35M
)
172 priv
->clk_csr
= STMMAC_CSR_20_35M
;
173 else if ((clk_rate
>= CSR_F_35M
) && (clk_rate
< CSR_F_60M
))
174 priv
->clk_csr
= STMMAC_CSR_35_60M
;
175 else if ((clk_rate
>= CSR_F_60M
) && (clk_rate
< CSR_F_100M
))
176 priv
->clk_csr
= STMMAC_CSR_60_100M
;
177 else if ((clk_rate
>= CSR_F_100M
) && (clk_rate
< CSR_F_150M
))
178 priv
->clk_csr
= STMMAC_CSR_100_150M
;
179 else if ((clk_rate
>= CSR_F_150M
) && (clk_rate
< CSR_F_250M
))
180 priv
->clk_csr
= STMMAC_CSR_150_250M
;
181 else if ((clk_rate
>= CSR_F_250M
) && (clk_rate
< CSR_F_300M
))
182 priv
->clk_csr
= STMMAC_CSR_250_300M
;
186 static void print_pkt(unsigned char *buf
, int len
)
188 pr_debug("len = %d byte, buf addr: 0x%p\n", len
, buf
);
189 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET
, buf
, len
);
192 static inline u32
stmmac_tx_avail(struct stmmac_priv
*priv
)
196 if (priv
->dirty_tx
> priv
->cur_tx
)
197 avail
= priv
->dirty_tx
- priv
->cur_tx
- 1;
199 avail
= DMA_TX_SIZE
- priv
->cur_tx
+ priv
->dirty_tx
- 1;
204 static inline u32
stmmac_rx_dirty(struct stmmac_priv
*priv
)
208 if (priv
->dirty_rx
<= priv
->cur_rx
)
209 dirty
= priv
->cur_rx
- priv
->dirty_rx
;
211 dirty
= DMA_RX_SIZE
- priv
->dirty_rx
+ priv
->cur_rx
;
217 * stmmac_hw_fix_mac_speed - callback for speed selection
218 * @priv: driver private structure
219 * Description: on some platforms (e.g. ST), some HW system configuraton
220 * registers have to be set according to the link speed negotiated.
222 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv
*priv
)
224 struct phy_device
*phydev
= priv
->phydev
;
226 if (likely(priv
->plat
->fix_mac_speed
))
227 priv
->plat
->fix_mac_speed(priv
->plat
->bsp_priv
, phydev
->speed
);
231 * stmmac_enable_eee_mode - check and enter in LPI mode
232 * @priv: driver private structure
233 * Description: this function is to verify and enter in LPI mode in case of
236 static void stmmac_enable_eee_mode(struct stmmac_priv
*priv
)
238 /* Check and enter in LPI mode */
239 if ((priv
->dirty_tx
== priv
->cur_tx
) &&
240 (priv
->tx_path_in_lpi_mode
== false))
241 priv
->hw
->mac
->set_eee_mode(priv
->hw
);
245 * stmmac_disable_eee_mode - disable and exit from LPI mode
246 * @priv: driver private structure
247 * Description: this function is to exit and disable EEE in case of
248 * LPI state is true. This is called by the xmit.
250 void stmmac_disable_eee_mode(struct stmmac_priv
*priv
)
252 priv
->hw
->mac
->reset_eee_mode(priv
->hw
);
253 del_timer_sync(&priv
->eee_ctrl_timer
);
254 priv
->tx_path_in_lpi_mode
= false;
258 * stmmac_eee_ctrl_timer - EEE TX SW timer.
261 * if there is no data transfer and if we are not in LPI state,
262 * then MAC Transmitter can be moved to LPI state.
264 static void stmmac_eee_ctrl_timer(unsigned long arg
)
266 struct stmmac_priv
*priv
= (struct stmmac_priv
*)arg
;
268 stmmac_enable_eee_mode(priv
);
269 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
273 * stmmac_eee_init - init EEE
274 * @priv: driver private structure
276 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
277 * can also manage EEE, this function enable the LPI state and start related
280 bool stmmac_eee_init(struct stmmac_priv
*priv
)
285 /* Using PCS we cannot dial with the phy registers at this stage
286 * so we do not support extra feature like EEE.
288 if ((priv
->pcs
== STMMAC_PCS_RGMII
) || (priv
->pcs
== STMMAC_PCS_TBI
) ||
289 (priv
->pcs
== STMMAC_PCS_RTBI
))
292 /* MAC core supports the EEE feature. */
293 if (priv
->dma_cap
.eee
) {
294 int tx_lpi_timer
= priv
->tx_lpi_timer
;
296 /* Check if the PHY supports EEE */
297 if (phy_init_eee(priv
->phydev
, 1)) {
298 /* To manage at run-time if the EEE cannot be supported
299 * anymore (for example because the lp caps have been
301 * In that case the driver disable own timers.
303 spin_lock_irqsave(&priv
->lock
, flags
);
304 if (priv
->eee_active
) {
305 pr_debug("stmmac: disable EEE\n");
306 del_timer_sync(&priv
->eee_ctrl_timer
);
307 priv
->hw
->mac
->set_eee_timer(priv
->hw
, 0,
310 priv
->eee_active
= 0;
311 spin_unlock_irqrestore(&priv
->lock
, flags
);
314 /* Activate the EEE and start timers */
315 spin_lock_irqsave(&priv
->lock
, flags
);
316 if (!priv
->eee_active
) {
317 priv
->eee_active
= 1;
318 setup_timer(&priv
->eee_ctrl_timer
,
319 stmmac_eee_ctrl_timer
,
320 (unsigned long)priv
);
321 mod_timer(&priv
->eee_ctrl_timer
,
322 STMMAC_LPI_T(eee_timer
));
324 priv
->hw
->mac
->set_eee_timer(priv
->hw
,
325 STMMAC_DEFAULT_LIT_LS
,
328 /* Set HW EEE according to the speed */
329 priv
->hw
->mac
->set_eee_pls(priv
->hw
, priv
->phydev
->link
);
332 spin_unlock_irqrestore(&priv
->lock
, flags
);
334 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
340 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
341 * @priv: driver private structure
342 * @entry : descriptor index to be used.
343 * @skb : the socket buffer
345 * This function will read timestamp from the descriptor & pass it to stack.
346 * and also perform some sanity checks.
348 static void stmmac_get_tx_hwtstamp(struct stmmac_priv
*priv
,
349 unsigned int entry
, struct sk_buff
*skb
)
351 struct skb_shared_hwtstamps shhwtstamp
;
355 if (!priv
->hwts_tx_en
)
358 /* exit if skb doesn't support hw tstamp */
359 if (likely(!skb
|| !(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)))
363 desc
= (priv
->dma_etx
+ entry
);
365 desc
= (priv
->dma_tx
+ entry
);
367 /* check tx tstamp status */
368 if (!priv
->hw
->desc
->get_tx_timestamp_status((struct dma_desc
*)desc
))
371 /* get the valid tstamp */
372 ns
= priv
->hw
->desc
->get_timestamp(desc
, priv
->adv_ts
);
374 memset(&shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
375 shhwtstamp
.hwtstamp
= ns_to_ktime(ns
);
376 /* pass tstamp to stack */
377 skb_tstamp_tx(skb
, &shhwtstamp
);
382 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
383 * @priv: driver private structure
384 * @entry : descriptor index to be used.
385 * @skb : the socket buffer
387 * This function will read received packet's timestamp from the descriptor
388 * and pass it to stack. It also perform some sanity checks.
390 static void stmmac_get_rx_hwtstamp(struct stmmac_priv
*priv
,
391 unsigned int entry
, struct sk_buff
*skb
)
393 struct skb_shared_hwtstamps
*shhwtstamp
= NULL
;
397 if (!priv
->hwts_rx_en
)
401 desc
= (priv
->dma_erx
+ entry
);
403 desc
= (priv
->dma_rx
+ entry
);
405 /* exit if rx tstamp is not valid */
406 if (!priv
->hw
->desc
->get_rx_timestamp_status(desc
, priv
->adv_ts
))
409 /* get valid tstamp */
410 ns
= priv
->hw
->desc
->get_timestamp(desc
, priv
->adv_ts
);
411 shhwtstamp
= skb_hwtstamps(skb
);
412 memset(shhwtstamp
, 0, sizeof(struct skb_shared_hwtstamps
));
413 shhwtstamp
->hwtstamp
= ns_to_ktime(ns
);
417 * stmmac_hwtstamp_ioctl - control hardware timestamping.
418 * @dev: device pointer.
419 * @ifr: An IOCTL specefic structure, that can contain a pointer to
420 * a proprietary structure used to pass information to the driver.
422 * This function configures the MAC to enable/disable both outgoing(TX)
423 * and incoming(RX) packets time stamping based on user input.
425 * 0 on success and an appropriate -ve integer on failure.
427 static int stmmac_hwtstamp_ioctl(struct net_device
*dev
, struct ifreq
*ifr
)
429 struct stmmac_priv
*priv
= netdev_priv(dev
);
430 struct hwtstamp_config config
;
431 struct timespec64 now
;
435 u32 ptp_over_ipv4_udp
= 0;
436 u32 ptp_over_ipv6_udp
= 0;
437 u32 ptp_over_ethernet
= 0;
438 u32 snap_type_sel
= 0;
439 u32 ts_master_en
= 0;
444 if (!(priv
->dma_cap
.time_stamp
|| priv
->adv_ts
)) {
445 netdev_alert(priv
->dev
, "No support for HW time stamping\n");
446 priv
->hwts_tx_en
= 0;
447 priv
->hwts_rx_en
= 0;
452 if (copy_from_user(&config
, ifr
->ifr_data
,
453 sizeof(struct hwtstamp_config
)))
456 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
457 __func__
, config
.flags
, config
.tx_type
, config
.rx_filter
);
459 /* reserved for future extensions */
463 if (config
.tx_type
!= HWTSTAMP_TX_OFF
&&
464 config
.tx_type
!= HWTSTAMP_TX_ON
)
468 switch (config
.rx_filter
) {
469 case HWTSTAMP_FILTER_NONE
:
470 /* time stamp no incoming packet at all */
471 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
474 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
475 /* PTP v1, UDP, any kind of event packet */
476 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
477 /* take time stamp for all event messages */
478 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
480 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
481 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
484 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
485 /* PTP v1, UDP, Sync packet */
486 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_SYNC
;
487 /* take time stamp for SYNC messages only */
488 ts_event_en
= PTP_TCR_TSEVNTENA
;
490 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
491 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
494 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
495 /* PTP v1, UDP, Delay_req packet */
496 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
;
497 /* take time stamp for Delay_Req messages only */
498 ts_master_en
= PTP_TCR_TSMSTRENA
;
499 ts_event_en
= PTP_TCR_TSEVNTENA
;
501 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
502 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
505 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
506 /* PTP v2, UDP, any kind of event packet */
507 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_EVENT
;
508 ptp_v2
= PTP_TCR_TSVER2ENA
;
509 /* take time stamp for all event messages */
510 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
512 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
513 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
516 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
517 /* PTP v2, UDP, Sync packet */
518 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_SYNC
;
519 ptp_v2
= PTP_TCR_TSVER2ENA
;
520 /* take time stamp for SYNC messages only */
521 ts_event_en
= PTP_TCR_TSEVNTENA
;
523 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
524 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
527 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
528 /* PTP v2, UDP, Delay_req packet */
529 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
;
530 ptp_v2
= PTP_TCR_TSVER2ENA
;
531 /* take time stamp for Delay_Req messages only */
532 ts_master_en
= PTP_TCR_TSMSTRENA
;
533 ts_event_en
= PTP_TCR_TSEVNTENA
;
535 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
536 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
539 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
540 /* PTP v2/802.AS1 any layer, any kind of event packet */
541 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
542 ptp_v2
= PTP_TCR_TSVER2ENA
;
543 /* take time stamp for all event messages */
544 snap_type_sel
= PTP_TCR_SNAPTYPSEL_1
;
546 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
547 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
548 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
551 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
552 /* PTP v2/802.AS1, any layer, Sync packet */
553 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_SYNC
;
554 ptp_v2
= PTP_TCR_TSVER2ENA
;
555 /* take time stamp for SYNC messages only */
556 ts_event_en
= PTP_TCR_TSEVNTENA
;
558 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
559 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
560 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
563 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
564 /* PTP v2/802.AS1, any layer, Delay_req packet */
565 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
;
566 ptp_v2
= PTP_TCR_TSVER2ENA
;
567 /* take time stamp for Delay_Req messages only */
568 ts_master_en
= PTP_TCR_TSMSTRENA
;
569 ts_event_en
= PTP_TCR_TSEVNTENA
;
571 ptp_over_ipv4_udp
= PTP_TCR_TSIPV4ENA
;
572 ptp_over_ipv6_udp
= PTP_TCR_TSIPV6ENA
;
573 ptp_over_ethernet
= PTP_TCR_TSIPENA
;
576 case HWTSTAMP_FILTER_ALL
:
577 /* time stamp any incoming packet */
578 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
579 tstamp_all
= PTP_TCR_TSENALL
;
586 switch (config
.rx_filter
) {
587 case HWTSTAMP_FILTER_NONE
:
588 config
.rx_filter
= HWTSTAMP_FILTER_NONE
;
591 /* PTP v1, UDP, any kind of event packet */
592 config
.rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
596 priv
->hwts_rx_en
= ((config
.rx_filter
== HWTSTAMP_FILTER_NONE
) ? 0 : 1);
597 priv
->hwts_tx_en
= config
.tx_type
== HWTSTAMP_TX_ON
;
599 if (!priv
->hwts_tx_en
&& !priv
->hwts_rx_en
)
600 priv
->hw
->ptp
->config_hw_tstamping(priv
->ioaddr
, 0);
602 value
= (PTP_TCR_TSENA
| PTP_TCR_TSCFUPDT
| PTP_TCR_TSCTRLSSR
|
603 tstamp_all
| ptp_v2
| ptp_over_ethernet
|
604 ptp_over_ipv6_udp
| ptp_over_ipv4_udp
| ts_event_en
|
605 ts_master_en
| snap_type_sel
);
606 priv
->hw
->ptp
->config_hw_tstamping(priv
->ioaddr
, value
);
608 /* program Sub Second Increment reg */
609 sec_inc
= priv
->hw
->ptp
->config_sub_second_increment(
610 priv
->ioaddr
, priv
->clk_ptp_rate
);
611 temp
= div_u64(1000000000ULL, sec_inc
);
613 /* calculate default added value:
615 * addend = (2^32)/freq_div_ratio;
616 * where, freq_div_ratio = 1e9ns/sec_inc
618 temp
= (u64
)(temp
<< 32);
619 priv
->default_addend
= div_u64(temp
, priv
->clk_ptp_rate
);
620 priv
->hw
->ptp
->config_addend(priv
->ioaddr
,
621 priv
->default_addend
);
623 /* initialize system time */
624 ktime_get_real_ts64(&now
);
626 /* lower 32 bits of tv_sec are safe until y2106 */
627 priv
->hw
->ptp
->init_systime(priv
->ioaddr
, (u32
)now
.tv_sec
,
631 return copy_to_user(ifr
->ifr_data
, &config
,
632 sizeof(struct hwtstamp_config
)) ? -EFAULT
: 0;
636 * stmmac_init_ptp - init PTP
637 * @priv: driver private structure
638 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
639 * This is done by looking at the HW cap. register.
640 * This function also registers the ptp driver.
642 static int stmmac_init_ptp(struct stmmac_priv
*priv
)
644 if (!(priv
->dma_cap
.time_stamp
|| priv
->dma_cap
.atime_stamp
))
647 /* Fall-back to main clock in case of no PTP ref is passed */
648 priv
->clk_ptp_ref
= devm_clk_get(priv
->device
, "clk_ptp_ref");
649 if (IS_ERR(priv
->clk_ptp_ref
)) {
650 priv
->clk_ptp_rate
= clk_get_rate(priv
->stmmac_clk
);
651 priv
->clk_ptp_ref
= NULL
;
653 clk_prepare_enable(priv
->clk_ptp_ref
);
654 priv
->clk_ptp_rate
= clk_get_rate(priv
->clk_ptp_ref
);
658 if (priv
->dma_cap
.atime_stamp
&& priv
->extend_desc
)
661 if (netif_msg_hw(priv
) && priv
->dma_cap
.time_stamp
)
662 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
664 if (netif_msg_hw(priv
) && priv
->adv_ts
)
665 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
667 priv
->hw
->ptp
= &stmmac_ptp
;
668 priv
->hwts_tx_en
= 0;
669 priv
->hwts_rx_en
= 0;
671 return stmmac_ptp_register(priv
);
674 static void stmmac_release_ptp(struct stmmac_priv
*priv
)
676 if (priv
->clk_ptp_ref
)
677 clk_disable_unprepare(priv
->clk_ptp_ref
);
678 stmmac_ptp_unregister(priv
);
682 * stmmac_adjust_link - adjusts the link parameters
683 * @dev: net device structure
684 * Description: this is the helper called by the physical abstraction layer
685 * drivers to communicate the phy link status. According the speed and duplex
686 * this driver can invoke registered glue-logic as well.
687 * It also invoke the eee initialization because it could happen when switch
688 * on different networks (that are eee capable).
690 static void stmmac_adjust_link(struct net_device
*dev
)
692 struct stmmac_priv
*priv
= netdev_priv(dev
);
693 struct phy_device
*phydev
= priv
->phydev
;
696 unsigned int fc
= priv
->flow_ctrl
, pause_time
= priv
->pause
;
701 spin_lock_irqsave(&priv
->lock
, flags
);
704 u32 ctrl
= readl(priv
->ioaddr
+ MAC_CTRL_REG
);
706 /* Now we make sure that we can be in full duplex mode.
707 * If not, we operate in half-duplex mode. */
708 if (phydev
->duplex
!= priv
->oldduplex
) {
710 if (!(phydev
->duplex
))
711 ctrl
&= ~priv
->hw
->link
.duplex
;
713 ctrl
|= priv
->hw
->link
.duplex
;
714 priv
->oldduplex
= phydev
->duplex
;
716 /* Flow Control operation */
718 priv
->hw
->mac
->flow_ctrl(priv
->hw
, phydev
->duplex
,
721 if (phydev
->speed
!= priv
->speed
) {
723 switch (phydev
->speed
) {
725 if (likely((priv
->plat
->has_gmac
) ||
726 (priv
->plat
->has_gmac4
)))
727 ctrl
&= ~priv
->hw
->link
.port
;
728 stmmac_hw_fix_mac_speed(priv
);
732 if (likely((priv
->plat
->has_gmac
) ||
733 (priv
->plat
->has_gmac4
))) {
734 ctrl
|= priv
->hw
->link
.port
;
735 if (phydev
->speed
== SPEED_100
) {
736 ctrl
|= priv
->hw
->link
.speed
;
738 ctrl
&= ~(priv
->hw
->link
.speed
);
741 ctrl
&= ~priv
->hw
->link
.port
;
743 stmmac_hw_fix_mac_speed(priv
);
746 if (netif_msg_link(priv
))
747 pr_warn("%s: Speed (%d) not 10/100\n",
748 dev
->name
, phydev
->speed
);
752 priv
->speed
= phydev
->speed
;
755 writel(ctrl
, priv
->ioaddr
+ MAC_CTRL_REG
);
757 if (!priv
->oldlink
) {
761 } else if (priv
->oldlink
) {
765 priv
->oldduplex
= -1;
768 if (new_state
&& netif_msg_link(priv
))
769 phy_print_status(phydev
);
771 spin_unlock_irqrestore(&priv
->lock
, flags
);
773 if (phydev
->is_pseudo_fixed_link
)
774 /* Stop PHY layer to call the hook to adjust the link in case
775 * of a switch is attached to the stmmac driver.
777 phydev
->irq
= PHY_IGNORE_INTERRUPT
;
779 /* At this stage, init the EEE if supported.
780 * Never called in case of fixed_link.
782 priv
->eee_enabled
= stmmac_eee_init(priv
);
786 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
787 * @priv: driver private structure
788 * Description: this is to verify if the HW supports the PCS.
789 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
790 * configured for the TBI, RTBI, or SGMII PHY interface.
792 static void stmmac_check_pcs_mode(struct stmmac_priv
*priv
)
794 int interface
= priv
->plat
->interface
;
796 if (priv
->dma_cap
.pcs
) {
797 if ((interface
== PHY_INTERFACE_MODE_RGMII
) ||
798 (interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
799 (interface
== PHY_INTERFACE_MODE_RGMII_RXID
) ||
800 (interface
== PHY_INTERFACE_MODE_RGMII_TXID
)) {
801 pr_debug("STMMAC: PCS RGMII support enable\n");
802 priv
->pcs
= STMMAC_PCS_RGMII
;
803 } else if (interface
== PHY_INTERFACE_MODE_SGMII
) {
804 pr_debug("STMMAC: PCS SGMII support enable\n");
805 priv
->pcs
= STMMAC_PCS_SGMII
;
811 * stmmac_init_phy - PHY initialization
812 * @dev: net device structure
813 * Description: it initializes the driver's PHY state, and attaches the PHY
818 static int stmmac_init_phy(struct net_device
*dev
)
820 struct stmmac_priv
*priv
= netdev_priv(dev
);
821 struct phy_device
*phydev
;
822 char phy_id_fmt
[MII_BUS_ID_SIZE
+ 3];
823 char bus_id
[MII_BUS_ID_SIZE
];
824 int interface
= priv
->plat
->interface
;
825 int max_speed
= priv
->plat
->max_speed
;
828 priv
->oldduplex
= -1;
830 if (priv
->plat
->phy_node
) {
831 phydev
= of_phy_connect(dev
, priv
->plat
->phy_node
,
832 &stmmac_adjust_link
, 0, interface
);
834 snprintf(bus_id
, MII_BUS_ID_SIZE
, "stmmac-%x",
837 snprintf(phy_id_fmt
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
, bus_id
,
838 priv
->plat
->phy_addr
);
839 pr_debug("stmmac_init_phy: trying to attach to %s\n",
842 phydev
= phy_connect(dev
, phy_id_fmt
, &stmmac_adjust_link
,
846 if (IS_ERR_OR_NULL(phydev
)) {
847 pr_err("%s: Could not attach to PHY\n", dev
->name
);
851 return PTR_ERR(phydev
);
854 /* Stop Advertising 1000BASE Capability if interface is not GMII */
855 if ((interface
== PHY_INTERFACE_MODE_MII
) ||
856 (interface
== PHY_INTERFACE_MODE_RMII
) ||
857 (max_speed
< 1000 && max_speed
> 0))
858 phydev
->advertising
&= ~(SUPPORTED_1000baseT_Half
|
859 SUPPORTED_1000baseT_Full
);
862 * Broken HW is sometimes missing the pull-up resistor on the
863 * MDIO line, which results in reads to non-existent devices returning
864 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
866 * Note: phydev->phy_id is the result of reading the UID PHY registers.
868 if (!priv
->plat
->phy_node
&& phydev
->phy_id
== 0) {
869 phy_disconnect(phydev
);
873 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
874 " Link = %d\n", dev
->name
, phydev
->phy_id
, phydev
->link
);
876 priv
->phydev
= phydev
;
881 static void stmmac_display_rings(struct stmmac_priv
*priv
)
883 void *head_rx
, *head_tx
;
885 if (priv
->extend_desc
) {
886 head_rx
= (void *)priv
->dma_erx
;
887 head_tx
= (void *)priv
->dma_etx
;
889 head_rx
= (void *)priv
->dma_rx
;
890 head_tx
= (void *)priv
->dma_tx
;
893 /* Display Rx ring */
894 priv
->hw
->desc
->display_ring(head_rx
, DMA_RX_SIZE
, true);
895 /* Display Tx ring */
896 priv
->hw
->desc
->display_ring(head_tx
, DMA_TX_SIZE
, false);
899 static int stmmac_set_bfsize(int mtu
, int bufsize
)
903 if (mtu
>= BUF_SIZE_4KiB
)
905 else if (mtu
>= BUF_SIZE_2KiB
)
907 else if (mtu
> DEFAULT_BUFSIZE
)
910 ret
= DEFAULT_BUFSIZE
;
916 * stmmac_clear_descriptors - clear descriptors
917 * @priv: driver private structure
918 * Description: this function is called to clear the tx and rx descriptors
919 * in case of both basic and extended descriptors are used.
921 static void stmmac_clear_descriptors(struct stmmac_priv
*priv
)
925 /* Clear the Rx/Tx descriptors */
926 for (i
= 0; i
< DMA_RX_SIZE
; i
++)
927 if (priv
->extend_desc
)
928 priv
->hw
->desc
->init_rx_desc(&priv
->dma_erx
[i
].basic
,
929 priv
->use_riwt
, priv
->mode
,
930 (i
== DMA_RX_SIZE
- 1));
932 priv
->hw
->desc
->init_rx_desc(&priv
->dma_rx
[i
],
933 priv
->use_riwt
, priv
->mode
,
934 (i
== DMA_RX_SIZE
- 1));
935 for (i
= 0; i
< DMA_TX_SIZE
; i
++)
936 if (priv
->extend_desc
)
937 priv
->hw
->desc
->init_tx_desc(&priv
->dma_etx
[i
].basic
,
939 (i
== DMA_TX_SIZE
- 1));
941 priv
->hw
->desc
->init_tx_desc(&priv
->dma_tx
[i
],
943 (i
== DMA_TX_SIZE
- 1));
947 * stmmac_init_rx_buffers - init the RX descriptor buffer.
948 * @priv: driver private structure
949 * @p: descriptor pointer
950 * @i: descriptor index
952 * Description: this function is called to allocate a receive buffer, perform
953 * the DMA mapping and init the descriptor.
955 static int stmmac_init_rx_buffers(struct stmmac_priv
*priv
, struct dma_desc
*p
,
960 skb
= __netdev_alloc_skb_ip_align(priv
->dev
, priv
->dma_buf_sz
, flags
);
962 pr_err("%s: Rx init fails; skb is NULL\n", __func__
);
965 priv
->rx_skbuff
[i
] = skb
;
966 priv
->rx_skbuff_dma
[i
] = dma_map_single(priv
->device
, skb
->data
,
969 if (dma_mapping_error(priv
->device
, priv
->rx_skbuff_dma
[i
])) {
970 pr_err("%s: DMA mapping error\n", __func__
);
971 dev_kfree_skb_any(skb
);
975 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
)
976 p
->des0
= priv
->rx_skbuff_dma
[i
];
978 p
->des2
= priv
->rx_skbuff_dma
[i
];
980 if ((priv
->hw
->mode
->init_desc3
) &&
981 (priv
->dma_buf_sz
== BUF_SIZE_16KiB
))
982 priv
->hw
->mode
->init_desc3(p
);
987 static void stmmac_free_rx_buffers(struct stmmac_priv
*priv
, int i
)
989 if (priv
->rx_skbuff
[i
]) {
990 dma_unmap_single(priv
->device
, priv
->rx_skbuff_dma
[i
],
991 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
992 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
994 priv
->rx_skbuff
[i
] = NULL
;
998 * init_dma_desc_rings - init the RX/TX descriptor rings
999 * @dev: net device structure
1001 * Description: this function initializes the DMA RX/TX descriptors
1002 * and allocates the socket buffers. It suppors the chained and ring
1005 static int init_dma_desc_rings(struct net_device
*dev
, gfp_t flags
)
1008 struct stmmac_priv
*priv
= netdev_priv(dev
);
1009 unsigned int bfsize
= 0;
1012 if (priv
->hw
->mode
->set_16kib_bfsize
)
1013 bfsize
= priv
->hw
->mode
->set_16kib_bfsize(dev
->mtu
);
1015 if (bfsize
< BUF_SIZE_16KiB
)
1016 bfsize
= stmmac_set_bfsize(dev
->mtu
, priv
->dma_buf_sz
);
1018 priv
->dma_buf_sz
= bfsize
;
1020 if (netif_msg_probe(priv
)) {
1021 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__
,
1022 (u32
) priv
->dma_rx_phy
, (u32
) priv
->dma_tx_phy
);
1024 /* RX INITIALIZATION */
1025 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1027 for (i
= 0; i
< DMA_RX_SIZE
; i
++) {
1029 if (priv
->extend_desc
)
1030 p
= &((priv
->dma_erx
+ i
)->basic
);
1032 p
= priv
->dma_rx
+ i
;
1034 ret
= stmmac_init_rx_buffers(priv
, p
, i
, flags
);
1036 goto err_init_rx_buffers
;
1038 if (netif_msg_probe(priv
))
1039 pr_debug("[%p]\t[%p]\t[%x]\n", priv
->rx_skbuff
[i
],
1040 priv
->rx_skbuff
[i
]->data
,
1041 (unsigned int)priv
->rx_skbuff_dma
[i
]);
1044 priv
->dirty_rx
= (unsigned int)(i
- DMA_RX_SIZE
);
1047 /* Setup the chained descriptor addresses */
1048 if (priv
->mode
== STMMAC_CHAIN_MODE
) {
1049 if (priv
->extend_desc
) {
1050 priv
->hw
->mode
->init(priv
->dma_erx
, priv
->dma_rx_phy
,
1052 priv
->hw
->mode
->init(priv
->dma_etx
, priv
->dma_tx_phy
,
1055 priv
->hw
->mode
->init(priv
->dma_rx
, priv
->dma_rx_phy
,
1057 priv
->hw
->mode
->init(priv
->dma_tx
, priv
->dma_tx_phy
,
1062 /* TX INITIALIZATION */
1063 for (i
= 0; i
< DMA_TX_SIZE
; i
++) {
1065 if (priv
->extend_desc
)
1066 p
= &((priv
->dma_etx
+ i
)->basic
);
1068 p
= priv
->dma_tx
+ i
;
1070 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
1079 priv
->tx_skbuff_dma
[i
].buf
= 0;
1080 priv
->tx_skbuff_dma
[i
].map_as_page
= false;
1081 priv
->tx_skbuff_dma
[i
].len
= 0;
1082 priv
->tx_skbuff_dma
[i
].last_segment
= false;
1083 priv
->tx_skbuff
[i
] = NULL
;
1088 netdev_reset_queue(priv
->dev
);
1090 stmmac_clear_descriptors(priv
);
1092 if (netif_msg_hw(priv
))
1093 stmmac_display_rings(priv
);
1096 err_init_rx_buffers
:
1098 stmmac_free_rx_buffers(priv
, i
);
1102 static void dma_free_rx_skbufs(struct stmmac_priv
*priv
)
1106 for (i
= 0; i
< DMA_RX_SIZE
; i
++)
1107 stmmac_free_rx_buffers(priv
, i
);
1110 static void dma_free_tx_skbufs(struct stmmac_priv
*priv
)
1114 for (i
= 0; i
< DMA_TX_SIZE
; i
++) {
1117 if (priv
->extend_desc
)
1118 p
= &((priv
->dma_etx
+ i
)->basic
);
1120 p
= priv
->dma_tx
+ i
;
1122 if (priv
->tx_skbuff_dma
[i
].buf
) {
1123 if (priv
->tx_skbuff_dma
[i
].map_as_page
)
1124 dma_unmap_page(priv
->device
,
1125 priv
->tx_skbuff_dma
[i
].buf
,
1126 priv
->tx_skbuff_dma
[i
].len
,
1129 dma_unmap_single(priv
->device
,
1130 priv
->tx_skbuff_dma
[i
].buf
,
1131 priv
->tx_skbuff_dma
[i
].len
,
1135 if (priv
->tx_skbuff
[i
] != NULL
) {
1136 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
1137 priv
->tx_skbuff
[i
] = NULL
;
1138 priv
->tx_skbuff_dma
[i
].buf
= 0;
1139 priv
->tx_skbuff_dma
[i
].map_as_page
= false;
1145 * alloc_dma_desc_resources - alloc TX/RX resources.
1146 * @priv: private structure
1147 * Description: according to which descriptor can be used (extend or basic)
1148 * this function allocates the resources for TX and RX paths. In case of
1149 * reception, for example, it pre-allocated the RX socket buffer in order to
1150 * allow zero-copy mechanism.
1152 static int alloc_dma_desc_resources(struct stmmac_priv
*priv
)
1156 priv
->rx_skbuff_dma
= kmalloc_array(DMA_RX_SIZE
, sizeof(dma_addr_t
),
1158 if (!priv
->rx_skbuff_dma
)
1161 priv
->rx_skbuff
= kmalloc_array(DMA_RX_SIZE
, sizeof(struct sk_buff
*),
1163 if (!priv
->rx_skbuff
)
1166 priv
->tx_skbuff_dma
= kmalloc_array(DMA_TX_SIZE
,
1167 sizeof(*priv
->tx_skbuff_dma
),
1169 if (!priv
->tx_skbuff_dma
)
1170 goto err_tx_skbuff_dma
;
1172 priv
->tx_skbuff
= kmalloc_array(DMA_TX_SIZE
, sizeof(struct sk_buff
*),
1174 if (!priv
->tx_skbuff
)
1177 if (priv
->extend_desc
) {
1178 priv
->dma_erx
= dma_zalloc_coherent(priv
->device
, DMA_RX_SIZE
*
1186 priv
->dma_etx
= dma_zalloc_coherent(priv
->device
, DMA_TX_SIZE
*
1191 if (!priv
->dma_etx
) {
1192 dma_free_coherent(priv
->device
, DMA_RX_SIZE
*
1193 sizeof(struct dma_extended_desc
),
1194 priv
->dma_erx
, priv
->dma_rx_phy
);
1198 priv
->dma_rx
= dma_zalloc_coherent(priv
->device
, DMA_RX_SIZE
*
1199 sizeof(struct dma_desc
),
1205 priv
->dma_tx
= dma_zalloc_coherent(priv
->device
, DMA_TX_SIZE
*
1206 sizeof(struct dma_desc
),
1209 if (!priv
->dma_tx
) {
1210 dma_free_coherent(priv
->device
, DMA_RX_SIZE
*
1211 sizeof(struct dma_desc
),
1212 priv
->dma_rx
, priv
->dma_rx_phy
);
1220 kfree(priv
->tx_skbuff
);
1222 kfree(priv
->tx_skbuff_dma
);
1224 kfree(priv
->rx_skbuff
);
1226 kfree(priv
->rx_skbuff_dma
);
1230 static void free_dma_desc_resources(struct stmmac_priv
*priv
)
1232 /* Release the DMA TX/RX socket buffers */
1233 dma_free_rx_skbufs(priv
);
1234 dma_free_tx_skbufs(priv
);
1236 /* Free DMA regions of consistent memory previously allocated */
1237 if (!priv
->extend_desc
) {
1238 dma_free_coherent(priv
->device
,
1239 DMA_TX_SIZE
* sizeof(struct dma_desc
),
1240 priv
->dma_tx
, priv
->dma_tx_phy
);
1241 dma_free_coherent(priv
->device
,
1242 DMA_RX_SIZE
* sizeof(struct dma_desc
),
1243 priv
->dma_rx
, priv
->dma_rx_phy
);
1245 dma_free_coherent(priv
->device
, DMA_TX_SIZE
*
1246 sizeof(struct dma_extended_desc
),
1247 priv
->dma_etx
, priv
->dma_tx_phy
);
1248 dma_free_coherent(priv
->device
, DMA_RX_SIZE
*
1249 sizeof(struct dma_extended_desc
),
1250 priv
->dma_erx
, priv
->dma_rx_phy
);
1252 kfree(priv
->rx_skbuff_dma
);
1253 kfree(priv
->rx_skbuff
);
1254 kfree(priv
->tx_skbuff_dma
);
1255 kfree(priv
->tx_skbuff
);
1259 * stmmac_dma_operation_mode - HW DMA operation mode
1260 * @priv: driver private structure
1261 * Description: it is used for configuring the DMA operation mode register in
1262 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1264 static void stmmac_dma_operation_mode(struct stmmac_priv
*priv
)
1266 int rxfifosz
= priv
->plat
->rx_fifo_size
;
1268 if (priv
->plat
->force_thresh_dma_mode
)
1269 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, tc
, rxfifosz
);
1270 else if (priv
->plat
->force_sf_dma_mode
|| priv
->plat
->tx_coe
) {
1272 * In case of GMAC, SF mode can be enabled
1273 * to perform the TX COE in HW. This depends on:
1274 * 1) TX COE if actually supported
1275 * 2) There is no bugged Jumbo frame support
1276 * that needs to not insert csum in the TDES.
1278 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, SF_DMA_MODE
, SF_DMA_MODE
,
1280 priv
->xstats
.threshold
= SF_DMA_MODE
;
1282 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, SF_DMA_MODE
,
1287 * stmmac_tx_clean - to manage the transmission completion
1288 * @priv: driver private structure
1289 * Description: it reclaims the transmit resources after transmission completes.
1291 static void stmmac_tx_clean(struct stmmac_priv
*priv
)
1293 unsigned int bytes_compl
= 0, pkts_compl
= 0;
1294 unsigned int entry
= priv
->dirty_tx
;
1296 spin_lock(&priv
->tx_lock
);
1298 priv
->xstats
.tx_clean
++;
1300 while (entry
!= priv
->cur_tx
) {
1301 struct sk_buff
*skb
= priv
->tx_skbuff
[entry
];
1305 if (priv
->extend_desc
)
1306 p
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
1308 p
= priv
->dma_tx
+ entry
;
1310 status
= priv
->hw
->desc
->tx_status(&priv
->dev
->stats
,
1313 /* Check if the descriptor is owned by the DMA */
1314 if (unlikely(status
& tx_dma_own
))
1317 /* Just consider the last segment and ...*/
1318 if (likely(!(status
& tx_not_ls
))) {
1319 /* ... verify the status error condition */
1320 if (unlikely(status
& tx_err
)) {
1321 priv
->dev
->stats
.tx_errors
++;
1323 priv
->dev
->stats
.tx_packets
++;
1324 priv
->xstats
.tx_pkt_n
++;
1326 stmmac_get_tx_hwtstamp(priv
, entry
, skb
);
1329 if (likely(priv
->tx_skbuff_dma
[entry
].buf
)) {
1330 if (priv
->tx_skbuff_dma
[entry
].map_as_page
)
1331 dma_unmap_page(priv
->device
,
1332 priv
->tx_skbuff_dma
[entry
].buf
,
1333 priv
->tx_skbuff_dma
[entry
].len
,
1336 dma_unmap_single(priv
->device
,
1337 priv
->tx_skbuff_dma
[entry
].buf
,
1338 priv
->tx_skbuff_dma
[entry
].len
,
1340 priv
->tx_skbuff_dma
[entry
].buf
= 0;
1341 priv
->tx_skbuff_dma
[entry
].len
= 0;
1342 priv
->tx_skbuff_dma
[entry
].map_as_page
= false;
1345 if (priv
->hw
->mode
->clean_desc3
)
1346 priv
->hw
->mode
->clean_desc3(priv
, p
);
1348 priv
->tx_skbuff_dma
[entry
].last_segment
= false;
1349 priv
->tx_skbuff_dma
[entry
].is_jumbo
= false;
1351 if (likely(skb
!= NULL
)) {
1353 bytes_compl
+= skb
->len
;
1354 dev_consume_skb_any(skb
);
1355 priv
->tx_skbuff
[entry
] = NULL
;
1358 priv
->hw
->desc
->release_tx_desc(p
, priv
->mode
);
1360 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
1362 priv
->dirty_tx
= entry
;
1364 netdev_completed_queue(priv
->dev
, pkts_compl
, bytes_compl
);
1366 if (unlikely(netif_queue_stopped(priv
->dev
) &&
1367 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH
)) {
1368 netif_tx_lock(priv
->dev
);
1369 if (netif_queue_stopped(priv
->dev
) &&
1370 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH
) {
1371 if (netif_msg_tx_done(priv
))
1372 pr_debug("%s: restart transmit\n", __func__
);
1373 netif_wake_queue(priv
->dev
);
1375 netif_tx_unlock(priv
->dev
);
1378 if ((priv
->eee_enabled
) && (!priv
->tx_path_in_lpi_mode
)) {
1379 stmmac_enable_eee_mode(priv
);
1380 mod_timer(&priv
->eee_ctrl_timer
, STMMAC_LPI_T(eee_timer
));
1382 spin_unlock(&priv
->tx_lock
);
1385 static inline void stmmac_enable_dma_irq(struct stmmac_priv
*priv
)
1387 priv
->hw
->dma
->enable_dma_irq(priv
->ioaddr
);
1390 static inline void stmmac_disable_dma_irq(struct stmmac_priv
*priv
)
1392 priv
->hw
->dma
->disable_dma_irq(priv
->ioaddr
);
1396 * stmmac_tx_err - to manage the tx error
1397 * @priv: driver private structure
1398 * Description: it cleans the descriptors and restarts the transmission
1399 * in case of transmission errors.
1401 static void stmmac_tx_err(struct stmmac_priv
*priv
)
1404 netif_stop_queue(priv
->dev
);
1406 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1407 dma_free_tx_skbufs(priv
);
1408 for (i
= 0; i
< DMA_TX_SIZE
; i
++)
1409 if (priv
->extend_desc
)
1410 priv
->hw
->desc
->init_tx_desc(&priv
->dma_etx
[i
].basic
,
1412 (i
== DMA_TX_SIZE
- 1));
1414 priv
->hw
->desc
->init_tx_desc(&priv
->dma_tx
[i
],
1416 (i
== DMA_TX_SIZE
- 1));
1419 netdev_reset_queue(priv
->dev
);
1420 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1422 priv
->dev
->stats
.tx_errors
++;
1423 netif_wake_queue(priv
->dev
);
1427 * stmmac_dma_interrupt - DMA ISR
1428 * @priv: driver private structure
1429 * Description: this is the DMA ISR. It is called by the main ISR.
1430 * It calls the dwmac dma routine and schedule poll method in case of some
1433 static void stmmac_dma_interrupt(struct stmmac_priv
*priv
)
1436 int rxfifosz
= priv
->plat
->rx_fifo_size
;
1438 status
= priv
->hw
->dma
->dma_interrupt(priv
->ioaddr
, &priv
->xstats
);
1439 if (likely((status
& handle_rx
)) || (status
& handle_tx
)) {
1440 if (likely(napi_schedule_prep(&priv
->napi
))) {
1441 stmmac_disable_dma_irq(priv
);
1442 __napi_schedule(&priv
->napi
);
1445 if (unlikely(status
& tx_hard_error_bump_tc
)) {
1446 /* Try to bump up the dma threshold on this failure */
1447 if (unlikely(priv
->xstats
.threshold
!= SF_DMA_MODE
) &&
1450 if (priv
->plat
->force_thresh_dma_mode
)
1451 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, tc
,
1454 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
,
1455 SF_DMA_MODE
, rxfifosz
);
1456 priv
->xstats
.threshold
= tc
;
1458 } else if (unlikely(status
== tx_hard_error
))
1459 stmmac_tx_err(priv
);
1463 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1464 * @priv: driver private structure
1465 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1467 static void stmmac_mmc_setup(struct stmmac_priv
*priv
)
1469 unsigned int mode
= MMC_CNTRL_RESET_ON_READ
| MMC_CNTRL_COUNTER_RESET
|
1470 MMC_CNTRL_PRESET
| MMC_CNTRL_FULL_HALF_PRESET
;
1472 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
)
1473 priv
->mmcaddr
= priv
->ioaddr
+ MMC_GMAC4_OFFSET
;
1475 priv
->mmcaddr
= priv
->ioaddr
+ MMC_GMAC3_X_OFFSET
;
1477 dwmac_mmc_intr_all_mask(priv
->mmcaddr
);
1479 if (priv
->dma_cap
.rmon
) {
1480 dwmac_mmc_ctrl(priv
->mmcaddr
, mode
);
1481 memset(&priv
->mmc
, 0, sizeof(struct stmmac_counters
));
1483 pr_info(" No MAC Management Counters available\n");
1487 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1488 * @priv: driver private structure
1489 * Description: select the Enhanced/Alternate or Normal descriptors.
1490 * In case of Enhanced/Alternate, it checks if the extended descriptors are
1491 * supported by the HW capability register.
1493 static void stmmac_selec_desc_mode(struct stmmac_priv
*priv
)
1495 if (priv
->plat
->enh_desc
) {
1496 pr_info(" Enhanced/Alternate descriptors\n");
1498 /* GMAC older than 3.50 has no extended descriptors */
1499 if (priv
->synopsys_id
>= DWMAC_CORE_3_50
) {
1500 pr_info("\tEnabled extended descriptors\n");
1501 priv
->extend_desc
= 1;
1503 pr_warn("Extended descriptors not supported\n");
1505 priv
->hw
->desc
= &enh_desc_ops
;
1507 pr_info(" Normal descriptors\n");
1508 priv
->hw
->desc
= &ndesc_ops
;
1513 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1514 * @priv: driver private structure
1516 * new GMAC chip generations have a new register to indicate the
1517 * presence of the optional feature/functions.
1518 * This can be also used to override the value passed through the
1519 * platform and necessary for old MAC10/100 and GMAC chips.
1521 static int stmmac_get_hw_features(struct stmmac_priv
*priv
)
1525 if (priv
->hw
->dma
->get_hw_feature
) {
1526 priv
->hw
->dma
->get_hw_feature(priv
->ioaddr
,
1535 * stmmac_check_ether_addr - check if the MAC addr is valid
1536 * @priv: driver private structure
1538 * it is to verify if the MAC address is valid, in case of failures it
1539 * generates a random MAC address
1541 static void stmmac_check_ether_addr(struct stmmac_priv
*priv
)
1543 if (!is_valid_ether_addr(priv
->dev
->dev_addr
)) {
1544 priv
->hw
->mac
->get_umac_addr(priv
->hw
,
1545 priv
->dev
->dev_addr
, 0);
1546 if (!is_valid_ether_addr(priv
->dev
->dev_addr
))
1547 eth_hw_addr_random(priv
->dev
);
1548 pr_info("%s: device MAC address %pM\n", priv
->dev
->name
,
1549 priv
->dev
->dev_addr
);
1554 * stmmac_init_dma_engine - DMA init.
1555 * @priv: driver private structure
1557 * It inits the DMA invoking the specific MAC/GMAC callback.
1558 * Some DMA parameters can be passed from the platform;
1559 * in case of these are not passed a default is kept for the MAC or GMAC.
1561 static int stmmac_init_dma_engine(struct stmmac_priv
*priv
)
1563 int pbl
= DEFAULT_DMA_PBL
, fixed_burst
= 0, aal
= 0;
1564 int mixed_burst
= 0;
1568 if (priv
->plat
->dma_cfg
) {
1569 pbl
= priv
->plat
->dma_cfg
->pbl
;
1570 fixed_burst
= priv
->plat
->dma_cfg
->fixed_burst
;
1571 mixed_burst
= priv
->plat
->dma_cfg
->mixed_burst
;
1572 aal
= priv
->plat
->dma_cfg
->aal
;
1575 if (priv
->extend_desc
&& (priv
->mode
== STMMAC_RING_MODE
))
1578 ret
= priv
->hw
->dma
->reset(priv
->ioaddr
);
1580 dev_err(priv
->device
, "Failed to reset the dma\n");
1584 priv
->hw
->dma
->init(priv
->ioaddr
, pbl
, fixed_burst
, mixed_burst
,
1585 aal
, priv
->dma_tx_phy
, priv
->dma_rx_phy
, atds
);
1587 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
1588 priv
->rx_tail_addr
= priv
->dma_rx_phy
+
1589 (DMA_RX_SIZE
* sizeof(struct dma_desc
));
1590 priv
->hw
->dma
->set_rx_tail_ptr(priv
->ioaddr
, priv
->rx_tail_addr
,
1593 priv
->tx_tail_addr
= priv
->dma_tx_phy
+
1594 (DMA_TX_SIZE
* sizeof(struct dma_desc
));
1595 priv
->hw
->dma
->set_tx_tail_ptr(priv
->ioaddr
, priv
->tx_tail_addr
,
1599 if (priv
->plat
->axi
&& priv
->hw
->dma
->axi
)
1600 priv
->hw
->dma
->axi(priv
->ioaddr
, priv
->plat
->axi
);
1606 * stmmac_tx_timer - mitigation sw timer for tx.
1607 * @data: data pointer
1609 * This is the timer handler to directly invoke the stmmac_tx_clean.
1611 static void stmmac_tx_timer(unsigned long data
)
1613 struct stmmac_priv
*priv
= (struct stmmac_priv
*)data
;
1615 stmmac_tx_clean(priv
);
1619 * stmmac_init_tx_coalesce - init tx mitigation options.
1620 * @priv: driver private structure
1622 * This inits the transmit coalesce parameters: i.e. timer rate,
1623 * timer handler and default threshold used for enabling the
1624 * interrupt on completion bit.
1626 static void stmmac_init_tx_coalesce(struct stmmac_priv
*priv
)
1628 priv
->tx_coal_frames
= STMMAC_TX_FRAMES
;
1629 priv
->tx_coal_timer
= STMMAC_COAL_TX_TIMER
;
1630 init_timer(&priv
->txtimer
);
1631 priv
->txtimer
.expires
= STMMAC_COAL_TIMER(priv
->tx_coal_timer
);
1632 priv
->txtimer
.data
= (unsigned long)priv
;
1633 priv
->txtimer
.function
= stmmac_tx_timer
;
1634 add_timer(&priv
->txtimer
);
1638 * stmmac_hw_setup - setup mac in a usable state.
1639 * @dev : pointer to the device structure.
1641 * this is the main function to setup the HW in a usable state because the
1642 * dma engine is reset, the core registers are configured (e.g. AXI,
1643 * Checksum features, timers). The DMA is ready to start receiving and
1646 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1649 static int stmmac_hw_setup(struct net_device
*dev
, bool init_ptp
)
1651 struct stmmac_priv
*priv
= netdev_priv(dev
);
1654 /* DMA initialization and SW reset */
1655 ret
= stmmac_init_dma_engine(priv
);
1657 pr_err("%s: DMA engine initialization failed\n", __func__
);
1661 /* Copy the MAC addr into the HW */
1662 priv
->hw
->mac
->set_umac_addr(priv
->hw
, dev
->dev_addr
, 0);
1664 /* If required, perform hw setup of the bus. */
1665 if (priv
->plat
->bus_setup
)
1666 priv
->plat
->bus_setup(priv
->ioaddr
);
1668 /* Initialize the MAC Core */
1669 priv
->hw
->mac
->core_init(priv
->hw
, dev
->mtu
);
1671 ret
= priv
->hw
->mac
->rx_ipc(priv
->hw
);
1673 pr_warn(" RX IPC Checksum Offload disabled\n");
1674 priv
->plat
->rx_coe
= STMMAC_RX_COE_NONE
;
1675 priv
->hw
->rx_csum
= 0;
1678 /* Enable the MAC Rx/Tx */
1679 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
)
1680 stmmac_dwmac4_set_mac(priv
->ioaddr
, true);
1682 stmmac_set_mac(priv
->ioaddr
, true);
1684 /* Set the HW DMA mode and the COE */
1685 stmmac_dma_operation_mode(priv
);
1687 stmmac_mmc_setup(priv
);
1690 ret
= stmmac_init_ptp(priv
);
1691 if (ret
&& ret
!= -EOPNOTSUPP
)
1692 pr_warn("%s: failed PTP initialisation\n", __func__
);
1695 #ifdef CONFIG_DEBUG_FS
1696 ret
= stmmac_init_fs(dev
);
1698 pr_warn("%s: failed debugFS registration\n", __func__
);
1700 /* Start the ball rolling... */
1701 pr_debug("%s: DMA RX/TX processes started...\n", dev
->name
);
1702 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1703 priv
->hw
->dma
->start_rx(priv
->ioaddr
);
1705 /* Dump DMA/MAC registers */
1706 if (netif_msg_hw(priv
)) {
1707 priv
->hw
->mac
->dump_regs(priv
->hw
);
1708 priv
->hw
->dma
->dump_regs(priv
->ioaddr
);
1710 priv
->tx_lpi_timer
= STMMAC_DEFAULT_TWT_LS
;
1712 if ((priv
->use_riwt
) && (priv
->hw
->dma
->rx_watchdog
)) {
1713 priv
->rx_riwt
= MAX_DMA_RIWT
;
1714 priv
->hw
->dma
->rx_watchdog(priv
->ioaddr
, MAX_DMA_RIWT
);
1717 if (priv
->pcs
&& priv
->hw
->mac
->ctrl_ane
)
1718 priv
->hw
->mac
->ctrl_ane(priv
->hw
, 0);
1720 /* set TX ring length */
1721 if (priv
->hw
->dma
->set_tx_ring_len
)
1722 priv
->hw
->dma
->set_tx_ring_len(priv
->ioaddr
,
1724 /* set RX ring length */
1725 if (priv
->hw
->dma
->set_rx_ring_len
)
1726 priv
->hw
->dma
->set_rx_ring_len(priv
->ioaddr
,
1730 priv
->hw
->dma
->enable_tso(priv
->ioaddr
, 1, STMMAC_CHAN0
);
1736 * stmmac_open - open entry point of the driver
1737 * @dev : pointer to the device structure.
1739 * This function is the open entry point of the driver.
1741 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1744 static int stmmac_open(struct net_device
*dev
)
1746 struct stmmac_priv
*priv
= netdev_priv(dev
);
1749 stmmac_check_ether_addr(priv
);
1751 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
1752 priv
->pcs
!= STMMAC_PCS_RTBI
) {
1753 ret
= stmmac_init_phy(dev
);
1755 pr_err("%s: Cannot attach to PHY (error: %d)\n",
1761 /* Extra statistics */
1762 memset(&priv
->xstats
, 0, sizeof(struct stmmac_extra_stats
));
1763 priv
->xstats
.threshold
= tc
;
1765 priv
->dma_buf_sz
= STMMAC_ALIGN(buf_sz
);
1766 priv
->rx_copybreak
= STMMAC_RX_COPYBREAK
;
1768 ret
= alloc_dma_desc_resources(priv
);
1770 pr_err("%s: DMA descriptors allocation failed\n", __func__
);
1771 goto dma_desc_error
;
1774 ret
= init_dma_desc_rings(dev
, GFP_KERNEL
);
1776 pr_err("%s: DMA descriptors initialization failed\n", __func__
);
1780 ret
= stmmac_hw_setup(dev
, true);
1782 pr_err("%s: Hw setup failed\n", __func__
);
1786 stmmac_init_tx_coalesce(priv
);
1789 phy_start(priv
->phydev
);
1791 /* Request the IRQ lines */
1792 ret
= request_irq(dev
->irq
, stmmac_interrupt
,
1793 IRQF_SHARED
, dev
->name
, dev
);
1794 if (unlikely(ret
< 0)) {
1795 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1796 __func__
, dev
->irq
, ret
);
1800 /* Request the Wake IRQ in case of another line is used for WoL */
1801 if (priv
->wol_irq
!= dev
->irq
) {
1802 ret
= request_irq(priv
->wol_irq
, stmmac_interrupt
,
1803 IRQF_SHARED
, dev
->name
, dev
);
1804 if (unlikely(ret
< 0)) {
1805 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1806 __func__
, priv
->wol_irq
, ret
);
1811 /* Request the IRQ lines */
1812 if (priv
->lpi_irq
> 0) {
1813 ret
= request_irq(priv
->lpi_irq
, stmmac_interrupt
, IRQF_SHARED
,
1815 if (unlikely(ret
< 0)) {
1816 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1817 __func__
, priv
->lpi_irq
, ret
);
1822 napi_enable(&priv
->napi
);
1823 netif_start_queue(dev
);
1828 if (priv
->wol_irq
!= dev
->irq
)
1829 free_irq(priv
->wol_irq
, dev
);
1831 free_irq(dev
->irq
, dev
);
1834 free_dma_desc_resources(priv
);
1837 phy_disconnect(priv
->phydev
);
1843 * stmmac_release - close entry point of the driver
1844 * @dev : device pointer.
1846 * This is the stop entry point of the driver.
1848 static int stmmac_release(struct net_device
*dev
)
1850 struct stmmac_priv
*priv
= netdev_priv(dev
);
1852 if (priv
->eee_enabled
)
1853 del_timer_sync(&priv
->eee_ctrl_timer
);
1855 /* Stop and disconnect the PHY */
1857 phy_stop(priv
->phydev
);
1858 phy_disconnect(priv
->phydev
);
1859 priv
->phydev
= NULL
;
1862 netif_stop_queue(dev
);
1864 napi_disable(&priv
->napi
);
1866 del_timer_sync(&priv
->txtimer
);
1868 /* Free the IRQ lines */
1869 free_irq(dev
->irq
, dev
);
1870 if (priv
->wol_irq
!= dev
->irq
)
1871 free_irq(priv
->wol_irq
, dev
);
1872 if (priv
->lpi_irq
> 0)
1873 free_irq(priv
->lpi_irq
, dev
);
1875 /* Stop TX/RX DMA and clear the descriptors */
1876 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1877 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
1879 /* Release and free the Rx/Tx resources */
1880 free_dma_desc_resources(priv
);
1882 /* Disable the MAC Rx/Tx */
1883 stmmac_set_mac(priv
->ioaddr
, false);
1885 netif_carrier_off(dev
);
1887 #ifdef CONFIG_DEBUG_FS
1888 stmmac_exit_fs(dev
);
1891 stmmac_release_ptp(priv
);
1897 * stmmac_tso_allocator - close entry point of the driver
1898 * @priv: driver private structure
1899 * @des: buffer start address
1900 * @total_len: total length to fill in descriptors
1901 * @last_segmant: condition for the last descriptor
1903 * This function fills descriptor and request new descriptors according to
1904 * buffer length to fill
1906 static void stmmac_tso_allocator(struct stmmac_priv
*priv
, unsigned int des
,
1907 int total_len
, bool last_segment
)
1909 struct dma_desc
*desc
;
1913 tmp_len
= total_len
;
1915 while (tmp_len
> 0) {
1916 priv
->cur_tx
= STMMAC_GET_ENTRY(priv
->cur_tx
, DMA_TX_SIZE
);
1917 desc
= priv
->dma_tx
+ priv
->cur_tx
;
1919 desc
->des0
= des
+ (total_len
- tmp_len
);
1920 buff_size
= tmp_len
>= TSO_MAX_BUFF_SIZE
?
1921 TSO_MAX_BUFF_SIZE
: tmp_len
;
1923 priv
->hw
->desc
->prepare_tso_tx_desc(desc
, 0, buff_size
,
1925 (last_segment
) && (buff_size
< TSO_MAX_BUFF_SIZE
),
1928 tmp_len
-= TSO_MAX_BUFF_SIZE
;
1933 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
1934 * @skb : the socket buffer
1935 * @dev : device pointer
1936 * Description: this is the transmit function that is called on TSO frames
1937 * (support available on GMAC4 and newer chips).
1938 * Diagram below show the ring programming in case of TSO frames:
1942 * | DES0 |---> buffer1 = L2/L3/L4 header
1943 * | DES1 |---> TCP Payload (can continue on next descr...)
1944 * | DES2 |---> buffer 1 and 2 len
1945 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
1951 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
1953 * | DES2 | --> buffer 1 and 2 len
1957 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
1959 static netdev_tx_t
stmmac_tso_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1962 int tmp_pay_len
= 0;
1963 struct stmmac_priv
*priv
= netdev_priv(dev
);
1964 int nfrags
= skb_shinfo(skb
)->nr_frags
;
1965 unsigned int first_entry
, des
;
1966 struct dma_desc
*desc
, *first
, *mss_desc
= NULL
;
1970 spin_lock(&priv
->tx_lock
);
1972 /* Compute header lengths */
1973 proto_hdr_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
);
1975 /* Desc availability based on threshold should be enough safe */
1976 if (unlikely(stmmac_tx_avail(priv
) <
1977 (((skb
->len
- proto_hdr_len
) / TSO_MAX_BUFF_SIZE
+ 1)))) {
1978 if (!netif_queue_stopped(dev
)) {
1979 netif_stop_queue(dev
);
1980 /* This is a hard error, log it. */
1981 pr_err("%s: Tx Ring full when queue awake\n", __func__
);
1983 spin_unlock(&priv
->tx_lock
);
1984 return NETDEV_TX_BUSY
;
1987 pay_len
= skb_headlen(skb
) - proto_hdr_len
; /* no frags */
1989 mss
= skb_shinfo(skb
)->gso_size
;
1991 /* set new MSS value if needed */
1992 if (mss
!= priv
->mss
) {
1993 mss_desc
= priv
->dma_tx
+ priv
->cur_tx
;
1994 priv
->hw
->desc
->set_mss(mss_desc
, mss
);
1996 priv
->cur_tx
= STMMAC_GET_ENTRY(priv
->cur_tx
, DMA_TX_SIZE
);
1999 if (netif_msg_tx_queued(priv
)) {
2000 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2001 __func__
, tcp_hdrlen(skb
), proto_hdr_len
, pay_len
, mss
);
2002 pr_info("\tskb->len %d, skb->data_len %d\n", skb
->len
,
2006 first_entry
= priv
->cur_tx
;
2008 desc
= priv
->dma_tx
+ first_entry
;
2011 /* first descriptor: fill Headers on Buf1 */
2012 des
= dma_map_single(priv
->device
, skb
->data
, skb_headlen(skb
),
2014 if (dma_mapping_error(priv
->device
, des
))
2017 priv
->tx_skbuff_dma
[first_entry
].buf
= des
;
2018 priv
->tx_skbuff_dma
[first_entry
].len
= skb_headlen(skb
);
2019 priv
->tx_skbuff
[first_entry
] = skb
;
2023 /* Fill start of payload in buff2 of first descriptor */
2025 first
->des1
= des
+ proto_hdr_len
;
2027 /* If needed take extra descriptors to fill the remaining payload */
2028 tmp_pay_len
= pay_len
- TSO_MAX_BUFF_SIZE
;
2030 stmmac_tso_allocator(priv
, des
, tmp_pay_len
, (nfrags
== 0));
2032 /* Prepare fragments */
2033 for (i
= 0; i
< nfrags
; i
++) {
2034 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2036 des
= skb_frag_dma_map(priv
->device
, frag
, 0,
2037 skb_frag_size(frag
),
2040 stmmac_tso_allocator(priv
, des
, skb_frag_size(frag
),
2043 priv
->tx_skbuff_dma
[priv
->cur_tx
].buf
= des
;
2044 priv
->tx_skbuff_dma
[priv
->cur_tx
].len
= skb_frag_size(frag
);
2045 priv
->tx_skbuff
[priv
->cur_tx
] = NULL
;
2046 priv
->tx_skbuff_dma
[priv
->cur_tx
].map_as_page
= true;
2049 priv
->tx_skbuff_dma
[priv
->cur_tx
].last_segment
= true;
2051 priv
->cur_tx
= STMMAC_GET_ENTRY(priv
->cur_tx
, DMA_TX_SIZE
);
2053 if (unlikely(stmmac_tx_avail(priv
) <= (MAX_SKB_FRAGS
+ 1))) {
2054 if (netif_msg_hw(priv
))
2055 pr_debug("%s: stop transmitted packets\n", __func__
);
2056 netif_stop_queue(dev
);
2059 dev
->stats
.tx_bytes
+= skb
->len
;
2060 priv
->xstats
.tx_tso_frames
++;
2061 priv
->xstats
.tx_tso_nfrags
+= nfrags
;
2063 /* Manage tx mitigation */
2064 priv
->tx_count_frames
+= nfrags
+ 1;
2065 if (likely(priv
->tx_coal_frames
> priv
->tx_count_frames
)) {
2066 mod_timer(&priv
->txtimer
,
2067 STMMAC_COAL_TIMER(priv
->tx_coal_timer
));
2069 priv
->tx_count_frames
= 0;
2070 priv
->hw
->desc
->set_tx_ic(desc
);
2071 priv
->xstats
.tx_set_ic_bit
++;
2074 if (!priv
->hwts_tx_en
)
2075 skb_tx_timestamp(skb
);
2077 if (unlikely((skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) &&
2078 priv
->hwts_tx_en
)) {
2079 /* declare that device is doing timestamping */
2080 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
2081 priv
->hw
->desc
->enable_tx_timestamp(first
);
2084 /* Complete the first descriptor before granting the DMA */
2085 priv
->hw
->desc
->prepare_tso_tx_desc(first
, 1,
2088 1, priv
->tx_skbuff_dma
[first_entry
].last_segment
,
2089 tcp_hdrlen(skb
) / 4, (skb
->len
- proto_hdr_len
));
2091 /* If context desc is used to change MSS */
2093 priv
->hw
->desc
->set_tx_owner(mss_desc
);
2095 /* The own bit must be the latest setting done when prepare the
2096 * descriptor and then barrier is needed to make sure that
2097 * all is coherent before granting the DMA engine.
2101 if (netif_msg_pktdata(priv
)) {
2102 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2103 __func__
, priv
->cur_tx
, priv
->dirty_tx
, first_entry
,
2104 priv
->cur_tx
, first
, nfrags
);
2106 priv
->hw
->desc
->display_ring((void *)priv
->dma_tx
, DMA_TX_SIZE
,
2109 pr_info(">>> frame to be transmitted: ");
2110 print_pkt(skb
->data
, skb_headlen(skb
));
2113 netdev_sent_queue(dev
, skb
->len
);
2115 priv
->hw
->dma
->set_tx_tail_ptr(priv
->ioaddr
, priv
->tx_tail_addr
,
2118 spin_unlock(&priv
->tx_lock
);
2119 return NETDEV_TX_OK
;
2122 spin_unlock(&priv
->tx_lock
);
2123 dev_err(priv
->device
, "Tx dma map failed\n");
2125 priv
->dev
->stats
.tx_dropped
++;
2126 return NETDEV_TX_OK
;
2130 * stmmac_xmit - Tx entry point of the driver
2131 * @skb : the socket buffer
2132 * @dev : device pointer
2133 * Description : this is the tx entry point of the driver.
2134 * It programs the chain or the ring and supports oversized frames
2137 static netdev_tx_t
stmmac_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2139 struct stmmac_priv
*priv
= netdev_priv(dev
);
2140 unsigned int nopaged_len
= skb_headlen(skb
);
2141 int i
, csum_insertion
= 0, is_jumbo
= 0;
2142 int nfrags
= skb_shinfo(skb
)->nr_frags
;
2143 unsigned int entry
, first_entry
;
2144 struct dma_desc
*desc
, *first
;
2145 unsigned int enh_desc
;
2148 /* Manage oversized TCP frames for GMAC4 device */
2149 if (skb_is_gso(skb
) && priv
->tso
) {
2150 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
2151 return stmmac_tso_xmit(skb
, dev
);
2154 spin_lock(&priv
->tx_lock
);
2156 if (unlikely(stmmac_tx_avail(priv
) < nfrags
+ 1)) {
2157 spin_unlock(&priv
->tx_lock
);
2158 if (!netif_queue_stopped(dev
)) {
2159 netif_stop_queue(dev
);
2160 /* This is a hard error, log it. */
2161 pr_err("%s: Tx Ring full when queue awake\n", __func__
);
2163 return NETDEV_TX_BUSY
;
2166 if (priv
->tx_path_in_lpi_mode
)
2167 stmmac_disable_eee_mode(priv
);
2169 entry
= priv
->cur_tx
;
2170 first_entry
= entry
;
2172 csum_insertion
= (skb
->ip_summed
== CHECKSUM_PARTIAL
);
2174 if (likely(priv
->extend_desc
))
2175 desc
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
2177 desc
= priv
->dma_tx
+ entry
;
2181 priv
->tx_skbuff
[first_entry
] = skb
;
2183 enh_desc
= priv
->plat
->enh_desc
;
2184 /* To program the descriptors according to the size of the frame */
2186 is_jumbo
= priv
->hw
->mode
->is_jumbo_frm(skb
->len
, enh_desc
);
2188 if (unlikely(is_jumbo
) && likely(priv
->synopsys_id
<
2190 entry
= priv
->hw
->mode
->jumbo_frm(priv
, skb
, csum_insertion
);
2191 if (unlikely(entry
< 0))
2195 for (i
= 0; i
< nfrags
; i
++) {
2196 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2197 int len
= skb_frag_size(frag
);
2198 bool last_segment
= (i
== (nfrags
- 1));
2200 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
2202 if (likely(priv
->extend_desc
))
2203 desc
= (struct dma_desc
*)(priv
->dma_etx
+ entry
);
2205 desc
= priv
->dma_tx
+ entry
;
2207 des
= skb_frag_dma_map(priv
->device
, frag
, 0, len
,
2209 if (dma_mapping_error(priv
->device
, des
))
2210 goto dma_map_err
; /* should reuse desc w/o issues */
2212 priv
->tx_skbuff
[entry
] = NULL
;
2214 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
)) {
2216 priv
->tx_skbuff_dma
[entry
].buf
= desc
->des0
;
2219 priv
->tx_skbuff_dma
[entry
].buf
= desc
->des2
;
2222 priv
->tx_skbuff_dma
[entry
].map_as_page
= true;
2223 priv
->tx_skbuff_dma
[entry
].len
= len
;
2224 priv
->tx_skbuff_dma
[entry
].last_segment
= last_segment
;
2226 /* Prepare the descriptor and set the own bit too */
2227 priv
->hw
->desc
->prepare_tx_desc(desc
, 0, len
, csum_insertion
,
2228 priv
->mode
, 1, last_segment
);
2231 entry
= STMMAC_GET_ENTRY(entry
, DMA_TX_SIZE
);
2233 priv
->cur_tx
= entry
;
2235 if (netif_msg_pktdata(priv
)) {
2238 pr_debug("%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
2239 __func__
, priv
->cur_tx
, priv
->dirty_tx
, first_entry
,
2240 entry
, first
, nfrags
);
2242 if (priv
->extend_desc
)
2243 tx_head
= (void *)priv
->dma_etx
;
2245 tx_head
= (void *)priv
->dma_tx
;
2247 priv
->hw
->desc
->display_ring(tx_head
, DMA_TX_SIZE
, false);
2249 pr_debug(">>> frame to be transmitted: ");
2250 print_pkt(skb
->data
, skb
->len
);
2253 if (unlikely(stmmac_tx_avail(priv
) <= (MAX_SKB_FRAGS
+ 1))) {
2254 if (netif_msg_hw(priv
))
2255 pr_debug("%s: stop transmitted packets\n", __func__
);
2256 netif_stop_queue(dev
);
2259 dev
->stats
.tx_bytes
+= skb
->len
;
2261 /* According to the coalesce parameter the IC bit for the latest
2262 * segment is reset and the timer re-started to clean the tx status.
2263 * This approach takes care about the fragments: desc is the first
2264 * element in case of no SG.
2266 priv
->tx_count_frames
+= nfrags
+ 1;
2267 if (likely(priv
->tx_coal_frames
> priv
->tx_count_frames
)) {
2268 mod_timer(&priv
->txtimer
,
2269 STMMAC_COAL_TIMER(priv
->tx_coal_timer
));
2271 priv
->tx_count_frames
= 0;
2272 priv
->hw
->desc
->set_tx_ic(desc
);
2273 priv
->xstats
.tx_set_ic_bit
++;
2276 if (!priv
->hwts_tx_en
)
2277 skb_tx_timestamp(skb
);
2279 /* Ready to fill the first descriptor and set the OWN bit w/o any
2280 * problems because all the descriptors are actually ready to be
2281 * passed to the DMA engine.
2283 if (likely(!is_jumbo
)) {
2284 bool last_segment
= (nfrags
== 0);
2286 des
= dma_map_single(priv
->device
, skb
->data
,
2287 nopaged_len
, DMA_TO_DEVICE
);
2288 if (dma_mapping_error(priv
->device
, des
))
2291 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
)) {
2293 priv
->tx_skbuff_dma
[first_entry
].buf
= first
->des0
;
2296 priv
->tx_skbuff_dma
[first_entry
].buf
= first
->des2
;
2299 priv
->tx_skbuff_dma
[first_entry
].len
= nopaged_len
;
2300 priv
->tx_skbuff_dma
[first_entry
].last_segment
= last_segment
;
2302 if (unlikely((skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
) &&
2303 priv
->hwts_tx_en
)) {
2304 /* declare that device is doing timestamping */
2305 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
2306 priv
->hw
->desc
->enable_tx_timestamp(first
);
2309 /* Prepare the first descriptor setting the OWN bit too */
2310 priv
->hw
->desc
->prepare_tx_desc(first
, 1, nopaged_len
,
2311 csum_insertion
, priv
->mode
, 1,
2314 /* The own bit must be the latest setting done when prepare the
2315 * descriptor and then barrier is needed to make sure that
2316 * all is coherent before granting the DMA engine.
2321 netdev_sent_queue(dev
, skb
->len
);
2323 if (priv
->synopsys_id
< DWMAC_CORE_4_00
)
2324 priv
->hw
->dma
->enable_dma_transmission(priv
->ioaddr
);
2326 priv
->hw
->dma
->set_tx_tail_ptr(priv
->ioaddr
, priv
->tx_tail_addr
,
2329 spin_unlock(&priv
->tx_lock
);
2330 return NETDEV_TX_OK
;
2333 spin_unlock(&priv
->tx_lock
);
2334 dev_err(priv
->device
, "Tx dma map failed\n");
2336 priv
->dev
->stats
.tx_dropped
++;
2337 return NETDEV_TX_OK
;
2340 static void stmmac_rx_vlan(struct net_device
*dev
, struct sk_buff
*skb
)
2342 struct ethhdr
*ehdr
;
2345 if ((dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
) ==
2346 NETIF_F_HW_VLAN_CTAG_RX
&&
2347 !__vlan_get_tag(skb
, &vlanid
)) {
2348 /* pop the vlan tag */
2349 ehdr
= (struct ethhdr
*)skb
->data
;
2350 memmove(skb
->data
+ VLAN_HLEN
, ehdr
, ETH_ALEN
* 2);
2351 skb_pull(skb
, VLAN_HLEN
);
2352 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
), vlanid
);
2357 static inline int stmmac_rx_threshold_count(struct stmmac_priv
*priv
)
2359 if (priv
->rx_zeroc_thresh
< STMMAC_RX_THRESH
)
2366 * stmmac_rx_refill - refill used skb preallocated buffers
2367 * @priv: driver private structure
2368 * Description : this is to reallocate the skb for the reception process
2369 * that is based on zero-copy.
2371 static inline void stmmac_rx_refill(struct stmmac_priv
*priv
)
2373 int bfsize
= priv
->dma_buf_sz
;
2374 unsigned int entry
= priv
->dirty_rx
;
2375 int dirty
= stmmac_rx_dirty(priv
);
2377 while (dirty
-- > 0) {
2380 if (priv
->extend_desc
)
2381 p
= (struct dma_desc
*)(priv
->dma_erx
+ entry
);
2383 p
= priv
->dma_rx
+ entry
;
2385 if (likely(priv
->rx_skbuff
[entry
] == NULL
)) {
2386 struct sk_buff
*skb
;
2388 skb
= netdev_alloc_skb_ip_align(priv
->dev
, bfsize
);
2389 if (unlikely(!skb
)) {
2390 /* so for a while no zero-copy! */
2391 priv
->rx_zeroc_thresh
= STMMAC_RX_THRESH
;
2392 if (unlikely(net_ratelimit()))
2393 dev_err(priv
->device
,
2394 "fail to alloc skb entry %d\n",
2399 priv
->rx_skbuff
[entry
] = skb
;
2400 priv
->rx_skbuff_dma
[entry
] =
2401 dma_map_single(priv
->device
, skb
->data
, bfsize
,
2403 if (dma_mapping_error(priv
->device
,
2404 priv
->rx_skbuff_dma
[entry
])) {
2405 dev_err(priv
->device
, "Rx dma map failed\n");
2410 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
)) {
2411 p
->des0
= priv
->rx_skbuff_dma
[entry
];
2414 p
->des2
= priv
->rx_skbuff_dma
[entry
];
2416 if (priv
->hw
->mode
->refill_desc3
)
2417 priv
->hw
->mode
->refill_desc3(priv
, p
);
2419 if (priv
->rx_zeroc_thresh
> 0)
2420 priv
->rx_zeroc_thresh
--;
2422 if (netif_msg_rx_status(priv
))
2423 pr_debug("\trefill entry #%d\n", entry
);
2427 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
))
2428 priv
->hw
->desc
->init_rx_desc(p
, priv
->use_riwt
, 0, 0);
2430 priv
->hw
->desc
->set_rx_owner(p
);
2434 entry
= STMMAC_GET_ENTRY(entry
, DMA_RX_SIZE
);
2436 priv
->dirty_rx
= entry
;
2440 * stmmac_rx - manage the receive process
2441 * @priv: driver private structure
2442 * @limit: napi bugget.
2443 * Description : this the function called by the napi poll method.
2444 * It gets all the frames inside the ring.
2446 static int stmmac_rx(struct stmmac_priv
*priv
, int limit
)
2448 unsigned int entry
= priv
->cur_rx
;
2449 unsigned int next_entry
;
2450 unsigned int count
= 0;
2451 int coe
= priv
->hw
->rx_csum
;
2453 if (netif_msg_rx_status(priv
)) {
2456 pr_debug("%s: descriptor ring:\n", __func__
);
2457 if (priv
->extend_desc
)
2458 rx_head
= (void *)priv
->dma_erx
;
2460 rx_head
= (void *)priv
->dma_rx
;
2462 priv
->hw
->desc
->display_ring(rx_head
, DMA_RX_SIZE
, true);
2464 while (count
< limit
) {
2468 if (priv
->extend_desc
)
2469 p
= (struct dma_desc
*)(priv
->dma_erx
+ entry
);
2471 p
= priv
->dma_rx
+ entry
;
2473 /* read the status of the incoming frame */
2474 status
= priv
->hw
->desc
->rx_status(&priv
->dev
->stats
,
2476 /* check if managed by the DMA otherwise go ahead */
2477 if (unlikely(status
& dma_own
))
2482 priv
->cur_rx
= STMMAC_GET_ENTRY(priv
->cur_rx
, DMA_RX_SIZE
);
2483 next_entry
= priv
->cur_rx
;
2485 if (priv
->extend_desc
)
2486 prefetch(priv
->dma_erx
+ next_entry
);
2488 prefetch(priv
->dma_rx
+ next_entry
);
2490 if ((priv
->extend_desc
) && (priv
->hw
->desc
->rx_extended_status
))
2491 priv
->hw
->desc
->rx_extended_status(&priv
->dev
->stats
,
2495 if (unlikely(status
== discard_frame
)) {
2496 priv
->dev
->stats
.rx_errors
++;
2497 if (priv
->hwts_rx_en
&& !priv
->extend_desc
) {
2498 /* DESC2 & DESC3 will be overwitten by device
2499 * with timestamp value, hence reinitialize
2500 * them in stmmac_rx_refill() function so that
2501 * device can reuse it.
2503 priv
->rx_skbuff
[entry
] = NULL
;
2504 dma_unmap_single(priv
->device
,
2505 priv
->rx_skbuff_dma
[entry
],
2510 struct sk_buff
*skb
;
2514 if (unlikely(priv
->synopsys_id
>= DWMAC_CORE_4_00
))
2519 frame_len
= priv
->hw
->desc
->get_rx_frame_len(p
, coe
);
2521 /* If frame length is greather than skb buffer size
2522 * (preallocated during init) then the packet is
2525 if (frame_len
> priv
->dma_buf_sz
) {
2526 pr_err("%s: len %d larger than size (%d)\n",
2527 priv
->dev
->name
, frame_len
,
2529 priv
->dev
->stats
.rx_length_errors
++;
2533 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2534 * Type frames (LLC/LLC-SNAP)
2536 if (unlikely(status
!= llc_snap
))
2537 frame_len
-= ETH_FCS_LEN
;
2539 if (netif_msg_rx_status(priv
)) {
2540 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2542 if (frame_len
> ETH_FRAME_LEN
)
2543 pr_debug("\tframe size %d, COE: %d\n",
2547 /* The zero-copy is always used for all the sizes
2548 * in case of GMAC4 because it needs
2549 * to refill the used descriptors, always.
2551 if (unlikely(!priv
->plat
->has_gmac4
&&
2552 ((frame_len
< priv
->rx_copybreak
) ||
2553 stmmac_rx_threshold_count(priv
)))) {
2554 skb
= netdev_alloc_skb_ip_align(priv
->dev
,
2556 if (unlikely(!skb
)) {
2557 if (net_ratelimit())
2558 dev_warn(priv
->device
,
2559 "packet dropped\n");
2560 priv
->dev
->stats
.rx_dropped
++;
2564 dma_sync_single_for_cpu(priv
->device
,
2568 skb_copy_to_linear_data(skb
,
2570 rx_skbuff
[entry
]->data
,
2573 skb_put(skb
, frame_len
);
2574 dma_sync_single_for_device(priv
->device
,
2579 skb
= priv
->rx_skbuff
[entry
];
2580 if (unlikely(!skb
)) {
2581 pr_err("%s: Inconsistent Rx chain\n",
2583 priv
->dev
->stats
.rx_dropped
++;
2586 prefetch(skb
->data
- NET_IP_ALIGN
);
2587 priv
->rx_skbuff
[entry
] = NULL
;
2588 priv
->rx_zeroc_thresh
++;
2590 skb_put(skb
, frame_len
);
2591 dma_unmap_single(priv
->device
,
2592 priv
->rx_skbuff_dma
[entry
],
2597 stmmac_get_rx_hwtstamp(priv
, entry
, skb
);
2599 if (netif_msg_pktdata(priv
)) {
2600 pr_debug("frame received (%dbytes)", frame_len
);
2601 print_pkt(skb
->data
, frame_len
);
2604 stmmac_rx_vlan(priv
->dev
, skb
);
2606 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
2609 skb_checksum_none_assert(skb
);
2611 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2613 napi_gro_receive(&priv
->napi
, skb
);
2615 priv
->dev
->stats
.rx_packets
++;
2616 priv
->dev
->stats
.rx_bytes
+= frame_len
;
2621 stmmac_rx_refill(priv
);
2623 priv
->xstats
.rx_pkt_n
+= count
;
2629 * stmmac_poll - stmmac poll method (NAPI)
2630 * @napi : pointer to the napi structure.
2631 * @budget : maximum number of packets that the current CPU can receive from
2634 * To look at the incoming frames and clear the tx resources.
2636 static int stmmac_poll(struct napi_struct
*napi
, int budget
)
2638 struct stmmac_priv
*priv
= container_of(napi
, struct stmmac_priv
, napi
);
2641 priv
->xstats
.napi_poll
++;
2642 stmmac_tx_clean(priv
);
2644 work_done
= stmmac_rx(priv
, budget
);
2645 if (work_done
< budget
) {
2646 napi_complete(napi
);
2647 stmmac_enable_dma_irq(priv
);
2654 * @dev : Pointer to net device structure
2655 * Description: this function is called when a packet transmission fails to
2656 * complete within a reasonable time. The driver will mark the error in the
2657 * netdev structure and arrange for the device to be reset to a sane state
2658 * in order to transmit a new packet.
2660 static void stmmac_tx_timeout(struct net_device
*dev
)
2662 struct stmmac_priv
*priv
= netdev_priv(dev
);
2664 /* Clear Tx resources and restart transmitting again */
2665 stmmac_tx_err(priv
);
2669 * stmmac_set_rx_mode - entry point for multicast addressing
2670 * @dev : pointer to the device structure
2672 * This function is a driver entry point which gets called by the kernel
2673 * whenever multicast addresses must be enabled/disabled.
2677 static void stmmac_set_rx_mode(struct net_device
*dev
)
2679 struct stmmac_priv
*priv
= netdev_priv(dev
);
2681 priv
->hw
->mac
->set_filter(priv
->hw
, dev
);
2685 * stmmac_change_mtu - entry point to change MTU size for the device.
2686 * @dev : device pointer.
2687 * @new_mtu : the new MTU size for the device.
2688 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
2689 * to drive packet transmission. Ethernet has an MTU of 1500 octets
2690 * (ETH_DATA_LEN). This value can be changed with ifconfig.
2692 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2695 static int stmmac_change_mtu(struct net_device
*dev
, int new_mtu
)
2697 struct stmmac_priv
*priv
= netdev_priv(dev
);
2700 if (netif_running(dev
)) {
2701 pr_err("%s: must be stopped to change its MTU\n", dev
->name
);
2705 if ((priv
->plat
->enh_desc
) || (priv
->synopsys_id
>= DWMAC_CORE_4_00
))
2706 max_mtu
= JUMBO_LEN
;
2708 max_mtu
= SKB_MAX_HEAD(NET_SKB_PAD
+ NET_IP_ALIGN
);
2710 if (priv
->plat
->maxmtu
< max_mtu
)
2711 max_mtu
= priv
->plat
->maxmtu
;
2713 if ((new_mtu
< 46) || (new_mtu
> max_mtu
)) {
2714 pr_err("%s: invalid MTU, max MTU is: %d\n", dev
->name
, max_mtu
);
2720 netdev_update_features(dev
);
2725 static netdev_features_t
stmmac_fix_features(struct net_device
*dev
,
2726 netdev_features_t features
)
2728 struct stmmac_priv
*priv
= netdev_priv(dev
);
2730 if (priv
->plat
->rx_coe
== STMMAC_RX_COE_NONE
)
2731 features
&= ~NETIF_F_RXCSUM
;
2733 if (!priv
->plat
->tx_coe
)
2734 features
&= ~NETIF_F_CSUM_MASK
;
2736 /* Some GMAC devices have a bugged Jumbo frame support that
2737 * needs to have the Tx COE disabled for oversized frames
2738 * (due to limited buffer sizes). In this case we disable
2739 * the TX csum insertionin the TDES and not use SF.
2741 if (priv
->plat
->bugged_jumbo
&& (dev
->mtu
> ETH_DATA_LEN
))
2742 features
&= ~NETIF_F_CSUM_MASK
;
2744 /* Disable tso if asked by ethtool */
2745 if ((priv
->plat
->tso_en
) && (priv
->dma_cap
.tsoen
)) {
2746 if (features
& NETIF_F_TSO
)
2755 static int stmmac_set_features(struct net_device
*netdev
,
2756 netdev_features_t features
)
2758 struct stmmac_priv
*priv
= netdev_priv(netdev
);
2760 /* Keep the COE Type in case of csum is supporting */
2761 if (features
& NETIF_F_RXCSUM
)
2762 priv
->hw
->rx_csum
= priv
->plat
->rx_coe
;
2764 priv
->hw
->rx_csum
= 0;
2765 /* No check needed because rx_coe has been set before and it will be
2766 * fixed in case of issue.
2768 priv
->hw
->mac
->rx_ipc(priv
->hw
);
2774 * stmmac_interrupt - main ISR
2775 * @irq: interrupt number.
2776 * @dev_id: to pass the net device pointer.
2777 * Description: this is the main driver interrupt service routine.
2779 * o DMA service routine (to manage incoming frame reception and transmission
2781 * o Core interrupts to manage: remote wake-up, management counter, LPI
2784 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
)
2786 struct net_device
*dev
= (struct net_device
*)dev_id
;
2787 struct stmmac_priv
*priv
= netdev_priv(dev
);
2790 pm_wakeup_event(priv
->device
, 0);
2792 if (unlikely(!dev
)) {
2793 pr_err("%s: invalid dev pointer\n", __func__
);
2797 /* To handle GMAC own interrupts */
2798 if ((priv
->plat
->has_gmac
) || (priv
->plat
->has_gmac4
)) {
2799 int status
= priv
->hw
->mac
->host_irq_status(priv
->hw
,
2801 if (unlikely(status
)) {
2802 /* For LPI we need to save the tx status */
2803 if (status
& CORE_IRQ_TX_PATH_IN_LPI_MODE
)
2804 priv
->tx_path_in_lpi_mode
= true;
2805 if (status
& CORE_IRQ_TX_PATH_EXIT_LPI_MODE
)
2806 priv
->tx_path_in_lpi_mode
= false;
2807 if (status
& CORE_IRQ_MTL_RX_OVERFLOW
)
2808 priv
->hw
->dma
->set_rx_tail_ptr(priv
->ioaddr
,
2814 /* To handle DMA interrupts */
2815 stmmac_dma_interrupt(priv
);
2820 #ifdef CONFIG_NET_POLL_CONTROLLER
2821 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2822 * to allow network I/O with interrupts disabled.
2824 static void stmmac_poll_controller(struct net_device
*dev
)
2826 disable_irq(dev
->irq
);
2827 stmmac_interrupt(dev
->irq
, dev
);
2828 enable_irq(dev
->irq
);
2833 * stmmac_ioctl - Entry point for the Ioctl
2834 * @dev: Device pointer.
2835 * @rq: An IOCTL specefic structure, that can contain a pointer to
2836 * a proprietary structure used to pass information to the driver.
2837 * @cmd: IOCTL command
2839 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2841 static int stmmac_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2843 struct stmmac_priv
*priv
= netdev_priv(dev
);
2844 int ret
= -EOPNOTSUPP
;
2846 if (!netif_running(dev
))
2855 ret
= phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
2858 ret
= stmmac_hwtstamp_ioctl(dev
, rq
);
2867 #ifdef CONFIG_DEBUG_FS
2868 static struct dentry
*stmmac_fs_dir
;
2870 static void sysfs_display_ring(void *head
, int size
, int extend_desc
,
2871 struct seq_file
*seq
)
2874 struct dma_extended_desc
*ep
= (struct dma_extended_desc
*)head
;
2875 struct dma_desc
*p
= (struct dma_desc
*)head
;
2877 for (i
= 0; i
< size
; i
++) {
2881 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2882 i
, (unsigned int)virt_to_phys(ep
),
2883 ep
->basic
.des0
, ep
->basic
.des1
,
2884 ep
->basic
.des2
, ep
->basic
.des3
);
2888 seq_printf(seq
, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2889 i
, (unsigned int)virt_to_phys(ep
),
2890 p
->des0
, p
->des1
, p
->des2
, p
->des3
);
2893 seq_printf(seq
, "\n");
2897 static int stmmac_sysfs_ring_read(struct seq_file
*seq
, void *v
)
2899 struct net_device
*dev
= seq
->private;
2900 struct stmmac_priv
*priv
= netdev_priv(dev
);
2902 if (priv
->extend_desc
) {
2903 seq_printf(seq
, "Extended RX descriptor ring:\n");
2904 sysfs_display_ring((void *)priv
->dma_erx
, DMA_RX_SIZE
, 1, seq
);
2905 seq_printf(seq
, "Extended TX descriptor ring:\n");
2906 sysfs_display_ring((void *)priv
->dma_etx
, DMA_TX_SIZE
, 1, seq
);
2908 seq_printf(seq
, "RX descriptor ring:\n");
2909 sysfs_display_ring((void *)priv
->dma_rx
, DMA_RX_SIZE
, 0, seq
);
2910 seq_printf(seq
, "TX descriptor ring:\n");
2911 sysfs_display_ring((void *)priv
->dma_tx
, DMA_TX_SIZE
, 0, seq
);
2917 static int stmmac_sysfs_ring_open(struct inode
*inode
, struct file
*file
)
2919 return single_open(file
, stmmac_sysfs_ring_read
, inode
->i_private
);
2922 static const struct file_operations stmmac_rings_status_fops
= {
2923 .owner
= THIS_MODULE
,
2924 .open
= stmmac_sysfs_ring_open
,
2926 .llseek
= seq_lseek
,
2927 .release
= single_release
,
2930 static int stmmac_sysfs_dma_cap_read(struct seq_file
*seq
, void *v
)
2932 struct net_device
*dev
= seq
->private;
2933 struct stmmac_priv
*priv
= netdev_priv(dev
);
2935 if (!priv
->hw_cap_support
) {
2936 seq_printf(seq
, "DMA HW features not supported\n");
2940 seq_printf(seq
, "==============================\n");
2941 seq_printf(seq
, "\tDMA HW features\n");
2942 seq_printf(seq
, "==============================\n");
2944 seq_printf(seq
, "\t10/100 Mbps %s\n",
2945 (priv
->dma_cap
.mbps_10_100
) ? "Y" : "N");
2946 seq_printf(seq
, "\t1000 Mbps %s\n",
2947 (priv
->dma_cap
.mbps_1000
) ? "Y" : "N");
2948 seq_printf(seq
, "\tHalf duple %s\n",
2949 (priv
->dma_cap
.half_duplex
) ? "Y" : "N");
2950 seq_printf(seq
, "\tHash Filter: %s\n",
2951 (priv
->dma_cap
.hash_filter
) ? "Y" : "N");
2952 seq_printf(seq
, "\tMultiple MAC address registers: %s\n",
2953 (priv
->dma_cap
.multi_addr
) ? "Y" : "N");
2954 seq_printf(seq
, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2955 (priv
->dma_cap
.pcs
) ? "Y" : "N");
2956 seq_printf(seq
, "\tSMA (MDIO) Interface: %s\n",
2957 (priv
->dma_cap
.sma_mdio
) ? "Y" : "N");
2958 seq_printf(seq
, "\tPMT Remote wake up: %s\n",
2959 (priv
->dma_cap
.pmt_remote_wake_up
) ? "Y" : "N");
2960 seq_printf(seq
, "\tPMT Magic Frame: %s\n",
2961 (priv
->dma_cap
.pmt_magic_frame
) ? "Y" : "N");
2962 seq_printf(seq
, "\tRMON module: %s\n",
2963 (priv
->dma_cap
.rmon
) ? "Y" : "N");
2964 seq_printf(seq
, "\tIEEE 1588-2002 Time Stamp: %s\n",
2965 (priv
->dma_cap
.time_stamp
) ? "Y" : "N");
2966 seq_printf(seq
, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2967 (priv
->dma_cap
.atime_stamp
) ? "Y" : "N");
2968 seq_printf(seq
, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2969 (priv
->dma_cap
.eee
) ? "Y" : "N");
2970 seq_printf(seq
, "\tAV features: %s\n", (priv
->dma_cap
.av
) ? "Y" : "N");
2971 seq_printf(seq
, "\tChecksum Offload in TX: %s\n",
2972 (priv
->dma_cap
.tx_coe
) ? "Y" : "N");
2973 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
2974 seq_printf(seq
, "\tIP Checksum Offload in RX: %s\n",
2975 (priv
->dma_cap
.rx_coe
) ? "Y" : "N");
2977 seq_printf(seq
, "\tIP Checksum Offload (type1) in RX: %s\n",
2978 (priv
->dma_cap
.rx_coe_type1
) ? "Y" : "N");
2979 seq_printf(seq
, "\tIP Checksum Offload (type2) in RX: %s\n",
2980 (priv
->dma_cap
.rx_coe_type2
) ? "Y" : "N");
2982 seq_printf(seq
, "\tRXFIFO > 2048bytes: %s\n",
2983 (priv
->dma_cap
.rxfifo_over_2048
) ? "Y" : "N");
2984 seq_printf(seq
, "\tNumber of Additional RX channel: %d\n",
2985 priv
->dma_cap
.number_rx_channel
);
2986 seq_printf(seq
, "\tNumber of Additional TX channel: %d\n",
2987 priv
->dma_cap
.number_tx_channel
);
2988 seq_printf(seq
, "\tEnhanced descriptors: %s\n",
2989 (priv
->dma_cap
.enh_desc
) ? "Y" : "N");
2994 static int stmmac_sysfs_dma_cap_open(struct inode
*inode
, struct file
*file
)
2996 return single_open(file
, stmmac_sysfs_dma_cap_read
, inode
->i_private
);
2999 static const struct file_operations stmmac_dma_cap_fops
= {
3000 .owner
= THIS_MODULE
,
3001 .open
= stmmac_sysfs_dma_cap_open
,
3003 .llseek
= seq_lseek
,
3004 .release
= single_release
,
3007 static int stmmac_init_fs(struct net_device
*dev
)
3009 struct stmmac_priv
*priv
= netdev_priv(dev
);
3011 /* Create per netdev entries */
3012 priv
->dbgfs_dir
= debugfs_create_dir(dev
->name
, stmmac_fs_dir
);
3014 if (!priv
->dbgfs_dir
|| IS_ERR(priv
->dbgfs_dir
)) {
3015 pr_err("ERROR %s/%s, debugfs create directory failed\n",
3016 STMMAC_RESOURCE_NAME
, dev
->name
);
3021 /* Entry to report DMA RX/TX rings */
3022 priv
->dbgfs_rings_status
=
3023 debugfs_create_file("descriptors_status", S_IRUGO
,
3024 priv
->dbgfs_dir
, dev
,
3025 &stmmac_rings_status_fops
);
3027 if (!priv
->dbgfs_rings_status
|| IS_ERR(priv
->dbgfs_rings_status
)) {
3028 pr_info("ERROR creating stmmac ring debugfs file\n");
3029 debugfs_remove_recursive(priv
->dbgfs_dir
);
3034 /* Entry to report the DMA HW features */
3035 priv
->dbgfs_dma_cap
= debugfs_create_file("dma_cap", S_IRUGO
,
3037 dev
, &stmmac_dma_cap_fops
);
3039 if (!priv
->dbgfs_dma_cap
|| IS_ERR(priv
->dbgfs_dma_cap
)) {
3040 pr_info("ERROR creating stmmac MMC debugfs file\n");
3041 debugfs_remove_recursive(priv
->dbgfs_dir
);
3049 static void stmmac_exit_fs(struct net_device
*dev
)
3051 struct stmmac_priv
*priv
= netdev_priv(dev
);
3053 debugfs_remove_recursive(priv
->dbgfs_dir
);
3055 #endif /* CONFIG_DEBUG_FS */
3057 static const struct net_device_ops stmmac_netdev_ops
= {
3058 .ndo_open
= stmmac_open
,
3059 .ndo_start_xmit
= stmmac_xmit
,
3060 .ndo_stop
= stmmac_release
,
3061 .ndo_change_mtu
= stmmac_change_mtu
,
3062 .ndo_fix_features
= stmmac_fix_features
,
3063 .ndo_set_features
= stmmac_set_features
,
3064 .ndo_set_rx_mode
= stmmac_set_rx_mode
,
3065 .ndo_tx_timeout
= stmmac_tx_timeout
,
3066 .ndo_do_ioctl
= stmmac_ioctl
,
3067 #ifdef CONFIG_NET_POLL_CONTROLLER
3068 .ndo_poll_controller
= stmmac_poll_controller
,
3070 .ndo_set_mac_address
= eth_mac_addr
,
3074 * stmmac_hw_init - Init the MAC device
3075 * @priv: driver private structure
3076 * Description: this function is to configure the MAC device according to
3077 * some platform parameters or the HW capability register. It prepares the
3078 * driver to use either ring or chain modes and to setup either enhanced or
3079 * normal descriptors.
3081 static int stmmac_hw_init(struct stmmac_priv
*priv
)
3083 struct mac_device_info
*mac
;
3085 /* Identify the MAC HW device */
3086 if (priv
->plat
->has_gmac
) {
3087 priv
->dev
->priv_flags
|= IFF_UNICAST_FLT
;
3088 mac
= dwmac1000_setup(priv
->ioaddr
,
3089 priv
->plat
->multicast_filter_bins
,
3090 priv
->plat
->unicast_filter_entries
,
3091 &priv
->synopsys_id
);
3092 } else if (priv
->plat
->has_gmac4
) {
3093 priv
->dev
->priv_flags
|= IFF_UNICAST_FLT
;
3094 mac
= dwmac4_setup(priv
->ioaddr
,
3095 priv
->plat
->multicast_filter_bins
,
3096 priv
->plat
->unicast_filter_entries
,
3097 &priv
->synopsys_id
);
3099 mac
= dwmac100_setup(priv
->ioaddr
, &priv
->synopsys_id
);
3106 /* To use the chained or ring mode */
3107 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
) {
3108 priv
->hw
->mode
= &dwmac4_ring_mode_ops
;
3111 priv
->hw
->mode
= &chain_mode_ops
;
3112 pr_info(" Chain mode enabled\n");
3113 priv
->mode
= STMMAC_CHAIN_MODE
;
3115 priv
->hw
->mode
= &ring_mode_ops
;
3116 pr_info(" Ring mode enabled\n");
3117 priv
->mode
= STMMAC_RING_MODE
;
3121 /* Get the HW capability (new GMAC newer than 3.50a) */
3122 priv
->hw_cap_support
= stmmac_get_hw_features(priv
);
3123 if (priv
->hw_cap_support
) {
3124 pr_info(" DMA HW capability register supported");
3126 /* We can override some gmac/dma configuration fields: e.g.
3127 * enh_desc, tx_coe (e.g. that are passed through the
3128 * platform) with the values from the HW capability
3129 * register (if supported).
3131 priv
->plat
->enh_desc
= priv
->dma_cap
.enh_desc
;
3132 priv
->plat
->pmt
= priv
->dma_cap
.pmt_remote_wake_up
;
3134 /* TXCOE doesn't work in thresh DMA mode */
3135 if (priv
->plat
->force_thresh_dma_mode
)
3136 priv
->plat
->tx_coe
= 0;
3138 priv
->plat
->tx_coe
= priv
->dma_cap
.tx_coe
;
3140 /* In case of GMAC4 rx_coe is from HW cap register. */
3141 priv
->plat
->rx_coe
= priv
->dma_cap
.rx_coe
;
3143 if (priv
->dma_cap
.rx_coe_type2
)
3144 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE2
;
3145 else if (priv
->dma_cap
.rx_coe_type1
)
3146 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE1
;
3149 pr_info(" No HW DMA feature register supported");
3151 /* To use alternate (extended), normal or GMAC4 descriptor structures */
3152 if (priv
->synopsys_id
>= DWMAC_CORE_4_00
)
3153 priv
->hw
->desc
= &dwmac4_desc_ops
;
3155 stmmac_selec_desc_mode(priv
);
3157 if (priv
->plat
->rx_coe
) {
3158 priv
->hw
->rx_csum
= priv
->plat
->rx_coe
;
3159 pr_info(" RX Checksum Offload Engine supported\n");
3160 if (priv
->synopsys_id
< DWMAC_CORE_4_00
)
3161 pr_info("\tCOE Type %d\n", priv
->hw
->rx_csum
);
3163 if (priv
->plat
->tx_coe
)
3164 pr_info(" TX Checksum insertion supported\n");
3166 if (priv
->plat
->pmt
) {
3167 pr_info(" Wake-Up On Lan supported\n");
3168 device_set_wakeup_capable(priv
->device
, 1);
3171 if (priv
->dma_cap
.tsoen
)
3172 pr_info(" TSO supported\n");
3179 * @device: device pointer
3180 * @plat_dat: platform data pointer
3181 * @res: stmmac resource pointer
3182 * Description: this is the main probe function used to
3183 * call the alloc_etherdev, allocate the priv structure.
3185 * returns 0 on success, otherwise errno.
3187 int stmmac_dvr_probe(struct device
*device
,
3188 struct plat_stmmacenet_data
*plat_dat
,
3189 struct stmmac_resources
*res
)
3192 struct net_device
*ndev
= NULL
;
3193 struct stmmac_priv
*priv
;
3195 ndev
= alloc_etherdev(sizeof(struct stmmac_priv
));
3199 SET_NETDEV_DEV(ndev
, device
);
3201 priv
= netdev_priv(ndev
);
3202 priv
->device
= device
;
3205 stmmac_set_ethtool_ops(ndev
);
3206 priv
->pause
= pause
;
3207 priv
->plat
= plat_dat
;
3208 priv
->ioaddr
= res
->addr
;
3209 priv
->dev
->base_addr
= (unsigned long)res
->addr
;
3211 priv
->dev
->irq
= res
->irq
;
3212 priv
->wol_irq
= res
->wol_irq
;
3213 priv
->lpi_irq
= res
->lpi_irq
;
3216 memcpy(priv
->dev
->dev_addr
, res
->mac
, ETH_ALEN
);
3218 dev_set_drvdata(device
, priv
->dev
);
3220 /* Verify driver arguments */
3221 stmmac_verify_args();
3223 /* Override with kernel parameters if supplied XXX CRS XXX
3224 * this needs to have multiple instances
3226 if ((phyaddr
>= 0) && (phyaddr
<= 31))
3227 priv
->plat
->phy_addr
= phyaddr
;
3229 priv
->stmmac_clk
= devm_clk_get(priv
->device
, STMMAC_RESOURCE_NAME
);
3230 if (IS_ERR(priv
->stmmac_clk
)) {
3231 dev_warn(priv
->device
, "%s: warning: cannot get CSR clock\n",
3233 /* If failed to obtain stmmac_clk and specific clk_csr value
3234 * is NOT passed from the platform, probe fail.
3236 if (!priv
->plat
->clk_csr
) {
3237 ret
= PTR_ERR(priv
->stmmac_clk
);
3240 priv
->stmmac_clk
= NULL
;
3243 clk_prepare_enable(priv
->stmmac_clk
);
3245 priv
->pclk
= devm_clk_get(priv
->device
, "pclk");
3246 if (IS_ERR(priv
->pclk
)) {
3247 if (PTR_ERR(priv
->pclk
) == -EPROBE_DEFER
) {
3248 ret
= -EPROBE_DEFER
;
3249 goto error_pclk_get
;
3253 clk_prepare_enable(priv
->pclk
);
3255 priv
->stmmac_rst
= devm_reset_control_get(priv
->device
,
3256 STMMAC_RESOURCE_NAME
);
3257 if (IS_ERR(priv
->stmmac_rst
)) {
3258 if (PTR_ERR(priv
->stmmac_rst
) == -EPROBE_DEFER
) {
3259 ret
= -EPROBE_DEFER
;
3262 dev_info(priv
->device
, "no reset control found\n");
3263 priv
->stmmac_rst
= NULL
;
3265 if (priv
->stmmac_rst
)
3266 reset_control_deassert(priv
->stmmac_rst
);
3268 /* Init MAC and get the capabilities */
3269 ret
= stmmac_hw_init(priv
);
3273 ndev
->netdev_ops
= &stmmac_netdev_ops
;
3275 ndev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
3278 if ((priv
->plat
->tso_en
) && (priv
->dma_cap
.tsoen
)) {
3279 ndev
->hw_features
|= NETIF_F_TSO
;
3281 pr_info(" TSO feature enabled\n");
3283 ndev
->features
|= ndev
->hw_features
| NETIF_F_HIGHDMA
;
3284 ndev
->watchdog_timeo
= msecs_to_jiffies(watchdog
);
3285 #ifdef STMMAC_VLAN_TAG_USED
3286 /* Both mac100 and gmac support receive VLAN tag detection */
3287 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_RX
;
3289 priv
->msg_enable
= netif_msg_init(debug
, default_msg_level
);
3292 priv
->flow_ctrl
= FLOW_AUTO
; /* RX/TX pause on */
3294 /* Rx Watchdog is available in the COREs newer than the 3.40.
3295 * In some case, for example on bugged HW this feature
3296 * has to be disable and this can be done by passing the
3297 * riwt_off field from the platform.
3299 if ((priv
->synopsys_id
>= DWMAC_CORE_3_50
) && (!priv
->plat
->riwt_off
)) {
3301 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
3304 netif_napi_add(ndev
, &priv
->napi
, stmmac_poll
, 64);
3306 spin_lock_init(&priv
->lock
);
3307 spin_lock_init(&priv
->tx_lock
);
3309 ret
= register_netdev(ndev
);
3311 pr_err("%s: ERROR %i registering the device\n", __func__
, ret
);
3312 goto error_netdev_register
;
3315 /* If a specific clk_csr value is passed from the platform
3316 * this means that the CSR Clock Range selection cannot be
3317 * changed at run-time and it is fixed. Viceversa the driver'll try to
3318 * set the MDC clock dynamically according to the csr actual
3321 if (!priv
->plat
->clk_csr
)
3322 stmmac_clk_csr_set(priv
);
3324 priv
->clk_csr
= priv
->plat
->clk_csr
;
3326 stmmac_check_pcs_mode(priv
);
3328 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
3329 priv
->pcs
!= STMMAC_PCS_RTBI
) {
3330 /* MDIO bus Registration */
3331 ret
= stmmac_mdio_register(ndev
);
3333 pr_debug("%s: MDIO bus (id: %d) registration failed",
3334 __func__
, priv
->plat
->bus_id
);
3335 goto error_mdio_register
;
3341 error_mdio_register
:
3342 unregister_netdev(ndev
);
3343 error_netdev_register
:
3344 netif_napi_del(&priv
->napi
);
3346 clk_disable_unprepare(priv
->pclk
);
3348 clk_disable_unprepare(priv
->stmmac_clk
);
3354 EXPORT_SYMBOL_GPL(stmmac_dvr_probe
);
3358 * @dev: device pointer
3359 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
3360 * changes the link status, releases the DMA descriptor rings.
3362 int stmmac_dvr_remove(struct device
*dev
)
3364 struct net_device
*ndev
= dev_get_drvdata(dev
);
3365 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3367 pr_info("%s:\n\tremoving driver", __func__
);
3369 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
3370 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
3372 stmmac_set_mac(priv
->ioaddr
, false);
3373 netif_carrier_off(ndev
);
3374 unregister_netdev(ndev
);
3375 if (priv
->stmmac_rst
)
3376 reset_control_assert(priv
->stmmac_rst
);
3377 clk_disable_unprepare(priv
->pclk
);
3378 clk_disable_unprepare(priv
->stmmac_clk
);
3379 if (priv
->pcs
!= STMMAC_PCS_RGMII
&& priv
->pcs
!= STMMAC_PCS_TBI
&&
3380 priv
->pcs
!= STMMAC_PCS_RTBI
)
3381 stmmac_mdio_unregister(ndev
);
3386 EXPORT_SYMBOL_GPL(stmmac_dvr_remove
);
3389 * stmmac_suspend - suspend callback
3390 * @dev: device pointer
3391 * Description: this is the function to suspend the device and it is called
3392 * by the platform driver to stop the network queue, release the resources,
3393 * program the PMT register (for WoL), clean and release driver resources.
3395 int stmmac_suspend(struct device
*dev
)
3397 struct net_device
*ndev
= dev_get_drvdata(dev
);
3398 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3399 unsigned long flags
;
3401 if (!ndev
|| !netif_running(ndev
))
3405 phy_stop(priv
->phydev
);
3407 spin_lock_irqsave(&priv
->lock
, flags
);
3409 netif_device_detach(ndev
);
3410 netif_stop_queue(ndev
);
3412 napi_disable(&priv
->napi
);
3414 /* Stop TX/RX DMA */
3415 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
3416 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
3418 /* Enable Power down mode by programming the PMT regs */
3419 if (device_may_wakeup(priv
->device
)) {
3420 priv
->hw
->mac
->pmt(priv
->hw
, priv
->wolopts
);
3423 stmmac_set_mac(priv
->ioaddr
, false);
3424 pinctrl_pm_select_sleep_state(priv
->device
);
3425 /* Disable clock in case of PWM is off */
3426 clk_disable(priv
->pclk
);
3427 clk_disable(priv
->stmmac_clk
);
3429 spin_unlock_irqrestore(&priv
->lock
, flags
);
3433 priv
->oldduplex
= -1;
3436 EXPORT_SYMBOL_GPL(stmmac_suspend
);
3439 * stmmac_resume - resume callback
3440 * @dev: device pointer
3441 * Description: when resume this function is invoked to setup the DMA and CORE
3442 * in a usable state.
3444 int stmmac_resume(struct device
*dev
)
3446 struct net_device
*ndev
= dev_get_drvdata(dev
);
3447 struct stmmac_priv
*priv
= netdev_priv(ndev
);
3448 unsigned long flags
;
3450 if (!netif_running(ndev
))
3453 spin_lock_irqsave(&priv
->lock
, flags
);
3455 /* Power Down bit, into the PM register, is cleared
3456 * automatically as soon as a magic packet or a Wake-up frame
3457 * is received. Anyway, it's better to manually clear
3458 * this bit because it can generate problems while resuming
3459 * from another devices (e.g. serial console).
3461 if (device_may_wakeup(priv
->device
)) {
3462 priv
->hw
->mac
->pmt(priv
->hw
, 0);
3465 pinctrl_pm_select_default_state(priv
->device
);
3466 /* enable the clk prevously disabled */
3467 clk_enable(priv
->stmmac_clk
);
3468 clk_enable(priv
->pclk
);
3469 /* reset the phy so that it's ready */
3471 stmmac_mdio_reset(priv
->mii
);
3474 netif_device_attach(ndev
);
3480 /* reset private mss value to force mss context settings at
3481 * next tso xmit (only used for gmac4).
3485 stmmac_clear_descriptors(priv
);
3487 stmmac_hw_setup(ndev
, false);
3488 stmmac_init_tx_coalesce(priv
);
3489 stmmac_set_rx_mode(ndev
);
3491 napi_enable(&priv
->napi
);
3493 netif_start_queue(ndev
);
3495 spin_unlock_irqrestore(&priv
->lock
, flags
);
3498 phy_start(priv
->phydev
);
3502 EXPORT_SYMBOL_GPL(stmmac_resume
);
3505 static int __init
stmmac_cmdline_opt(char *str
)
3511 while ((opt
= strsep(&str
, ",")) != NULL
) {
3512 if (!strncmp(opt
, "debug:", 6)) {
3513 if (kstrtoint(opt
+ 6, 0, &debug
))
3515 } else if (!strncmp(opt
, "phyaddr:", 8)) {
3516 if (kstrtoint(opt
+ 8, 0, &phyaddr
))
3518 } else if (!strncmp(opt
, "buf_sz:", 7)) {
3519 if (kstrtoint(opt
+ 7, 0, &buf_sz
))
3521 } else if (!strncmp(opt
, "tc:", 3)) {
3522 if (kstrtoint(opt
+ 3, 0, &tc
))
3524 } else if (!strncmp(opt
, "watchdog:", 9)) {
3525 if (kstrtoint(opt
+ 9, 0, &watchdog
))
3527 } else if (!strncmp(opt
, "flow_ctrl:", 10)) {
3528 if (kstrtoint(opt
+ 10, 0, &flow_ctrl
))
3530 } else if (!strncmp(opt
, "pause:", 6)) {
3531 if (kstrtoint(opt
+ 6, 0, &pause
))
3533 } else if (!strncmp(opt
, "eee_timer:", 10)) {
3534 if (kstrtoint(opt
+ 10, 0, &eee_timer
))
3536 } else if (!strncmp(opt
, "chain_mode:", 11)) {
3537 if (kstrtoint(opt
+ 11, 0, &chain_mode
))
3544 pr_err("%s: ERROR broken module parameter conversion", __func__
);
3548 __setup("stmmaceth=", stmmac_cmdline_opt
);
3551 static int __init
stmmac_init(void)
3553 #ifdef CONFIG_DEBUG_FS
3554 /* Create debugfs main directory if it doesn't exist yet */
3555 if (!stmmac_fs_dir
) {
3556 stmmac_fs_dir
= debugfs_create_dir(STMMAC_RESOURCE_NAME
, NULL
);
3558 if (!stmmac_fs_dir
|| IS_ERR(stmmac_fs_dir
)) {
3559 pr_err("ERROR %s, debugfs create directory failed\n",
3560 STMMAC_RESOURCE_NAME
);
3570 static void __exit
stmmac_exit(void)
3572 #ifdef CONFIG_DEBUG_FS
3573 debugfs_remove_recursive(stmmac_fs_dir
);
3577 module_init(stmmac_init
)
3578 module_exit(stmmac_exit
)
3580 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3581 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3582 MODULE_LICENSE("GPL");