1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 Documentation available at:
26 http://www.stlinux.com
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
31 #include <linux/kernel.h>
32 #include <linux/interrupt.h>
34 #include <linux/tcp.h>
35 #include <linux/skbuff.h>
36 #include <linux/ethtool.h>
37 #include <linux/if_ether.h>
38 #include <linux/crc32.h>
39 #include <linux/mii.h>
41 #include <linux/if_vlan.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/slab.h>
44 #include <linux/prefetch.h>
45 #ifdef CONFIG_STMMAC_DEBUG_FS
46 #include <linux/debugfs.h>
47 #include <linux/seq_file.h>
52 /*#define STMMAC_DEBUG*/
54 #define DBG(nlevel, klevel, fmt, args...) \
55 ((void)(netif_msg_##nlevel(priv) && \
56 printk(KERN_##klevel fmt, ## args)))
58 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
61 #undef STMMAC_RX_DEBUG
62 /*#define STMMAC_RX_DEBUG*/
63 #ifdef STMMAC_RX_DEBUG
64 #define RX_DBG(fmt, args...) printk(fmt, ## args)
66 #define RX_DBG(fmt, args...) do { } while (0)
69 #undef STMMAC_XMIT_DEBUG
70 /*#define STMMAC_XMIT_DEBUG*/
71 #ifdef STMMAC_TX_DEBUG
72 #define TX_DBG(fmt, args...) printk(fmt, ## args)
74 #define TX_DBG(fmt, args...) do { } while (0)
77 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
78 #define JUMBO_LEN 9000
80 /* Module parameters */
81 #define TX_TIMEO 5000 /* default 5 seconds */
82 static int watchdog
= TX_TIMEO
;
83 module_param(watchdog
, int, S_IRUGO
| S_IWUSR
);
84 MODULE_PARM_DESC(watchdog
, "Transmit timeout in milliseconds");
86 static int debug
= -1; /* -1: default, 0: no output, 16: all */
87 module_param(debug
, int, S_IRUGO
| S_IWUSR
);
88 MODULE_PARM_DESC(debug
, "Message Level (0: no output, 16: all)");
91 module_param(phyaddr
, int, S_IRUGO
);
92 MODULE_PARM_DESC(phyaddr
, "Physical device address");
94 #define DMA_TX_SIZE 256
95 static int dma_txsize
= DMA_TX_SIZE
;
96 module_param(dma_txsize
, int, S_IRUGO
| S_IWUSR
);
97 MODULE_PARM_DESC(dma_txsize
, "Number of descriptors in the TX list");
99 #define DMA_RX_SIZE 256
100 static int dma_rxsize
= DMA_RX_SIZE
;
101 module_param(dma_rxsize
, int, S_IRUGO
| S_IWUSR
);
102 MODULE_PARM_DESC(dma_rxsize
, "Number of descriptors in the RX list");
104 static int flow_ctrl
= FLOW_OFF
;
105 module_param(flow_ctrl
, int, S_IRUGO
| S_IWUSR
);
106 MODULE_PARM_DESC(flow_ctrl
, "Flow control ability [on/off]");
108 static int pause
= PAUSE_TIME
;
109 module_param(pause
, int, S_IRUGO
| S_IWUSR
);
110 MODULE_PARM_DESC(pause
, "Flow Control Pause Time");
112 #define TC_DEFAULT 64
113 static int tc
= TC_DEFAULT
;
114 module_param(tc
, int, S_IRUGO
| S_IWUSR
);
115 MODULE_PARM_DESC(tc
, "DMA threshold control value");
117 /* Pay attention to tune this parameter; take care of both
118 * hardware capability and network stabitily/performance impact.
119 * Many tests showed that ~4ms latency seems to be good enough. */
120 #ifdef CONFIG_STMMAC_TIMER
121 #define DEFAULT_PERIODIC_RATE 256
122 static int tmrate
= DEFAULT_PERIODIC_RATE
;
123 module_param(tmrate
, int, S_IRUGO
| S_IWUSR
);
124 MODULE_PARM_DESC(tmrate
, "External timer freq. (default: 256Hz)");
127 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
128 static int buf_sz
= DMA_BUFFER_SIZE
;
129 module_param(buf_sz
, int, S_IRUGO
| S_IWUSR
);
130 MODULE_PARM_DESC(buf_sz
, "DMA buffer size");
132 static const u32 default_msg_level
= (NETIF_MSG_DRV
| NETIF_MSG_PROBE
|
133 NETIF_MSG_LINK
| NETIF_MSG_IFUP
|
134 NETIF_MSG_IFDOWN
| NETIF_MSG_TIMER
);
136 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
);
138 #ifdef CONFIG_STMMAC_DEBUG_FS
139 static int stmmac_init_fs(struct net_device
*dev
);
140 static void stmmac_exit_fs(void);
144 * stmmac_verify_args - verify the driver parameters.
145 * Description: it verifies if some wrong parameter is passed to the driver.
146 * Note that wrong parameters are replaced with the default values.
148 static void stmmac_verify_args(void)
150 if (unlikely(watchdog
< 0))
152 if (unlikely(dma_rxsize
< 0))
153 dma_rxsize
= DMA_RX_SIZE
;
154 if (unlikely(dma_txsize
< 0))
155 dma_txsize
= DMA_TX_SIZE
;
156 if (unlikely((buf_sz
< DMA_BUFFER_SIZE
) || (buf_sz
> BUF_SIZE_16KiB
)))
157 buf_sz
= DMA_BUFFER_SIZE
;
158 if (unlikely(flow_ctrl
> 1))
159 flow_ctrl
= FLOW_AUTO
;
160 else if (likely(flow_ctrl
< 0))
161 flow_ctrl
= FLOW_OFF
;
162 if (unlikely((pause
< 0) || (pause
> 0xffff)))
166 static void stmmac_clk_csr_set(struct stmmac_priv
*priv
)
168 #ifdef CONFIG_HAVE_CLK
171 clk_rate
= clk_get_rate(priv
->stmmac_clk
);
173 /* Platform provided default clk_csr would be assumed valid
174 * for all other cases except for the below mentioned ones. */
175 if (!(priv
->clk_csr
& MAC_CSR_H_FRQ_MASK
)) {
176 if (clk_rate
< CSR_F_35M
)
177 priv
->clk_csr
= STMMAC_CSR_20_35M
;
178 else if ((clk_rate
>= CSR_F_35M
) && (clk_rate
< CSR_F_60M
))
179 priv
->clk_csr
= STMMAC_CSR_35_60M
;
180 else if ((clk_rate
>= CSR_F_60M
) && (clk_rate
< CSR_F_100M
))
181 priv
->clk_csr
= STMMAC_CSR_60_100M
;
182 else if ((clk_rate
>= CSR_F_100M
) && (clk_rate
< CSR_F_150M
))
183 priv
->clk_csr
= STMMAC_CSR_100_150M
;
184 else if ((clk_rate
>= CSR_F_150M
) && (clk_rate
< CSR_F_250M
))
185 priv
->clk_csr
= STMMAC_CSR_150_250M
;
186 else if ((clk_rate
>= CSR_F_250M
) && (clk_rate
< CSR_F_300M
))
187 priv
->clk_csr
= STMMAC_CSR_250_300M
;
188 } /* For values higher than the IEEE 802.3 specified frequency
189 * we can not estimate the proper divider as it is not known
190 * the frequency of clk_csr_i. So we do not change the default
195 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
196 static void print_pkt(unsigned char *buf
, int len
)
199 pr_info("len = %d byte, buf addr: 0x%p", len
, buf
);
200 for (j
= 0; j
< len
; j
++) {
202 pr_info("\n %03x:", j
);
203 pr_info(" %02x", buf
[j
]);
209 /* minimum number of free TX descriptors required to wake up TX process */
210 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
212 static inline u32
stmmac_tx_avail(struct stmmac_priv
*priv
)
214 return priv
->dirty_tx
+ priv
->dma_tx_size
- priv
->cur_tx
- 1;
217 /* On some ST platforms, some HW system configuraton registers have to be
218 * set according to the link speed negotiated.
220 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv
*priv
)
222 struct phy_device
*phydev
= priv
->phydev
;
224 if (likely(priv
->plat
->fix_mac_speed
))
225 priv
->plat
->fix_mac_speed(priv
->plat
->bsp_priv
,
231 * @dev: net device structure
232 * Description: it adjusts the link parameters.
234 static void stmmac_adjust_link(struct net_device
*dev
)
236 struct stmmac_priv
*priv
= netdev_priv(dev
);
237 struct phy_device
*phydev
= priv
->phydev
;
240 unsigned int fc
= priv
->flow_ctrl
, pause_time
= priv
->pause
;
245 DBG(probe
, DEBUG
, "stmmac_adjust_link: called. address %d link %d\n",
246 phydev
->addr
, phydev
->link
);
248 spin_lock_irqsave(&priv
->lock
, flags
);
250 u32 ctrl
= readl(priv
->ioaddr
+ MAC_CTRL_REG
);
252 /* Now we make sure that we can be in full duplex mode.
253 * If not, we operate in half-duplex mode. */
254 if (phydev
->duplex
!= priv
->oldduplex
) {
256 if (!(phydev
->duplex
))
257 ctrl
&= ~priv
->hw
->link
.duplex
;
259 ctrl
|= priv
->hw
->link
.duplex
;
260 priv
->oldduplex
= phydev
->duplex
;
262 /* Flow Control operation */
264 priv
->hw
->mac
->flow_ctrl(priv
->ioaddr
, phydev
->duplex
,
267 if (phydev
->speed
!= priv
->speed
) {
269 switch (phydev
->speed
) {
271 if (likely(priv
->plat
->has_gmac
))
272 ctrl
&= ~priv
->hw
->link
.port
;
273 stmmac_hw_fix_mac_speed(priv
);
277 if (priv
->plat
->has_gmac
) {
278 ctrl
|= priv
->hw
->link
.port
;
279 if (phydev
->speed
== SPEED_100
) {
280 ctrl
|= priv
->hw
->link
.speed
;
282 ctrl
&= ~(priv
->hw
->link
.speed
);
285 ctrl
&= ~priv
->hw
->link
.port
;
287 stmmac_hw_fix_mac_speed(priv
);
290 if (netif_msg_link(priv
))
291 pr_warning("%s: Speed (%d) is not 10"
292 " or 100!\n", dev
->name
, phydev
->speed
);
296 priv
->speed
= phydev
->speed
;
299 writel(ctrl
, priv
->ioaddr
+ MAC_CTRL_REG
);
301 if (!priv
->oldlink
) {
305 } else if (priv
->oldlink
) {
309 priv
->oldduplex
= -1;
312 if (new_state
&& netif_msg_link(priv
))
313 phy_print_status(phydev
);
315 spin_unlock_irqrestore(&priv
->lock
, flags
);
317 DBG(probe
, DEBUG
, "stmmac_adjust_link: exiting\n");
321 * stmmac_init_phy - PHY initialization
322 * @dev: net device structure
323 * Description: it initializes the driver's PHY state, and attaches the PHY
328 static int stmmac_init_phy(struct net_device
*dev
)
330 struct stmmac_priv
*priv
= netdev_priv(dev
);
331 struct phy_device
*phydev
;
332 char phy_id
[MII_BUS_ID_SIZE
+ 3];
333 char bus_id
[MII_BUS_ID_SIZE
];
334 int interface
= priv
->plat
->interface
;
337 priv
->oldduplex
= -1;
339 if (priv
->plat
->phy_bus_name
)
340 snprintf(bus_id
, MII_BUS_ID_SIZE
, "%s-%x",
341 priv
->plat
->phy_bus_name
, priv
->plat
->bus_id
);
343 snprintf(bus_id
, MII_BUS_ID_SIZE
, "stmmac-%x",
346 snprintf(phy_id
, MII_BUS_ID_SIZE
+ 3, PHY_ID_FMT
, bus_id
,
347 priv
->plat
->phy_addr
);
348 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id
);
350 phydev
= phy_connect(dev
, phy_id
, &stmmac_adjust_link
, 0, interface
);
352 if (IS_ERR(phydev
)) {
353 pr_err("%s: Could not attach to PHY\n", dev
->name
);
354 return PTR_ERR(phydev
);
357 /* Stop Advertising 1000BASE Capability if interface is not GMII */
358 if ((interface
== PHY_INTERFACE_MODE_MII
) ||
359 (interface
== PHY_INTERFACE_MODE_RMII
))
360 phydev
->advertising
&= ~(SUPPORTED_1000baseT_Half
|
361 SUPPORTED_1000baseT_Full
);
364 * Broken HW is sometimes missing the pull-up resistor on the
365 * MDIO line, which results in reads to non-existent devices returning
366 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
368 * Note: phydev->phy_id is the result of reading the UID PHY registers.
370 if (phydev
->phy_id
== 0) {
371 phy_disconnect(phydev
);
374 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
375 " Link = %d\n", dev
->name
, phydev
->phy_id
, phydev
->link
);
377 priv
->phydev
= phydev
;
384 * @p: pointer to the ring.
385 * @size: size of the ring.
386 * Description: display all the descriptors within the ring.
388 static void display_ring(struct dma_desc
*p
, int size
)
396 for (i
= 0; i
< size
; i
++) {
397 struct tmp_s
*x
= (struct tmp_s
*)(p
+ i
);
398 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
399 i
, (unsigned int)virt_to_phys(&p
[i
]),
400 (unsigned int)(x
->a
), (unsigned int)((x
->a
) >> 32),
406 static int stmmac_set_bfsize(int mtu
, int bufsize
)
410 if (mtu
>= BUF_SIZE_4KiB
)
412 else if (mtu
>= BUF_SIZE_2KiB
)
414 else if (mtu
>= DMA_BUFFER_SIZE
)
417 ret
= DMA_BUFFER_SIZE
;
423 * init_dma_desc_rings - init the RX/TX descriptor rings
424 * @dev: net device structure
425 * Description: this function initializes the DMA RX/TX descriptors
426 * and allocates the socket buffers. It suppors the chained and ring
429 static void init_dma_desc_rings(struct net_device
*dev
)
432 struct stmmac_priv
*priv
= netdev_priv(dev
);
434 unsigned int txsize
= priv
->dma_tx_size
;
435 unsigned int rxsize
= priv
->dma_rx_size
;
438 int des3_as_data_buf
= 0;
440 /* Set the max buffer size according to the DESC mode
441 * and the MTU. Note that RING mode allows 16KiB bsize. */
442 bfsize
= priv
->hw
->ring
->set_16kib_bfsize(dev
->mtu
);
444 if (bfsize
== BUF_SIZE_16KiB
)
445 des3_as_data_buf
= 1;
447 bfsize
= stmmac_set_bfsize(dev
->mtu
, priv
->dma_buf_sz
);
449 #ifdef CONFIG_STMMAC_TIMER
450 /* Disable interrupts on completion for the reception if timer is on */
451 if (likely(priv
->tm
->enable
))
455 DBG(probe
, INFO
, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
456 txsize
, rxsize
, bfsize
);
458 priv
->rx_skbuff_dma
= kmalloc(rxsize
* sizeof(dma_addr_t
), GFP_KERNEL
);
460 kmalloc(sizeof(struct sk_buff
*) * rxsize
, GFP_KERNEL
);
462 (struct dma_desc
*)dma_alloc_coherent(priv
->device
,
464 sizeof(struct dma_desc
),
467 priv
->tx_skbuff
= kmalloc(sizeof(struct sk_buff
*) * txsize
,
470 (struct dma_desc
*)dma_alloc_coherent(priv
->device
,
472 sizeof(struct dma_desc
),
476 if ((priv
->dma_rx
== NULL
) || (priv
->dma_tx
== NULL
)) {
477 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__
);
481 DBG(probe
, INFO
, "stmmac (%s) DMA desc: virt addr (Rx %p, "
482 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
483 dev
->name
, priv
->dma_rx
, priv
->dma_tx
,
484 (unsigned int)priv
->dma_rx_phy
, (unsigned int)priv
->dma_tx_phy
);
486 /* RX INITIALIZATION */
487 DBG(probe
, INFO
, "stmmac: SKB addresses:\n"
488 "skb\t\tskb data\tdma data\n");
490 for (i
= 0; i
< rxsize
; i
++) {
491 struct dma_desc
*p
= priv
->dma_rx
+ i
;
493 skb
= __netdev_alloc_skb(dev
, bfsize
+ NET_IP_ALIGN
,
495 if (unlikely(skb
== NULL
)) {
496 pr_err("%s: Rx init fails; skb is NULL\n", __func__
);
499 skb_reserve(skb
, NET_IP_ALIGN
);
500 priv
->rx_skbuff
[i
] = skb
;
501 priv
->rx_skbuff_dma
[i
] = dma_map_single(priv
->device
, skb
->data
,
502 bfsize
, DMA_FROM_DEVICE
);
504 p
->des2
= priv
->rx_skbuff_dma
[i
];
506 priv
->hw
->ring
->init_desc3(des3_as_data_buf
, p
);
508 DBG(probe
, INFO
, "[%p]\t[%p]\t[%x]\n", priv
->rx_skbuff
[i
],
509 priv
->rx_skbuff
[i
]->data
, priv
->rx_skbuff_dma
[i
]);
512 priv
->dirty_rx
= (unsigned int)(i
- rxsize
);
513 priv
->dma_buf_sz
= bfsize
;
516 /* TX INITIALIZATION */
517 for (i
= 0; i
< txsize
; i
++) {
518 priv
->tx_skbuff
[i
] = NULL
;
519 priv
->dma_tx
[i
].des2
= 0;
522 /* In case of Chained mode this sets the des3 to the next
523 * element in the chain */
524 priv
->hw
->ring
->init_dma_chain(priv
->dma_rx
, priv
->dma_rx_phy
, rxsize
);
525 priv
->hw
->ring
->init_dma_chain(priv
->dma_tx
, priv
->dma_tx_phy
, txsize
);
530 /* Clear the Rx/Tx descriptors */
531 priv
->hw
->desc
->init_rx_desc(priv
->dma_rx
, rxsize
, dis_ic
);
532 priv
->hw
->desc
->init_tx_desc(priv
->dma_tx
, txsize
);
534 if (netif_msg_hw(priv
)) {
535 pr_info("RX descriptor ring:\n");
536 display_ring(priv
->dma_rx
, rxsize
);
537 pr_info("TX descriptor ring:\n");
538 display_ring(priv
->dma_tx
, txsize
);
542 static void dma_free_rx_skbufs(struct stmmac_priv
*priv
)
546 for (i
= 0; i
< priv
->dma_rx_size
; i
++) {
547 if (priv
->rx_skbuff
[i
]) {
548 dma_unmap_single(priv
->device
, priv
->rx_skbuff_dma
[i
],
549 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
550 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
552 priv
->rx_skbuff
[i
] = NULL
;
556 static void dma_free_tx_skbufs(struct stmmac_priv
*priv
)
560 for (i
= 0; i
< priv
->dma_tx_size
; i
++) {
561 if (priv
->tx_skbuff
[i
] != NULL
) {
562 struct dma_desc
*p
= priv
->dma_tx
+ i
;
564 dma_unmap_single(priv
->device
, p
->des2
,
565 priv
->hw
->desc
->get_tx_len(p
),
567 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
568 priv
->tx_skbuff
[i
] = NULL
;
573 static void free_dma_desc_resources(struct stmmac_priv
*priv
)
575 /* Release the DMA TX/RX socket buffers */
576 dma_free_rx_skbufs(priv
);
577 dma_free_tx_skbufs(priv
);
579 /* Free the region of consistent memory previously allocated for
581 dma_free_coherent(priv
->device
,
582 priv
->dma_tx_size
* sizeof(struct dma_desc
),
583 priv
->dma_tx
, priv
->dma_tx_phy
);
584 dma_free_coherent(priv
->device
,
585 priv
->dma_rx_size
* sizeof(struct dma_desc
),
586 priv
->dma_rx
, priv
->dma_rx_phy
);
587 kfree(priv
->rx_skbuff_dma
);
588 kfree(priv
->rx_skbuff
);
589 kfree(priv
->tx_skbuff
);
593 * stmmac_dma_operation_mode - HW DMA operation mode
594 * @priv : pointer to the private device structure.
595 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
596 * or Store-And-Forward capability.
598 static void stmmac_dma_operation_mode(struct stmmac_priv
*priv
)
600 if (likely(priv
->plat
->force_sf_dma_mode
||
601 ((priv
->plat
->tx_coe
) && (!priv
->no_csum_insertion
)))) {
603 * In case of GMAC, SF mode can be enabled
604 * to perform the TX COE in HW. This depends on:
605 * 1) TX COE if actually supported
606 * 2) There is no bugged Jumbo frame support
607 * that needs to not insert csum in the TDES.
609 priv
->hw
->dma
->dma_mode(priv
->ioaddr
,
610 SF_DMA_MODE
, SF_DMA_MODE
);
613 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, SF_DMA_MODE
);
618 * @priv: private driver structure
619 * Description: it reclaims resources after transmission completes.
621 static void stmmac_tx(struct stmmac_priv
*priv
)
623 unsigned int txsize
= priv
->dma_tx_size
;
625 spin_lock(&priv
->tx_lock
);
627 while (priv
->dirty_tx
!= priv
->cur_tx
) {
629 unsigned int entry
= priv
->dirty_tx
% txsize
;
630 struct sk_buff
*skb
= priv
->tx_skbuff
[entry
];
631 struct dma_desc
*p
= priv
->dma_tx
+ entry
;
633 /* Check if the descriptor is owned by the DMA. */
634 if (priv
->hw
->desc
->get_tx_owner(p
))
637 /* Verify tx error by looking at the last segment */
638 last
= priv
->hw
->desc
->get_tx_ls(p
);
641 priv
->hw
->desc
->tx_status(&priv
->dev
->stats
,
644 if (likely(tx_error
== 0)) {
645 priv
->dev
->stats
.tx_packets
++;
646 priv
->xstats
.tx_pkt_n
++;
648 priv
->dev
->stats
.tx_errors
++;
650 TX_DBG("%s: curr %d, dirty %d\n", __func__
,
651 priv
->cur_tx
, priv
->dirty_tx
);
654 dma_unmap_single(priv
->device
, p
->des2
,
655 priv
->hw
->desc
->get_tx_len(p
),
657 priv
->hw
->ring
->clean_desc3(p
);
659 if (likely(skb
!= NULL
)) {
661 * If there's room in the queue (limit it to size)
662 * we add this skb back into the pool,
663 * if it's the right size.
665 if ((skb_queue_len(&priv
->rx_recycle
) <
666 priv
->dma_rx_size
) &&
667 skb_recycle_check(skb
, priv
->dma_buf_sz
))
668 __skb_queue_head(&priv
->rx_recycle
, skb
);
672 priv
->tx_skbuff
[entry
] = NULL
;
675 priv
->hw
->desc
->release_tx_desc(p
);
677 entry
= (++priv
->dirty_tx
) % txsize
;
679 if (unlikely(netif_queue_stopped(priv
->dev
) &&
680 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH(priv
))) {
681 netif_tx_lock(priv
->dev
);
682 if (netif_queue_stopped(priv
->dev
) &&
683 stmmac_tx_avail(priv
) > STMMAC_TX_THRESH(priv
)) {
684 TX_DBG("%s: restart transmit\n", __func__
);
685 netif_wake_queue(priv
->dev
);
687 netif_tx_unlock(priv
->dev
);
689 spin_unlock(&priv
->tx_lock
);
692 static inline void stmmac_enable_irq(struct stmmac_priv
*priv
)
694 #ifdef CONFIG_STMMAC_TIMER
695 if (likely(priv
->tm
->enable
))
696 priv
->tm
->timer_start(tmrate
);
699 priv
->hw
->dma
->enable_dma_irq(priv
->ioaddr
);
702 static inline void stmmac_disable_irq(struct stmmac_priv
*priv
)
704 #ifdef CONFIG_STMMAC_TIMER
705 if (likely(priv
->tm
->enable
))
706 priv
->tm
->timer_stop();
709 priv
->hw
->dma
->disable_dma_irq(priv
->ioaddr
);
712 static int stmmac_has_work(struct stmmac_priv
*priv
)
714 unsigned int has_work
= 0;
715 int rxret
, tx_work
= 0;
717 rxret
= priv
->hw
->desc
->get_rx_owner(priv
->dma_rx
+
718 (priv
->cur_rx
% priv
->dma_rx_size
));
720 if (priv
->dirty_tx
!= priv
->cur_tx
)
723 if (likely(!rxret
|| tx_work
))
729 static inline void _stmmac_schedule(struct stmmac_priv
*priv
)
731 if (likely(stmmac_has_work(priv
))) {
732 stmmac_disable_irq(priv
);
733 napi_schedule(&priv
->napi
);
737 #ifdef CONFIG_STMMAC_TIMER
738 void stmmac_schedule(struct net_device
*dev
)
740 struct stmmac_priv
*priv
= netdev_priv(dev
);
742 priv
->xstats
.sched_timer_n
++;
744 _stmmac_schedule(priv
);
747 static void stmmac_no_timer_started(unsigned int x
)
751 static void stmmac_no_timer_stopped(void)
758 * @priv: pointer to the private device structure
759 * Description: it cleans the descriptors and restarts the transmission
762 static void stmmac_tx_err(struct stmmac_priv
*priv
)
764 netif_stop_queue(priv
->dev
);
766 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
767 dma_free_tx_skbufs(priv
);
768 priv
->hw
->desc
->init_tx_desc(priv
->dma_tx
, priv
->dma_tx_size
);
771 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
773 priv
->dev
->stats
.tx_errors
++;
774 netif_wake_queue(priv
->dev
);
778 static void stmmac_dma_interrupt(struct stmmac_priv
*priv
)
782 status
= priv
->hw
->dma
->dma_interrupt(priv
->ioaddr
, &priv
->xstats
);
783 if (likely(status
== handle_tx_rx
))
784 _stmmac_schedule(priv
);
786 else if (unlikely(status
== tx_hard_error_bump_tc
)) {
787 /* Try to bump up the dma threshold on this failure */
788 if (unlikely(tc
!= SF_DMA_MODE
) && (tc
<= 256)) {
790 priv
->hw
->dma
->dma_mode(priv
->ioaddr
, tc
, SF_DMA_MODE
);
791 priv
->xstats
.threshold
= tc
;
793 } else if (unlikely(status
== tx_hard_error
))
797 static void stmmac_mmc_setup(struct stmmac_priv
*priv
)
799 unsigned int mode
= MMC_CNTRL_RESET_ON_READ
| MMC_CNTRL_COUNTER_RESET
|
800 MMC_CNTRL_PRESET
| MMC_CNTRL_FULL_HALF_PRESET
;
802 /* Mask MMC irq, counters are managed in SW and registers
803 * are cleared on each READ eventually. */
804 dwmac_mmc_intr_all_mask(priv
->ioaddr
);
806 if (priv
->dma_cap
.rmon
) {
807 dwmac_mmc_ctrl(priv
->ioaddr
, mode
);
808 memset(&priv
->mmc
, 0, sizeof(struct stmmac_counters
));
810 pr_info(" No MAC Management Counters available\n");
813 static u32
stmmac_get_synopsys_id(struct stmmac_priv
*priv
)
815 u32 hwid
= priv
->hw
->synopsys_uid
;
817 /* Only check valid Synopsys Id because old MAC chips
818 * have no HW registers where get the ID */
820 u32 uid
= ((hwid
& 0x0000ff00) >> 8);
821 u32 synid
= (hwid
& 0x000000ff);
823 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
832 * stmmac_selec_desc_mode
833 * @dev : device pointer
834 * Description: select the Enhanced/Alternate or Normal descriptors */
835 static void stmmac_selec_desc_mode(struct stmmac_priv
*priv
)
837 if (priv
->plat
->enh_desc
) {
838 pr_info(" Enhanced/Alternate descriptors\n");
839 priv
->hw
->desc
= &enh_desc_ops
;
841 pr_info(" Normal descriptors\n");
842 priv
->hw
->desc
= &ndesc_ops
;
847 * stmmac_get_hw_features
848 * @priv : private device pointer
850 * new GMAC chip generations have a new register to indicate the
851 * presence of the optional feature/functions.
852 * This can be also used to override the value passed through the
853 * platform and necessary for old MAC10/100 and GMAC chips.
855 static int stmmac_get_hw_features(struct stmmac_priv
*priv
)
859 if (priv
->hw
->dma
->get_hw_feature
) {
860 hw_cap
= priv
->hw
->dma
->get_hw_feature(priv
->ioaddr
);
862 priv
->dma_cap
.mbps_10_100
= (hw_cap
& DMA_HW_FEAT_MIISEL
);
863 priv
->dma_cap
.mbps_1000
= (hw_cap
& DMA_HW_FEAT_GMIISEL
) >> 1;
864 priv
->dma_cap
.half_duplex
= (hw_cap
& DMA_HW_FEAT_HDSEL
) >> 2;
865 priv
->dma_cap
.hash_filter
= (hw_cap
& DMA_HW_FEAT_HASHSEL
) >> 4;
866 priv
->dma_cap
.multi_addr
=
867 (hw_cap
& DMA_HW_FEAT_ADDMACADRSEL
) >> 5;
868 priv
->dma_cap
.pcs
= (hw_cap
& DMA_HW_FEAT_PCSSEL
) >> 6;
869 priv
->dma_cap
.sma_mdio
= (hw_cap
& DMA_HW_FEAT_SMASEL
) >> 8;
870 priv
->dma_cap
.pmt_remote_wake_up
=
871 (hw_cap
& DMA_HW_FEAT_RWKSEL
) >> 9;
872 priv
->dma_cap
.pmt_magic_frame
=
873 (hw_cap
& DMA_HW_FEAT_MGKSEL
) >> 10;
875 priv
->dma_cap
.rmon
= (hw_cap
& DMA_HW_FEAT_MMCSEL
) >> 11;
877 priv
->dma_cap
.time_stamp
=
878 (hw_cap
& DMA_HW_FEAT_TSVER1SEL
) >> 12;
880 priv
->dma_cap
.atime_stamp
=
881 (hw_cap
& DMA_HW_FEAT_TSVER2SEL
) >> 13;
882 /* 802.3az - Energy-Efficient Ethernet (EEE) */
883 priv
->dma_cap
.eee
= (hw_cap
& DMA_HW_FEAT_EEESEL
) >> 14;
884 priv
->dma_cap
.av
= (hw_cap
& DMA_HW_FEAT_AVSEL
) >> 15;
886 priv
->dma_cap
.tx_coe
= (hw_cap
& DMA_HW_FEAT_TXCOESEL
) >> 16;
887 priv
->dma_cap
.rx_coe_type1
=
888 (hw_cap
& DMA_HW_FEAT_RXTYP1COE
) >> 17;
889 priv
->dma_cap
.rx_coe_type2
=
890 (hw_cap
& DMA_HW_FEAT_RXTYP2COE
) >> 18;
891 priv
->dma_cap
.rxfifo_over_2048
=
892 (hw_cap
& DMA_HW_FEAT_RXFIFOSIZE
) >> 19;
893 /* TX and RX number of channels */
894 priv
->dma_cap
.number_rx_channel
=
895 (hw_cap
& DMA_HW_FEAT_RXCHCNT
) >> 20;
896 priv
->dma_cap
.number_tx_channel
=
897 (hw_cap
& DMA_HW_FEAT_TXCHCNT
) >> 22;
898 /* Alternate (enhanced) DESC mode*/
899 priv
->dma_cap
.enh_desc
=
900 (hw_cap
& DMA_HW_FEAT_ENHDESSEL
) >> 24;
907 static void stmmac_check_ether_addr(struct stmmac_priv
*priv
)
909 /* verify if the MAC address is valid, in case of failures it
910 * generates a random MAC address */
911 if (!is_valid_ether_addr(priv
->dev
->dev_addr
)) {
912 priv
->hw
->mac
->get_umac_addr((void __iomem
*)
913 priv
->dev
->base_addr
,
914 priv
->dev
->dev_addr
, 0);
915 if (!is_valid_ether_addr(priv
->dev
->dev_addr
))
916 eth_hw_addr_random(priv
->dev
);
918 pr_warning("%s: device MAC address %pM\n", priv
->dev
->name
,
919 priv
->dev
->dev_addr
);
923 * stmmac_open - open entry point of the driver
924 * @dev : pointer to the device structure.
926 * This function is the open entry point of the driver.
928 * 0 on success and an appropriate (-)ve integer as defined in errno.h
931 static int stmmac_open(struct net_device
*dev
)
933 struct stmmac_priv
*priv
= netdev_priv(dev
);
936 stmmac_clk_enable(priv
);
938 stmmac_check_ether_addr(priv
);
940 /* MDIO bus Registration */
941 ret
= stmmac_mdio_register(dev
);
943 pr_debug("%s: MDIO bus (id: %d) registration failed",
944 __func__
, priv
->plat
->bus_id
);
948 #ifdef CONFIG_STMMAC_TIMER
949 priv
->tm
= kzalloc(sizeof(struct stmmac_timer
*), GFP_KERNEL
);
950 if (unlikely(priv
->tm
== NULL
)) {
955 priv
->tm
->freq
= tmrate
;
957 /* Test if the external timer can be actually used.
958 * In case of failure continue without timer. */
959 if (unlikely((stmmac_open_ext_timer(dev
, priv
->tm
)) < 0)) {
960 pr_warning("stmmaceth: cannot attach the external timer.\n");
962 priv
->tm
->timer_start
= stmmac_no_timer_started
;
963 priv
->tm
->timer_stop
= stmmac_no_timer_stopped
;
965 priv
->tm
->enable
= 1;
967 ret
= stmmac_init_phy(dev
);
969 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__
, ret
);
973 /* Create and initialize the TX/RX descriptors chains. */
974 priv
->dma_tx_size
= STMMAC_ALIGN(dma_txsize
);
975 priv
->dma_rx_size
= STMMAC_ALIGN(dma_rxsize
);
976 priv
->dma_buf_sz
= STMMAC_ALIGN(buf_sz
);
977 init_dma_desc_rings(dev
);
979 /* DMA initialization and SW reset */
980 ret
= priv
->hw
->dma
->init(priv
->ioaddr
, priv
->plat
->dma_cfg
->pbl
,
981 priv
->plat
->dma_cfg
->fixed_burst
,
982 priv
->plat
->dma_cfg
->burst_len
,
983 priv
->dma_tx_phy
, priv
->dma_rx_phy
);
985 pr_err("%s: DMA initialization failed\n", __func__
);
989 /* Copy the MAC addr into the HW */
990 priv
->hw
->mac
->set_umac_addr(priv
->ioaddr
, dev
->dev_addr
, 0);
992 /* If required, perform hw setup of the bus. */
993 if (priv
->plat
->bus_setup
)
994 priv
->plat
->bus_setup(priv
->ioaddr
);
996 /* Initialize the MAC Core */
997 priv
->hw
->mac
->core_init(priv
->ioaddr
);
999 /* Request the IRQ lines */
1000 ret
= request_irq(dev
->irq
, stmmac_interrupt
,
1001 IRQF_SHARED
, dev
->name
, dev
);
1002 if (unlikely(ret
< 0)) {
1003 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1004 __func__
, dev
->irq
, ret
);
1008 /* Request the Wake IRQ in case of another line is used for WoL */
1009 if (priv
->wol_irq
!= dev
->irq
) {
1010 ret
= request_irq(priv
->wol_irq
, stmmac_interrupt
,
1011 IRQF_SHARED
, dev
->name
, dev
);
1012 if (unlikely(ret
< 0)) {
1013 pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
1014 "(error: %d)\n", __func__
, priv
->wol_irq
, ret
);
1015 goto open_error_wolirq
;
1019 /* Enable the MAC Rx/Tx */
1020 stmmac_set_mac(priv
->ioaddr
, true);
1022 /* Set the HW DMA mode and the COE */
1023 stmmac_dma_operation_mode(priv
);
1025 /* Extra statistics */
1026 memset(&priv
->xstats
, 0, sizeof(struct stmmac_extra_stats
));
1027 priv
->xstats
.threshold
= tc
;
1029 stmmac_mmc_setup(priv
);
1031 #ifdef CONFIG_STMMAC_DEBUG_FS
1032 ret
= stmmac_init_fs(dev
);
1034 pr_warning("%s: failed debugFS registration\n", __func__
);
1036 /* Start the ball rolling... */
1037 DBG(probe
, DEBUG
, "%s: DMA RX/TX processes started...\n", dev
->name
);
1038 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
1039 priv
->hw
->dma
->start_rx(priv
->ioaddr
);
1041 #ifdef CONFIG_STMMAC_TIMER
1042 priv
->tm
->timer_start(tmrate
);
1045 /* Dump DMA/MAC registers */
1046 if (netif_msg_hw(priv
)) {
1047 priv
->hw
->mac
->dump_regs(priv
->ioaddr
);
1048 priv
->hw
->dma
->dump_regs(priv
->ioaddr
);
1052 phy_start(priv
->phydev
);
1054 napi_enable(&priv
->napi
);
1055 skb_queue_head_init(&priv
->rx_recycle
);
1056 netif_start_queue(dev
);
1061 free_irq(dev
->irq
, dev
);
1064 #ifdef CONFIG_STMMAC_TIMER
1068 phy_disconnect(priv
->phydev
);
1071 stmmac_clk_disable(priv
);
1076 * stmmac_release - close entry point of the driver
1077 * @dev : device pointer.
1079 * This is the stop entry point of the driver.
1081 static int stmmac_release(struct net_device
*dev
)
1083 struct stmmac_priv
*priv
= netdev_priv(dev
);
1085 /* Stop and disconnect the PHY */
1087 phy_stop(priv
->phydev
);
1088 phy_disconnect(priv
->phydev
);
1089 priv
->phydev
= NULL
;
1092 netif_stop_queue(dev
);
1094 #ifdef CONFIG_STMMAC_TIMER
1095 /* Stop and release the timer */
1096 stmmac_close_ext_timer();
1097 if (priv
->tm
!= NULL
)
1100 napi_disable(&priv
->napi
);
1101 skb_queue_purge(&priv
->rx_recycle
);
1103 /* Free the IRQ lines */
1104 free_irq(dev
->irq
, dev
);
1105 if (priv
->wol_irq
!= dev
->irq
)
1106 free_irq(priv
->wol_irq
, dev
);
1108 /* Stop TX/RX DMA and clear the descriptors */
1109 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1110 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
1112 /* Release and free the Rx/Tx resources */
1113 free_dma_desc_resources(priv
);
1115 /* Disable the MAC Rx/Tx */
1116 stmmac_set_mac(priv
->ioaddr
, false);
1118 netif_carrier_off(dev
);
1120 #ifdef CONFIG_STMMAC_DEBUG_FS
1123 stmmac_mdio_unregister(dev
);
1124 stmmac_clk_disable(priv
);
1131 * @skb : the socket buffer
1132 * @dev : device pointer
1133 * Description : Tx entry point of the driver.
1135 static netdev_tx_t
stmmac_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1137 struct stmmac_priv
*priv
= netdev_priv(dev
);
1138 unsigned int txsize
= priv
->dma_tx_size
;
1140 int i
, csum_insertion
= 0;
1141 int nfrags
= skb_shinfo(skb
)->nr_frags
;
1142 struct dma_desc
*desc
, *first
;
1143 unsigned int nopaged_len
= skb_headlen(skb
);
1145 if (unlikely(stmmac_tx_avail(priv
) < nfrags
+ 1)) {
1146 if (!netif_queue_stopped(dev
)) {
1147 netif_stop_queue(dev
);
1148 /* This is a hard error, log it. */
1149 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1152 return NETDEV_TX_BUSY
;
1155 spin_lock(&priv
->tx_lock
);
1157 entry
= priv
->cur_tx
% txsize
;
1159 #ifdef STMMAC_XMIT_DEBUG
1160 if ((skb
->len
> ETH_FRAME_LEN
) || nfrags
)
1161 pr_info("stmmac xmit:\n"
1162 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1163 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1164 skb
, skb
->len
, nopaged_len
, nfrags
, skb
->ip_summed
,
1165 !skb_is_gso(skb
) ? "isn't" : "is");
1168 csum_insertion
= (skb
->ip_summed
== CHECKSUM_PARTIAL
);
1170 desc
= priv
->dma_tx
+ entry
;
1173 #ifdef STMMAC_XMIT_DEBUG
1174 if ((nfrags
> 0) || (skb
->len
> ETH_FRAME_LEN
))
1175 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1176 "\t\tn_frags: %d, ip_summed: %d\n",
1177 skb
->len
, nopaged_len
, nfrags
, skb
->ip_summed
);
1179 priv
->tx_skbuff
[entry
] = skb
;
1181 if (priv
->hw
->ring
->is_jumbo_frm(skb
->len
, priv
->plat
->enh_desc
)) {
1182 entry
= priv
->hw
->ring
->jumbo_frm(priv
, skb
, csum_insertion
);
1183 desc
= priv
->dma_tx
+ entry
;
1185 desc
->des2
= dma_map_single(priv
->device
, skb
->data
,
1186 nopaged_len
, DMA_TO_DEVICE
);
1187 priv
->hw
->desc
->prepare_tx_desc(desc
, 1, nopaged_len
,
1191 for (i
= 0; i
< nfrags
; i
++) {
1192 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1193 int len
= skb_frag_size(frag
);
1195 entry
= (++priv
->cur_tx
) % txsize
;
1196 desc
= priv
->dma_tx
+ entry
;
1198 TX_DBG("\t[entry %d] segment len: %d\n", entry
, len
);
1199 desc
->des2
= skb_frag_dma_map(priv
->device
, frag
, 0, len
,
1201 priv
->tx_skbuff
[entry
] = NULL
;
1202 priv
->hw
->desc
->prepare_tx_desc(desc
, 0, len
, csum_insertion
);
1204 priv
->hw
->desc
->set_tx_owner(desc
);
1207 /* Interrupt on completition only for the latest segment */
1208 priv
->hw
->desc
->close_tx_desc(desc
);
1210 #ifdef CONFIG_STMMAC_TIMER
1211 /* Clean IC while using timer */
1212 if (likely(priv
->tm
->enable
))
1213 priv
->hw
->desc
->clear_tx_ic(desc
);
1218 /* To avoid raise condition */
1219 priv
->hw
->desc
->set_tx_owner(first
);
1223 #ifdef STMMAC_XMIT_DEBUG
1224 if (netif_msg_pktdata(priv
)) {
1225 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1226 "first=%p, nfrags=%d\n",
1227 (priv
->cur_tx
% txsize
), (priv
->dirty_tx
% txsize
),
1228 entry
, first
, nfrags
);
1229 display_ring(priv
->dma_tx
, txsize
);
1230 pr_info(">>> frame to be transmitted: ");
1231 print_pkt(skb
->data
, skb
->len
);
1234 if (unlikely(stmmac_tx_avail(priv
) <= (MAX_SKB_FRAGS
+ 1))) {
1235 TX_DBG("%s: stop transmitted packets\n", __func__
);
1236 netif_stop_queue(dev
);
1239 dev
->stats
.tx_bytes
+= skb
->len
;
1241 skb_tx_timestamp(skb
);
1243 priv
->hw
->dma
->enable_dma_transmission(priv
->ioaddr
);
1245 spin_unlock(&priv
->tx_lock
);
1247 return NETDEV_TX_OK
;
1250 static inline void stmmac_rx_refill(struct stmmac_priv
*priv
)
1252 unsigned int rxsize
= priv
->dma_rx_size
;
1253 int bfsize
= priv
->dma_buf_sz
;
1254 struct dma_desc
*p
= priv
->dma_rx
;
1256 for (; priv
->cur_rx
- priv
->dirty_rx
> 0; priv
->dirty_rx
++) {
1257 unsigned int entry
= priv
->dirty_rx
% rxsize
;
1258 if (likely(priv
->rx_skbuff
[entry
] == NULL
)) {
1259 struct sk_buff
*skb
;
1261 skb
= __skb_dequeue(&priv
->rx_recycle
);
1263 skb
= netdev_alloc_skb_ip_align(priv
->dev
,
1266 if (unlikely(skb
== NULL
))
1269 priv
->rx_skbuff
[entry
] = skb
;
1270 priv
->rx_skbuff_dma
[entry
] =
1271 dma_map_single(priv
->device
, skb
->data
, bfsize
,
1274 (p
+ entry
)->des2
= priv
->rx_skbuff_dma
[entry
];
1276 if (unlikely(priv
->plat
->has_gmac
))
1277 priv
->hw
->ring
->refill_desc3(bfsize
, p
+ entry
);
1279 RX_DBG(KERN_INFO
"\trefill entry #%d\n", entry
);
1282 priv
->hw
->desc
->set_rx_owner(p
+ entry
);
1286 static int stmmac_rx(struct stmmac_priv
*priv
, int limit
)
1288 unsigned int rxsize
= priv
->dma_rx_size
;
1289 unsigned int entry
= priv
->cur_rx
% rxsize
;
1290 unsigned int next_entry
;
1291 unsigned int count
= 0;
1292 struct dma_desc
*p
= priv
->dma_rx
+ entry
;
1293 struct dma_desc
*p_next
;
1295 #ifdef STMMAC_RX_DEBUG
1296 if (netif_msg_hw(priv
)) {
1297 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1298 display_ring(priv
->dma_rx
, rxsize
);
1302 while (!priv
->hw
->desc
->get_rx_owner(p
)) {
1310 next_entry
= (++priv
->cur_rx
) % rxsize
;
1311 p_next
= priv
->dma_rx
+ next_entry
;
1314 /* read the status of the incoming frame */
1315 status
= (priv
->hw
->desc
->rx_status(&priv
->dev
->stats
,
1317 if (unlikely(status
== discard_frame
))
1318 priv
->dev
->stats
.rx_errors
++;
1320 struct sk_buff
*skb
;
1323 frame_len
= priv
->hw
->desc
->get_rx_frame_len(p
,
1324 priv
->plat
->rx_coe
);
1325 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1326 * Type frames (LLC/LLC-SNAP) */
1327 if (unlikely(status
!= llc_snap
))
1328 frame_len
-= ETH_FCS_LEN
;
1329 #ifdef STMMAC_RX_DEBUG
1330 if (frame_len
> ETH_FRAME_LEN
)
1331 pr_debug("\tRX frame size %d, COE status: %d\n",
1334 if (netif_msg_hw(priv
))
1335 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1338 skb
= priv
->rx_skbuff
[entry
];
1339 if (unlikely(!skb
)) {
1340 pr_err("%s: Inconsistent Rx descriptor chain\n",
1342 priv
->dev
->stats
.rx_dropped
++;
1345 prefetch(skb
->data
- NET_IP_ALIGN
);
1346 priv
->rx_skbuff
[entry
] = NULL
;
1348 skb_put(skb
, frame_len
);
1349 dma_unmap_single(priv
->device
,
1350 priv
->rx_skbuff_dma
[entry
],
1351 priv
->dma_buf_sz
, DMA_FROM_DEVICE
);
1352 #ifdef STMMAC_RX_DEBUG
1353 if (netif_msg_pktdata(priv
)) {
1354 pr_info(" frame received (%dbytes)", frame_len
);
1355 print_pkt(skb
->data
, frame_len
);
1358 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
1360 if (unlikely(!priv
->plat
->rx_coe
)) {
1361 /* No RX COE for old mac10/100 devices */
1362 skb_checksum_none_assert(skb
);
1363 netif_receive_skb(skb
);
1365 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1366 napi_gro_receive(&priv
->napi
, skb
);
1369 priv
->dev
->stats
.rx_packets
++;
1370 priv
->dev
->stats
.rx_bytes
+= frame_len
;
1373 p
= p_next
; /* use prefetched values */
1376 stmmac_rx_refill(priv
);
1378 priv
->xstats
.rx_pkt_n
+= count
;
1384 * stmmac_poll - stmmac poll method (NAPI)
1385 * @napi : pointer to the napi structure.
1386 * @budget : maximum number of packets that the current CPU can receive from
1389 * This function implements the the reception process.
1390 * Also it runs the TX completion thread
1392 static int stmmac_poll(struct napi_struct
*napi
, int budget
)
1394 struct stmmac_priv
*priv
= container_of(napi
, struct stmmac_priv
, napi
);
1397 priv
->xstats
.poll_n
++;
1399 work_done
= stmmac_rx(priv
, budget
);
1401 if (work_done
< budget
) {
1402 napi_complete(napi
);
1403 stmmac_enable_irq(priv
);
1410 * @dev : Pointer to net device structure
1411 * Description: this function is called when a packet transmission fails to
1412 * complete within a reasonable tmrate. The driver will mark the error in the
1413 * netdev structure and arrange for the device to be reset to a sane state
1414 * in order to transmit a new packet.
1416 static void stmmac_tx_timeout(struct net_device
*dev
)
1418 struct stmmac_priv
*priv
= netdev_priv(dev
);
1420 /* Clear Tx resources and restart transmitting again */
1421 stmmac_tx_err(priv
);
1424 /* Configuration changes (passed on by ifconfig) */
1425 static int stmmac_config(struct net_device
*dev
, struct ifmap
*map
)
1427 if (dev
->flags
& IFF_UP
) /* can't act on a running interface */
1430 /* Don't allow changing the I/O address */
1431 if (map
->base_addr
!= dev
->base_addr
) {
1432 pr_warning("%s: can't change I/O address\n", dev
->name
);
1436 /* Don't allow changing the IRQ */
1437 if (map
->irq
!= dev
->irq
) {
1438 pr_warning("%s: can't change IRQ number %d\n",
1439 dev
->name
, dev
->irq
);
1443 /* ignore other fields */
1448 * stmmac_set_rx_mode - entry point for multicast addressing
1449 * @dev : pointer to the device structure
1451 * This function is a driver entry point which gets called by the kernel
1452 * whenever multicast addresses must be enabled/disabled.
1456 static void stmmac_set_rx_mode(struct net_device
*dev
)
1458 struct stmmac_priv
*priv
= netdev_priv(dev
);
1460 spin_lock(&priv
->lock
);
1461 priv
->hw
->mac
->set_filter(dev
);
1462 spin_unlock(&priv
->lock
);
1466 * stmmac_change_mtu - entry point to change MTU size for the device.
1467 * @dev : device pointer.
1468 * @new_mtu : the new MTU size for the device.
1469 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1470 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1471 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1473 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1476 static int stmmac_change_mtu(struct net_device
*dev
, int new_mtu
)
1478 struct stmmac_priv
*priv
= netdev_priv(dev
);
1481 if (netif_running(dev
)) {
1482 pr_err("%s: must be stopped to change its MTU\n", dev
->name
);
1486 if (priv
->plat
->enh_desc
)
1487 max_mtu
= JUMBO_LEN
;
1489 max_mtu
= SKB_MAX_HEAD(NET_SKB_PAD
+ NET_IP_ALIGN
);
1491 if ((new_mtu
< 46) || (new_mtu
> max_mtu
)) {
1492 pr_err("%s: invalid MTU, max MTU is: %d\n", dev
->name
, max_mtu
);
1497 netdev_update_features(dev
);
1502 static netdev_features_t
stmmac_fix_features(struct net_device
*dev
,
1503 netdev_features_t features
)
1505 struct stmmac_priv
*priv
= netdev_priv(dev
);
1507 if (priv
->plat
->rx_coe
== STMMAC_RX_COE_NONE
)
1508 features
&= ~NETIF_F_RXCSUM
;
1509 else if (priv
->plat
->rx_coe
== STMMAC_RX_COE_TYPE1
)
1510 features
&= ~NETIF_F_IPV6_CSUM
;
1511 if (!priv
->plat
->tx_coe
)
1512 features
&= ~NETIF_F_ALL_CSUM
;
1514 /* Some GMAC devices have a bugged Jumbo frame support that
1515 * needs to have the Tx COE disabled for oversized frames
1516 * (due to limited buffer sizes). In this case we disable
1517 * the TX csum insertionin the TDES and not use SF. */
1518 if (priv
->plat
->bugged_jumbo
&& (dev
->mtu
> ETH_DATA_LEN
))
1519 features
&= ~NETIF_F_ALL_CSUM
;
1524 static irqreturn_t
stmmac_interrupt(int irq
, void *dev_id
)
1526 struct net_device
*dev
= (struct net_device
*)dev_id
;
1527 struct stmmac_priv
*priv
= netdev_priv(dev
);
1529 if (unlikely(!dev
)) {
1530 pr_err("%s: invalid dev pointer\n", __func__
);
1534 if (priv
->plat
->has_gmac
)
1535 /* To handle GMAC own interrupts */
1536 priv
->hw
->mac
->host_irq_status((void __iomem
*) dev
->base_addr
);
1538 stmmac_dma_interrupt(priv
);
1543 #ifdef CONFIG_NET_POLL_CONTROLLER
1544 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1545 * to allow network I/O with interrupts disabled. */
1546 static void stmmac_poll_controller(struct net_device
*dev
)
1548 disable_irq(dev
->irq
);
1549 stmmac_interrupt(dev
->irq
, dev
);
1550 enable_irq(dev
->irq
);
1555 * stmmac_ioctl - Entry point for the Ioctl
1556 * @dev: Device pointer.
1557 * @rq: An IOCTL specefic structure, that can contain a pointer to
1558 * a proprietary structure used to pass information to the driver.
1559 * @cmd: IOCTL command
1561 * Currently there are no special functionality supported in IOCTL, just the
1562 * phy_mii_ioctl(...) can be invoked.
1564 static int stmmac_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
1566 struct stmmac_priv
*priv
= netdev_priv(dev
);
1569 if (!netif_running(dev
))
1575 ret
= phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
1580 #ifdef CONFIG_STMMAC_DEBUG_FS
1581 static struct dentry
*stmmac_fs_dir
;
1582 static struct dentry
*stmmac_rings_status
;
1583 static struct dentry
*stmmac_dma_cap
;
1585 static int stmmac_sysfs_ring_read(struct seq_file
*seq
, void *v
)
1593 struct net_device
*dev
= seq
->private;
1594 struct stmmac_priv
*priv
= netdev_priv(dev
);
1596 seq_printf(seq
, "=======================\n");
1597 seq_printf(seq
, " RX descriptor ring\n");
1598 seq_printf(seq
, "=======================\n");
1600 for (i
= 0; i
< priv
->dma_rx_size
; i
++) {
1601 struct tmp_s
*x
= (struct tmp_s
*)(priv
->dma_rx
+ i
);
1602 seq_printf(seq
, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1603 i
, (unsigned int)(x
->a
),
1604 (unsigned int)((x
->a
) >> 32), x
->b
, x
->c
);
1605 seq_printf(seq
, "\n");
1608 seq_printf(seq
, "\n");
1609 seq_printf(seq
, "=======================\n");
1610 seq_printf(seq
, " TX descriptor ring\n");
1611 seq_printf(seq
, "=======================\n");
1613 for (i
= 0; i
< priv
->dma_tx_size
; i
++) {
1614 struct tmp_s
*x
= (struct tmp_s
*)(priv
->dma_tx
+ i
);
1615 seq_printf(seq
, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1616 i
, (unsigned int)(x
->a
),
1617 (unsigned int)((x
->a
) >> 32), x
->b
, x
->c
);
1618 seq_printf(seq
, "\n");
1624 static int stmmac_sysfs_ring_open(struct inode
*inode
, struct file
*file
)
1626 return single_open(file
, stmmac_sysfs_ring_read
, inode
->i_private
);
1629 static const struct file_operations stmmac_rings_status_fops
= {
1630 .owner
= THIS_MODULE
,
1631 .open
= stmmac_sysfs_ring_open
,
1633 .llseek
= seq_lseek
,
1634 .release
= seq_release
,
1637 static int stmmac_sysfs_dma_cap_read(struct seq_file
*seq
, void *v
)
1639 struct net_device
*dev
= seq
->private;
1640 struct stmmac_priv
*priv
= netdev_priv(dev
);
1642 if (!priv
->hw_cap_support
) {
1643 seq_printf(seq
, "DMA HW features not supported\n");
1647 seq_printf(seq
, "==============================\n");
1648 seq_printf(seq
, "\tDMA HW features\n");
1649 seq_printf(seq
, "==============================\n");
1651 seq_printf(seq
, "\t10/100 Mbps %s\n",
1652 (priv
->dma_cap
.mbps_10_100
) ? "Y" : "N");
1653 seq_printf(seq
, "\t1000 Mbps %s\n",
1654 (priv
->dma_cap
.mbps_1000
) ? "Y" : "N");
1655 seq_printf(seq
, "\tHalf duple %s\n",
1656 (priv
->dma_cap
.half_duplex
) ? "Y" : "N");
1657 seq_printf(seq
, "\tHash Filter: %s\n",
1658 (priv
->dma_cap
.hash_filter
) ? "Y" : "N");
1659 seq_printf(seq
, "\tMultiple MAC address registers: %s\n",
1660 (priv
->dma_cap
.multi_addr
) ? "Y" : "N");
1661 seq_printf(seq
, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1662 (priv
->dma_cap
.pcs
) ? "Y" : "N");
1663 seq_printf(seq
, "\tSMA (MDIO) Interface: %s\n",
1664 (priv
->dma_cap
.sma_mdio
) ? "Y" : "N");
1665 seq_printf(seq
, "\tPMT Remote wake up: %s\n",
1666 (priv
->dma_cap
.pmt_remote_wake_up
) ? "Y" : "N");
1667 seq_printf(seq
, "\tPMT Magic Frame: %s\n",
1668 (priv
->dma_cap
.pmt_magic_frame
) ? "Y" : "N");
1669 seq_printf(seq
, "\tRMON module: %s\n",
1670 (priv
->dma_cap
.rmon
) ? "Y" : "N");
1671 seq_printf(seq
, "\tIEEE 1588-2002 Time Stamp: %s\n",
1672 (priv
->dma_cap
.time_stamp
) ? "Y" : "N");
1673 seq_printf(seq
, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1674 (priv
->dma_cap
.atime_stamp
) ? "Y" : "N");
1675 seq_printf(seq
, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1676 (priv
->dma_cap
.eee
) ? "Y" : "N");
1677 seq_printf(seq
, "\tAV features: %s\n", (priv
->dma_cap
.av
) ? "Y" : "N");
1678 seq_printf(seq
, "\tChecksum Offload in TX: %s\n",
1679 (priv
->dma_cap
.tx_coe
) ? "Y" : "N");
1680 seq_printf(seq
, "\tIP Checksum Offload (type1) in RX: %s\n",
1681 (priv
->dma_cap
.rx_coe_type1
) ? "Y" : "N");
1682 seq_printf(seq
, "\tIP Checksum Offload (type2) in RX: %s\n",
1683 (priv
->dma_cap
.rx_coe_type2
) ? "Y" : "N");
1684 seq_printf(seq
, "\tRXFIFO > 2048bytes: %s\n",
1685 (priv
->dma_cap
.rxfifo_over_2048
) ? "Y" : "N");
1686 seq_printf(seq
, "\tNumber of Additional RX channel: %d\n",
1687 priv
->dma_cap
.number_rx_channel
);
1688 seq_printf(seq
, "\tNumber of Additional TX channel: %d\n",
1689 priv
->dma_cap
.number_tx_channel
);
1690 seq_printf(seq
, "\tEnhanced descriptors: %s\n",
1691 (priv
->dma_cap
.enh_desc
) ? "Y" : "N");
1696 static int stmmac_sysfs_dma_cap_open(struct inode
*inode
, struct file
*file
)
1698 return single_open(file
, stmmac_sysfs_dma_cap_read
, inode
->i_private
);
1701 static const struct file_operations stmmac_dma_cap_fops
= {
1702 .owner
= THIS_MODULE
,
1703 .open
= stmmac_sysfs_dma_cap_open
,
1705 .llseek
= seq_lseek
,
1706 .release
= seq_release
,
1709 static int stmmac_init_fs(struct net_device
*dev
)
1711 /* Create debugfs entries */
1712 stmmac_fs_dir
= debugfs_create_dir(STMMAC_RESOURCE_NAME
, NULL
);
1714 if (!stmmac_fs_dir
|| IS_ERR(stmmac_fs_dir
)) {
1715 pr_err("ERROR %s, debugfs create directory failed\n",
1716 STMMAC_RESOURCE_NAME
);
1721 /* Entry to report DMA RX/TX rings */
1722 stmmac_rings_status
= debugfs_create_file("descriptors_status",
1723 S_IRUGO
, stmmac_fs_dir
, dev
,
1724 &stmmac_rings_status_fops
);
1726 if (!stmmac_rings_status
|| IS_ERR(stmmac_rings_status
)) {
1727 pr_info("ERROR creating stmmac ring debugfs file\n");
1728 debugfs_remove(stmmac_fs_dir
);
1733 /* Entry to report the DMA HW features */
1734 stmmac_dma_cap
= debugfs_create_file("dma_cap", S_IRUGO
, stmmac_fs_dir
,
1735 dev
, &stmmac_dma_cap_fops
);
1737 if (!stmmac_dma_cap
|| IS_ERR(stmmac_dma_cap
)) {
1738 pr_info("ERROR creating stmmac MMC debugfs file\n");
1739 debugfs_remove(stmmac_rings_status
);
1740 debugfs_remove(stmmac_fs_dir
);
1748 static void stmmac_exit_fs(void)
1750 debugfs_remove(stmmac_rings_status
);
1751 debugfs_remove(stmmac_dma_cap
);
1752 debugfs_remove(stmmac_fs_dir
);
1754 #endif /* CONFIG_STMMAC_DEBUG_FS */
1756 static const struct net_device_ops stmmac_netdev_ops
= {
1757 .ndo_open
= stmmac_open
,
1758 .ndo_start_xmit
= stmmac_xmit
,
1759 .ndo_stop
= stmmac_release
,
1760 .ndo_change_mtu
= stmmac_change_mtu
,
1761 .ndo_fix_features
= stmmac_fix_features
,
1762 .ndo_set_rx_mode
= stmmac_set_rx_mode
,
1763 .ndo_tx_timeout
= stmmac_tx_timeout
,
1764 .ndo_do_ioctl
= stmmac_ioctl
,
1765 .ndo_set_config
= stmmac_config
,
1766 #ifdef CONFIG_NET_POLL_CONTROLLER
1767 .ndo_poll_controller
= stmmac_poll_controller
,
1769 .ndo_set_mac_address
= eth_mac_addr
,
1773 * stmmac_hw_init - Init the MAC device
1774 * @priv : pointer to the private device structure.
1775 * Description: this function detects which MAC device
1776 * (GMAC/MAC10-100) has to attached, checks the HW capability
1777 * (if supported) and sets the driver's features (for example
1778 * to use the ring or chaine mode or support the normal/enh
1779 * descriptor structure).
1781 static int stmmac_hw_init(struct stmmac_priv
*priv
)
1784 struct mac_device_info
*mac
;
1786 /* Identify the MAC HW device */
1787 if (priv
->plat
->has_gmac
)
1788 mac
= dwmac1000_setup(priv
->ioaddr
);
1790 mac
= dwmac100_setup(priv
->ioaddr
);
1796 /* To use the chained or ring mode */
1797 priv
->hw
->ring
= &ring_mode_ops
;
1799 /* Get and dump the chip ID */
1800 stmmac_get_synopsys_id(priv
);
1802 /* Get the HW capability (new GMAC newer than 3.50a) */
1803 priv
->hw_cap_support
= stmmac_get_hw_features(priv
);
1804 if (priv
->hw_cap_support
) {
1805 pr_info(" DMA HW capability register supported");
1807 /* We can override some gmac/dma configuration fields: e.g.
1808 * enh_desc, tx_coe (e.g. that are passed through the
1809 * platform) with the values from the HW capability
1810 * register (if supported).
1812 priv
->plat
->enh_desc
= priv
->dma_cap
.enh_desc
;
1813 priv
->plat
->pmt
= priv
->dma_cap
.pmt_remote_wake_up
;
1815 priv
->plat
->tx_coe
= priv
->dma_cap
.tx_coe
;
1817 if (priv
->dma_cap
.rx_coe_type2
)
1818 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE2
;
1819 else if (priv
->dma_cap
.rx_coe_type1
)
1820 priv
->plat
->rx_coe
= STMMAC_RX_COE_TYPE1
;
1823 pr_info(" No HW DMA feature register supported");
1825 /* Select the enhnaced/normal descriptor structures */
1826 stmmac_selec_desc_mode(priv
);
1828 /* Enable the IPC (Checksum Offload) and check if the feature has been
1829 * enabled during the core configuration. */
1830 ret
= priv
->hw
->mac
->rx_ipc(priv
->ioaddr
);
1832 pr_warning(" RX IPC Checksum Offload not configured.\n");
1833 priv
->plat
->rx_coe
= STMMAC_RX_COE_NONE
;
1836 if (priv
->plat
->rx_coe
)
1837 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
1838 priv
->plat
->rx_coe
);
1839 if (priv
->plat
->tx_coe
)
1840 pr_info(" TX Checksum insertion supported\n");
1842 if (priv
->plat
->pmt
) {
1843 pr_info(" Wake-Up On Lan supported\n");
1844 device_set_wakeup_capable(priv
->device
, 1);
1852 * @device: device pointer
1853 * Description: this is the main probe function used to
1854 * call the alloc_etherdev, allocate the priv structure.
1856 struct stmmac_priv
*stmmac_dvr_probe(struct device
*device
,
1857 struct plat_stmmacenet_data
*plat_dat
,
1861 struct net_device
*ndev
= NULL
;
1862 struct stmmac_priv
*priv
;
1864 ndev
= alloc_etherdev(sizeof(struct stmmac_priv
));
1868 SET_NETDEV_DEV(ndev
, device
);
1870 priv
= netdev_priv(ndev
);
1871 priv
->device
= device
;
1876 stmmac_set_ethtool_ops(ndev
);
1877 priv
->pause
= pause
;
1878 priv
->plat
= plat_dat
;
1879 priv
->ioaddr
= addr
;
1880 priv
->dev
->base_addr
= (unsigned long)addr
;
1882 /* Verify driver arguments */
1883 stmmac_verify_args();
1885 /* Override with kernel parameters if supplied XXX CRS XXX
1886 * this needs to have multiple instances */
1887 if ((phyaddr
>= 0) && (phyaddr
<= 31))
1888 priv
->plat
->phy_addr
= phyaddr
;
1890 /* Init MAC and get the capabilities */
1891 stmmac_hw_init(priv
);
1893 ndev
->netdev_ops
= &stmmac_netdev_ops
;
1895 ndev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
1897 ndev
->features
|= ndev
->hw_features
| NETIF_F_HIGHDMA
;
1898 ndev
->watchdog_timeo
= msecs_to_jiffies(watchdog
);
1899 #ifdef STMMAC_VLAN_TAG_USED
1900 /* Both mac100 and gmac support receive VLAN tag detection */
1901 ndev
->features
|= NETIF_F_HW_VLAN_RX
;
1903 priv
->msg_enable
= netif_msg_init(debug
, default_msg_level
);
1906 priv
->flow_ctrl
= FLOW_AUTO
; /* RX/TX pause on */
1908 netif_napi_add(ndev
, &priv
->napi
, stmmac_poll
, 64);
1910 spin_lock_init(&priv
->lock
);
1911 spin_lock_init(&priv
->tx_lock
);
1913 ret
= register_netdev(ndev
);
1915 pr_err("%s: ERROR %i registering the device\n", __func__
, ret
);
1919 if (stmmac_clk_get(priv
))
1922 /* If a specific clk_csr value is passed from the platform
1923 * this means that the CSR Clock Range selection cannot be
1924 * changed at run-time and it is fixed. Viceversa the driver'll try to
1925 * set the MDC clock dynamically according to the csr actual
1928 if (!priv
->plat
->clk_csr
)
1929 stmmac_clk_csr_set(priv
);
1931 priv
->clk_csr
= priv
->plat
->clk_csr
;
1936 netif_napi_del(&priv
->napi
);
1938 unregister_netdev(ndev
);
1946 * @ndev: net device pointer
1947 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1948 * changes the link status, releases the DMA descriptor rings.
1950 int stmmac_dvr_remove(struct net_device
*ndev
)
1952 struct stmmac_priv
*priv
= netdev_priv(ndev
);
1954 pr_info("%s:\n\tremoving driver", __func__
);
1956 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
1957 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1959 stmmac_set_mac(priv
->ioaddr
, false);
1960 netif_carrier_off(ndev
);
1961 unregister_netdev(ndev
);
1968 int stmmac_suspend(struct net_device
*ndev
)
1970 struct stmmac_priv
*priv
= netdev_priv(ndev
);
1973 if (!ndev
|| !netif_running(ndev
))
1977 phy_stop(priv
->phydev
);
1979 spin_lock(&priv
->lock
);
1981 netif_device_detach(ndev
);
1982 netif_stop_queue(ndev
);
1984 #ifdef CONFIG_STMMAC_TIMER
1985 priv
->tm
->timer_stop();
1986 if (likely(priv
->tm
->enable
))
1989 napi_disable(&priv
->napi
);
1991 /* Stop TX/RX DMA */
1992 priv
->hw
->dma
->stop_tx(priv
->ioaddr
);
1993 priv
->hw
->dma
->stop_rx(priv
->ioaddr
);
1994 /* Clear the Rx/Tx descriptors */
1995 priv
->hw
->desc
->init_rx_desc(priv
->dma_rx
, priv
->dma_rx_size
,
1997 priv
->hw
->desc
->init_tx_desc(priv
->dma_tx
, priv
->dma_tx_size
);
1999 /* Enable Power down mode by programming the PMT regs */
2000 if (device_may_wakeup(priv
->device
))
2001 priv
->hw
->mac
->pmt(priv
->ioaddr
, priv
->wolopts
);
2003 stmmac_set_mac(priv
->ioaddr
, false);
2004 /* Disable clock in case of PWM is off */
2005 stmmac_clk_disable(priv
);
2007 spin_unlock(&priv
->lock
);
2011 int stmmac_resume(struct net_device
*ndev
)
2013 struct stmmac_priv
*priv
= netdev_priv(ndev
);
2015 if (!netif_running(ndev
))
2018 spin_lock(&priv
->lock
);
2020 /* Power Down bit, into the PM register, is cleared
2021 * automatically as soon as a magic packet or a Wake-up frame
2022 * is received. Anyway, it's better to manually clear
2023 * this bit because it can generate problems while resuming
2024 * from another devices (e.g. serial console). */
2025 if (device_may_wakeup(priv
->device
))
2026 priv
->hw
->mac
->pmt(priv
->ioaddr
, 0);
2028 /* enable the clk prevously disabled */
2029 stmmac_clk_enable(priv
);
2031 netif_device_attach(ndev
);
2033 /* Enable the MAC and DMA */
2034 stmmac_set_mac(priv
->ioaddr
, true);
2035 priv
->hw
->dma
->start_tx(priv
->ioaddr
);
2036 priv
->hw
->dma
->start_rx(priv
->ioaddr
);
2038 #ifdef CONFIG_STMMAC_TIMER
2039 if (likely(priv
->tm
->enable
))
2040 priv
->tm
->timer_start(tmrate
);
2042 napi_enable(&priv
->napi
);
2044 netif_start_queue(ndev
);
2046 spin_unlock(&priv
->lock
);
2049 phy_start(priv
->phydev
);
2054 int stmmac_freeze(struct net_device
*ndev
)
2056 if (!ndev
|| !netif_running(ndev
))
2059 return stmmac_release(ndev
);
2062 int stmmac_restore(struct net_device
*ndev
)
2064 if (!ndev
|| !netif_running(ndev
))
2067 return stmmac_open(ndev
);
2069 #endif /* CONFIG_PM */
2072 static int __init
stmmac_cmdline_opt(char *str
)
2078 while ((opt
= strsep(&str
, ",")) != NULL
) {
2079 if (!strncmp(opt
, "debug:", 6)) {
2080 if (strict_strtoul(opt
+ 6, 0, (unsigned long *)&debug
))
2082 } else if (!strncmp(opt
, "phyaddr:", 8)) {
2083 if (strict_strtoul(opt
+ 8, 0,
2084 (unsigned long *)&phyaddr
))
2086 } else if (!strncmp(opt
, "dma_txsize:", 11)) {
2087 if (strict_strtoul(opt
+ 11, 0,
2088 (unsigned long *)&dma_txsize
))
2090 } else if (!strncmp(opt
, "dma_rxsize:", 11)) {
2091 if (strict_strtoul(opt
+ 11, 0,
2092 (unsigned long *)&dma_rxsize
))
2094 } else if (!strncmp(opt
, "buf_sz:", 7)) {
2095 if (strict_strtoul(opt
+ 7, 0,
2096 (unsigned long *)&buf_sz
))
2098 } else if (!strncmp(opt
, "tc:", 3)) {
2099 if (strict_strtoul(opt
+ 3, 0, (unsigned long *)&tc
))
2101 } else if (!strncmp(opt
, "watchdog:", 9)) {
2102 if (strict_strtoul(opt
+ 9, 0,
2103 (unsigned long *)&watchdog
))
2105 } else if (!strncmp(opt
, "flow_ctrl:", 10)) {
2106 if (strict_strtoul(opt
+ 10, 0,
2107 (unsigned long *)&flow_ctrl
))
2109 } else if (!strncmp(opt
, "pause:", 6)) {
2110 if (strict_strtoul(opt
+ 6, 0, (unsigned long *)&pause
))
2112 #ifdef CONFIG_STMMAC_TIMER
2113 } else if (!strncmp(opt
, "tmrate:", 7)) {
2114 if (strict_strtoul(opt
+ 7, 0,
2115 (unsigned long *)&tmrate
))
2123 pr_err("%s: ERROR broken module parameter conversion", __func__
);
2127 __setup("stmmaceth=", stmmac_cmdline_opt
);
2130 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2131 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2132 MODULE_LICENSE("GPL");