2 * Texas Instruments Ethernet Switch Driver
4 * Copyright (C) 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
39 #include <linux/pinctrl/consumer.h>
44 #include "davinci_cpdma.h"
46 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
55 #define cpsw_info(priv, type, format, ...) \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
61 #define cpsw_err(priv, type, format, ...) \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
67 #define cpsw_dbg(priv, type, format, ...) \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
73 #define cpsw_notice(priv, type, format, ...) \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
79 #define ALE_ALL_PORTS 0x7
81 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
85 #define CPSW_VERSION_1 0x19010a
86 #define CPSW_VERSION_2 0x19010c
87 #define CPSW_VERSION_3 0x19010f
88 #define CPSW_VERSION_4 0x190112
90 #define HOST_PORT_NUM 0
91 #define SLIVER_SIZE 0x40
93 #define CPSW1_HOST_PORT_OFFSET 0x028
94 #define CPSW1_SLAVE_OFFSET 0x050
95 #define CPSW1_SLAVE_SIZE 0x040
96 #define CPSW1_CPDMA_OFFSET 0x100
97 #define CPSW1_STATERAM_OFFSET 0x200
98 #define CPSW1_HW_STATS 0x400
99 #define CPSW1_CPTS_OFFSET 0x500
100 #define CPSW1_ALE_OFFSET 0x600
101 #define CPSW1_SLIVER_OFFSET 0x700
103 #define CPSW2_HOST_PORT_OFFSET 0x108
104 #define CPSW2_SLAVE_OFFSET 0x200
105 #define CPSW2_SLAVE_SIZE 0x100
106 #define CPSW2_CPDMA_OFFSET 0x800
107 #define CPSW2_HW_STATS 0x900
108 #define CPSW2_STATERAM_OFFSET 0xa00
109 #define CPSW2_CPTS_OFFSET 0xc00
110 #define CPSW2_ALE_OFFSET 0xd00
111 #define CPSW2_SLIVER_OFFSET 0xd80
112 #define CPSW2_BD_OFFSET 0x2000
114 #define CPDMA_RXTHRESH 0x0c0
115 #define CPDMA_RXFREE 0x0e0
116 #define CPDMA_TXHDP 0x00
117 #define CPDMA_RXHDP 0x20
118 #define CPDMA_TXCP 0x40
119 #define CPDMA_RXCP 0x60
121 #define CPSW_POLL_WEIGHT 64
122 #define CPSW_MIN_PACKET_SIZE 60
123 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
125 #define RX_PRIORITY_MAPPING 0x76543210
126 #define TX_PRIORITY_MAPPING 0x33221100
127 #define CPDMA_TX_PRIORITY_MAP 0x76543210
129 #define CPSW_VLAN_AWARE BIT(1)
130 #define CPSW_ALE_VLAN_AWARE 1
132 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
136 #define CPSW_INTPACEEN (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT 63
139 #define CPSW_CMINTMIN_CNT 2
140 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
143 #define cpsw_slave_index(priv) \
144 ((priv->data.dual_emac) ? priv->emac_port : \
145 priv->data.active_slave)
147 static int debug_level
;
148 module_param(debug_level
, int, 0);
149 MODULE_PARM_DESC(debug_level
, "cpsw debug level (NETIF_MSG bits)");
151 static int ale_ageout
= 10;
152 module_param(ale_ageout
, int, 0);
153 MODULE_PARM_DESC(ale_ageout
, "cpsw ale ageout interval (seconds)");
155 static int rx_packet_max
= CPSW_MAX_PACKET_SIZE
;
156 module_param(rx_packet_max
, int, 0);
157 MODULE_PARM_DESC(rx_packet_max
, "maximum receive packet size (bytes)");
159 struct cpsw_wr_regs
{
179 struct cpsw_ss_regs
{
196 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
197 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
198 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
199 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
200 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
201 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
202 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
203 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
206 #define CPSW2_CONTROL 0x00 /* Control Register */
207 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
208 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
209 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
210 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
211 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
212 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
214 /* CPSW_PORT_V1 and V2 */
215 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
216 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
217 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
219 /* CPSW_PORT_V2 only */
220 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
221 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
222 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
223 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
224 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
225 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
226 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
227 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
229 /* Bit definitions for the CPSW2_CONTROL register */
230 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
231 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
232 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
233 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
234 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
235 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
236 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
237 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
238 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
239 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
240 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
241 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
242 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
243 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
244 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
245 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
246 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
248 #define CTRL_V2_TS_BITS \
249 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
250 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
252 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
253 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
254 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
257 #define CTRL_V3_TS_BITS \
258 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
259 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
262 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
263 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
264 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
269 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270 #define TS_MSG_TYPE_EN_MASK (0xffff)
272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
275 /* Bit definitions for the CPSW1_TS_CTL register */
276 #define CPSW_V1_TS_RX_EN BIT(0)
277 #define CPSW_V1_TS_TX_EN BIT(4)
278 #define CPSW_V1_MSG_TYPE_OFS 16
280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
283 struct cpsw_host_regs
{
289 u32 cpdma_tx_pri_map
;
290 u32 cpdma_rx_chan_map
;
293 struct cpsw_sliver_regs
{
306 struct cpsw_hw_stats
{
308 u32 rxbroadcastframes
;
309 u32 rxmulticastframes
;
312 u32 rxaligncodeerrors
;
313 u32 rxoversizedframes
;
315 u32 rxundersizedframes
;
320 u32 txbroadcastframes
;
321 u32 txmulticastframes
;
323 u32 txdeferredframes
;
324 u32 txcollisionframes
;
325 u32 txsinglecollframes
;
326 u32 txmultcollframes
;
327 u32 txexcessivecollisions
;
328 u32 txlatecollisions
;
330 u32 txcarriersenseerrors
;
333 u32 octetframes65t127
;
334 u32 octetframes128t255
;
335 u32 octetframes256t511
;
336 u32 octetframes512t1023
;
337 u32 octetframes1024tup
;
346 struct cpsw_sliver_regs __iomem
*sliver
;
349 struct cpsw_slave_data
*data
;
350 struct phy_device
*phy
;
351 struct net_device
*ndev
;
356 static inline u32
slave_read(struct cpsw_slave
*slave
, u32 offset
)
358 return __raw_readl(slave
->regs
+ offset
);
361 static inline void slave_write(struct cpsw_slave
*slave
, u32 val
, u32 offset
)
363 __raw_writel(val
, slave
->regs
+ offset
);
367 struct platform_device
*pdev
;
368 struct net_device
*ndev
;
369 struct napi_struct napi_rx
;
370 struct napi_struct napi_tx
;
372 struct cpsw_platform_data data
;
373 struct cpsw_ss_regs __iomem
*regs
;
374 struct cpsw_wr_regs __iomem
*wr_regs
;
375 u8 __iomem
*hw_stats
;
376 struct cpsw_host_regs __iomem
*host_port_regs
;
383 u8 mac_addr
[ETH_ALEN
];
384 struct cpsw_slave
*slaves
;
385 struct cpdma_ctlr
*dma
;
386 struct cpdma_chan
*txch
, *rxch
;
387 struct cpsw_ale
*ale
;
391 bool rx_irq_disabled
;
392 bool tx_irq_disabled
;
393 /* snapshot of IRQ numbers */
401 char stat_string
[ETH_GSTRING_LEN
];
413 #define CPSW_STAT(m) CPSW_STATS, \
414 sizeof(((struct cpsw_hw_stats *)0)->m), \
415 offsetof(struct cpsw_hw_stats, m)
416 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
417 sizeof(((struct cpdma_chan_stats *)0)->m), \
418 offsetof(struct cpdma_chan_stats, m)
419 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
420 sizeof(((struct cpdma_chan_stats *)0)->m), \
421 offsetof(struct cpdma_chan_stats, m)
423 static const struct cpsw_stats cpsw_gstrings_stats
[] = {
424 { "Good Rx Frames", CPSW_STAT(rxgoodframes
) },
425 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes
) },
426 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes
) },
427 { "Pause Rx Frames", CPSW_STAT(rxpauseframes
) },
428 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors
) },
429 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors
) },
430 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes
) },
431 { "Rx Jabbers", CPSW_STAT(rxjabberframes
) },
432 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes
) },
433 { "Rx Fragments", CPSW_STAT(rxfragments
) },
434 { "Rx Octets", CPSW_STAT(rxoctets
) },
435 { "Good Tx Frames", CPSW_STAT(txgoodframes
) },
436 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes
) },
437 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes
) },
438 { "Pause Tx Frames", CPSW_STAT(txpauseframes
) },
439 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes
) },
440 { "Collisions", CPSW_STAT(txcollisionframes
) },
441 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes
) },
442 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes
) },
443 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions
) },
444 { "Late Collisions", CPSW_STAT(txlatecollisions
) },
445 { "Tx Underrun", CPSW_STAT(txunderrun
) },
446 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors
) },
447 { "Tx Octets", CPSW_STAT(txoctets
) },
448 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64
) },
449 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127
) },
450 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255
) },
451 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511
) },
452 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023
) },
453 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup
) },
454 { "Net Octets", CPSW_STAT(netoctets
) },
455 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns
) },
456 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns
) },
457 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns
) },
458 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue
) },
459 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue
) },
460 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue
) },
461 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued
) },
462 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail
) },
463 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail
) },
464 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff
) },
465 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff
) },
466 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue
) },
467 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue
) },
468 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue
) },
469 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue
) },
470 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue
) },
471 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue
) },
472 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue
) },
473 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue
) },
474 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued
) },
475 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail
) },
476 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail
) },
477 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff
) },
478 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff
) },
479 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue
) },
480 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue
) },
481 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue
) },
482 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue
) },
483 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue
) },
486 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
488 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
489 #define for_each_slave(priv, func, arg...) \
491 struct cpsw_slave *slave; \
493 if (priv->data.dual_emac) \
494 (func)((priv)->slaves + priv->emac_port, ##arg);\
496 for (n = (priv)->data.slaves, \
497 slave = (priv)->slaves; \
499 (func)(slave++, ##arg); \
501 #define cpsw_get_slave_ndev(priv, __slave_no__) \
502 ((__slave_no__ < priv->data.slaves) ? \
503 priv->slaves[__slave_no__].ndev : NULL)
504 #define cpsw_get_slave_priv(priv, __slave_no__) \
505 (((__slave_no__ < priv->data.slaves) && \
506 (priv->slaves[__slave_no__].ndev)) ? \
507 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
509 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
511 if (!priv->data.dual_emac) \
513 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
514 ndev = cpsw_get_slave_ndev(priv, 0); \
515 priv = netdev_priv(ndev); \
517 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
518 ndev = cpsw_get_slave_ndev(priv, 1); \
519 priv = netdev_priv(ndev); \
523 #define cpsw_add_mcast(priv, addr) \
525 if (priv->data.dual_emac) { \
526 struct cpsw_slave *slave = priv->slaves + \
528 int slave_port = cpsw_get_slave_port(priv, \
530 cpsw_ale_add_mcast(priv->ale, addr, \
531 1 << slave_port | ALE_PORT_HOST, \
532 ALE_VLAN, slave->port_vlan, 0); \
534 cpsw_ale_add_mcast(priv->ale, addr, \
540 static inline int cpsw_get_slave_port(struct cpsw_priv
*priv
, u32 slave_num
)
542 return slave_num
+ 1;
545 static void cpsw_set_promiscious(struct net_device
*ndev
, bool enable
)
547 struct cpsw_priv
*priv
= netdev_priv(ndev
);
548 struct cpsw_ale
*ale
= priv
->ale
;
551 if (priv
->data
.dual_emac
) {
554 /* Enabling promiscuous mode for one interface will be
555 * common for both the interface as the interface shares
556 * the same hardware resource.
558 for (i
= 0; i
< priv
->data
.slaves
; i
++)
559 if (priv
->slaves
[i
].ndev
->flags
& IFF_PROMISC
)
562 if (!enable
&& flag
) {
564 dev_err(&ndev
->dev
, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
569 cpsw_ale_control_set(ale
, 0, ALE_BYPASS
, 1);
571 dev_dbg(&ndev
->dev
, "promiscuity enabled\n");
574 cpsw_ale_control_set(ale
, 0, ALE_BYPASS
, 0);
575 dev_dbg(&ndev
->dev
, "promiscuity disabled\n");
579 unsigned long timeout
= jiffies
+ HZ
;
581 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
582 for (i
= 0; i
<= priv
->data
.slaves
; i
++) {
583 cpsw_ale_control_set(ale
, i
,
584 ALE_PORT_NOLEARN
, 1);
585 cpsw_ale_control_set(ale
, i
,
586 ALE_PORT_NO_SA_UPDATE
, 1);
589 /* Clear All Untouched entries */
590 cpsw_ale_control_set(ale
, 0, ALE_AGEOUT
, 1);
593 if (cpsw_ale_control_get(ale
, 0, ALE_AGEOUT
))
595 } while (time_after(timeout
, jiffies
));
596 cpsw_ale_control_set(ale
, 0, ALE_AGEOUT
, 1);
598 /* Clear all mcast from ALE */
599 cpsw_ale_flush_multicast(ale
, ALE_ALL_PORTS
, -1);
601 /* Flood All Unicast Packets to Host port */
602 cpsw_ale_control_set(ale
, 0, ALE_P0_UNI_FLOOD
, 1);
603 dev_dbg(&ndev
->dev
, "promiscuity enabled\n");
605 /* Don't Flood All Unicast Packets to Host port */
606 cpsw_ale_control_set(ale
, 0, ALE_P0_UNI_FLOOD
, 0);
608 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
609 for (i
= 0; i
<= priv
->data
.slaves
; i
++) {
610 cpsw_ale_control_set(ale
, i
,
611 ALE_PORT_NOLEARN
, 0);
612 cpsw_ale_control_set(ale
, i
,
613 ALE_PORT_NO_SA_UPDATE
, 0);
615 dev_dbg(&ndev
->dev
, "promiscuity disabled\n");
620 static void cpsw_ndo_set_rx_mode(struct net_device
*ndev
)
622 struct cpsw_priv
*priv
= netdev_priv(ndev
);
625 if (priv
->data
.dual_emac
)
626 vid
= priv
->slaves
[priv
->emac_port
].port_vlan
;
628 vid
= priv
->data
.default_vlan
;
630 if (ndev
->flags
& IFF_PROMISC
) {
631 /* Enable promiscuous mode */
632 cpsw_set_promiscious(ndev
, true);
633 cpsw_ale_set_allmulti(priv
->ale
, IFF_ALLMULTI
);
636 /* Disable promiscuous mode */
637 cpsw_set_promiscious(ndev
, false);
640 /* Restore allmulti on vlans if necessary */
641 cpsw_ale_set_allmulti(priv
->ale
, priv
->ndev
->flags
& IFF_ALLMULTI
);
643 /* Clear all mcast from ALE */
644 cpsw_ale_flush_multicast(priv
->ale
, ALE_ALL_PORTS
, vid
);
646 if (!netdev_mc_empty(ndev
)) {
647 struct netdev_hw_addr
*ha
;
649 /* program multicast address list into ALE register */
650 netdev_for_each_mc_addr(ha
, ndev
) {
651 cpsw_add_mcast(priv
, (u8
*)ha
->addr
);
656 static void cpsw_intr_enable(struct cpsw_priv
*priv
)
658 __raw_writel(0xFF, &priv
->wr_regs
->tx_en
);
659 __raw_writel(0xFF, &priv
->wr_regs
->rx_en
);
661 cpdma_ctlr_int_ctrl(priv
->dma
, true);
665 static void cpsw_intr_disable(struct cpsw_priv
*priv
)
667 __raw_writel(0, &priv
->wr_regs
->tx_en
);
668 __raw_writel(0, &priv
->wr_regs
->rx_en
);
670 cpdma_ctlr_int_ctrl(priv
->dma
, false);
674 static void cpsw_tx_handler(void *token
, int len
, int status
)
676 struct sk_buff
*skb
= token
;
677 struct net_device
*ndev
= skb
->dev
;
678 struct cpsw_priv
*priv
= netdev_priv(ndev
);
680 /* Check whether the queue is stopped due to stalled tx dma, if the
681 * queue is stopped then start the queue as we have free desc for tx
683 if (unlikely(netif_queue_stopped(ndev
)))
684 netif_wake_queue(ndev
);
685 cpts_tx_timestamp(priv
->cpts
, skb
);
686 ndev
->stats
.tx_packets
++;
687 ndev
->stats
.tx_bytes
+= len
;
688 dev_kfree_skb_any(skb
);
691 static void cpsw_rx_handler(void *token
, int len
, int status
)
693 struct sk_buff
*skb
= token
;
694 struct sk_buff
*new_skb
;
695 struct net_device
*ndev
= skb
->dev
;
696 struct cpsw_priv
*priv
= netdev_priv(ndev
);
699 cpsw_dual_emac_src_port_detect(status
, priv
, ndev
, skb
);
701 if (unlikely(status
< 0) || unlikely(!netif_running(ndev
))) {
702 bool ndev_status
= false;
703 struct cpsw_slave
*slave
= priv
->slaves
;
706 if (priv
->data
.dual_emac
) {
707 /* In dual emac mode check for all interfaces */
708 for (n
= priv
->data
.slaves
; n
; n
--, slave
++)
709 if (netif_running(slave
->ndev
))
713 if (ndev_status
&& (status
>= 0)) {
714 /* The packet received is for the interface which
715 * is already down and the other interface is up
716 * and running, instead of freeing which results
717 * in reducing of the number of rx descriptor in
718 * DMA engine, requeue skb back to cpdma.
724 /* the interface is going down, skbs are purged */
725 dev_kfree_skb_any(skb
);
729 new_skb
= netdev_alloc_skb_ip_align(ndev
, priv
->rx_packet_max
);
732 cpts_rx_timestamp(priv
->cpts
, skb
);
733 skb
->protocol
= eth_type_trans(skb
, ndev
);
734 netif_receive_skb(skb
);
735 ndev
->stats
.rx_bytes
+= len
;
736 ndev
->stats
.rx_packets
++;
738 ndev
->stats
.rx_dropped
++;
743 ret
= cpdma_chan_submit(priv
->rxch
, new_skb
, new_skb
->data
,
744 skb_tailroom(new_skb
), 0);
745 if (WARN_ON(ret
< 0))
746 dev_kfree_skb_any(new_skb
);
749 static irqreturn_t
cpsw_tx_interrupt(int irq
, void *dev_id
)
751 struct cpsw_priv
*priv
= dev_id
;
753 writel(0, &priv
->wr_regs
->tx_en
);
754 cpdma_ctlr_eoi(priv
->dma
, CPDMA_EOI_TX
);
756 if (priv
->quirk_irq
) {
757 disable_irq_nosync(priv
->irqs_table
[1]);
758 priv
->tx_irq_disabled
= true;
761 napi_schedule(&priv
->napi_tx
);
765 static irqreturn_t
cpsw_rx_interrupt(int irq
, void *dev_id
)
767 struct cpsw_priv
*priv
= dev_id
;
769 cpdma_ctlr_eoi(priv
->dma
, CPDMA_EOI_RX
);
770 writel(0, &priv
->wr_regs
->rx_en
);
772 if (priv
->quirk_irq
) {
773 disable_irq_nosync(priv
->irqs_table
[0]);
774 priv
->rx_irq_disabled
= true;
777 napi_schedule(&priv
->napi_rx
);
781 static int cpsw_tx_poll(struct napi_struct
*napi_tx
, int budget
)
783 struct cpsw_priv
*priv
= napi_to_priv(napi_tx
);
786 num_tx
= cpdma_chan_process(priv
->txch
, budget
);
787 if (num_tx
< budget
) {
788 napi_complete(napi_tx
);
789 writel(0xff, &priv
->wr_regs
->tx_en
);
790 if (priv
->quirk_irq
&& priv
->tx_irq_disabled
) {
791 priv
->tx_irq_disabled
= false;
792 enable_irq(priv
->irqs_table
[1]);
797 cpsw_dbg(priv
, intr
, "poll %d tx pkts\n", num_tx
);
802 static int cpsw_rx_poll(struct napi_struct
*napi_rx
, int budget
)
804 struct cpsw_priv
*priv
= napi_to_priv(napi_rx
);
807 num_rx
= cpdma_chan_process(priv
->rxch
, budget
);
808 if (num_rx
< budget
) {
809 napi_complete(napi_rx
);
810 writel(0xff, &priv
->wr_regs
->rx_en
);
811 if (priv
->quirk_irq
&& priv
->rx_irq_disabled
) {
812 priv
->rx_irq_disabled
= false;
813 enable_irq(priv
->irqs_table
[0]);
818 cpsw_dbg(priv
, intr
, "poll %d rx pkts\n", num_rx
);
823 static inline void soft_reset(const char *module
, void __iomem
*reg
)
825 unsigned long timeout
= jiffies
+ HZ
;
827 __raw_writel(1, reg
);
830 } while ((__raw_readl(reg
) & 1) && time_after(timeout
, jiffies
));
832 WARN(__raw_readl(reg
) & 1, "failed to soft-reset %s\n", module
);
835 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
836 ((mac)[2] << 16) | ((mac)[3] << 24))
837 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
839 static void cpsw_set_slave_mac(struct cpsw_slave
*slave
,
840 struct cpsw_priv
*priv
)
842 slave_write(slave
, mac_hi(priv
->mac_addr
), SA_HI
);
843 slave_write(slave
, mac_lo(priv
->mac_addr
), SA_LO
);
846 static void _cpsw_adjust_link(struct cpsw_slave
*slave
,
847 struct cpsw_priv
*priv
, bool *link
)
849 struct phy_device
*phy
= slave
->phy
;
856 slave_port
= cpsw_get_slave_port(priv
, slave
->slave_num
);
859 mac_control
= priv
->data
.mac_control
;
861 /* enable forwarding */
862 cpsw_ale_control_set(priv
->ale
, slave_port
,
863 ALE_PORT_STATE
, ALE_PORT_STATE_FORWARD
);
865 if (phy
->speed
== 1000)
866 mac_control
|= BIT(7); /* GIGABITEN */
868 mac_control
|= BIT(0); /* FULLDUPLEXEN */
870 /* set speed_in input in case RMII mode is used in 100Mbps */
871 if (phy
->speed
== 100)
872 mac_control
|= BIT(15);
873 else if (phy
->speed
== 10)
874 mac_control
|= BIT(18); /* In Band mode */
877 mac_control
|= BIT(3);
880 mac_control
|= BIT(4);
885 /* disable forwarding */
886 cpsw_ale_control_set(priv
->ale
, slave_port
,
887 ALE_PORT_STATE
, ALE_PORT_STATE_DISABLE
);
890 if (mac_control
!= slave
->mac_control
) {
891 phy_print_status(phy
);
892 __raw_writel(mac_control
, &slave
->sliver
->mac_control
);
895 slave
->mac_control
= mac_control
;
898 static void cpsw_adjust_link(struct net_device
*ndev
)
900 struct cpsw_priv
*priv
= netdev_priv(ndev
);
903 for_each_slave(priv
, _cpsw_adjust_link
, priv
, &link
);
906 netif_carrier_on(ndev
);
907 if (netif_running(ndev
))
908 netif_wake_queue(ndev
);
910 netif_carrier_off(ndev
);
911 netif_stop_queue(ndev
);
915 static int cpsw_get_coalesce(struct net_device
*ndev
,
916 struct ethtool_coalesce
*coal
)
918 struct cpsw_priv
*priv
= netdev_priv(ndev
);
920 coal
->rx_coalesce_usecs
= priv
->coal_intvl
;
924 static int cpsw_set_coalesce(struct net_device
*ndev
,
925 struct ethtool_coalesce
*coal
)
927 struct cpsw_priv
*priv
= netdev_priv(ndev
);
929 u32 num_interrupts
= 0;
934 coal_intvl
= coal
->rx_coalesce_usecs
;
936 int_ctrl
= readl(&priv
->wr_regs
->int_control
);
937 prescale
= priv
->bus_freq_mhz
* 4;
939 if (!coal
->rx_coalesce_usecs
) {
940 int_ctrl
&= ~(CPSW_INTPRESCALE_MASK
| CPSW_INTPACEEN
);
944 if (coal_intvl
< CPSW_CMINTMIN_INTVL
)
945 coal_intvl
= CPSW_CMINTMIN_INTVL
;
947 if (coal_intvl
> CPSW_CMINTMAX_INTVL
) {
948 /* Interrupt pacer works with 4us Pulse, we can
949 * throttle further by dilating the 4us pulse.
951 addnl_dvdr
= CPSW_INTPRESCALE_MASK
/ prescale
;
953 if (addnl_dvdr
> 1) {
954 prescale
*= addnl_dvdr
;
955 if (coal_intvl
> (CPSW_CMINTMAX_INTVL
* addnl_dvdr
))
956 coal_intvl
= (CPSW_CMINTMAX_INTVL
960 coal_intvl
= CPSW_CMINTMAX_INTVL
;
964 num_interrupts
= (1000 * addnl_dvdr
) / coal_intvl
;
965 writel(num_interrupts
, &priv
->wr_regs
->rx_imax
);
966 writel(num_interrupts
, &priv
->wr_regs
->tx_imax
);
968 int_ctrl
|= CPSW_INTPACEEN
;
969 int_ctrl
&= (~CPSW_INTPRESCALE_MASK
);
970 int_ctrl
|= (prescale
& CPSW_INTPRESCALE_MASK
);
973 writel(int_ctrl
, &priv
->wr_regs
->int_control
);
975 cpsw_notice(priv
, timer
, "Set coalesce to %d usecs.\n", coal_intvl
);
976 if (priv
->data
.dual_emac
) {
979 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
980 priv
= netdev_priv(priv
->slaves
[i
].ndev
);
981 priv
->coal_intvl
= coal_intvl
;
984 priv
->coal_intvl
= coal_intvl
;
990 static int cpsw_get_sset_count(struct net_device
*ndev
, int sset
)
994 return CPSW_STATS_LEN
;
1000 static void cpsw_get_strings(struct net_device
*ndev
, u32 stringset
, u8
*data
)
1005 switch (stringset
) {
1007 for (i
= 0; i
< CPSW_STATS_LEN
; i
++) {
1008 memcpy(p
, cpsw_gstrings_stats
[i
].stat_string
,
1010 p
+= ETH_GSTRING_LEN
;
1016 static void cpsw_get_ethtool_stats(struct net_device
*ndev
,
1017 struct ethtool_stats
*stats
, u64
*data
)
1019 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1020 struct cpdma_chan_stats rx_stats
;
1021 struct cpdma_chan_stats tx_stats
;
1026 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1027 cpdma_chan_get_stats(priv
->rxch
, &rx_stats
);
1028 cpdma_chan_get_stats(priv
->txch
, &tx_stats
);
1030 for (i
= 0; i
< CPSW_STATS_LEN
; i
++) {
1031 switch (cpsw_gstrings_stats
[i
].type
) {
1033 val
= readl(priv
->hw_stats
+
1034 cpsw_gstrings_stats
[i
].stat_offset
);
1038 case CPDMA_RX_STATS
:
1039 p
= (u8
*)&rx_stats
+
1040 cpsw_gstrings_stats
[i
].stat_offset
;
1041 data
[i
] = *(u32
*)p
;
1044 case CPDMA_TX_STATS
:
1045 p
= (u8
*)&tx_stats
+
1046 cpsw_gstrings_stats
[i
].stat_offset
;
1047 data
[i
] = *(u32
*)p
;
1053 static int cpsw_common_res_usage_state(struct cpsw_priv
*priv
)
1056 u32 usage_count
= 0;
1058 if (!priv
->data
.dual_emac
)
1061 for (i
= 0; i
< priv
->data
.slaves
; i
++)
1062 if (priv
->slaves
[i
].open_stat
)
1068 static inline int cpsw_tx_packet_submit(struct net_device
*ndev
,
1069 struct cpsw_priv
*priv
, struct sk_buff
*skb
)
1071 if (!priv
->data
.dual_emac
)
1072 return cpdma_chan_submit(priv
->txch
, skb
, skb
->data
,
1075 if (ndev
== cpsw_get_slave_ndev(priv
, 0))
1076 return cpdma_chan_submit(priv
->txch
, skb
, skb
->data
,
1079 return cpdma_chan_submit(priv
->txch
, skb
, skb
->data
,
1083 static inline void cpsw_add_dual_emac_def_ale_entries(
1084 struct cpsw_priv
*priv
, struct cpsw_slave
*slave
,
1087 u32 port_mask
= 1 << slave_port
| ALE_PORT_HOST
;
1089 if (priv
->version
== CPSW_VERSION_1
)
1090 slave_write(slave
, slave
->port_vlan
, CPSW1_PORT_VLAN
);
1092 slave_write(slave
, slave
->port_vlan
, CPSW2_PORT_VLAN
);
1093 cpsw_ale_add_vlan(priv
->ale
, slave
->port_vlan
, port_mask
,
1094 port_mask
, port_mask
, 0);
1095 cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1096 port_mask
, ALE_VLAN
, slave
->port_vlan
, 0);
1097 cpsw_ale_add_ucast(priv
->ale
, priv
->mac_addr
,
1098 HOST_PORT_NUM
, ALE_VLAN
| ALE_SECURE
, slave
->port_vlan
);
1101 static void soft_reset_slave(struct cpsw_slave
*slave
)
1105 snprintf(name
, sizeof(name
), "slave-%d", slave
->slave_num
);
1106 soft_reset(name
, &slave
->sliver
->soft_reset
);
1109 static void cpsw_slave_open(struct cpsw_slave
*slave
, struct cpsw_priv
*priv
)
1113 soft_reset_slave(slave
);
1115 /* setup priority mapping */
1116 __raw_writel(RX_PRIORITY_MAPPING
, &slave
->sliver
->rx_pri_map
);
1118 switch (priv
->version
) {
1119 case CPSW_VERSION_1
:
1120 slave_write(slave
, TX_PRIORITY_MAPPING
, CPSW1_TX_PRI_MAP
);
1122 case CPSW_VERSION_2
:
1123 case CPSW_VERSION_3
:
1124 case CPSW_VERSION_4
:
1125 slave_write(slave
, TX_PRIORITY_MAPPING
, CPSW2_TX_PRI_MAP
);
1129 /* setup max packet size, and mac address */
1130 __raw_writel(priv
->rx_packet_max
, &slave
->sliver
->rx_maxlen
);
1131 cpsw_set_slave_mac(slave
, priv
);
1133 slave
->mac_control
= 0; /* no link yet */
1135 slave_port
= cpsw_get_slave_port(priv
, slave
->slave_num
);
1137 if (priv
->data
.dual_emac
)
1138 cpsw_add_dual_emac_def_ale_entries(priv
, slave
, slave_port
);
1140 cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1141 1 << slave_port
, 0, 0, ALE_MCAST_FWD_2
);
1143 if (slave
->data
->phy_node
) {
1144 slave
->phy
= of_phy_connect(priv
->ndev
, slave
->data
->phy_node
,
1145 &cpsw_adjust_link
, 0, slave
->data
->phy_if
);
1147 dev_err(priv
->dev
, "phy \"%s\" not found on slave %d\n",
1148 slave
->data
->phy_node
->full_name
,
1153 slave
->phy
= phy_connect(priv
->ndev
, slave
->data
->phy_id
,
1154 &cpsw_adjust_link
, slave
->data
->phy_if
);
1155 if (IS_ERR(slave
->phy
)) {
1157 "phy \"%s\" not found on slave %d, err %ld\n",
1158 slave
->data
->phy_id
, slave
->slave_num
,
1159 PTR_ERR(slave
->phy
));
1165 phy_attached_info(slave
->phy
);
1167 phy_start(slave
->phy
);
1169 /* Configure GMII_SEL register */
1170 cpsw_phy_sel(&priv
->pdev
->dev
, slave
->phy
->interface
, slave
->slave_num
);
1173 static inline void cpsw_add_default_vlan(struct cpsw_priv
*priv
)
1175 const int vlan
= priv
->data
.default_vlan
;
1178 int unreg_mcast_mask
;
1180 reg
= (priv
->version
== CPSW_VERSION_1
) ? CPSW1_PORT_VLAN
:
1183 writel(vlan
, &priv
->host_port_regs
->port_vlan
);
1185 for (i
= 0; i
< priv
->data
.slaves
; i
++)
1186 slave_write(priv
->slaves
+ i
, vlan
, reg
);
1188 if (priv
->ndev
->flags
& IFF_ALLMULTI
)
1189 unreg_mcast_mask
= ALE_ALL_PORTS
;
1191 unreg_mcast_mask
= ALE_PORT_1
| ALE_PORT_2
;
1193 cpsw_ale_add_vlan(priv
->ale
, vlan
, ALE_ALL_PORTS
,
1194 ALE_ALL_PORTS
, ALE_ALL_PORTS
,
1198 static void cpsw_init_host_port(struct cpsw_priv
*priv
)
1203 /* soft reset the controller and initialize ale */
1204 soft_reset("cpsw", &priv
->regs
->soft_reset
);
1205 cpsw_ale_start(priv
->ale
);
1207 /* switch to vlan unaware mode */
1208 cpsw_ale_control_set(priv
->ale
, HOST_PORT_NUM
, ALE_VLAN_AWARE
,
1209 CPSW_ALE_VLAN_AWARE
);
1210 control_reg
= readl(&priv
->regs
->control
);
1211 control_reg
|= CPSW_VLAN_AWARE
;
1212 writel(control_reg
, &priv
->regs
->control
);
1213 fifo_mode
= (priv
->data
.dual_emac
) ? CPSW_FIFO_DUAL_MAC_MODE
:
1214 CPSW_FIFO_NORMAL_MODE
;
1215 writel(fifo_mode
, &priv
->host_port_regs
->tx_in_ctl
);
1217 /* setup host port priority mapping */
1218 __raw_writel(CPDMA_TX_PRIORITY_MAP
,
1219 &priv
->host_port_regs
->cpdma_tx_pri_map
);
1220 __raw_writel(0, &priv
->host_port_regs
->cpdma_rx_chan_map
);
1222 cpsw_ale_control_set(priv
->ale
, HOST_PORT_NUM
,
1223 ALE_PORT_STATE
, ALE_PORT_STATE_FORWARD
);
1225 if (!priv
->data
.dual_emac
) {
1226 cpsw_ale_add_ucast(priv
->ale
, priv
->mac_addr
, HOST_PORT_NUM
,
1228 cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1229 ALE_PORT_HOST
, 0, 0, ALE_MCAST_FWD_2
);
1233 static void cpsw_slave_stop(struct cpsw_slave
*slave
, struct cpsw_priv
*priv
)
1237 slave_port
= cpsw_get_slave_port(priv
, slave
->slave_num
);
1241 phy_stop(slave
->phy
);
1242 phy_disconnect(slave
->phy
);
1244 cpsw_ale_control_set(priv
->ale
, slave_port
,
1245 ALE_PORT_STATE
, ALE_PORT_STATE_DISABLE
);
1246 soft_reset_slave(slave
);
1249 static int cpsw_ndo_open(struct net_device
*ndev
)
1251 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1255 ret
= pm_runtime_get_sync(&priv
->pdev
->dev
);
1257 pm_runtime_put_noidle(&priv
->pdev
->dev
);
1261 if (!cpsw_common_res_usage_state(priv
))
1262 cpsw_intr_disable(priv
);
1263 netif_carrier_off(ndev
);
1265 reg
= priv
->version
;
1267 dev_info(priv
->dev
, "initializing cpsw version %d.%d (%d)\n",
1268 CPSW_MAJOR_VERSION(reg
), CPSW_MINOR_VERSION(reg
),
1269 CPSW_RTL_VERSION(reg
));
1271 /* initialize host and slave ports */
1272 if (!cpsw_common_res_usage_state(priv
))
1273 cpsw_init_host_port(priv
);
1274 for_each_slave(priv
, cpsw_slave_open
, priv
);
1276 /* Add default VLAN */
1277 if (!priv
->data
.dual_emac
)
1278 cpsw_add_default_vlan(priv
);
1280 cpsw_ale_add_vlan(priv
->ale
, priv
->data
.default_vlan
,
1281 ALE_ALL_PORTS
, ALE_ALL_PORTS
, 0, 0);
1283 if (!cpsw_common_res_usage_state(priv
)) {
1284 struct cpsw_priv
*priv_sl0
= cpsw_get_slave_priv(priv
, 0);
1287 /* setup tx dma to fixed prio and zero offset */
1288 cpdma_control_set(priv
->dma
, CPDMA_TX_PRIO_FIXED
, 1);
1289 cpdma_control_set(priv
->dma
, CPDMA_RX_BUFFER_OFFSET
, 0);
1291 /* disable priority elevation */
1292 __raw_writel(0, &priv
->regs
->ptype
);
1294 /* enable statistics collection only on all ports */
1295 __raw_writel(0x7, &priv
->regs
->stat_port_en
);
1297 /* Enable internal fifo flow control */
1298 writel(0x7, &priv
->regs
->flow_control
);
1300 napi_enable(&priv_sl0
->napi_rx
);
1301 napi_enable(&priv_sl0
->napi_tx
);
1303 if (priv_sl0
->tx_irq_disabled
) {
1304 priv_sl0
->tx_irq_disabled
= false;
1305 enable_irq(priv
->irqs_table
[1]);
1308 if (priv_sl0
->rx_irq_disabled
) {
1309 priv_sl0
->rx_irq_disabled
= false;
1310 enable_irq(priv
->irqs_table
[0]);
1313 buf_num
= cpdma_chan_get_rx_buf_num(priv
->dma
);
1314 for (i
= 0; i
< buf_num
; i
++) {
1315 struct sk_buff
*skb
;
1318 skb
= __netdev_alloc_skb_ip_align(priv
->ndev
,
1319 priv
->rx_packet_max
, GFP_KERNEL
);
1322 ret
= cpdma_chan_submit(priv
->rxch
, skb
, skb
->data
,
1323 skb_tailroom(skb
), 0);
1329 /* continue even if we didn't manage to submit all
1332 cpsw_info(priv
, ifup
, "submitted %d rx descriptors\n", i
);
1334 if (cpts_register(&priv
->pdev
->dev
, priv
->cpts
,
1335 priv
->data
.cpts_clock_mult
,
1336 priv
->data
.cpts_clock_shift
))
1337 dev_err(priv
->dev
, "error registering cpts device\n");
1341 /* Enable Interrupt pacing if configured */
1342 if (priv
->coal_intvl
!= 0) {
1343 struct ethtool_coalesce coal
;
1345 coal
.rx_coalesce_usecs
= priv
->coal_intvl
;
1346 cpsw_set_coalesce(ndev
, &coal
);
1349 cpdma_ctlr_start(priv
->dma
);
1350 cpsw_intr_enable(priv
);
1352 if (priv
->data
.dual_emac
)
1353 priv
->slaves
[priv
->emac_port
].open_stat
= true;
1357 cpdma_ctlr_stop(priv
->dma
);
1358 for_each_slave(priv
, cpsw_slave_stop
, priv
);
1359 pm_runtime_put_sync(&priv
->pdev
->dev
);
1360 netif_carrier_off(priv
->ndev
);
1364 static int cpsw_ndo_stop(struct net_device
*ndev
)
1366 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1368 cpsw_info(priv
, ifdown
, "shutting down cpsw device\n");
1369 netif_stop_queue(priv
->ndev
);
1370 netif_carrier_off(priv
->ndev
);
1372 if (cpsw_common_res_usage_state(priv
) <= 1) {
1373 struct cpsw_priv
*priv_sl0
= cpsw_get_slave_priv(priv
, 0);
1375 napi_disable(&priv_sl0
->napi_rx
);
1376 napi_disable(&priv_sl0
->napi_tx
);
1377 cpts_unregister(priv
->cpts
);
1378 cpsw_intr_disable(priv
);
1379 cpdma_ctlr_stop(priv
->dma
);
1380 cpsw_ale_stop(priv
->ale
);
1382 for_each_slave(priv
, cpsw_slave_stop
, priv
);
1383 pm_runtime_put_sync(&priv
->pdev
->dev
);
1384 if (priv
->data
.dual_emac
)
1385 priv
->slaves
[priv
->emac_port
].open_stat
= false;
1389 static netdev_tx_t
cpsw_ndo_start_xmit(struct sk_buff
*skb
,
1390 struct net_device
*ndev
)
1392 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1395 netif_trans_update(ndev
);
1397 if (skb_padto(skb
, CPSW_MIN_PACKET_SIZE
)) {
1398 cpsw_err(priv
, tx_err
, "packet pad failed\n");
1399 ndev
->stats
.tx_dropped
++;
1400 return NETDEV_TX_OK
;
1403 if (skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
&&
1404 priv
->cpts
->tx_enable
)
1405 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
1407 skb_tx_timestamp(skb
);
1409 ret
= cpsw_tx_packet_submit(ndev
, priv
, skb
);
1410 if (unlikely(ret
!= 0)) {
1411 cpsw_err(priv
, tx_err
, "desc submit failed\n");
1415 /* If there is no more tx desc left free then we need to
1416 * tell the kernel to stop sending us tx frames.
1418 if (unlikely(!cpdma_check_free_tx_desc(priv
->txch
)))
1419 netif_stop_queue(ndev
);
1421 return NETDEV_TX_OK
;
1423 ndev
->stats
.tx_dropped
++;
1424 netif_stop_queue(ndev
);
1425 return NETDEV_TX_BUSY
;
1428 #ifdef CONFIG_TI_CPTS
1430 static void cpsw_hwtstamp_v1(struct cpsw_priv
*priv
)
1432 struct cpsw_slave
*slave
= &priv
->slaves
[priv
->data
.active_slave
];
1435 if (!priv
->cpts
->tx_enable
&& !priv
->cpts
->rx_enable
) {
1436 slave_write(slave
, 0, CPSW1_TS_CTL
);
1440 seq_id
= (30 << CPSW_V1_SEQ_ID_OFS_SHIFT
) | ETH_P_1588
;
1441 ts_en
= EVENT_MSG_BITS
<< CPSW_V1_MSG_TYPE_OFS
;
1443 if (priv
->cpts
->tx_enable
)
1444 ts_en
|= CPSW_V1_TS_TX_EN
;
1446 if (priv
->cpts
->rx_enable
)
1447 ts_en
|= CPSW_V1_TS_RX_EN
;
1449 slave_write(slave
, ts_en
, CPSW1_TS_CTL
);
1450 slave_write(slave
, seq_id
, CPSW1_TS_SEQ_LTYPE
);
1453 static void cpsw_hwtstamp_v2(struct cpsw_priv
*priv
)
1455 struct cpsw_slave
*slave
;
1458 if (priv
->data
.dual_emac
)
1459 slave
= &priv
->slaves
[priv
->emac_port
];
1461 slave
= &priv
->slaves
[priv
->data
.active_slave
];
1463 ctrl
= slave_read(slave
, CPSW2_CONTROL
);
1464 switch (priv
->version
) {
1465 case CPSW_VERSION_2
:
1466 ctrl
&= ~CTRL_V2_ALL_TS_MASK
;
1468 if (priv
->cpts
->tx_enable
)
1469 ctrl
|= CTRL_V2_TX_TS_BITS
;
1471 if (priv
->cpts
->rx_enable
)
1472 ctrl
|= CTRL_V2_RX_TS_BITS
;
1474 case CPSW_VERSION_3
:
1476 ctrl
&= ~CTRL_V3_ALL_TS_MASK
;
1478 if (priv
->cpts
->tx_enable
)
1479 ctrl
|= CTRL_V3_TX_TS_BITS
;
1481 if (priv
->cpts
->rx_enable
)
1482 ctrl
|= CTRL_V3_RX_TS_BITS
;
1486 mtype
= (30 << TS_SEQ_ID_OFFSET_SHIFT
) | EVENT_MSG_BITS
;
1488 slave_write(slave
, mtype
, CPSW2_TS_SEQ_MTYPE
);
1489 slave_write(slave
, ctrl
, CPSW2_CONTROL
);
1490 __raw_writel(ETH_P_1588
, &priv
->regs
->ts_ltype
);
1493 static int cpsw_hwtstamp_set(struct net_device
*dev
, struct ifreq
*ifr
)
1495 struct cpsw_priv
*priv
= netdev_priv(dev
);
1496 struct cpts
*cpts
= priv
->cpts
;
1497 struct hwtstamp_config cfg
;
1499 if (priv
->version
!= CPSW_VERSION_1
&&
1500 priv
->version
!= CPSW_VERSION_2
&&
1501 priv
->version
!= CPSW_VERSION_3
)
1504 if (copy_from_user(&cfg
, ifr
->ifr_data
, sizeof(cfg
)))
1507 /* reserved for future extensions */
1511 if (cfg
.tx_type
!= HWTSTAMP_TX_OFF
&& cfg
.tx_type
!= HWTSTAMP_TX_ON
)
1514 switch (cfg
.rx_filter
) {
1515 case HWTSTAMP_FILTER_NONE
:
1516 cpts
->rx_enable
= 0;
1518 case HWTSTAMP_FILTER_ALL
:
1519 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
1520 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
1521 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
1523 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
1524 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
1525 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
1526 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
1527 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
1528 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
1529 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
1530 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
1531 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
1532 cpts
->rx_enable
= 1;
1533 cfg
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
1539 cpts
->tx_enable
= cfg
.tx_type
== HWTSTAMP_TX_ON
;
1541 switch (priv
->version
) {
1542 case CPSW_VERSION_1
:
1543 cpsw_hwtstamp_v1(priv
);
1545 case CPSW_VERSION_2
:
1546 case CPSW_VERSION_3
:
1547 cpsw_hwtstamp_v2(priv
);
1553 return copy_to_user(ifr
->ifr_data
, &cfg
, sizeof(cfg
)) ? -EFAULT
: 0;
1556 static int cpsw_hwtstamp_get(struct net_device
*dev
, struct ifreq
*ifr
)
1558 struct cpsw_priv
*priv
= netdev_priv(dev
);
1559 struct cpts
*cpts
= priv
->cpts
;
1560 struct hwtstamp_config cfg
;
1562 if (priv
->version
!= CPSW_VERSION_1
&&
1563 priv
->version
!= CPSW_VERSION_2
&&
1564 priv
->version
!= CPSW_VERSION_3
)
1568 cfg
.tx_type
= cpts
->tx_enable
? HWTSTAMP_TX_ON
: HWTSTAMP_TX_OFF
;
1569 cfg
.rx_filter
= (cpts
->rx_enable
?
1570 HWTSTAMP_FILTER_PTP_V2_EVENT
: HWTSTAMP_FILTER_NONE
);
1572 return copy_to_user(ifr
->ifr_data
, &cfg
, sizeof(cfg
)) ? -EFAULT
: 0;
1575 #endif /*CONFIG_TI_CPTS*/
1577 static int cpsw_ndo_ioctl(struct net_device
*dev
, struct ifreq
*req
, int cmd
)
1579 struct cpsw_priv
*priv
= netdev_priv(dev
);
1580 int slave_no
= cpsw_slave_index(priv
);
1582 if (!netif_running(dev
))
1586 #ifdef CONFIG_TI_CPTS
1588 return cpsw_hwtstamp_set(dev
, req
);
1590 return cpsw_hwtstamp_get(dev
, req
);
1594 if (!priv
->slaves
[slave_no
].phy
)
1596 return phy_mii_ioctl(priv
->slaves
[slave_no
].phy
, req
, cmd
);
1599 static void cpsw_ndo_tx_timeout(struct net_device
*ndev
)
1601 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1603 cpsw_err(priv
, tx_err
, "transmit timeout, restarting dma\n");
1604 ndev
->stats
.tx_errors
++;
1605 cpsw_intr_disable(priv
);
1606 cpdma_chan_stop(priv
->txch
);
1607 cpdma_chan_start(priv
->txch
);
1608 cpsw_intr_enable(priv
);
1611 static int cpsw_ndo_set_mac_address(struct net_device
*ndev
, void *p
)
1613 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1614 struct sockaddr
*addr
= (struct sockaddr
*)p
;
1618 if (!is_valid_ether_addr(addr
->sa_data
))
1619 return -EADDRNOTAVAIL
;
1621 if (priv
->data
.dual_emac
) {
1622 vid
= priv
->slaves
[priv
->emac_port
].port_vlan
;
1626 cpsw_ale_del_ucast(priv
->ale
, priv
->mac_addr
, HOST_PORT_NUM
,
1628 cpsw_ale_add_ucast(priv
->ale
, addr
->sa_data
, HOST_PORT_NUM
,
1631 memcpy(priv
->mac_addr
, addr
->sa_data
, ETH_ALEN
);
1632 memcpy(ndev
->dev_addr
, priv
->mac_addr
, ETH_ALEN
);
1633 for_each_slave(priv
, cpsw_set_slave_mac
, priv
);
1638 #ifdef CONFIG_NET_POLL_CONTROLLER
1639 static void cpsw_ndo_poll_controller(struct net_device
*ndev
)
1641 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1643 cpsw_intr_disable(priv
);
1644 cpsw_rx_interrupt(priv
->irqs_table
[0], priv
);
1645 cpsw_tx_interrupt(priv
->irqs_table
[1], priv
);
1646 cpsw_intr_enable(priv
);
1650 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv
*priv
,
1654 int unreg_mcast_mask
= 0;
1657 if (priv
->data
.dual_emac
) {
1658 port_mask
= (1 << (priv
->emac_port
+ 1)) | ALE_PORT_HOST
;
1660 if (priv
->ndev
->flags
& IFF_ALLMULTI
)
1661 unreg_mcast_mask
= port_mask
;
1663 port_mask
= ALE_ALL_PORTS
;
1665 if (priv
->ndev
->flags
& IFF_ALLMULTI
)
1666 unreg_mcast_mask
= ALE_ALL_PORTS
;
1668 unreg_mcast_mask
= ALE_PORT_1
| ALE_PORT_2
;
1671 ret
= cpsw_ale_add_vlan(priv
->ale
, vid
, port_mask
, 0, port_mask
,
1676 ret
= cpsw_ale_add_ucast(priv
->ale
, priv
->mac_addr
,
1677 HOST_PORT_NUM
, ALE_VLAN
, vid
);
1681 ret
= cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1682 port_mask
, ALE_VLAN
, vid
, 0);
1684 goto clean_vlan_ucast
;
1688 cpsw_ale_del_ucast(priv
->ale
, priv
->mac_addr
,
1689 HOST_PORT_NUM
, ALE_VLAN
, vid
);
1691 cpsw_ale_del_vlan(priv
->ale
, vid
, 0);
1695 static int cpsw_ndo_vlan_rx_add_vid(struct net_device
*ndev
,
1696 __be16 proto
, u16 vid
)
1698 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1700 if (vid
== priv
->data
.default_vlan
)
1703 if (priv
->data
.dual_emac
) {
1704 /* In dual EMAC, reserved VLAN id should not be used for
1705 * creating VLAN interfaces as this can break the dual
1706 * EMAC port separation
1710 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
1711 if (vid
== priv
->slaves
[i
].port_vlan
)
1716 dev_info(priv
->dev
, "Adding vlanid %d to vlan filter\n", vid
);
1717 return cpsw_add_vlan_ale_entry(priv
, vid
);
1720 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device
*ndev
,
1721 __be16 proto
, u16 vid
)
1723 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1726 if (vid
== priv
->data
.default_vlan
)
1729 if (priv
->data
.dual_emac
) {
1732 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
1733 if (vid
== priv
->slaves
[i
].port_vlan
)
1738 dev_info(priv
->dev
, "removing vlanid %d from vlan filter\n", vid
);
1739 ret
= cpsw_ale_del_vlan(priv
->ale
, vid
, 0);
1743 ret
= cpsw_ale_del_ucast(priv
->ale
, priv
->mac_addr
,
1744 HOST_PORT_NUM
, ALE_VLAN
, vid
);
1748 return cpsw_ale_del_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1752 static const struct net_device_ops cpsw_netdev_ops
= {
1753 .ndo_open
= cpsw_ndo_open
,
1754 .ndo_stop
= cpsw_ndo_stop
,
1755 .ndo_start_xmit
= cpsw_ndo_start_xmit
,
1756 .ndo_set_mac_address
= cpsw_ndo_set_mac_address
,
1757 .ndo_do_ioctl
= cpsw_ndo_ioctl
,
1758 .ndo_validate_addr
= eth_validate_addr
,
1759 .ndo_change_mtu
= eth_change_mtu
,
1760 .ndo_tx_timeout
= cpsw_ndo_tx_timeout
,
1761 .ndo_set_rx_mode
= cpsw_ndo_set_rx_mode
,
1762 #ifdef CONFIG_NET_POLL_CONTROLLER
1763 .ndo_poll_controller
= cpsw_ndo_poll_controller
,
1765 .ndo_vlan_rx_add_vid
= cpsw_ndo_vlan_rx_add_vid
,
1766 .ndo_vlan_rx_kill_vid
= cpsw_ndo_vlan_rx_kill_vid
,
1769 static int cpsw_get_regs_len(struct net_device
*ndev
)
1771 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1773 return priv
->data
.ale_entries
* ALE_ENTRY_WORDS
* sizeof(u32
);
1776 static void cpsw_get_regs(struct net_device
*ndev
,
1777 struct ethtool_regs
*regs
, void *p
)
1779 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1782 /* update CPSW IP version */
1783 regs
->version
= priv
->version
;
1785 cpsw_ale_dump(priv
->ale
, reg
);
1788 static void cpsw_get_drvinfo(struct net_device
*ndev
,
1789 struct ethtool_drvinfo
*info
)
1791 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1793 strlcpy(info
->driver
, "cpsw", sizeof(info
->driver
));
1794 strlcpy(info
->version
, "1.0", sizeof(info
->version
));
1795 strlcpy(info
->bus_info
, priv
->pdev
->name
, sizeof(info
->bus_info
));
1798 static u32
cpsw_get_msglevel(struct net_device
*ndev
)
1800 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1801 return priv
->msg_enable
;
1804 static void cpsw_set_msglevel(struct net_device
*ndev
, u32 value
)
1806 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1807 priv
->msg_enable
= value
;
1810 static int cpsw_get_ts_info(struct net_device
*ndev
,
1811 struct ethtool_ts_info
*info
)
1813 #ifdef CONFIG_TI_CPTS
1814 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1816 info
->so_timestamping
=
1817 SOF_TIMESTAMPING_TX_HARDWARE
|
1818 SOF_TIMESTAMPING_TX_SOFTWARE
|
1819 SOF_TIMESTAMPING_RX_HARDWARE
|
1820 SOF_TIMESTAMPING_RX_SOFTWARE
|
1821 SOF_TIMESTAMPING_SOFTWARE
|
1822 SOF_TIMESTAMPING_RAW_HARDWARE
;
1823 info
->phc_index
= priv
->cpts
->phc_index
;
1825 (1 << HWTSTAMP_TX_OFF
) |
1826 (1 << HWTSTAMP_TX_ON
);
1828 (1 << HWTSTAMP_FILTER_NONE
) |
1829 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT
);
1831 info
->so_timestamping
=
1832 SOF_TIMESTAMPING_TX_SOFTWARE
|
1833 SOF_TIMESTAMPING_RX_SOFTWARE
|
1834 SOF_TIMESTAMPING_SOFTWARE
;
1835 info
->phc_index
= -1;
1837 info
->rx_filters
= 0;
1842 static int cpsw_get_settings(struct net_device
*ndev
,
1843 struct ethtool_cmd
*ecmd
)
1845 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1846 int slave_no
= cpsw_slave_index(priv
);
1848 if (priv
->slaves
[slave_no
].phy
)
1849 return phy_ethtool_gset(priv
->slaves
[slave_no
].phy
, ecmd
);
1854 static int cpsw_set_settings(struct net_device
*ndev
, struct ethtool_cmd
*ecmd
)
1856 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1857 int slave_no
= cpsw_slave_index(priv
);
1859 if (priv
->slaves
[slave_no
].phy
)
1860 return phy_ethtool_sset(priv
->slaves
[slave_no
].phy
, ecmd
);
1865 static void cpsw_get_wol(struct net_device
*ndev
, struct ethtool_wolinfo
*wol
)
1867 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1868 int slave_no
= cpsw_slave_index(priv
);
1873 if (priv
->slaves
[slave_no
].phy
)
1874 phy_ethtool_get_wol(priv
->slaves
[slave_no
].phy
, wol
);
1877 static int cpsw_set_wol(struct net_device
*ndev
, struct ethtool_wolinfo
*wol
)
1879 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1880 int slave_no
= cpsw_slave_index(priv
);
1882 if (priv
->slaves
[slave_no
].phy
)
1883 return phy_ethtool_set_wol(priv
->slaves
[slave_no
].phy
, wol
);
1888 static void cpsw_get_pauseparam(struct net_device
*ndev
,
1889 struct ethtool_pauseparam
*pause
)
1891 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1893 pause
->autoneg
= AUTONEG_DISABLE
;
1894 pause
->rx_pause
= priv
->rx_pause
? true : false;
1895 pause
->tx_pause
= priv
->tx_pause
? true : false;
1898 static int cpsw_set_pauseparam(struct net_device
*ndev
,
1899 struct ethtool_pauseparam
*pause
)
1901 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1904 priv
->rx_pause
= pause
->rx_pause
? true : false;
1905 priv
->tx_pause
= pause
->tx_pause
? true : false;
1907 for_each_slave(priv
, _cpsw_adjust_link
, priv
, &link
);
1912 static const struct ethtool_ops cpsw_ethtool_ops
= {
1913 .get_drvinfo
= cpsw_get_drvinfo
,
1914 .get_msglevel
= cpsw_get_msglevel
,
1915 .set_msglevel
= cpsw_set_msglevel
,
1916 .get_link
= ethtool_op_get_link
,
1917 .get_ts_info
= cpsw_get_ts_info
,
1918 .get_settings
= cpsw_get_settings
,
1919 .set_settings
= cpsw_set_settings
,
1920 .get_coalesce
= cpsw_get_coalesce
,
1921 .set_coalesce
= cpsw_set_coalesce
,
1922 .get_sset_count
= cpsw_get_sset_count
,
1923 .get_strings
= cpsw_get_strings
,
1924 .get_ethtool_stats
= cpsw_get_ethtool_stats
,
1925 .get_pauseparam
= cpsw_get_pauseparam
,
1926 .set_pauseparam
= cpsw_set_pauseparam
,
1927 .get_wol
= cpsw_get_wol
,
1928 .set_wol
= cpsw_set_wol
,
1929 .get_regs_len
= cpsw_get_regs_len
,
1930 .get_regs
= cpsw_get_regs
,
1933 static void cpsw_slave_init(struct cpsw_slave
*slave
, struct cpsw_priv
*priv
,
1934 u32 slave_reg_ofs
, u32 sliver_reg_ofs
)
1936 void __iomem
*regs
= priv
->regs
;
1937 int slave_num
= slave
->slave_num
;
1938 struct cpsw_slave_data
*data
= priv
->data
.slave_data
+ slave_num
;
1941 slave
->regs
= regs
+ slave_reg_ofs
;
1942 slave
->sliver
= regs
+ sliver_reg_ofs
;
1943 slave
->port_vlan
= data
->dual_emac_res_vlan
;
1946 static int cpsw_probe_dt(struct cpsw_platform_data
*data
,
1947 struct platform_device
*pdev
)
1949 struct device_node
*node
= pdev
->dev
.of_node
;
1950 struct device_node
*slave_node
;
1957 if (of_property_read_u32(node
, "slaves", &prop
)) {
1958 dev_err(&pdev
->dev
, "Missing slaves property in the DT.\n");
1961 data
->slaves
= prop
;
1963 if (of_property_read_u32(node
, "active_slave", &prop
)) {
1964 dev_err(&pdev
->dev
, "Missing active_slave property in the DT.\n");
1967 data
->active_slave
= prop
;
1969 if (of_property_read_u32(node
, "cpts_clock_mult", &prop
)) {
1970 dev_err(&pdev
->dev
, "Missing cpts_clock_mult property in the DT.\n");
1973 data
->cpts_clock_mult
= prop
;
1975 if (of_property_read_u32(node
, "cpts_clock_shift", &prop
)) {
1976 dev_err(&pdev
->dev
, "Missing cpts_clock_shift property in the DT.\n");
1979 data
->cpts_clock_shift
= prop
;
1981 data
->slave_data
= devm_kzalloc(&pdev
->dev
, data
->slaves
1982 * sizeof(struct cpsw_slave_data
),
1984 if (!data
->slave_data
)
1987 if (of_property_read_u32(node
, "cpdma_channels", &prop
)) {
1988 dev_err(&pdev
->dev
, "Missing cpdma_channels property in the DT.\n");
1991 data
->channels
= prop
;
1993 if (of_property_read_u32(node
, "ale_entries", &prop
)) {
1994 dev_err(&pdev
->dev
, "Missing ale_entries property in the DT.\n");
1997 data
->ale_entries
= prop
;
1999 if (of_property_read_u32(node
, "bd_ram_size", &prop
)) {
2000 dev_err(&pdev
->dev
, "Missing bd_ram_size property in the DT.\n");
2003 data
->bd_ram_size
= prop
;
2005 if (of_property_read_u32(node
, "mac_control", &prop
)) {
2006 dev_err(&pdev
->dev
, "Missing mac_control property in the DT.\n");
2009 data
->mac_control
= prop
;
2011 if (of_property_read_bool(node
, "dual_emac"))
2012 data
->dual_emac
= 1;
2015 * Populate all the child nodes here...
2017 ret
= of_platform_populate(node
, NULL
, NULL
, &pdev
->dev
);
2018 /* We do not want to force this, as in some cases may not have child */
2020 dev_warn(&pdev
->dev
, "Doesn't have any child node\n");
2022 for_each_available_child_of_node(node
, slave_node
) {
2023 struct cpsw_slave_data
*slave_data
= data
->slave_data
+ i
;
2024 const void *mac_addr
= NULL
;
2028 /* This is no slave child node, continue */
2029 if (strcmp(slave_node
->name
, "slave"))
2032 slave_data
->phy_node
= of_parse_phandle(slave_node
,
2034 parp
= of_get_property(slave_node
, "phy_id", &lenp
);
2035 if (slave_data
->phy_node
) {
2037 "slave[%d] using phy-handle=\"%s\"\n",
2038 i
, slave_data
->phy_node
->full_name
);
2039 } else if (of_phy_is_fixed_link(slave_node
)) {
2040 /* In the case of a fixed PHY, the DT node associated
2041 * to the PHY is the Ethernet MAC DT node.
2043 ret
= of_phy_register_fixed_link(slave_node
);
2046 slave_data
->phy_node
= of_node_get(slave_node
);
2049 struct device_node
*mdio_node
;
2050 struct platform_device
*mdio
;
2052 if (lenp
!= (sizeof(__be32
) * 2)) {
2053 dev_err(&pdev
->dev
, "Invalid slave[%d] phy_id property\n", i
);
2056 mdio_node
= of_find_node_by_phandle(be32_to_cpup(parp
));
2057 phyid
= be32_to_cpup(parp
+1);
2058 mdio
= of_find_device_by_node(mdio_node
);
2059 of_node_put(mdio_node
);
2061 dev_err(&pdev
->dev
, "Missing mdio platform device\n");
2064 snprintf(slave_data
->phy_id
, sizeof(slave_data
->phy_id
),
2065 PHY_ID_FMT
, mdio
->name
, phyid
);
2068 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2072 slave_data
->phy_if
= of_get_phy_mode(slave_node
);
2073 if (slave_data
->phy_if
< 0) {
2074 dev_err(&pdev
->dev
, "Missing or malformed slave[%d] phy-mode property\n",
2076 return slave_data
->phy_if
;
2080 mac_addr
= of_get_mac_address(slave_node
);
2082 memcpy(slave_data
->mac_addr
, mac_addr
, ETH_ALEN
);
2084 ret
= ti_cm_get_macid(&pdev
->dev
, i
,
2085 slave_data
->mac_addr
);
2089 if (data
->dual_emac
) {
2090 if (of_property_read_u32(slave_node
, "dual_emac_res_vlan",
2092 dev_err(&pdev
->dev
, "Missing dual_emac_res_vlan in DT.\n");
2093 slave_data
->dual_emac_res_vlan
= i
+1;
2094 dev_err(&pdev
->dev
, "Using %d as Reserved VLAN for %d slave\n",
2095 slave_data
->dual_emac_res_vlan
, i
);
2097 slave_data
->dual_emac_res_vlan
= prop
;
2102 if (i
== data
->slaves
)
2109 static int cpsw_probe_dual_emac(struct platform_device
*pdev
,
2110 struct cpsw_priv
*priv
)
2112 struct cpsw_platform_data
*data
= &priv
->data
;
2113 struct net_device
*ndev
;
2114 struct cpsw_priv
*priv_sl2
;
2117 ndev
= alloc_etherdev(sizeof(struct cpsw_priv
));
2119 dev_err(&pdev
->dev
, "cpsw: error allocating net_device\n");
2123 priv_sl2
= netdev_priv(ndev
);
2124 priv_sl2
->data
= *data
;
2125 priv_sl2
->pdev
= pdev
;
2126 priv_sl2
->ndev
= ndev
;
2127 priv_sl2
->dev
= &ndev
->dev
;
2128 priv_sl2
->msg_enable
= netif_msg_init(debug_level
, CPSW_DEBUG
);
2129 priv_sl2
->rx_packet_max
= max(rx_packet_max
, 128);
2131 if (is_valid_ether_addr(data
->slave_data
[1].mac_addr
)) {
2132 memcpy(priv_sl2
->mac_addr
, data
->slave_data
[1].mac_addr
,
2134 dev_info(&pdev
->dev
, "cpsw: Detected MACID = %pM\n", priv_sl2
->mac_addr
);
2136 random_ether_addr(priv_sl2
->mac_addr
);
2137 dev_info(&pdev
->dev
, "cpsw: Random MACID = %pM\n", priv_sl2
->mac_addr
);
2139 memcpy(ndev
->dev_addr
, priv_sl2
->mac_addr
, ETH_ALEN
);
2141 priv_sl2
->slaves
= priv
->slaves
;
2142 priv_sl2
->clk
= priv
->clk
;
2144 priv_sl2
->coal_intvl
= 0;
2145 priv_sl2
->bus_freq_mhz
= priv
->bus_freq_mhz
;
2147 priv_sl2
->regs
= priv
->regs
;
2148 priv_sl2
->host_port_regs
= priv
->host_port_regs
;
2149 priv_sl2
->wr_regs
= priv
->wr_regs
;
2150 priv_sl2
->hw_stats
= priv
->hw_stats
;
2151 priv_sl2
->dma
= priv
->dma
;
2152 priv_sl2
->txch
= priv
->txch
;
2153 priv_sl2
->rxch
= priv
->rxch
;
2154 priv_sl2
->ale
= priv
->ale
;
2155 priv_sl2
->emac_port
= 1;
2156 priv
->slaves
[1].ndev
= ndev
;
2157 priv_sl2
->cpts
= priv
->cpts
;
2158 priv_sl2
->version
= priv
->version
;
2160 for (i
= 0; i
< priv
->num_irqs
; i
++) {
2161 priv_sl2
->irqs_table
[i
] = priv
->irqs_table
[i
];
2162 priv_sl2
->num_irqs
= priv
->num_irqs
;
2164 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
2166 ndev
->netdev_ops
= &cpsw_netdev_ops
;
2167 ndev
->ethtool_ops
= &cpsw_ethtool_ops
;
2169 /* register the network device */
2170 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
2171 ret
= register_netdev(ndev
);
2173 dev_err(&pdev
->dev
, "cpsw: error registering net device\n");
2181 #define CPSW_QUIRK_IRQ BIT(0)
2183 static struct platform_device_id cpsw_devtype
[] = {
2185 /* keep it for existing comaptibles */
2187 .driver_data
= CPSW_QUIRK_IRQ
,
2189 .name
= "am335x-cpsw",
2190 .driver_data
= CPSW_QUIRK_IRQ
,
2192 .name
= "am4372-cpsw",
2195 .name
= "dra7-cpsw",
2201 MODULE_DEVICE_TABLE(platform
, cpsw_devtype
);
2210 static const struct of_device_id cpsw_of_mtable
[] = {
2211 { .compatible
= "ti,cpsw", .data
= &cpsw_devtype
[CPSW
], },
2212 { .compatible
= "ti,am335x-cpsw", .data
= &cpsw_devtype
[AM335X_CPSW
], },
2213 { .compatible
= "ti,am4372-cpsw", .data
= &cpsw_devtype
[AM4372_CPSW
], },
2214 { .compatible
= "ti,dra7-cpsw", .data
= &cpsw_devtype
[DRA7_CPSW
], },
2217 MODULE_DEVICE_TABLE(of
, cpsw_of_mtable
);
2219 static int cpsw_probe(struct platform_device
*pdev
)
2221 struct cpsw_platform_data
*data
;
2222 struct net_device
*ndev
;
2223 struct cpsw_priv
*priv
;
2224 struct cpdma_params dma_params
;
2225 struct cpsw_ale_params ale_params
;
2226 void __iomem
*ss_regs
;
2227 struct resource
*res
, *ss_res
;
2228 const struct of_device_id
*of_id
;
2229 struct gpio_descs
*mode
;
2230 u32 slave_offset
, sliver_offset
, slave_size
;
2234 ndev
= alloc_etherdev(sizeof(struct cpsw_priv
));
2236 dev_err(&pdev
->dev
, "error allocating net_device\n");
2240 platform_set_drvdata(pdev
, ndev
);
2241 priv
= netdev_priv(ndev
);
2244 priv
->dev
= &ndev
->dev
;
2245 priv
->msg_enable
= netif_msg_init(debug_level
, CPSW_DEBUG
);
2246 priv
->rx_packet_max
= max(rx_packet_max
, 128);
2247 priv
->cpts
= devm_kzalloc(&pdev
->dev
, sizeof(struct cpts
), GFP_KERNEL
);
2249 dev_err(&pdev
->dev
, "error allocating cpts\n");
2251 goto clean_ndev_ret
;
2254 mode
= devm_gpiod_get_array_optional(&pdev
->dev
, "mode", GPIOD_OUT_LOW
);
2256 ret
= PTR_ERR(mode
);
2257 dev_err(&pdev
->dev
, "gpio request failed, ret %d\n", ret
);
2258 goto clean_ndev_ret
;
2262 * This may be required here for child devices.
2264 pm_runtime_enable(&pdev
->dev
);
2266 /* Select default pin state */
2267 pinctrl_pm_select_default_state(&pdev
->dev
);
2269 if (cpsw_probe_dt(&priv
->data
, pdev
)) {
2270 dev_err(&pdev
->dev
, "cpsw: platform data missing\n");
2272 goto clean_runtime_disable_ret
;
2276 if (is_valid_ether_addr(data
->slave_data
[0].mac_addr
)) {
2277 memcpy(priv
->mac_addr
, data
->slave_data
[0].mac_addr
, ETH_ALEN
);
2278 dev_info(&pdev
->dev
, "Detected MACID = %pM\n", priv
->mac_addr
);
2280 eth_random_addr(priv
->mac_addr
);
2281 dev_info(&pdev
->dev
, "Random MACID = %pM\n", priv
->mac_addr
);
2284 memcpy(ndev
->dev_addr
, priv
->mac_addr
, ETH_ALEN
);
2286 priv
->slaves
= devm_kzalloc(&pdev
->dev
,
2287 sizeof(struct cpsw_slave
) * data
->slaves
,
2289 if (!priv
->slaves
) {
2291 goto clean_runtime_disable_ret
;
2293 for (i
= 0; i
< data
->slaves
; i
++)
2294 priv
->slaves
[i
].slave_num
= i
;
2296 priv
->slaves
[0].ndev
= ndev
;
2297 priv
->emac_port
= 0;
2299 priv
->clk
= devm_clk_get(&pdev
->dev
, "fck");
2300 if (IS_ERR(priv
->clk
)) {
2301 dev_err(priv
->dev
, "fck is not found\n");
2303 goto clean_runtime_disable_ret
;
2305 priv
->coal_intvl
= 0;
2306 priv
->bus_freq_mhz
= clk_get_rate(priv
->clk
) / 1000000;
2308 ss_res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2309 ss_regs
= devm_ioremap_resource(&pdev
->dev
, ss_res
);
2310 if (IS_ERR(ss_regs
)) {
2311 ret
= PTR_ERR(ss_regs
);
2312 goto clean_runtime_disable_ret
;
2314 priv
->regs
= ss_regs
;
2316 /* Need to enable clocks with runtime PM api to access module
2319 ret
= pm_runtime_get_sync(&pdev
->dev
);
2321 pm_runtime_put_noidle(&pdev
->dev
);
2322 goto clean_runtime_disable_ret
;
2324 priv
->version
= readl(&priv
->regs
->id_ver
);
2325 pm_runtime_put_sync(&pdev
->dev
);
2327 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
2328 priv
->wr_regs
= devm_ioremap_resource(&pdev
->dev
, res
);
2329 if (IS_ERR(priv
->wr_regs
)) {
2330 ret
= PTR_ERR(priv
->wr_regs
);
2331 goto clean_runtime_disable_ret
;
2334 memset(&dma_params
, 0, sizeof(dma_params
));
2335 memset(&ale_params
, 0, sizeof(ale_params
));
2337 switch (priv
->version
) {
2338 case CPSW_VERSION_1
:
2339 priv
->host_port_regs
= ss_regs
+ CPSW1_HOST_PORT_OFFSET
;
2340 priv
->cpts
->reg
= ss_regs
+ CPSW1_CPTS_OFFSET
;
2341 priv
->hw_stats
= ss_regs
+ CPSW1_HW_STATS
;
2342 dma_params
.dmaregs
= ss_regs
+ CPSW1_CPDMA_OFFSET
;
2343 dma_params
.txhdp
= ss_regs
+ CPSW1_STATERAM_OFFSET
;
2344 ale_params
.ale_regs
= ss_regs
+ CPSW1_ALE_OFFSET
;
2345 slave_offset
= CPSW1_SLAVE_OFFSET
;
2346 slave_size
= CPSW1_SLAVE_SIZE
;
2347 sliver_offset
= CPSW1_SLIVER_OFFSET
;
2348 dma_params
.desc_mem_phys
= 0;
2350 case CPSW_VERSION_2
:
2351 case CPSW_VERSION_3
:
2352 case CPSW_VERSION_4
:
2353 priv
->host_port_regs
= ss_regs
+ CPSW2_HOST_PORT_OFFSET
;
2354 priv
->cpts
->reg
= ss_regs
+ CPSW2_CPTS_OFFSET
;
2355 priv
->hw_stats
= ss_regs
+ CPSW2_HW_STATS
;
2356 dma_params
.dmaregs
= ss_regs
+ CPSW2_CPDMA_OFFSET
;
2357 dma_params
.txhdp
= ss_regs
+ CPSW2_STATERAM_OFFSET
;
2358 ale_params
.ale_regs
= ss_regs
+ CPSW2_ALE_OFFSET
;
2359 slave_offset
= CPSW2_SLAVE_OFFSET
;
2360 slave_size
= CPSW2_SLAVE_SIZE
;
2361 sliver_offset
= CPSW2_SLIVER_OFFSET
;
2362 dma_params
.desc_mem_phys
=
2363 (u32 __force
) ss_res
->start
+ CPSW2_BD_OFFSET
;
2366 dev_err(priv
->dev
, "unknown version 0x%08x\n", priv
->version
);
2368 goto clean_runtime_disable_ret
;
2370 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
2371 struct cpsw_slave
*slave
= &priv
->slaves
[i
];
2372 cpsw_slave_init(slave
, priv
, slave_offset
, sliver_offset
);
2373 slave_offset
+= slave_size
;
2374 sliver_offset
+= SLIVER_SIZE
;
2377 dma_params
.dev
= &pdev
->dev
;
2378 dma_params
.rxthresh
= dma_params
.dmaregs
+ CPDMA_RXTHRESH
;
2379 dma_params
.rxfree
= dma_params
.dmaregs
+ CPDMA_RXFREE
;
2380 dma_params
.rxhdp
= dma_params
.txhdp
+ CPDMA_RXHDP
;
2381 dma_params
.txcp
= dma_params
.txhdp
+ CPDMA_TXCP
;
2382 dma_params
.rxcp
= dma_params
.txhdp
+ CPDMA_RXCP
;
2384 dma_params
.num_chan
= data
->channels
;
2385 dma_params
.has_soft_reset
= true;
2386 dma_params
.min_packet_size
= CPSW_MIN_PACKET_SIZE
;
2387 dma_params
.desc_mem_size
= data
->bd_ram_size
;
2388 dma_params
.desc_align
= 16;
2389 dma_params
.has_ext_regs
= true;
2390 dma_params
.desc_hw_addr
= dma_params
.desc_mem_phys
;
2392 priv
->dma
= cpdma_ctlr_create(&dma_params
);
2394 dev_err(priv
->dev
, "error initializing dma\n");
2396 goto clean_runtime_disable_ret
;
2399 priv
->txch
= cpdma_chan_create(priv
->dma
, tx_chan_num(0),
2401 priv
->rxch
= cpdma_chan_create(priv
->dma
, rx_chan_num(0),
2404 if (WARN_ON(!priv
->txch
|| !priv
->rxch
)) {
2405 dev_err(priv
->dev
, "error initializing dma channels\n");
2410 ale_params
.dev
= &ndev
->dev
;
2411 ale_params
.ale_ageout
= ale_ageout
;
2412 ale_params
.ale_entries
= data
->ale_entries
;
2413 ale_params
.ale_ports
= data
->slaves
;
2415 priv
->ale
= cpsw_ale_create(&ale_params
);
2417 dev_err(priv
->dev
, "error initializing ale engine\n");
2422 ndev
->irq
= platform_get_irq(pdev
, 1);
2423 if (ndev
->irq
< 0) {
2424 dev_err(priv
->dev
, "error getting irq resource\n");
2429 of_id
= of_match_device(cpsw_of_mtable
, &pdev
->dev
);
2431 pdev
->id_entry
= of_id
->data
;
2432 if (pdev
->id_entry
->driver_data
)
2433 priv
->quirk_irq
= true;
2436 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2437 * MISC IRQs which are always kept disabled with this driver so
2438 * we will not request them.
2440 * If anyone wants to implement support for those, make sure to
2441 * first request and append them to irqs_table array.
2445 irq
= platform_get_irq(pdev
, 1);
2451 priv
->irqs_table
[0] = irq
;
2452 ret
= devm_request_irq(&pdev
->dev
, irq
, cpsw_rx_interrupt
,
2453 0, dev_name(&pdev
->dev
), priv
);
2455 dev_err(priv
->dev
, "error attaching irq (%d)\n", ret
);
2460 irq
= platform_get_irq(pdev
, 2);
2466 priv
->irqs_table
[1] = irq
;
2467 ret
= devm_request_irq(&pdev
->dev
, irq
, cpsw_tx_interrupt
,
2468 0, dev_name(&pdev
->dev
), priv
);
2470 dev_err(priv
->dev
, "error attaching irq (%d)\n", ret
);
2475 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
2477 ndev
->netdev_ops
= &cpsw_netdev_ops
;
2478 ndev
->ethtool_ops
= &cpsw_ethtool_ops
;
2479 netif_napi_add(ndev
, &priv
->napi_rx
, cpsw_rx_poll
, CPSW_POLL_WEIGHT
);
2480 netif_tx_napi_add(ndev
, &priv
->napi_tx
, cpsw_tx_poll
, CPSW_POLL_WEIGHT
);
2482 /* register the network device */
2483 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
2484 ret
= register_netdev(ndev
);
2486 dev_err(priv
->dev
, "error registering net device\n");
2491 cpsw_notice(priv
, probe
, "initialized device (regs %pa, irq %d)\n",
2492 &ss_res
->start
, ndev
->irq
);
2494 if (priv
->data
.dual_emac
) {
2495 ret
= cpsw_probe_dual_emac(pdev
, priv
);
2497 cpsw_err(priv
, probe
, "error probe slave 2 emac interface\n");
2505 cpsw_ale_destroy(priv
->ale
);
2507 cpdma_chan_destroy(priv
->txch
);
2508 cpdma_chan_destroy(priv
->rxch
);
2509 cpdma_ctlr_destroy(priv
->dma
);
2510 clean_runtime_disable_ret
:
2511 pm_runtime_disable(&pdev
->dev
);
2513 free_netdev(priv
->ndev
);
2517 static int cpsw_remove_child_device(struct device
*dev
, void *c
)
2519 struct platform_device
*pdev
= to_platform_device(dev
);
2521 of_device_unregister(pdev
);
2526 static int cpsw_remove(struct platform_device
*pdev
)
2528 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2529 struct cpsw_priv
*priv
= netdev_priv(ndev
);
2531 if (priv
->data
.dual_emac
)
2532 unregister_netdev(cpsw_get_slave_ndev(priv
, 1));
2533 unregister_netdev(ndev
);
2535 cpsw_ale_destroy(priv
->ale
);
2536 cpdma_chan_destroy(priv
->txch
);
2537 cpdma_chan_destroy(priv
->rxch
);
2538 cpdma_ctlr_destroy(priv
->dma
);
2539 pm_runtime_disable(&pdev
->dev
);
2540 device_for_each_child(&pdev
->dev
, NULL
, cpsw_remove_child_device
);
2541 if (priv
->data
.dual_emac
)
2542 free_netdev(cpsw_get_slave_ndev(priv
, 1));
2547 #ifdef CONFIG_PM_SLEEP
2548 static int cpsw_suspend(struct device
*dev
)
2550 struct platform_device
*pdev
= to_platform_device(dev
);
2551 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2552 struct cpsw_priv
*priv
= netdev_priv(ndev
);
2554 if (priv
->data
.dual_emac
) {
2557 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
2558 if (netif_running(priv
->slaves
[i
].ndev
))
2559 cpsw_ndo_stop(priv
->slaves
[i
].ndev
);
2562 if (netif_running(ndev
))
2563 cpsw_ndo_stop(ndev
);
2566 /* Select sleep pin state */
2567 pinctrl_pm_select_sleep_state(&pdev
->dev
);
2572 static int cpsw_resume(struct device
*dev
)
2574 struct platform_device
*pdev
= to_platform_device(dev
);
2575 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2576 struct cpsw_priv
*priv
= netdev_priv(ndev
);
2578 /* Select default pin state */
2579 pinctrl_pm_select_default_state(&pdev
->dev
);
2581 if (priv
->data
.dual_emac
) {
2584 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
2585 if (netif_running(priv
->slaves
[i
].ndev
))
2586 cpsw_ndo_open(priv
->slaves
[i
].ndev
);
2589 if (netif_running(ndev
))
2590 cpsw_ndo_open(ndev
);
2596 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops
, cpsw_suspend
, cpsw_resume
);
2598 static struct platform_driver cpsw_driver
= {
2602 .of_match_table
= cpsw_of_mtable
,
2604 .probe
= cpsw_probe
,
2605 .remove
= cpsw_remove
,
2608 module_platform_driver(cpsw_driver
);
2610 MODULE_LICENSE("GPL");
2611 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2612 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2613 MODULE_DESCRIPTION("TI CPSW Ethernet driver");