2 * Texas Instruments Ethernet Switch Driver
4 * Copyright (C) 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
39 #include <linux/pinctrl/consumer.h>
44 #include "davinci_cpdma.h"
46 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
55 #define cpsw_info(priv, type, format, ...) \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
61 #define cpsw_err(priv, type, format, ...) \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
67 #define cpsw_dbg(priv, type, format, ...) \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
73 #define cpsw_notice(priv, type, format, ...) \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
79 #define ALE_ALL_PORTS 0x7
81 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
85 #define CPSW_VERSION_1 0x19010a
86 #define CPSW_VERSION_2 0x19010c
87 #define CPSW_VERSION_3 0x19010f
88 #define CPSW_VERSION_4 0x190112
90 #define HOST_PORT_NUM 0
91 #define SLIVER_SIZE 0x40
93 #define CPSW1_HOST_PORT_OFFSET 0x028
94 #define CPSW1_SLAVE_OFFSET 0x050
95 #define CPSW1_SLAVE_SIZE 0x040
96 #define CPSW1_CPDMA_OFFSET 0x100
97 #define CPSW1_STATERAM_OFFSET 0x200
98 #define CPSW1_HW_STATS 0x400
99 #define CPSW1_CPTS_OFFSET 0x500
100 #define CPSW1_ALE_OFFSET 0x600
101 #define CPSW1_SLIVER_OFFSET 0x700
103 #define CPSW2_HOST_PORT_OFFSET 0x108
104 #define CPSW2_SLAVE_OFFSET 0x200
105 #define CPSW2_SLAVE_SIZE 0x100
106 #define CPSW2_CPDMA_OFFSET 0x800
107 #define CPSW2_HW_STATS 0x900
108 #define CPSW2_STATERAM_OFFSET 0xa00
109 #define CPSW2_CPTS_OFFSET 0xc00
110 #define CPSW2_ALE_OFFSET 0xd00
111 #define CPSW2_SLIVER_OFFSET 0xd80
112 #define CPSW2_BD_OFFSET 0x2000
114 #define CPDMA_RXTHRESH 0x0c0
115 #define CPDMA_RXFREE 0x0e0
116 #define CPDMA_TXHDP 0x00
117 #define CPDMA_RXHDP 0x20
118 #define CPDMA_TXCP 0x40
119 #define CPDMA_RXCP 0x60
121 #define CPSW_POLL_WEIGHT 64
122 #define CPSW_MIN_PACKET_SIZE 60
123 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
125 #define RX_PRIORITY_MAPPING 0x76543210
126 #define TX_PRIORITY_MAPPING 0x33221100
127 #define CPDMA_TX_PRIORITY_MAP 0x76543210
129 #define CPSW_VLAN_AWARE BIT(1)
130 #define CPSW_ALE_VLAN_AWARE 1
132 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
136 #define CPSW_INTPACEEN (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT 63
139 #define CPSW_CMINTMIN_CNT 2
140 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
143 #define cpsw_slave_index(priv) \
144 ((priv->data.dual_emac) ? priv->emac_port : \
145 priv->data.active_slave)
147 static int debug_level
;
148 module_param(debug_level
, int, 0);
149 MODULE_PARM_DESC(debug_level
, "cpsw debug level (NETIF_MSG bits)");
151 static int ale_ageout
= 10;
152 module_param(ale_ageout
, int, 0);
153 MODULE_PARM_DESC(ale_ageout
, "cpsw ale ageout interval (seconds)");
155 static int rx_packet_max
= CPSW_MAX_PACKET_SIZE
;
156 module_param(rx_packet_max
, int, 0);
157 MODULE_PARM_DESC(rx_packet_max
, "maximum receive packet size (bytes)");
159 struct cpsw_wr_regs
{
179 struct cpsw_ss_regs
{
196 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
197 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
198 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
199 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
200 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
201 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
202 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
203 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
206 #define CPSW2_CONTROL 0x00 /* Control Register */
207 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
208 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
209 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
210 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
211 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
212 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
214 /* CPSW_PORT_V1 and V2 */
215 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
216 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
217 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
219 /* CPSW_PORT_V2 only */
220 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
221 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
222 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
223 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
224 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
225 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
226 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
227 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
229 /* Bit definitions for the CPSW2_CONTROL register */
230 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
231 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
232 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
233 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
234 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
235 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
236 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
237 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
238 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
239 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
240 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
241 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
242 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
243 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
244 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
245 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
246 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
248 #define CTRL_V2_TS_BITS \
249 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
250 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
252 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
253 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
254 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
257 #define CTRL_V3_TS_BITS \
258 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
259 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
262 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
263 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
264 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
269 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270 #define TS_MSG_TYPE_EN_MASK (0xffff)
272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
275 /* Bit definitions for the CPSW1_TS_CTL register */
276 #define CPSW_V1_TS_RX_EN BIT(0)
277 #define CPSW_V1_TS_TX_EN BIT(4)
278 #define CPSW_V1_MSG_TYPE_OFS 16
280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
283 struct cpsw_host_regs
{
289 u32 cpdma_tx_pri_map
;
290 u32 cpdma_rx_chan_map
;
293 struct cpsw_sliver_regs
{
306 struct cpsw_hw_stats
{
308 u32 rxbroadcastframes
;
309 u32 rxmulticastframes
;
312 u32 rxaligncodeerrors
;
313 u32 rxoversizedframes
;
315 u32 rxundersizedframes
;
320 u32 txbroadcastframes
;
321 u32 txmulticastframes
;
323 u32 txdeferredframes
;
324 u32 txcollisionframes
;
325 u32 txsinglecollframes
;
326 u32 txmultcollframes
;
327 u32 txexcessivecollisions
;
328 u32 txlatecollisions
;
330 u32 txcarriersenseerrors
;
333 u32 octetframes65t127
;
334 u32 octetframes128t255
;
335 u32 octetframes256t511
;
336 u32 octetframes512t1023
;
337 u32 octetframes1024tup
;
346 struct cpsw_sliver_regs __iomem
*sliver
;
349 struct cpsw_slave_data
*data
;
350 struct phy_device
*phy
;
351 struct net_device
*ndev
;
356 static inline u32
slave_read(struct cpsw_slave
*slave
, u32 offset
)
358 return __raw_readl(slave
->regs
+ offset
);
361 static inline void slave_write(struct cpsw_slave
*slave
, u32 val
, u32 offset
)
363 __raw_writel(val
, slave
->regs
+ offset
);
368 struct platform_device
*pdev
;
369 struct net_device
*ndev
;
370 struct napi_struct napi_rx
;
371 struct napi_struct napi_tx
;
373 struct cpsw_platform_data data
;
374 struct cpsw_ss_regs __iomem
*regs
;
375 struct cpsw_wr_regs __iomem
*wr_regs
;
376 u8 __iomem
*hw_stats
;
377 struct cpsw_host_regs __iomem
*host_port_regs
;
384 u8 mac_addr
[ETH_ALEN
];
385 struct cpsw_slave
*slaves
;
386 struct cpdma_ctlr
*dma
;
387 struct cpdma_chan
*txch
, *rxch
;
388 struct cpsw_ale
*ale
;
392 bool rx_irq_disabled
;
393 bool tx_irq_disabled
;
394 /* snapshot of IRQ numbers */
402 char stat_string
[ETH_GSTRING_LEN
];
414 #define CPSW_STAT(m) CPSW_STATS, \
415 sizeof(((struct cpsw_hw_stats *)0)->m), \
416 offsetof(struct cpsw_hw_stats, m)
417 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
418 sizeof(((struct cpdma_chan_stats *)0)->m), \
419 offsetof(struct cpdma_chan_stats, m)
420 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
421 sizeof(((struct cpdma_chan_stats *)0)->m), \
422 offsetof(struct cpdma_chan_stats, m)
424 static const struct cpsw_stats cpsw_gstrings_stats
[] = {
425 { "Good Rx Frames", CPSW_STAT(rxgoodframes
) },
426 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes
) },
427 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes
) },
428 { "Pause Rx Frames", CPSW_STAT(rxpauseframes
) },
429 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors
) },
430 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors
) },
431 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes
) },
432 { "Rx Jabbers", CPSW_STAT(rxjabberframes
) },
433 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes
) },
434 { "Rx Fragments", CPSW_STAT(rxfragments
) },
435 { "Rx Octets", CPSW_STAT(rxoctets
) },
436 { "Good Tx Frames", CPSW_STAT(txgoodframes
) },
437 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes
) },
438 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes
) },
439 { "Pause Tx Frames", CPSW_STAT(txpauseframes
) },
440 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes
) },
441 { "Collisions", CPSW_STAT(txcollisionframes
) },
442 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes
) },
443 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes
) },
444 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions
) },
445 { "Late Collisions", CPSW_STAT(txlatecollisions
) },
446 { "Tx Underrun", CPSW_STAT(txunderrun
) },
447 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors
) },
448 { "Tx Octets", CPSW_STAT(txoctets
) },
449 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64
) },
450 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127
) },
451 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255
) },
452 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511
) },
453 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023
) },
454 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup
) },
455 { "Net Octets", CPSW_STAT(netoctets
) },
456 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns
) },
457 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns
) },
458 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns
) },
459 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue
) },
460 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue
) },
461 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue
) },
462 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued
) },
463 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail
) },
464 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail
) },
465 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff
) },
466 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff
) },
467 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue
) },
468 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue
) },
469 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue
) },
470 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue
) },
471 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue
) },
472 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue
) },
473 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue
) },
474 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue
) },
475 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued
) },
476 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail
) },
477 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail
) },
478 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff
) },
479 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff
) },
480 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue
) },
481 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue
) },
482 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue
) },
483 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue
) },
484 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue
) },
487 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
489 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
490 #define for_each_slave(priv, func, arg...) \
492 struct cpsw_slave *slave; \
494 if (priv->data.dual_emac) \
495 (func)((priv)->slaves + priv->emac_port, ##arg);\
497 for (n = (priv)->data.slaves, \
498 slave = (priv)->slaves; \
500 (func)(slave++, ##arg); \
502 #define cpsw_get_slave_ndev(priv, __slave_no__) \
503 ((__slave_no__ < priv->data.slaves) ? \
504 priv->slaves[__slave_no__].ndev : NULL)
505 #define cpsw_get_slave_priv(priv, __slave_no__) \
506 (((__slave_no__ < priv->data.slaves) && \
507 (priv->slaves[__slave_no__].ndev)) ? \
508 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
510 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
512 if (!priv->data.dual_emac) \
514 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
515 ndev = cpsw_get_slave_ndev(priv, 0); \
516 priv = netdev_priv(ndev); \
518 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
519 ndev = cpsw_get_slave_ndev(priv, 1); \
520 priv = netdev_priv(ndev); \
524 #define cpsw_add_mcast(priv, addr) \
526 if (priv->data.dual_emac) { \
527 struct cpsw_slave *slave = priv->slaves + \
529 int slave_port = cpsw_get_slave_port(priv, \
531 cpsw_ale_add_mcast(priv->ale, addr, \
532 1 << slave_port | ALE_PORT_HOST, \
533 ALE_VLAN, slave->port_vlan, 0); \
535 cpsw_ale_add_mcast(priv->ale, addr, \
541 static inline int cpsw_get_slave_port(struct cpsw_priv
*priv
, u32 slave_num
)
543 return slave_num
+ 1;
546 static void cpsw_set_promiscious(struct net_device
*ndev
, bool enable
)
548 struct cpsw_priv
*priv
= netdev_priv(ndev
);
549 struct cpsw_ale
*ale
= priv
->ale
;
552 if (priv
->data
.dual_emac
) {
555 /* Enabling promiscuous mode for one interface will be
556 * common for both the interface as the interface shares
557 * the same hardware resource.
559 for (i
= 0; i
< priv
->data
.slaves
; i
++)
560 if (priv
->slaves
[i
].ndev
->flags
& IFF_PROMISC
)
563 if (!enable
&& flag
) {
565 dev_err(&ndev
->dev
, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
570 cpsw_ale_control_set(ale
, 0, ALE_BYPASS
, 1);
572 dev_dbg(&ndev
->dev
, "promiscuity enabled\n");
575 cpsw_ale_control_set(ale
, 0, ALE_BYPASS
, 0);
576 dev_dbg(&ndev
->dev
, "promiscuity disabled\n");
580 unsigned long timeout
= jiffies
+ HZ
;
582 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
583 for (i
= 0; i
<= priv
->data
.slaves
; i
++) {
584 cpsw_ale_control_set(ale
, i
,
585 ALE_PORT_NOLEARN
, 1);
586 cpsw_ale_control_set(ale
, i
,
587 ALE_PORT_NO_SA_UPDATE
, 1);
590 /* Clear All Untouched entries */
591 cpsw_ale_control_set(ale
, 0, ALE_AGEOUT
, 1);
594 if (cpsw_ale_control_get(ale
, 0, ALE_AGEOUT
))
596 } while (time_after(timeout
, jiffies
));
597 cpsw_ale_control_set(ale
, 0, ALE_AGEOUT
, 1);
599 /* Clear all mcast from ALE */
600 cpsw_ale_flush_multicast(ale
, ALE_ALL_PORTS
, -1);
602 /* Flood All Unicast Packets to Host port */
603 cpsw_ale_control_set(ale
, 0, ALE_P0_UNI_FLOOD
, 1);
604 dev_dbg(&ndev
->dev
, "promiscuity enabled\n");
606 /* Don't Flood All Unicast Packets to Host port */
607 cpsw_ale_control_set(ale
, 0, ALE_P0_UNI_FLOOD
, 0);
609 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
610 for (i
= 0; i
<= priv
->data
.slaves
; i
++) {
611 cpsw_ale_control_set(ale
, i
,
612 ALE_PORT_NOLEARN
, 0);
613 cpsw_ale_control_set(ale
, i
,
614 ALE_PORT_NO_SA_UPDATE
, 0);
616 dev_dbg(&ndev
->dev
, "promiscuity disabled\n");
621 static void cpsw_ndo_set_rx_mode(struct net_device
*ndev
)
623 struct cpsw_priv
*priv
= netdev_priv(ndev
);
626 if (priv
->data
.dual_emac
)
627 vid
= priv
->slaves
[priv
->emac_port
].port_vlan
;
629 vid
= priv
->data
.default_vlan
;
631 if (ndev
->flags
& IFF_PROMISC
) {
632 /* Enable promiscuous mode */
633 cpsw_set_promiscious(ndev
, true);
634 cpsw_ale_set_allmulti(priv
->ale
, IFF_ALLMULTI
);
637 /* Disable promiscuous mode */
638 cpsw_set_promiscious(ndev
, false);
641 /* Restore allmulti on vlans if necessary */
642 cpsw_ale_set_allmulti(priv
->ale
, priv
->ndev
->flags
& IFF_ALLMULTI
);
644 /* Clear all mcast from ALE */
645 cpsw_ale_flush_multicast(priv
->ale
, ALE_ALL_PORTS
, vid
);
647 if (!netdev_mc_empty(ndev
)) {
648 struct netdev_hw_addr
*ha
;
650 /* program multicast address list into ALE register */
651 netdev_for_each_mc_addr(ha
, ndev
) {
652 cpsw_add_mcast(priv
, (u8
*)ha
->addr
);
657 static void cpsw_intr_enable(struct cpsw_priv
*priv
)
659 __raw_writel(0xFF, &priv
->wr_regs
->tx_en
);
660 __raw_writel(0xFF, &priv
->wr_regs
->rx_en
);
662 cpdma_ctlr_int_ctrl(priv
->dma
, true);
666 static void cpsw_intr_disable(struct cpsw_priv
*priv
)
668 __raw_writel(0, &priv
->wr_regs
->tx_en
);
669 __raw_writel(0, &priv
->wr_regs
->rx_en
);
671 cpdma_ctlr_int_ctrl(priv
->dma
, false);
675 static void cpsw_tx_handler(void *token
, int len
, int status
)
677 struct sk_buff
*skb
= token
;
678 struct net_device
*ndev
= skb
->dev
;
679 struct cpsw_priv
*priv
= netdev_priv(ndev
);
681 /* Check whether the queue is stopped due to stalled tx dma, if the
682 * queue is stopped then start the queue as we have free desc for tx
684 if (unlikely(netif_queue_stopped(ndev
)))
685 netif_wake_queue(ndev
);
686 cpts_tx_timestamp(priv
->cpts
, skb
);
687 ndev
->stats
.tx_packets
++;
688 ndev
->stats
.tx_bytes
+= len
;
689 dev_kfree_skb_any(skb
);
692 static void cpsw_rx_handler(void *token
, int len
, int status
)
694 struct sk_buff
*skb
= token
;
695 struct sk_buff
*new_skb
;
696 struct net_device
*ndev
= skb
->dev
;
697 struct cpsw_priv
*priv
= netdev_priv(ndev
);
700 cpsw_dual_emac_src_port_detect(status
, priv
, ndev
, skb
);
702 if (unlikely(status
< 0) || unlikely(!netif_running(ndev
))) {
703 bool ndev_status
= false;
704 struct cpsw_slave
*slave
= priv
->slaves
;
707 if (priv
->data
.dual_emac
) {
708 /* In dual emac mode check for all interfaces */
709 for (n
= priv
->data
.slaves
; n
; n
--, slave
++)
710 if (netif_running(slave
->ndev
))
714 if (ndev_status
&& (status
>= 0)) {
715 /* The packet received is for the interface which
716 * is already down and the other interface is up
717 * and running, instead of freeing which results
718 * in reducing of the number of rx descriptor in
719 * DMA engine, requeue skb back to cpdma.
725 /* the interface is going down, skbs are purged */
726 dev_kfree_skb_any(skb
);
730 new_skb
= netdev_alloc_skb_ip_align(ndev
, priv
->rx_packet_max
);
733 cpts_rx_timestamp(priv
->cpts
, skb
);
734 skb
->protocol
= eth_type_trans(skb
, ndev
);
735 netif_receive_skb(skb
);
736 ndev
->stats
.rx_bytes
+= len
;
737 ndev
->stats
.rx_packets
++;
739 ndev
->stats
.rx_dropped
++;
744 ret
= cpdma_chan_submit(priv
->rxch
, new_skb
, new_skb
->data
,
745 skb_tailroom(new_skb
), 0);
746 if (WARN_ON(ret
< 0))
747 dev_kfree_skb_any(new_skb
);
750 static irqreturn_t
cpsw_tx_interrupt(int irq
, void *dev_id
)
752 struct cpsw_priv
*priv
= dev_id
;
754 writel(0, &priv
->wr_regs
->tx_en
);
755 cpdma_ctlr_eoi(priv
->dma
, CPDMA_EOI_TX
);
757 if (priv
->quirk_irq
) {
758 disable_irq_nosync(priv
->irqs_table
[1]);
759 priv
->tx_irq_disabled
= true;
762 napi_schedule(&priv
->napi_tx
);
766 static irqreturn_t
cpsw_rx_interrupt(int irq
, void *dev_id
)
768 struct cpsw_priv
*priv
= dev_id
;
770 cpdma_ctlr_eoi(priv
->dma
, CPDMA_EOI_RX
);
771 writel(0, &priv
->wr_regs
->rx_en
);
773 if (priv
->quirk_irq
) {
774 disable_irq_nosync(priv
->irqs_table
[0]);
775 priv
->rx_irq_disabled
= true;
778 napi_schedule(&priv
->napi_rx
);
782 static int cpsw_tx_poll(struct napi_struct
*napi_tx
, int budget
)
784 struct cpsw_priv
*priv
= napi_to_priv(napi_tx
);
787 num_tx
= cpdma_chan_process(priv
->txch
, budget
);
788 if (num_tx
< budget
) {
789 napi_complete(napi_tx
);
790 writel(0xff, &priv
->wr_regs
->tx_en
);
791 if (priv
->quirk_irq
&& priv
->tx_irq_disabled
) {
792 priv
->tx_irq_disabled
= false;
793 enable_irq(priv
->irqs_table
[1]);
798 cpsw_dbg(priv
, intr
, "poll %d tx pkts\n", num_tx
);
803 static int cpsw_rx_poll(struct napi_struct
*napi_rx
, int budget
)
805 struct cpsw_priv
*priv
= napi_to_priv(napi_rx
);
808 num_rx
= cpdma_chan_process(priv
->rxch
, budget
);
809 if (num_rx
< budget
) {
810 napi_complete(napi_rx
);
811 writel(0xff, &priv
->wr_regs
->rx_en
);
812 if (priv
->quirk_irq
&& priv
->rx_irq_disabled
) {
813 priv
->rx_irq_disabled
= false;
814 enable_irq(priv
->irqs_table
[0]);
819 cpsw_dbg(priv
, intr
, "poll %d rx pkts\n", num_rx
);
824 static inline void soft_reset(const char *module
, void __iomem
*reg
)
826 unsigned long timeout
= jiffies
+ HZ
;
828 __raw_writel(1, reg
);
831 } while ((__raw_readl(reg
) & 1) && time_after(timeout
, jiffies
));
833 WARN(__raw_readl(reg
) & 1, "failed to soft-reset %s\n", module
);
836 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
837 ((mac)[2] << 16) | ((mac)[3] << 24))
838 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
840 static void cpsw_set_slave_mac(struct cpsw_slave
*slave
,
841 struct cpsw_priv
*priv
)
843 slave_write(slave
, mac_hi(priv
->mac_addr
), SA_HI
);
844 slave_write(slave
, mac_lo(priv
->mac_addr
), SA_LO
);
847 static void _cpsw_adjust_link(struct cpsw_slave
*slave
,
848 struct cpsw_priv
*priv
, bool *link
)
850 struct phy_device
*phy
= slave
->phy
;
857 slave_port
= cpsw_get_slave_port(priv
, slave
->slave_num
);
860 mac_control
= priv
->data
.mac_control
;
862 /* enable forwarding */
863 cpsw_ale_control_set(priv
->ale
, slave_port
,
864 ALE_PORT_STATE
, ALE_PORT_STATE_FORWARD
);
866 if (phy
->speed
== 1000)
867 mac_control
|= BIT(7); /* GIGABITEN */
869 mac_control
|= BIT(0); /* FULLDUPLEXEN */
871 /* set speed_in input in case RMII mode is used in 100Mbps */
872 if (phy
->speed
== 100)
873 mac_control
|= BIT(15);
874 else if (phy
->speed
== 10)
875 mac_control
|= BIT(18); /* In Band mode */
878 mac_control
|= BIT(3);
881 mac_control
|= BIT(4);
886 /* disable forwarding */
887 cpsw_ale_control_set(priv
->ale
, slave_port
,
888 ALE_PORT_STATE
, ALE_PORT_STATE_DISABLE
);
891 if (mac_control
!= slave
->mac_control
) {
892 phy_print_status(phy
);
893 __raw_writel(mac_control
, &slave
->sliver
->mac_control
);
896 slave
->mac_control
= mac_control
;
899 static void cpsw_adjust_link(struct net_device
*ndev
)
901 struct cpsw_priv
*priv
= netdev_priv(ndev
);
904 for_each_slave(priv
, _cpsw_adjust_link
, priv
, &link
);
907 netif_carrier_on(ndev
);
908 if (netif_running(ndev
))
909 netif_wake_queue(ndev
);
911 netif_carrier_off(ndev
);
912 netif_stop_queue(ndev
);
916 static int cpsw_get_coalesce(struct net_device
*ndev
,
917 struct ethtool_coalesce
*coal
)
919 struct cpsw_priv
*priv
= netdev_priv(ndev
);
921 coal
->rx_coalesce_usecs
= priv
->coal_intvl
;
925 static int cpsw_set_coalesce(struct net_device
*ndev
,
926 struct ethtool_coalesce
*coal
)
928 struct cpsw_priv
*priv
= netdev_priv(ndev
);
930 u32 num_interrupts
= 0;
935 coal_intvl
= coal
->rx_coalesce_usecs
;
937 int_ctrl
= readl(&priv
->wr_regs
->int_control
);
938 prescale
= priv
->bus_freq_mhz
* 4;
940 if (!coal
->rx_coalesce_usecs
) {
941 int_ctrl
&= ~(CPSW_INTPRESCALE_MASK
| CPSW_INTPACEEN
);
945 if (coal_intvl
< CPSW_CMINTMIN_INTVL
)
946 coal_intvl
= CPSW_CMINTMIN_INTVL
;
948 if (coal_intvl
> CPSW_CMINTMAX_INTVL
) {
949 /* Interrupt pacer works with 4us Pulse, we can
950 * throttle further by dilating the 4us pulse.
952 addnl_dvdr
= CPSW_INTPRESCALE_MASK
/ prescale
;
954 if (addnl_dvdr
> 1) {
955 prescale
*= addnl_dvdr
;
956 if (coal_intvl
> (CPSW_CMINTMAX_INTVL
* addnl_dvdr
))
957 coal_intvl
= (CPSW_CMINTMAX_INTVL
961 coal_intvl
= CPSW_CMINTMAX_INTVL
;
965 num_interrupts
= (1000 * addnl_dvdr
) / coal_intvl
;
966 writel(num_interrupts
, &priv
->wr_regs
->rx_imax
);
967 writel(num_interrupts
, &priv
->wr_regs
->tx_imax
);
969 int_ctrl
|= CPSW_INTPACEEN
;
970 int_ctrl
&= (~CPSW_INTPRESCALE_MASK
);
971 int_ctrl
|= (prescale
& CPSW_INTPRESCALE_MASK
);
974 writel(int_ctrl
, &priv
->wr_regs
->int_control
);
976 cpsw_notice(priv
, timer
, "Set coalesce to %d usecs.\n", coal_intvl
);
977 if (priv
->data
.dual_emac
) {
980 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
981 priv
= netdev_priv(priv
->slaves
[i
].ndev
);
982 priv
->coal_intvl
= coal_intvl
;
985 priv
->coal_intvl
= coal_intvl
;
991 static int cpsw_get_sset_count(struct net_device
*ndev
, int sset
)
995 return CPSW_STATS_LEN
;
1001 static void cpsw_get_strings(struct net_device
*ndev
, u32 stringset
, u8
*data
)
1006 switch (stringset
) {
1008 for (i
= 0; i
< CPSW_STATS_LEN
; i
++) {
1009 memcpy(p
, cpsw_gstrings_stats
[i
].stat_string
,
1011 p
+= ETH_GSTRING_LEN
;
1017 static void cpsw_get_ethtool_stats(struct net_device
*ndev
,
1018 struct ethtool_stats
*stats
, u64
*data
)
1020 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1021 struct cpdma_chan_stats rx_stats
;
1022 struct cpdma_chan_stats tx_stats
;
1027 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1028 cpdma_chan_get_stats(priv
->rxch
, &rx_stats
);
1029 cpdma_chan_get_stats(priv
->txch
, &tx_stats
);
1031 for (i
= 0; i
< CPSW_STATS_LEN
; i
++) {
1032 switch (cpsw_gstrings_stats
[i
].type
) {
1034 val
= readl(priv
->hw_stats
+
1035 cpsw_gstrings_stats
[i
].stat_offset
);
1039 case CPDMA_RX_STATS
:
1040 p
= (u8
*)&rx_stats
+
1041 cpsw_gstrings_stats
[i
].stat_offset
;
1042 data
[i
] = *(u32
*)p
;
1045 case CPDMA_TX_STATS
:
1046 p
= (u8
*)&tx_stats
+
1047 cpsw_gstrings_stats
[i
].stat_offset
;
1048 data
[i
] = *(u32
*)p
;
1054 static int cpsw_common_res_usage_state(struct cpsw_priv
*priv
)
1057 u32 usage_count
= 0;
1059 if (!priv
->data
.dual_emac
)
1062 for (i
= 0; i
< priv
->data
.slaves
; i
++)
1063 if (priv
->slaves
[i
].open_stat
)
1069 static inline int cpsw_tx_packet_submit(struct net_device
*ndev
,
1070 struct cpsw_priv
*priv
, struct sk_buff
*skb
)
1072 if (!priv
->data
.dual_emac
)
1073 return cpdma_chan_submit(priv
->txch
, skb
, skb
->data
,
1076 if (ndev
== cpsw_get_slave_ndev(priv
, 0))
1077 return cpdma_chan_submit(priv
->txch
, skb
, skb
->data
,
1080 return cpdma_chan_submit(priv
->txch
, skb
, skb
->data
,
1084 static inline void cpsw_add_dual_emac_def_ale_entries(
1085 struct cpsw_priv
*priv
, struct cpsw_slave
*slave
,
1088 u32 port_mask
= 1 << slave_port
| ALE_PORT_HOST
;
1090 if (priv
->version
== CPSW_VERSION_1
)
1091 slave_write(slave
, slave
->port_vlan
, CPSW1_PORT_VLAN
);
1093 slave_write(slave
, slave
->port_vlan
, CPSW2_PORT_VLAN
);
1094 cpsw_ale_add_vlan(priv
->ale
, slave
->port_vlan
, port_mask
,
1095 port_mask
, port_mask
, 0);
1096 cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1097 port_mask
, ALE_VLAN
, slave
->port_vlan
, 0);
1098 cpsw_ale_add_ucast(priv
->ale
, priv
->mac_addr
,
1099 HOST_PORT_NUM
, ALE_VLAN
| ALE_SECURE
, slave
->port_vlan
);
1102 static void soft_reset_slave(struct cpsw_slave
*slave
)
1106 snprintf(name
, sizeof(name
), "slave-%d", slave
->slave_num
);
1107 soft_reset(name
, &slave
->sliver
->soft_reset
);
1110 static void cpsw_slave_open(struct cpsw_slave
*slave
, struct cpsw_priv
*priv
)
1114 soft_reset_slave(slave
);
1116 /* setup priority mapping */
1117 __raw_writel(RX_PRIORITY_MAPPING
, &slave
->sliver
->rx_pri_map
);
1119 switch (priv
->version
) {
1120 case CPSW_VERSION_1
:
1121 slave_write(slave
, TX_PRIORITY_MAPPING
, CPSW1_TX_PRI_MAP
);
1123 case CPSW_VERSION_2
:
1124 case CPSW_VERSION_3
:
1125 case CPSW_VERSION_4
:
1126 slave_write(slave
, TX_PRIORITY_MAPPING
, CPSW2_TX_PRI_MAP
);
1130 /* setup max packet size, and mac address */
1131 __raw_writel(priv
->rx_packet_max
, &slave
->sliver
->rx_maxlen
);
1132 cpsw_set_slave_mac(slave
, priv
);
1134 slave
->mac_control
= 0; /* no link yet */
1136 slave_port
= cpsw_get_slave_port(priv
, slave
->slave_num
);
1138 if (priv
->data
.dual_emac
)
1139 cpsw_add_dual_emac_def_ale_entries(priv
, slave
, slave_port
);
1141 cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1142 1 << slave_port
, 0, 0, ALE_MCAST_FWD_2
);
1144 if (slave
->data
->phy_node
) {
1145 slave
->phy
= of_phy_connect(priv
->ndev
, slave
->data
->phy_node
,
1146 &cpsw_adjust_link
, 0, slave
->data
->phy_if
);
1148 dev_err(priv
->dev
, "phy \"%s\" not found on slave %d\n",
1149 slave
->data
->phy_node
->full_name
,
1154 slave
->phy
= phy_connect(priv
->ndev
, slave
->data
->phy_id
,
1155 &cpsw_adjust_link
, slave
->data
->phy_if
);
1156 if (IS_ERR(slave
->phy
)) {
1158 "phy \"%s\" not found on slave %d, err %ld\n",
1159 slave
->data
->phy_id
, slave
->slave_num
,
1160 PTR_ERR(slave
->phy
));
1166 phy_attached_info(slave
->phy
);
1168 phy_start(slave
->phy
);
1170 /* Configure GMII_SEL register */
1171 cpsw_phy_sel(&priv
->pdev
->dev
, slave
->phy
->interface
, slave
->slave_num
);
1174 static inline void cpsw_add_default_vlan(struct cpsw_priv
*priv
)
1176 const int vlan
= priv
->data
.default_vlan
;
1179 int unreg_mcast_mask
;
1181 reg
= (priv
->version
== CPSW_VERSION_1
) ? CPSW1_PORT_VLAN
:
1184 writel(vlan
, &priv
->host_port_regs
->port_vlan
);
1186 for (i
= 0; i
< priv
->data
.slaves
; i
++)
1187 slave_write(priv
->slaves
+ i
, vlan
, reg
);
1189 if (priv
->ndev
->flags
& IFF_ALLMULTI
)
1190 unreg_mcast_mask
= ALE_ALL_PORTS
;
1192 unreg_mcast_mask
= ALE_PORT_1
| ALE_PORT_2
;
1194 cpsw_ale_add_vlan(priv
->ale
, vlan
, ALE_ALL_PORTS
,
1195 ALE_ALL_PORTS
, ALE_ALL_PORTS
,
1199 static void cpsw_init_host_port(struct cpsw_priv
*priv
)
1204 /* soft reset the controller and initialize ale */
1205 soft_reset("cpsw", &priv
->regs
->soft_reset
);
1206 cpsw_ale_start(priv
->ale
);
1208 /* switch to vlan unaware mode */
1209 cpsw_ale_control_set(priv
->ale
, HOST_PORT_NUM
, ALE_VLAN_AWARE
,
1210 CPSW_ALE_VLAN_AWARE
);
1211 control_reg
= readl(&priv
->regs
->control
);
1212 control_reg
|= CPSW_VLAN_AWARE
;
1213 writel(control_reg
, &priv
->regs
->control
);
1214 fifo_mode
= (priv
->data
.dual_emac
) ? CPSW_FIFO_DUAL_MAC_MODE
:
1215 CPSW_FIFO_NORMAL_MODE
;
1216 writel(fifo_mode
, &priv
->host_port_regs
->tx_in_ctl
);
1218 /* setup host port priority mapping */
1219 __raw_writel(CPDMA_TX_PRIORITY_MAP
,
1220 &priv
->host_port_regs
->cpdma_tx_pri_map
);
1221 __raw_writel(0, &priv
->host_port_regs
->cpdma_rx_chan_map
);
1223 cpsw_ale_control_set(priv
->ale
, HOST_PORT_NUM
,
1224 ALE_PORT_STATE
, ALE_PORT_STATE_FORWARD
);
1226 if (!priv
->data
.dual_emac
) {
1227 cpsw_ale_add_ucast(priv
->ale
, priv
->mac_addr
, HOST_PORT_NUM
,
1229 cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1230 ALE_PORT_HOST
, 0, 0, ALE_MCAST_FWD_2
);
1234 static void cpsw_slave_stop(struct cpsw_slave
*slave
, struct cpsw_priv
*priv
)
1238 slave_port
= cpsw_get_slave_port(priv
, slave
->slave_num
);
1242 phy_stop(slave
->phy
);
1243 phy_disconnect(slave
->phy
);
1245 cpsw_ale_control_set(priv
->ale
, slave_port
,
1246 ALE_PORT_STATE
, ALE_PORT_STATE_DISABLE
);
1249 static int cpsw_ndo_open(struct net_device
*ndev
)
1251 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1255 pm_runtime_get_sync(&priv
->pdev
->dev
);
1257 if (!cpsw_common_res_usage_state(priv
))
1258 cpsw_intr_disable(priv
);
1259 netif_carrier_off(ndev
);
1261 reg
= priv
->version
;
1263 dev_info(priv
->dev
, "initializing cpsw version %d.%d (%d)\n",
1264 CPSW_MAJOR_VERSION(reg
), CPSW_MINOR_VERSION(reg
),
1265 CPSW_RTL_VERSION(reg
));
1267 /* initialize host and slave ports */
1268 if (!cpsw_common_res_usage_state(priv
))
1269 cpsw_init_host_port(priv
);
1270 for_each_slave(priv
, cpsw_slave_open
, priv
);
1272 /* Add default VLAN */
1273 if (!priv
->data
.dual_emac
)
1274 cpsw_add_default_vlan(priv
);
1276 cpsw_ale_add_vlan(priv
->ale
, priv
->data
.default_vlan
,
1277 ALE_ALL_PORTS
, ALE_ALL_PORTS
, 0, 0);
1279 if (!cpsw_common_res_usage_state(priv
)) {
1280 struct cpsw_priv
*priv_sl0
= cpsw_get_slave_priv(priv
, 0);
1282 /* setup tx dma to fixed prio and zero offset */
1283 cpdma_control_set(priv
->dma
, CPDMA_TX_PRIO_FIXED
, 1);
1284 cpdma_control_set(priv
->dma
, CPDMA_RX_BUFFER_OFFSET
, 0);
1286 /* disable priority elevation */
1287 __raw_writel(0, &priv
->regs
->ptype
);
1289 /* enable statistics collection only on all ports */
1290 __raw_writel(0x7, &priv
->regs
->stat_port_en
);
1292 /* Enable internal fifo flow control */
1293 writel(0x7, &priv
->regs
->flow_control
);
1295 napi_enable(&priv_sl0
->napi_rx
);
1296 napi_enable(&priv_sl0
->napi_tx
);
1298 if (priv_sl0
->tx_irq_disabled
) {
1299 priv_sl0
->tx_irq_disabled
= false;
1300 enable_irq(priv
->irqs_table
[1]);
1303 if (priv_sl0
->rx_irq_disabled
) {
1304 priv_sl0
->rx_irq_disabled
= false;
1305 enable_irq(priv
->irqs_table
[0]);
1308 if (WARN_ON(!priv
->data
.rx_descs
))
1309 priv
->data
.rx_descs
= 128;
1311 for (i
= 0; i
< priv
->data
.rx_descs
; i
++) {
1312 struct sk_buff
*skb
;
1315 skb
= __netdev_alloc_skb_ip_align(priv
->ndev
,
1316 priv
->rx_packet_max
, GFP_KERNEL
);
1319 ret
= cpdma_chan_submit(priv
->rxch
, skb
, skb
->data
,
1320 skb_tailroom(skb
), 0);
1326 /* continue even if we didn't manage to submit all
1329 cpsw_info(priv
, ifup
, "submitted %d rx descriptors\n", i
);
1331 if (cpts_register(&priv
->pdev
->dev
, priv
->cpts
,
1332 priv
->data
.cpts_clock_mult
,
1333 priv
->data
.cpts_clock_shift
))
1334 dev_err(priv
->dev
, "error registering cpts device\n");
1338 /* Enable Interrupt pacing if configured */
1339 if (priv
->coal_intvl
!= 0) {
1340 struct ethtool_coalesce coal
;
1342 coal
.rx_coalesce_usecs
= priv
->coal_intvl
;
1343 cpsw_set_coalesce(ndev
, &coal
);
1346 cpdma_ctlr_start(priv
->dma
);
1347 cpsw_intr_enable(priv
);
1349 if (priv
->data
.dual_emac
)
1350 priv
->slaves
[priv
->emac_port
].open_stat
= true;
1354 cpdma_ctlr_stop(priv
->dma
);
1355 for_each_slave(priv
, cpsw_slave_stop
, priv
);
1356 pm_runtime_put_sync(&priv
->pdev
->dev
);
1357 netif_carrier_off(priv
->ndev
);
1361 static int cpsw_ndo_stop(struct net_device
*ndev
)
1363 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1365 cpsw_info(priv
, ifdown
, "shutting down cpsw device\n");
1366 netif_stop_queue(priv
->ndev
);
1367 netif_carrier_off(priv
->ndev
);
1369 if (cpsw_common_res_usage_state(priv
) <= 1) {
1370 struct cpsw_priv
*priv_sl0
= cpsw_get_slave_priv(priv
, 0);
1372 napi_disable(&priv_sl0
->napi_rx
);
1373 napi_disable(&priv_sl0
->napi_tx
);
1374 cpts_unregister(priv
->cpts
);
1375 cpsw_intr_disable(priv
);
1376 cpdma_ctlr_stop(priv
->dma
);
1377 cpsw_ale_stop(priv
->ale
);
1379 for_each_slave(priv
, cpsw_slave_stop
, priv
);
1380 pm_runtime_put_sync(&priv
->pdev
->dev
);
1381 if (priv
->data
.dual_emac
)
1382 priv
->slaves
[priv
->emac_port
].open_stat
= false;
1386 static netdev_tx_t
cpsw_ndo_start_xmit(struct sk_buff
*skb
,
1387 struct net_device
*ndev
)
1389 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1392 netif_trans_update(ndev
);
1394 if (skb_padto(skb
, CPSW_MIN_PACKET_SIZE
)) {
1395 cpsw_err(priv
, tx_err
, "packet pad failed\n");
1396 ndev
->stats
.tx_dropped
++;
1397 return NETDEV_TX_OK
;
1400 if (skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
&&
1401 priv
->cpts
->tx_enable
)
1402 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
1404 skb_tx_timestamp(skb
);
1406 ret
= cpsw_tx_packet_submit(ndev
, priv
, skb
);
1407 if (unlikely(ret
!= 0)) {
1408 cpsw_err(priv
, tx_err
, "desc submit failed\n");
1412 /* If there is no more tx desc left free then we need to
1413 * tell the kernel to stop sending us tx frames.
1415 if (unlikely(!cpdma_check_free_tx_desc(priv
->txch
)))
1416 netif_stop_queue(ndev
);
1418 return NETDEV_TX_OK
;
1420 ndev
->stats
.tx_dropped
++;
1421 netif_stop_queue(ndev
);
1422 return NETDEV_TX_BUSY
;
1425 #ifdef CONFIG_TI_CPTS
1427 static void cpsw_hwtstamp_v1(struct cpsw_priv
*priv
)
1429 struct cpsw_slave
*slave
= &priv
->slaves
[priv
->data
.active_slave
];
1432 if (!priv
->cpts
->tx_enable
&& !priv
->cpts
->rx_enable
) {
1433 slave_write(slave
, 0, CPSW1_TS_CTL
);
1437 seq_id
= (30 << CPSW_V1_SEQ_ID_OFS_SHIFT
) | ETH_P_1588
;
1438 ts_en
= EVENT_MSG_BITS
<< CPSW_V1_MSG_TYPE_OFS
;
1440 if (priv
->cpts
->tx_enable
)
1441 ts_en
|= CPSW_V1_TS_TX_EN
;
1443 if (priv
->cpts
->rx_enable
)
1444 ts_en
|= CPSW_V1_TS_RX_EN
;
1446 slave_write(slave
, ts_en
, CPSW1_TS_CTL
);
1447 slave_write(slave
, seq_id
, CPSW1_TS_SEQ_LTYPE
);
1450 static void cpsw_hwtstamp_v2(struct cpsw_priv
*priv
)
1452 struct cpsw_slave
*slave
;
1455 if (priv
->data
.dual_emac
)
1456 slave
= &priv
->slaves
[priv
->emac_port
];
1458 slave
= &priv
->slaves
[priv
->data
.active_slave
];
1460 ctrl
= slave_read(slave
, CPSW2_CONTROL
);
1461 switch (priv
->version
) {
1462 case CPSW_VERSION_2
:
1463 ctrl
&= ~CTRL_V2_ALL_TS_MASK
;
1465 if (priv
->cpts
->tx_enable
)
1466 ctrl
|= CTRL_V2_TX_TS_BITS
;
1468 if (priv
->cpts
->rx_enable
)
1469 ctrl
|= CTRL_V2_RX_TS_BITS
;
1471 case CPSW_VERSION_3
:
1473 ctrl
&= ~CTRL_V3_ALL_TS_MASK
;
1475 if (priv
->cpts
->tx_enable
)
1476 ctrl
|= CTRL_V3_TX_TS_BITS
;
1478 if (priv
->cpts
->rx_enable
)
1479 ctrl
|= CTRL_V3_RX_TS_BITS
;
1483 mtype
= (30 << TS_SEQ_ID_OFFSET_SHIFT
) | EVENT_MSG_BITS
;
1485 slave_write(slave
, mtype
, CPSW2_TS_SEQ_MTYPE
);
1486 slave_write(slave
, ctrl
, CPSW2_CONTROL
);
1487 __raw_writel(ETH_P_1588
, &priv
->regs
->ts_ltype
);
1490 static int cpsw_hwtstamp_set(struct net_device
*dev
, struct ifreq
*ifr
)
1492 struct cpsw_priv
*priv
= netdev_priv(dev
);
1493 struct cpts
*cpts
= priv
->cpts
;
1494 struct hwtstamp_config cfg
;
1496 if (priv
->version
!= CPSW_VERSION_1
&&
1497 priv
->version
!= CPSW_VERSION_2
&&
1498 priv
->version
!= CPSW_VERSION_3
)
1501 if (copy_from_user(&cfg
, ifr
->ifr_data
, sizeof(cfg
)))
1504 /* reserved for future extensions */
1508 if (cfg
.tx_type
!= HWTSTAMP_TX_OFF
&& cfg
.tx_type
!= HWTSTAMP_TX_ON
)
1511 switch (cfg
.rx_filter
) {
1512 case HWTSTAMP_FILTER_NONE
:
1513 cpts
->rx_enable
= 0;
1515 case HWTSTAMP_FILTER_ALL
:
1516 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
1517 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
1518 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
1520 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
1521 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
1522 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
1523 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
1524 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
1525 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
1526 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
1527 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
1528 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
1529 cpts
->rx_enable
= 1;
1530 cfg
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
1536 cpts
->tx_enable
= cfg
.tx_type
== HWTSTAMP_TX_ON
;
1538 switch (priv
->version
) {
1539 case CPSW_VERSION_1
:
1540 cpsw_hwtstamp_v1(priv
);
1542 case CPSW_VERSION_2
:
1543 case CPSW_VERSION_3
:
1544 cpsw_hwtstamp_v2(priv
);
1550 return copy_to_user(ifr
->ifr_data
, &cfg
, sizeof(cfg
)) ? -EFAULT
: 0;
1553 static int cpsw_hwtstamp_get(struct net_device
*dev
, struct ifreq
*ifr
)
1555 struct cpsw_priv
*priv
= netdev_priv(dev
);
1556 struct cpts
*cpts
= priv
->cpts
;
1557 struct hwtstamp_config cfg
;
1559 if (priv
->version
!= CPSW_VERSION_1
&&
1560 priv
->version
!= CPSW_VERSION_2
&&
1561 priv
->version
!= CPSW_VERSION_3
)
1565 cfg
.tx_type
= cpts
->tx_enable
? HWTSTAMP_TX_ON
: HWTSTAMP_TX_OFF
;
1566 cfg
.rx_filter
= (cpts
->rx_enable
?
1567 HWTSTAMP_FILTER_PTP_V2_EVENT
: HWTSTAMP_FILTER_NONE
);
1569 return copy_to_user(ifr
->ifr_data
, &cfg
, sizeof(cfg
)) ? -EFAULT
: 0;
1572 #endif /*CONFIG_TI_CPTS*/
1574 static int cpsw_ndo_ioctl(struct net_device
*dev
, struct ifreq
*req
, int cmd
)
1576 struct cpsw_priv
*priv
= netdev_priv(dev
);
1577 int slave_no
= cpsw_slave_index(priv
);
1579 if (!netif_running(dev
))
1583 #ifdef CONFIG_TI_CPTS
1585 return cpsw_hwtstamp_set(dev
, req
);
1587 return cpsw_hwtstamp_get(dev
, req
);
1591 if (!priv
->slaves
[slave_no
].phy
)
1593 return phy_mii_ioctl(priv
->slaves
[slave_no
].phy
, req
, cmd
);
1596 static void cpsw_ndo_tx_timeout(struct net_device
*ndev
)
1598 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1600 cpsw_err(priv
, tx_err
, "transmit timeout, restarting dma\n");
1601 ndev
->stats
.tx_errors
++;
1602 cpsw_intr_disable(priv
);
1603 cpdma_chan_stop(priv
->txch
);
1604 cpdma_chan_start(priv
->txch
);
1605 cpsw_intr_enable(priv
);
1608 static int cpsw_ndo_set_mac_address(struct net_device
*ndev
, void *p
)
1610 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1611 struct sockaddr
*addr
= (struct sockaddr
*)p
;
1615 if (!is_valid_ether_addr(addr
->sa_data
))
1616 return -EADDRNOTAVAIL
;
1618 if (priv
->data
.dual_emac
) {
1619 vid
= priv
->slaves
[priv
->emac_port
].port_vlan
;
1623 cpsw_ale_del_ucast(priv
->ale
, priv
->mac_addr
, HOST_PORT_NUM
,
1625 cpsw_ale_add_ucast(priv
->ale
, addr
->sa_data
, HOST_PORT_NUM
,
1628 memcpy(priv
->mac_addr
, addr
->sa_data
, ETH_ALEN
);
1629 memcpy(ndev
->dev_addr
, priv
->mac_addr
, ETH_ALEN
);
1630 for_each_slave(priv
, cpsw_set_slave_mac
, priv
);
1635 #ifdef CONFIG_NET_POLL_CONTROLLER
1636 static void cpsw_ndo_poll_controller(struct net_device
*ndev
)
1638 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1640 cpsw_intr_disable(priv
);
1641 cpsw_rx_interrupt(priv
->irqs_table
[0], priv
);
1642 cpsw_tx_interrupt(priv
->irqs_table
[1], priv
);
1643 cpsw_intr_enable(priv
);
1647 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv
*priv
,
1651 int unreg_mcast_mask
= 0;
1654 if (priv
->data
.dual_emac
) {
1655 port_mask
= (1 << (priv
->emac_port
+ 1)) | ALE_PORT_HOST
;
1657 if (priv
->ndev
->flags
& IFF_ALLMULTI
)
1658 unreg_mcast_mask
= port_mask
;
1660 port_mask
= ALE_ALL_PORTS
;
1662 if (priv
->ndev
->flags
& IFF_ALLMULTI
)
1663 unreg_mcast_mask
= ALE_ALL_PORTS
;
1665 unreg_mcast_mask
= ALE_PORT_1
| ALE_PORT_2
;
1668 ret
= cpsw_ale_add_vlan(priv
->ale
, vid
, port_mask
, 0, port_mask
,
1673 ret
= cpsw_ale_add_ucast(priv
->ale
, priv
->mac_addr
,
1674 HOST_PORT_NUM
, ALE_VLAN
, vid
);
1678 ret
= cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1679 port_mask
, ALE_VLAN
, vid
, 0);
1681 goto clean_vlan_ucast
;
1685 cpsw_ale_del_ucast(priv
->ale
, priv
->mac_addr
,
1686 HOST_PORT_NUM
, ALE_VLAN
, vid
);
1688 cpsw_ale_del_vlan(priv
->ale
, vid
, 0);
1692 static int cpsw_ndo_vlan_rx_add_vid(struct net_device
*ndev
,
1693 __be16 proto
, u16 vid
)
1695 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1697 if (vid
== priv
->data
.default_vlan
)
1700 if (priv
->data
.dual_emac
) {
1701 /* In dual EMAC, reserved VLAN id should not be used for
1702 * creating VLAN interfaces as this can break the dual
1703 * EMAC port separation
1707 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
1708 if (vid
== priv
->slaves
[i
].port_vlan
)
1713 dev_info(priv
->dev
, "Adding vlanid %d to vlan filter\n", vid
);
1714 return cpsw_add_vlan_ale_entry(priv
, vid
);
1717 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device
*ndev
,
1718 __be16 proto
, u16 vid
)
1720 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1723 if (vid
== priv
->data
.default_vlan
)
1726 if (priv
->data
.dual_emac
) {
1729 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
1730 if (vid
== priv
->slaves
[i
].port_vlan
)
1735 dev_info(priv
->dev
, "removing vlanid %d from vlan filter\n", vid
);
1736 ret
= cpsw_ale_del_vlan(priv
->ale
, vid
, 0);
1740 ret
= cpsw_ale_del_ucast(priv
->ale
, priv
->mac_addr
,
1741 HOST_PORT_NUM
, ALE_VLAN
, vid
);
1745 return cpsw_ale_del_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1749 static const struct net_device_ops cpsw_netdev_ops
= {
1750 .ndo_open
= cpsw_ndo_open
,
1751 .ndo_stop
= cpsw_ndo_stop
,
1752 .ndo_start_xmit
= cpsw_ndo_start_xmit
,
1753 .ndo_set_mac_address
= cpsw_ndo_set_mac_address
,
1754 .ndo_do_ioctl
= cpsw_ndo_ioctl
,
1755 .ndo_validate_addr
= eth_validate_addr
,
1756 .ndo_change_mtu
= eth_change_mtu
,
1757 .ndo_tx_timeout
= cpsw_ndo_tx_timeout
,
1758 .ndo_set_rx_mode
= cpsw_ndo_set_rx_mode
,
1759 #ifdef CONFIG_NET_POLL_CONTROLLER
1760 .ndo_poll_controller
= cpsw_ndo_poll_controller
,
1762 .ndo_vlan_rx_add_vid
= cpsw_ndo_vlan_rx_add_vid
,
1763 .ndo_vlan_rx_kill_vid
= cpsw_ndo_vlan_rx_kill_vid
,
1766 static int cpsw_get_regs_len(struct net_device
*ndev
)
1768 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1770 return priv
->data
.ale_entries
* ALE_ENTRY_WORDS
* sizeof(u32
);
1773 static void cpsw_get_regs(struct net_device
*ndev
,
1774 struct ethtool_regs
*regs
, void *p
)
1776 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1779 /* update CPSW IP version */
1780 regs
->version
= priv
->version
;
1782 cpsw_ale_dump(priv
->ale
, reg
);
1785 static void cpsw_get_drvinfo(struct net_device
*ndev
,
1786 struct ethtool_drvinfo
*info
)
1788 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1790 strlcpy(info
->driver
, "cpsw", sizeof(info
->driver
));
1791 strlcpy(info
->version
, "1.0", sizeof(info
->version
));
1792 strlcpy(info
->bus_info
, priv
->pdev
->name
, sizeof(info
->bus_info
));
1795 static u32
cpsw_get_msglevel(struct net_device
*ndev
)
1797 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1798 return priv
->msg_enable
;
1801 static void cpsw_set_msglevel(struct net_device
*ndev
, u32 value
)
1803 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1804 priv
->msg_enable
= value
;
1807 static int cpsw_get_ts_info(struct net_device
*ndev
,
1808 struct ethtool_ts_info
*info
)
1810 #ifdef CONFIG_TI_CPTS
1811 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1813 info
->so_timestamping
=
1814 SOF_TIMESTAMPING_TX_HARDWARE
|
1815 SOF_TIMESTAMPING_TX_SOFTWARE
|
1816 SOF_TIMESTAMPING_RX_HARDWARE
|
1817 SOF_TIMESTAMPING_RX_SOFTWARE
|
1818 SOF_TIMESTAMPING_SOFTWARE
|
1819 SOF_TIMESTAMPING_RAW_HARDWARE
;
1820 info
->phc_index
= priv
->cpts
->phc_index
;
1822 (1 << HWTSTAMP_TX_OFF
) |
1823 (1 << HWTSTAMP_TX_ON
);
1825 (1 << HWTSTAMP_FILTER_NONE
) |
1826 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT
);
1828 info
->so_timestamping
=
1829 SOF_TIMESTAMPING_TX_SOFTWARE
|
1830 SOF_TIMESTAMPING_RX_SOFTWARE
|
1831 SOF_TIMESTAMPING_SOFTWARE
;
1832 info
->phc_index
= -1;
1834 info
->rx_filters
= 0;
1839 static int cpsw_get_settings(struct net_device
*ndev
,
1840 struct ethtool_cmd
*ecmd
)
1842 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1843 int slave_no
= cpsw_slave_index(priv
);
1845 if (priv
->slaves
[slave_no
].phy
)
1846 return phy_ethtool_gset(priv
->slaves
[slave_no
].phy
, ecmd
);
1851 static int cpsw_set_settings(struct net_device
*ndev
, struct ethtool_cmd
*ecmd
)
1853 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1854 int slave_no
= cpsw_slave_index(priv
);
1856 if (priv
->slaves
[slave_no
].phy
)
1857 return phy_ethtool_sset(priv
->slaves
[slave_no
].phy
, ecmd
);
1862 static void cpsw_get_wol(struct net_device
*ndev
, struct ethtool_wolinfo
*wol
)
1864 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1865 int slave_no
= cpsw_slave_index(priv
);
1870 if (priv
->slaves
[slave_no
].phy
)
1871 phy_ethtool_get_wol(priv
->slaves
[slave_no
].phy
, wol
);
1874 static int cpsw_set_wol(struct net_device
*ndev
, struct ethtool_wolinfo
*wol
)
1876 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1877 int slave_no
= cpsw_slave_index(priv
);
1879 if (priv
->slaves
[slave_no
].phy
)
1880 return phy_ethtool_set_wol(priv
->slaves
[slave_no
].phy
, wol
);
1885 static void cpsw_get_pauseparam(struct net_device
*ndev
,
1886 struct ethtool_pauseparam
*pause
)
1888 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1890 pause
->autoneg
= AUTONEG_DISABLE
;
1891 pause
->rx_pause
= priv
->rx_pause
? true : false;
1892 pause
->tx_pause
= priv
->tx_pause
? true : false;
1895 static int cpsw_set_pauseparam(struct net_device
*ndev
,
1896 struct ethtool_pauseparam
*pause
)
1898 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1901 priv
->rx_pause
= pause
->rx_pause
? true : false;
1902 priv
->tx_pause
= pause
->tx_pause
? true : false;
1904 for_each_slave(priv
, _cpsw_adjust_link
, priv
, &link
);
1909 static const struct ethtool_ops cpsw_ethtool_ops
= {
1910 .get_drvinfo
= cpsw_get_drvinfo
,
1911 .get_msglevel
= cpsw_get_msglevel
,
1912 .set_msglevel
= cpsw_set_msglevel
,
1913 .get_link
= ethtool_op_get_link
,
1914 .get_ts_info
= cpsw_get_ts_info
,
1915 .get_settings
= cpsw_get_settings
,
1916 .set_settings
= cpsw_set_settings
,
1917 .get_coalesce
= cpsw_get_coalesce
,
1918 .set_coalesce
= cpsw_set_coalesce
,
1919 .get_sset_count
= cpsw_get_sset_count
,
1920 .get_strings
= cpsw_get_strings
,
1921 .get_ethtool_stats
= cpsw_get_ethtool_stats
,
1922 .get_pauseparam
= cpsw_get_pauseparam
,
1923 .set_pauseparam
= cpsw_set_pauseparam
,
1924 .get_wol
= cpsw_get_wol
,
1925 .set_wol
= cpsw_set_wol
,
1926 .get_regs_len
= cpsw_get_regs_len
,
1927 .get_regs
= cpsw_get_regs
,
1930 static void cpsw_slave_init(struct cpsw_slave
*slave
, struct cpsw_priv
*priv
,
1931 u32 slave_reg_ofs
, u32 sliver_reg_ofs
)
1933 void __iomem
*regs
= priv
->regs
;
1934 int slave_num
= slave
->slave_num
;
1935 struct cpsw_slave_data
*data
= priv
->data
.slave_data
+ slave_num
;
1938 slave
->regs
= regs
+ slave_reg_ofs
;
1939 slave
->sliver
= regs
+ sliver_reg_ofs
;
1940 slave
->port_vlan
= data
->dual_emac_res_vlan
;
1943 static int cpsw_probe_dt(struct cpsw_platform_data
*data
,
1944 struct platform_device
*pdev
)
1946 struct device_node
*node
= pdev
->dev
.of_node
;
1947 struct device_node
*slave_node
;
1954 if (of_property_read_u32(node
, "slaves", &prop
)) {
1955 dev_err(&pdev
->dev
, "Missing slaves property in the DT.\n");
1958 data
->slaves
= prop
;
1960 if (of_property_read_u32(node
, "active_slave", &prop
)) {
1961 dev_err(&pdev
->dev
, "Missing active_slave property in the DT.\n");
1964 data
->active_slave
= prop
;
1966 if (of_property_read_u32(node
, "cpts_clock_mult", &prop
)) {
1967 dev_err(&pdev
->dev
, "Missing cpts_clock_mult property in the DT.\n");
1970 data
->cpts_clock_mult
= prop
;
1972 if (of_property_read_u32(node
, "cpts_clock_shift", &prop
)) {
1973 dev_err(&pdev
->dev
, "Missing cpts_clock_shift property in the DT.\n");
1976 data
->cpts_clock_shift
= prop
;
1978 data
->slave_data
= devm_kzalloc(&pdev
->dev
, data
->slaves
1979 * sizeof(struct cpsw_slave_data
),
1981 if (!data
->slave_data
)
1984 if (of_property_read_u32(node
, "cpdma_channels", &prop
)) {
1985 dev_err(&pdev
->dev
, "Missing cpdma_channels property in the DT.\n");
1988 data
->channels
= prop
;
1990 if (of_property_read_u32(node
, "ale_entries", &prop
)) {
1991 dev_err(&pdev
->dev
, "Missing ale_entries property in the DT.\n");
1994 data
->ale_entries
= prop
;
1996 if (of_property_read_u32(node
, "bd_ram_size", &prop
)) {
1997 dev_err(&pdev
->dev
, "Missing bd_ram_size property in the DT.\n");
2000 data
->bd_ram_size
= prop
;
2002 if (of_property_read_u32(node
, "rx_descs", &prop
)) {
2003 dev_err(&pdev
->dev
, "Missing rx_descs property in the DT.\n");
2006 data
->rx_descs
= prop
;
2008 if (of_property_read_u32(node
, "mac_control", &prop
)) {
2009 dev_err(&pdev
->dev
, "Missing mac_control property in the DT.\n");
2012 data
->mac_control
= prop
;
2014 if (of_property_read_bool(node
, "dual_emac"))
2015 data
->dual_emac
= 1;
2018 * Populate all the child nodes here...
2020 ret
= of_platform_populate(node
, NULL
, NULL
, &pdev
->dev
);
2021 /* We do not want to force this, as in some cases may not have child */
2023 dev_warn(&pdev
->dev
, "Doesn't have any child node\n");
2025 for_each_child_of_node(node
, slave_node
) {
2026 struct cpsw_slave_data
*slave_data
= data
->slave_data
+ i
;
2027 const void *mac_addr
= NULL
;
2031 /* This is no slave child node, continue */
2032 if (strcmp(slave_node
->name
, "slave"))
2035 slave_data
->phy_node
= of_parse_phandle(slave_node
,
2037 parp
= of_get_property(slave_node
, "phy_id", &lenp
);
2038 if (slave_data
->phy_node
) {
2040 "slave[%d] using phy-handle=\"%s\"\n",
2041 i
, slave_data
->phy_node
->full_name
);
2042 } else if (of_phy_is_fixed_link(slave_node
)) {
2043 /* In the case of a fixed PHY, the DT node associated
2044 * to the PHY is the Ethernet MAC DT node.
2046 ret
= of_phy_register_fixed_link(slave_node
);
2049 slave_data
->phy_node
= of_node_get(slave_node
);
2052 struct device_node
*mdio_node
;
2053 struct platform_device
*mdio
;
2055 if (lenp
!= (sizeof(__be32
) * 2)) {
2056 dev_err(&pdev
->dev
, "Invalid slave[%d] phy_id property\n", i
);
2059 mdio_node
= of_find_node_by_phandle(be32_to_cpup(parp
));
2060 phyid
= be32_to_cpup(parp
+1);
2061 mdio
= of_find_device_by_node(mdio_node
);
2062 of_node_put(mdio_node
);
2064 dev_err(&pdev
->dev
, "Missing mdio platform device\n");
2067 snprintf(slave_data
->phy_id
, sizeof(slave_data
->phy_id
),
2068 PHY_ID_FMT
, mdio
->name
, phyid
);
2071 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2075 slave_data
->phy_if
= of_get_phy_mode(slave_node
);
2076 if (slave_data
->phy_if
< 0) {
2077 dev_err(&pdev
->dev
, "Missing or malformed slave[%d] phy-mode property\n",
2079 return slave_data
->phy_if
;
2083 mac_addr
= of_get_mac_address(slave_node
);
2085 memcpy(slave_data
->mac_addr
, mac_addr
, ETH_ALEN
);
2087 ret
= ti_cm_get_macid(&pdev
->dev
, i
,
2088 slave_data
->mac_addr
);
2092 if (data
->dual_emac
) {
2093 if (of_property_read_u32(slave_node
, "dual_emac_res_vlan",
2095 dev_err(&pdev
->dev
, "Missing dual_emac_res_vlan in DT.\n");
2096 slave_data
->dual_emac_res_vlan
= i
+1;
2097 dev_err(&pdev
->dev
, "Using %d as Reserved VLAN for %d slave\n",
2098 slave_data
->dual_emac_res_vlan
, i
);
2100 slave_data
->dual_emac_res_vlan
= prop
;
2105 if (i
== data
->slaves
)
2112 static int cpsw_probe_dual_emac(struct platform_device
*pdev
,
2113 struct cpsw_priv
*priv
)
2115 struct cpsw_platform_data
*data
= &priv
->data
;
2116 struct net_device
*ndev
;
2117 struct cpsw_priv
*priv_sl2
;
2120 ndev
= alloc_etherdev(sizeof(struct cpsw_priv
));
2122 dev_err(&pdev
->dev
, "cpsw: error allocating net_device\n");
2126 priv_sl2
= netdev_priv(ndev
);
2127 spin_lock_init(&priv_sl2
->lock
);
2128 priv_sl2
->data
= *data
;
2129 priv_sl2
->pdev
= pdev
;
2130 priv_sl2
->ndev
= ndev
;
2131 priv_sl2
->dev
= &ndev
->dev
;
2132 priv_sl2
->msg_enable
= netif_msg_init(debug_level
, CPSW_DEBUG
);
2133 priv_sl2
->rx_packet_max
= max(rx_packet_max
, 128);
2135 if (is_valid_ether_addr(data
->slave_data
[1].mac_addr
)) {
2136 memcpy(priv_sl2
->mac_addr
, data
->slave_data
[1].mac_addr
,
2138 dev_info(&pdev
->dev
, "cpsw: Detected MACID = %pM\n", priv_sl2
->mac_addr
);
2140 random_ether_addr(priv_sl2
->mac_addr
);
2141 dev_info(&pdev
->dev
, "cpsw: Random MACID = %pM\n", priv_sl2
->mac_addr
);
2143 memcpy(ndev
->dev_addr
, priv_sl2
->mac_addr
, ETH_ALEN
);
2145 priv_sl2
->slaves
= priv
->slaves
;
2146 priv_sl2
->clk
= priv
->clk
;
2148 priv_sl2
->coal_intvl
= 0;
2149 priv_sl2
->bus_freq_mhz
= priv
->bus_freq_mhz
;
2151 priv_sl2
->regs
= priv
->regs
;
2152 priv_sl2
->host_port_regs
= priv
->host_port_regs
;
2153 priv_sl2
->wr_regs
= priv
->wr_regs
;
2154 priv_sl2
->hw_stats
= priv
->hw_stats
;
2155 priv_sl2
->dma
= priv
->dma
;
2156 priv_sl2
->txch
= priv
->txch
;
2157 priv_sl2
->rxch
= priv
->rxch
;
2158 priv_sl2
->ale
= priv
->ale
;
2159 priv_sl2
->emac_port
= 1;
2160 priv
->slaves
[1].ndev
= ndev
;
2161 priv_sl2
->cpts
= priv
->cpts
;
2162 priv_sl2
->version
= priv
->version
;
2164 for (i
= 0; i
< priv
->num_irqs
; i
++) {
2165 priv_sl2
->irqs_table
[i
] = priv
->irqs_table
[i
];
2166 priv_sl2
->num_irqs
= priv
->num_irqs
;
2168 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
2170 ndev
->netdev_ops
= &cpsw_netdev_ops
;
2171 ndev
->ethtool_ops
= &cpsw_ethtool_ops
;
2173 /* register the network device */
2174 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
2175 ret
= register_netdev(ndev
);
2177 dev_err(&pdev
->dev
, "cpsw: error registering net device\n");
2185 #define CPSW_QUIRK_IRQ BIT(0)
2187 static struct platform_device_id cpsw_devtype
[] = {
2189 /* keep it for existing comaptibles */
2191 .driver_data
= CPSW_QUIRK_IRQ
,
2193 .name
= "am335x-cpsw",
2194 .driver_data
= CPSW_QUIRK_IRQ
,
2196 .name
= "am4372-cpsw",
2199 .name
= "dra7-cpsw",
2205 MODULE_DEVICE_TABLE(platform
, cpsw_devtype
);
2214 static const struct of_device_id cpsw_of_mtable
[] = {
2215 { .compatible
= "ti,cpsw", .data
= &cpsw_devtype
[CPSW
], },
2216 { .compatible
= "ti,am335x-cpsw", .data
= &cpsw_devtype
[AM335X_CPSW
], },
2217 { .compatible
= "ti,am4372-cpsw", .data
= &cpsw_devtype
[AM4372_CPSW
], },
2218 { .compatible
= "ti,dra7-cpsw", .data
= &cpsw_devtype
[DRA7_CPSW
], },
2221 MODULE_DEVICE_TABLE(of
, cpsw_of_mtable
);
2223 static int cpsw_probe(struct platform_device
*pdev
)
2225 struct cpsw_platform_data
*data
;
2226 struct net_device
*ndev
;
2227 struct cpsw_priv
*priv
;
2228 struct cpdma_params dma_params
;
2229 struct cpsw_ale_params ale_params
;
2230 void __iomem
*ss_regs
;
2231 struct resource
*res
, *ss_res
;
2232 const struct of_device_id
*of_id
;
2233 struct gpio_descs
*mode
;
2234 u32 slave_offset
, sliver_offset
, slave_size
;
2238 ndev
= alloc_etherdev(sizeof(struct cpsw_priv
));
2240 dev_err(&pdev
->dev
, "error allocating net_device\n");
2244 platform_set_drvdata(pdev
, ndev
);
2245 priv
= netdev_priv(ndev
);
2246 spin_lock_init(&priv
->lock
);
2249 priv
->dev
= &ndev
->dev
;
2250 priv
->msg_enable
= netif_msg_init(debug_level
, CPSW_DEBUG
);
2251 priv
->rx_packet_max
= max(rx_packet_max
, 128);
2252 priv
->cpts
= devm_kzalloc(&pdev
->dev
, sizeof(struct cpts
), GFP_KERNEL
);
2254 dev_err(&pdev
->dev
, "error allocating cpts\n");
2256 goto clean_ndev_ret
;
2259 mode
= devm_gpiod_get_array_optional(&pdev
->dev
, "mode", GPIOD_OUT_LOW
);
2261 ret
= PTR_ERR(mode
);
2262 dev_err(&pdev
->dev
, "gpio request failed, ret %d\n", ret
);
2263 goto clean_ndev_ret
;
2267 * This may be required here for child devices.
2269 pm_runtime_enable(&pdev
->dev
);
2271 /* Select default pin state */
2272 pinctrl_pm_select_default_state(&pdev
->dev
);
2274 if (cpsw_probe_dt(&priv
->data
, pdev
)) {
2275 dev_err(&pdev
->dev
, "cpsw: platform data missing\n");
2277 goto clean_runtime_disable_ret
;
2281 if (is_valid_ether_addr(data
->slave_data
[0].mac_addr
)) {
2282 memcpy(priv
->mac_addr
, data
->slave_data
[0].mac_addr
, ETH_ALEN
);
2283 dev_info(&pdev
->dev
, "Detected MACID = %pM\n", priv
->mac_addr
);
2285 eth_random_addr(priv
->mac_addr
);
2286 dev_info(&pdev
->dev
, "Random MACID = %pM\n", priv
->mac_addr
);
2289 memcpy(ndev
->dev_addr
, priv
->mac_addr
, ETH_ALEN
);
2291 priv
->slaves
= devm_kzalloc(&pdev
->dev
,
2292 sizeof(struct cpsw_slave
) * data
->slaves
,
2294 if (!priv
->slaves
) {
2296 goto clean_runtime_disable_ret
;
2298 for (i
= 0; i
< data
->slaves
; i
++)
2299 priv
->slaves
[i
].slave_num
= i
;
2301 priv
->slaves
[0].ndev
= ndev
;
2302 priv
->emac_port
= 0;
2304 priv
->clk
= devm_clk_get(&pdev
->dev
, "fck");
2305 if (IS_ERR(priv
->clk
)) {
2306 dev_err(priv
->dev
, "fck is not found\n");
2308 goto clean_runtime_disable_ret
;
2310 priv
->coal_intvl
= 0;
2311 priv
->bus_freq_mhz
= clk_get_rate(priv
->clk
) / 1000000;
2313 ss_res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2314 ss_regs
= devm_ioremap_resource(&pdev
->dev
, ss_res
);
2315 if (IS_ERR(ss_regs
)) {
2316 ret
= PTR_ERR(ss_regs
);
2317 goto clean_runtime_disable_ret
;
2319 priv
->regs
= ss_regs
;
2321 /* Need to enable clocks with runtime PM api to access module
2324 pm_runtime_get_sync(&pdev
->dev
);
2325 priv
->version
= readl(&priv
->regs
->id_ver
);
2326 pm_runtime_put_sync(&pdev
->dev
);
2328 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
2329 priv
->wr_regs
= devm_ioremap_resource(&pdev
->dev
, res
);
2330 if (IS_ERR(priv
->wr_regs
)) {
2331 ret
= PTR_ERR(priv
->wr_regs
);
2332 goto clean_runtime_disable_ret
;
2335 memset(&dma_params
, 0, sizeof(dma_params
));
2336 memset(&ale_params
, 0, sizeof(ale_params
));
2338 switch (priv
->version
) {
2339 case CPSW_VERSION_1
:
2340 priv
->host_port_regs
= ss_regs
+ CPSW1_HOST_PORT_OFFSET
;
2341 priv
->cpts
->reg
= ss_regs
+ CPSW1_CPTS_OFFSET
;
2342 priv
->hw_stats
= ss_regs
+ CPSW1_HW_STATS
;
2343 dma_params
.dmaregs
= ss_regs
+ CPSW1_CPDMA_OFFSET
;
2344 dma_params
.txhdp
= ss_regs
+ CPSW1_STATERAM_OFFSET
;
2345 ale_params
.ale_regs
= ss_regs
+ CPSW1_ALE_OFFSET
;
2346 slave_offset
= CPSW1_SLAVE_OFFSET
;
2347 slave_size
= CPSW1_SLAVE_SIZE
;
2348 sliver_offset
= CPSW1_SLIVER_OFFSET
;
2349 dma_params
.desc_mem_phys
= 0;
2351 case CPSW_VERSION_2
:
2352 case CPSW_VERSION_3
:
2353 case CPSW_VERSION_4
:
2354 priv
->host_port_regs
= ss_regs
+ CPSW2_HOST_PORT_OFFSET
;
2355 priv
->cpts
->reg
= ss_regs
+ CPSW2_CPTS_OFFSET
;
2356 priv
->hw_stats
= ss_regs
+ CPSW2_HW_STATS
;
2357 dma_params
.dmaregs
= ss_regs
+ CPSW2_CPDMA_OFFSET
;
2358 dma_params
.txhdp
= ss_regs
+ CPSW2_STATERAM_OFFSET
;
2359 ale_params
.ale_regs
= ss_regs
+ CPSW2_ALE_OFFSET
;
2360 slave_offset
= CPSW2_SLAVE_OFFSET
;
2361 slave_size
= CPSW2_SLAVE_SIZE
;
2362 sliver_offset
= CPSW2_SLIVER_OFFSET
;
2363 dma_params
.desc_mem_phys
=
2364 (u32 __force
) ss_res
->start
+ CPSW2_BD_OFFSET
;
2367 dev_err(priv
->dev
, "unknown version 0x%08x\n", priv
->version
);
2369 goto clean_runtime_disable_ret
;
2371 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
2372 struct cpsw_slave
*slave
= &priv
->slaves
[i
];
2373 cpsw_slave_init(slave
, priv
, slave_offset
, sliver_offset
);
2374 slave_offset
+= slave_size
;
2375 sliver_offset
+= SLIVER_SIZE
;
2378 dma_params
.dev
= &pdev
->dev
;
2379 dma_params
.rxthresh
= dma_params
.dmaregs
+ CPDMA_RXTHRESH
;
2380 dma_params
.rxfree
= dma_params
.dmaregs
+ CPDMA_RXFREE
;
2381 dma_params
.rxhdp
= dma_params
.txhdp
+ CPDMA_RXHDP
;
2382 dma_params
.txcp
= dma_params
.txhdp
+ CPDMA_TXCP
;
2383 dma_params
.rxcp
= dma_params
.txhdp
+ CPDMA_RXCP
;
2385 dma_params
.num_chan
= data
->channels
;
2386 dma_params
.has_soft_reset
= true;
2387 dma_params
.min_packet_size
= CPSW_MIN_PACKET_SIZE
;
2388 dma_params
.desc_mem_size
= data
->bd_ram_size
;
2389 dma_params
.desc_align
= 16;
2390 dma_params
.has_ext_regs
= true;
2391 dma_params
.desc_hw_addr
= dma_params
.desc_mem_phys
;
2393 priv
->dma
= cpdma_ctlr_create(&dma_params
);
2395 dev_err(priv
->dev
, "error initializing dma\n");
2397 goto clean_runtime_disable_ret
;
2400 priv
->txch
= cpdma_chan_create(priv
->dma
, tx_chan_num(0),
2402 priv
->rxch
= cpdma_chan_create(priv
->dma
, rx_chan_num(0),
2405 if (WARN_ON(!priv
->txch
|| !priv
->rxch
)) {
2406 dev_err(priv
->dev
, "error initializing dma channels\n");
2411 ale_params
.dev
= &ndev
->dev
;
2412 ale_params
.ale_ageout
= ale_ageout
;
2413 ale_params
.ale_entries
= data
->ale_entries
;
2414 ale_params
.ale_ports
= data
->slaves
;
2416 priv
->ale
= cpsw_ale_create(&ale_params
);
2418 dev_err(priv
->dev
, "error initializing ale engine\n");
2423 ndev
->irq
= platform_get_irq(pdev
, 1);
2424 if (ndev
->irq
< 0) {
2425 dev_err(priv
->dev
, "error getting irq resource\n");
2430 of_id
= of_match_device(cpsw_of_mtable
, &pdev
->dev
);
2432 pdev
->id_entry
= of_id
->data
;
2433 if (pdev
->id_entry
->driver_data
)
2434 priv
->quirk_irq
= true;
2437 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2438 * MISC IRQs which are always kept disabled with this driver so
2439 * we will not request them.
2441 * If anyone wants to implement support for those, make sure to
2442 * first request and append them to irqs_table array.
2446 irq
= platform_get_irq(pdev
, 1);
2452 priv
->irqs_table
[0] = irq
;
2453 ret
= devm_request_irq(&pdev
->dev
, irq
, cpsw_rx_interrupt
,
2454 0, dev_name(&pdev
->dev
), priv
);
2456 dev_err(priv
->dev
, "error attaching irq (%d)\n", ret
);
2461 irq
= platform_get_irq(pdev
, 2);
2467 priv
->irqs_table
[1] = irq
;
2468 ret
= devm_request_irq(&pdev
->dev
, irq
, cpsw_tx_interrupt
,
2469 0, dev_name(&pdev
->dev
), priv
);
2471 dev_err(priv
->dev
, "error attaching irq (%d)\n", ret
);
2476 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
2478 ndev
->netdev_ops
= &cpsw_netdev_ops
;
2479 ndev
->ethtool_ops
= &cpsw_ethtool_ops
;
2480 netif_napi_add(ndev
, &priv
->napi_rx
, cpsw_rx_poll
, CPSW_POLL_WEIGHT
);
2481 netif_tx_napi_add(ndev
, &priv
->napi_tx
, cpsw_tx_poll
, CPSW_POLL_WEIGHT
);
2483 /* register the network device */
2484 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
2485 ret
= register_netdev(ndev
);
2487 dev_err(priv
->dev
, "error registering net device\n");
2492 cpsw_notice(priv
, probe
, "initialized device (regs %pa, irq %d)\n",
2493 &ss_res
->start
, ndev
->irq
);
2495 if (priv
->data
.dual_emac
) {
2496 ret
= cpsw_probe_dual_emac(pdev
, priv
);
2498 cpsw_err(priv
, probe
, "error probe slave 2 emac interface\n");
2506 cpsw_ale_destroy(priv
->ale
);
2508 cpdma_chan_destroy(priv
->txch
);
2509 cpdma_chan_destroy(priv
->rxch
);
2510 cpdma_ctlr_destroy(priv
->dma
);
2511 clean_runtime_disable_ret
:
2512 pm_runtime_disable(&pdev
->dev
);
2514 free_netdev(priv
->ndev
);
2518 static int cpsw_remove_child_device(struct device
*dev
, void *c
)
2520 struct platform_device
*pdev
= to_platform_device(dev
);
2522 of_device_unregister(pdev
);
2527 static int cpsw_remove(struct platform_device
*pdev
)
2529 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2530 struct cpsw_priv
*priv
= netdev_priv(ndev
);
2532 if (priv
->data
.dual_emac
)
2533 unregister_netdev(cpsw_get_slave_ndev(priv
, 1));
2534 unregister_netdev(ndev
);
2536 cpsw_ale_destroy(priv
->ale
);
2537 cpdma_chan_destroy(priv
->txch
);
2538 cpdma_chan_destroy(priv
->rxch
);
2539 cpdma_ctlr_destroy(priv
->dma
);
2540 pm_runtime_disable(&pdev
->dev
);
2541 device_for_each_child(&pdev
->dev
, NULL
, cpsw_remove_child_device
);
2542 if (priv
->data
.dual_emac
)
2543 free_netdev(cpsw_get_slave_ndev(priv
, 1));
2548 #ifdef CONFIG_PM_SLEEP
2549 static int cpsw_suspend(struct device
*dev
)
2551 struct platform_device
*pdev
= to_platform_device(dev
);
2552 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2553 struct cpsw_priv
*priv
= netdev_priv(ndev
);
2555 if (priv
->data
.dual_emac
) {
2558 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
2559 if (netif_running(priv
->slaves
[i
].ndev
))
2560 cpsw_ndo_stop(priv
->slaves
[i
].ndev
);
2561 soft_reset_slave(priv
->slaves
+ i
);
2564 if (netif_running(ndev
))
2565 cpsw_ndo_stop(ndev
);
2566 for_each_slave(priv
, soft_reset_slave
);
2569 pm_runtime_put_sync(&pdev
->dev
);
2571 /* Select sleep pin state */
2572 pinctrl_pm_select_sleep_state(&pdev
->dev
);
2577 static int cpsw_resume(struct device
*dev
)
2579 struct platform_device
*pdev
= to_platform_device(dev
);
2580 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2581 struct cpsw_priv
*priv
= netdev_priv(ndev
);
2583 pm_runtime_get_sync(&pdev
->dev
);
2585 /* Select default pin state */
2586 pinctrl_pm_select_default_state(&pdev
->dev
);
2588 if (priv
->data
.dual_emac
) {
2591 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
2592 if (netif_running(priv
->slaves
[i
].ndev
))
2593 cpsw_ndo_open(priv
->slaves
[i
].ndev
);
2596 if (netif_running(ndev
))
2597 cpsw_ndo_open(ndev
);
2603 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops
, cpsw_suspend
, cpsw_resume
);
2605 static struct platform_driver cpsw_driver
= {
2609 .of_match_table
= cpsw_of_mtable
,
2611 .probe
= cpsw_probe
,
2612 .remove
= cpsw_remove
,
2615 module_platform_driver(cpsw_driver
);
2617 MODULE_LICENSE("GPL");
2618 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2619 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2620 MODULE_DESCRIPTION("TI CPSW Ethernet driver");