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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / net / ethernet / ti / cpsw.c
1 /*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/of.h>
33 #include <linux/of_net.h>
34 #include <linux/of_device.h>
35 #include <linux/if_vlan.h>
36
37 #include <linux/pinctrl/consumer.h>
38
39 #include "cpsw.h"
40 #include "cpsw_ale.h"
41 #include "cpts.h"
42 #include "davinci_cpdma.h"
43
44 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
45 NETIF_MSG_DRV | NETIF_MSG_LINK | \
46 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
47 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
48 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
49 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
50 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
51 NETIF_MSG_RX_STATUS)
52
53 #define cpsw_info(priv, type, format, ...) \
54 do { \
55 if (netif_msg_##type(priv) && net_ratelimit()) \
56 dev_info(priv->dev, format, ## __VA_ARGS__); \
57 } while (0)
58
59 #define cpsw_err(priv, type, format, ...) \
60 do { \
61 if (netif_msg_##type(priv) && net_ratelimit()) \
62 dev_err(priv->dev, format, ## __VA_ARGS__); \
63 } while (0)
64
65 #define cpsw_dbg(priv, type, format, ...) \
66 do { \
67 if (netif_msg_##type(priv) && net_ratelimit()) \
68 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
69 } while (0)
70
71 #define cpsw_notice(priv, type, format, ...) \
72 do { \
73 if (netif_msg_##type(priv) && net_ratelimit()) \
74 dev_notice(priv->dev, format, ## __VA_ARGS__); \
75 } while (0)
76
77 #define ALE_ALL_PORTS 0x7
78
79 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
80 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
81 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
82
83 #define CPSW_VERSION_1 0x19010a
84 #define CPSW_VERSION_2 0x19010c
85 #define CPSW_VERSION_3 0x19010f
86 #define CPSW_VERSION_4 0x190112
87
88 #define HOST_PORT_NUM 0
89 #define SLIVER_SIZE 0x40
90
91 #define CPSW1_HOST_PORT_OFFSET 0x028
92 #define CPSW1_SLAVE_OFFSET 0x050
93 #define CPSW1_SLAVE_SIZE 0x040
94 #define CPSW1_CPDMA_OFFSET 0x100
95 #define CPSW1_STATERAM_OFFSET 0x200
96 #define CPSW1_HW_STATS 0x400
97 #define CPSW1_CPTS_OFFSET 0x500
98 #define CPSW1_ALE_OFFSET 0x600
99 #define CPSW1_SLIVER_OFFSET 0x700
100
101 #define CPSW2_HOST_PORT_OFFSET 0x108
102 #define CPSW2_SLAVE_OFFSET 0x200
103 #define CPSW2_SLAVE_SIZE 0x100
104 #define CPSW2_CPDMA_OFFSET 0x800
105 #define CPSW2_HW_STATS 0x900
106 #define CPSW2_STATERAM_OFFSET 0xa00
107 #define CPSW2_CPTS_OFFSET 0xc00
108 #define CPSW2_ALE_OFFSET 0xd00
109 #define CPSW2_SLIVER_OFFSET 0xd80
110 #define CPSW2_BD_OFFSET 0x2000
111
112 #define CPDMA_RXTHRESH 0x0c0
113 #define CPDMA_RXFREE 0x0e0
114 #define CPDMA_TXHDP 0x00
115 #define CPDMA_RXHDP 0x20
116 #define CPDMA_TXCP 0x40
117 #define CPDMA_RXCP 0x60
118
119 #define CPSW_POLL_WEIGHT 64
120 #define CPSW_MIN_PACKET_SIZE 60
121 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
122
123 #define RX_PRIORITY_MAPPING 0x76543210
124 #define TX_PRIORITY_MAPPING 0x33221100
125 #define CPDMA_TX_PRIORITY_MAP 0x76543210
126
127 #define CPSW_VLAN_AWARE BIT(1)
128 #define CPSW_ALE_VLAN_AWARE 1
129
130 #define CPSW_FIFO_NORMAL_MODE (0 << 15)
131 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15)
132 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15)
133
134 #define CPSW_INTPACEEN (0x3f << 16)
135 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
136 #define CPSW_CMINTMAX_CNT 63
137 #define CPSW_CMINTMIN_CNT 2
138 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
139 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
140
141 #define cpsw_enable_irq(priv) \
142 do { \
143 u32 i; \
144 for (i = 0; i < priv->num_irqs; i++) \
145 enable_irq(priv->irqs_table[i]); \
146 } while (0);
147 #define cpsw_disable_irq(priv) \
148 do { \
149 u32 i; \
150 for (i = 0; i < priv->num_irqs; i++) \
151 disable_irq_nosync(priv->irqs_table[i]); \
152 } while (0);
153
154 #define cpsw_slave_index(priv) \
155 ((priv->data.dual_emac) ? priv->emac_port : \
156 priv->data.active_slave)
157
158 static int debug_level;
159 module_param(debug_level, int, 0);
160 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
161
162 static int ale_ageout = 10;
163 module_param(ale_ageout, int, 0);
164 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
165
166 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
167 module_param(rx_packet_max, int, 0);
168 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
169
170 struct cpsw_wr_regs {
171 u32 id_ver;
172 u32 soft_reset;
173 u32 control;
174 u32 int_control;
175 u32 rx_thresh_en;
176 u32 rx_en;
177 u32 tx_en;
178 u32 misc_en;
179 u32 mem_allign1[8];
180 u32 rx_thresh_stat;
181 u32 rx_stat;
182 u32 tx_stat;
183 u32 misc_stat;
184 u32 mem_allign2[8];
185 u32 rx_imax;
186 u32 tx_imax;
187
188 };
189
190 struct cpsw_ss_regs {
191 u32 id_ver;
192 u32 control;
193 u32 soft_reset;
194 u32 stat_port_en;
195 u32 ptype;
196 u32 soft_idle;
197 u32 thru_rate;
198 u32 gap_thresh;
199 u32 tx_start_wds;
200 u32 flow_control;
201 u32 vlan_ltype;
202 u32 ts_ltype;
203 u32 dlr_ltype;
204 };
205
206 /* CPSW_PORT_V1 */
207 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
208 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
209 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
210 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
211 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
212 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
213 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
214 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
215
216 /* CPSW_PORT_V2 */
217 #define CPSW2_CONTROL 0x00 /* Control Register */
218 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
219 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
220 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
221 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
222 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
223 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
224
225 /* CPSW_PORT_V1 and V2 */
226 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
227 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
228 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
229
230 /* CPSW_PORT_V2 only */
231 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
232 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
233 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
234 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
235 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
236 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
237 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
238 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
239
240 /* Bit definitions for the CPSW2_CONTROL register */
241 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
242 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
243 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
244 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
245 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
246 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
247 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
248 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
249 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
250 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
251 #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */
252 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
253 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
254 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
255 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
256 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
257
258 #define CTRL_TS_BITS \
259 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
260 TS_ANNEX_D_EN | TS_LTYPE1_EN)
261
262 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
263 #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN)
264 #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN)
265
266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
269 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270 #define TS_MSG_TYPE_EN_MASK (0xffff)
271
272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
274
275 /* Bit definitions for the CPSW1_TS_CTL register */
276 #define CPSW_V1_TS_RX_EN BIT(0)
277 #define CPSW_V1_TS_TX_EN BIT(4)
278 #define CPSW_V1_MSG_TYPE_OFS 16
279
280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
282
283 struct cpsw_host_regs {
284 u32 max_blks;
285 u32 blk_cnt;
286 u32 tx_in_ctl;
287 u32 port_vlan;
288 u32 tx_pri_map;
289 u32 cpdma_tx_pri_map;
290 u32 cpdma_rx_chan_map;
291 };
292
293 struct cpsw_sliver_regs {
294 u32 id_ver;
295 u32 mac_control;
296 u32 mac_status;
297 u32 soft_reset;
298 u32 rx_maxlen;
299 u32 __reserved_0;
300 u32 rx_pause;
301 u32 tx_pause;
302 u32 __reserved_1;
303 u32 rx_pri_map;
304 };
305
306 struct cpsw_hw_stats {
307 u32 rxgoodframes;
308 u32 rxbroadcastframes;
309 u32 rxmulticastframes;
310 u32 rxpauseframes;
311 u32 rxcrcerrors;
312 u32 rxaligncodeerrors;
313 u32 rxoversizedframes;
314 u32 rxjabberframes;
315 u32 rxundersizedframes;
316 u32 rxfragments;
317 u32 __pad_0[2];
318 u32 rxoctets;
319 u32 txgoodframes;
320 u32 txbroadcastframes;
321 u32 txmulticastframes;
322 u32 txpauseframes;
323 u32 txdeferredframes;
324 u32 txcollisionframes;
325 u32 txsinglecollframes;
326 u32 txmultcollframes;
327 u32 txexcessivecollisions;
328 u32 txlatecollisions;
329 u32 txunderrun;
330 u32 txcarriersenseerrors;
331 u32 txoctets;
332 u32 octetframes64;
333 u32 octetframes65t127;
334 u32 octetframes128t255;
335 u32 octetframes256t511;
336 u32 octetframes512t1023;
337 u32 octetframes1024tup;
338 u32 netoctets;
339 u32 rxsofoverruns;
340 u32 rxmofoverruns;
341 u32 rxdmaoverruns;
342 };
343
344 struct cpsw_slave {
345 void __iomem *regs;
346 struct cpsw_sliver_regs __iomem *sliver;
347 int slave_num;
348 u32 mac_control;
349 struct cpsw_slave_data *data;
350 struct phy_device *phy;
351 struct net_device *ndev;
352 u32 port_vlan;
353 u32 open_stat;
354 };
355
356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
357 {
358 return __raw_readl(slave->regs + offset);
359 }
360
361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
362 {
363 __raw_writel(val, slave->regs + offset);
364 }
365
366 struct cpsw_priv {
367 spinlock_t lock;
368 struct platform_device *pdev;
369 struct net_device *ndev;
370 struct napi_struct napi;
371 struct device *dev;
372 struct cpsw_platform_data data;
373 struct cpsw_ss_regs __iomem *regs;
374 struct cpsw_wr_regs __iomem *wr_regs;
375 u8 __iomem *hw_stats;
376 struct cpsw_host_regs __iomem *host_port_regs;
377 u32 msg_enable;
378 u32 version;
379 u32 coal_intvl;
380 u32 bus_freq_mhz;
381 struct net_device_stats stats;
382 int rx_packet_max;
383 int host_port;
384 struct clk *clk;
385 u8 mac_addr[ETH_ALEN];
386 struct cpsw_slave *slaves;
387 struct cpdma_ctlr *dma;
388 struct cpdma_chan *txch, *rxch;
389 struct cpsw_ale *ale;
390 /* snapshot of IRQ numbers */
391 u32 irqs_table[4];
392 u32 num_irqs;
393 bool irq_enabled;
394 struct cpts *cpts;
395 u32 emac_port;
396 };
397
398 struct cpsw_stats {
399 char stat_string[ETH_GSTRING_LEN];
400 int type;
401 int sizeof_stat;
402 int stat_offset;
403 };
404
405 enum {
406 CPSW_STATS,
407 CPDMA_RX_STATS,
408 CPDMA_TX_STATS,
409 };
410
411 #define CPSW_STAT(m) CPSW_STATS, \
412 sizeof(((struct cpsw_hw_stats *)0)->m), \
413 offsetof(struct cpsw_hw_stats, m)
414 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
415 sizeof(((struct cpdma_chan_stats *)0)->m), \
416 offsetof(struct cpdma_chan_stats, m)
417 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
418 sizeof(((struct cpdma_chan_stats *)0)->m), \
419 offsetof(struct cpdma_chan_stats, m)
420
421 static const struct cpsw_stats cpsw_gstrings_stats[] = {
422 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
423 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
424 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
425 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
426 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
427 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
428 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
429 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
430 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
431 { "Rx Fragments", CPSW_STAT(rxfragments) },
432 { "Rx Octets", CPSW_STAT(rxoctets) },
433 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
434 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
435 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
436 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
437 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
438 { "Collisions", CPSW_STAT(txcollisionframes) },
439 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
440 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
441 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
442 { "Late Collisions", CPSW_STAT(txlatecollisions) },
443 { "Tx Underrun", CPSW_STAT(txunderrun) },
444 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
445 { "Tx Octets", CPSW_STAT(txoctets) },
446 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
447 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
448 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
449 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
450 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
451 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
452 { "Net Octets", CPSW_STAT(netoctets) },
453 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
454 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
455 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
456 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
457 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
458 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
459 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
460 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
461 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
462 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
463 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
464 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
465 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
466 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
467 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
468 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
469 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
470 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
471 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
472 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
473 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
474 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
475 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
476 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
477 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
478 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
479 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
480 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
481 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
482 };
483
484 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
485
486 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
487 #define for_each_slave(priv, func, arg...) \
488 do { \
489 struct cpsw_slave *slave; \
490 int n; \
491 if (priv->data.dual_emac) \
492 (func)((priv)->slaves + priv->emac_port, ##arg);\
493 else \
494 for (n = (priv)->data.slaves, \
495 slave = (priv)->slaves; \
496 n; n--) \
497 (func)(slave++, ##arg); \
498 } while (0)
499 #define cpsw_get_slave_ndev(priv, __slave_no__) \
500 (priv->slaves[__slave_no__].ndev)
501 #define cpsw_get_slave_priv(priv, __slave_no__) \
502 ((priv->slaves[__slave_no__].ndev) ? \
503 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
504
505 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
506 do { \
507 if (!priv->data.dual_emac) \
508 break; \
509 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
510 ndev = cpsw_get_slave_ndev(priv, 0); \
511 priv = netdev_priv(ndev); \
512 skb->dev = ndev; \
513 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
514 ndev = cpsw_get_slave_ndev(priv, 1); \
515 priv = netdev_priv(ndev); \
516 skb->dev = ndev; \
517 } \
518 } while (0)
519 #define cpsw_add_mcast(priv, addr) \
520 do { \
521 if (priv->data.dual_emac) { \
522 struct cpsw_slave *slave = priv->slaves + \
523 priv->emac_port; \
524 int slave_port = cpsw_get_slave_port(priv, \
525 slave->slave_num); \
526 cpsw_ale_add_mcast(priv->ale, addr, \
527 1 << slave_port | 1 << priv->host_port, \
528 ALE_VLAN, slave->port_vlan, 0); \
529 } else { \
530 cpsw_ale_add_mcast(priv->ale, addr, \
531 ALE_ALL_PORTS << priv->host_port, \
532 0, 0, 0); \
533 } \
534 } while (0)
535
536 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
537 {
538 if (priv->host_port == 0)
539 return slave_num + 1;
540 else
541 return slave_num;
542 }
543
544 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
545 {
546 struct cpsw_priv *priv = netdev_priv(ndev);
547
548 if (ndev->flags & IFF_PROMISC) {
549 /* Enable promiscuous mode */
550 dev_err(priv->dev, "Ignoring Promiscuous mode\n");
551 return;
552 }
553
554 /* Clear all mcast from ALE */
555 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
556
557 if (!netdev_mc_empty(ndev)) {
558 struct netdev_hw_addr *ha;
559
560 /* program multicast address list into ALE register */
561 netdev_for_each_mc_addr(ha, ndev) {
562 cpsw_add_mcast(priv, (u8 *)ha->addr);
563 }
564 }
565 }
566
567 static void cpsw_intr_enable(struct cpsw_priv *priv)
568 {
569 __raw_writel(0xFF, &priv->wr_regs->tx_en);
570 __raw_writel(0xFF, &priv->wr_regs->rx_en);
571
572 cpdma_ctlr_int_ctrl(priv->dma, true);
573 return;
574 }
575
576 static void cpsw_intr_disable(struct cpsw_priv *priv)
577 {
578 __raw_writel(0, &priv->wr_regs->tx_en);
579 __raw_writel(0, &priv->wr_regs->rx_en);
580
581 cpdma_ctlr_int_ctrl(priv->dma, false);
582 return;
583 }
584
585 static void cpsw_tx_handler(void *token, int len, int status)
586 {
587 struct sk_buff *skb = token;
588 struct net_device *ndev = skb->dev;
589 struct cpsw_priv *priv = netdev_priv(ndev);
590
591 /* Check whether the queue is stopped due to stalled tx dma, if the
592 * queue is stopped then start the queue as we have free desc for tx
593 */
594 if (unlikely(netif_queue_stopped(ndev)))
595 netif_wake_queue(ndev);
596 cpts_tx_timestamp(priv->cpts, skb);
597 priv->stats.tx_packets++;
598 priv->stats.tx_bytes += len;
599 dev_kfree_skb_any(skb);
600 }
601
602 static void cpsw_rx_handler(void *token, int len, int status)
603 {
604 struct sk_buff *skb = token;
605 struct sk_buff *new_skb;
606 struct net_device *ndev = skb->dev;
607 struct cpsw_priv *priv = netdev_priv(ndev);
608 int ret = 0;
609
610 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
611
612 if (unlikely(status < 0)) {
613 /* the interface is going down, skbs are purged */
614 dev_kfree_skb_any(skb);
615 return;
616 }
617
618 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
619 if (new_skb) {
620 skb_put(skb, len);
621 cpts_rx_timestamp(priv->cpts, skb);
622 skb->protocol = eth_type_trans(skb, ndev);
623 netif_receive_skb(skb);
624 priv->stats.rx_bytes += len;
625 priv->stats.rx_packets++;
626 } else {
627 priv->stats.rx_dropped++;
628 new_skb = skb;
629 }
630
631 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
632 skb_tailroom(new_skb), 0);
633 if (WARN_ON(ret < 0))
634 dev_kfree_skb_any(new_skb);
635 }
636
637 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
638 {
639 struct cpsw_priv *priv = dev_id;
640
641 cpsw_intr_disable(priv);
642 if (priv->irq_enabled == true) {
643 cpsw_disable_irq(priv);
644 priv->irq_enabled = false;
645 }
646
647 if (netif_running(priv->ndev)) {
648 napi_schedule(&priv->napi);
649 return IRQ_HANDLED;
650 }
651
652 priv = cpsw_get_slave_priv(priv, 1);
653 if (!priv)
654 return IRQ_NONE;
655
656 if (netif_running(priv->ndev)) {
657 napi_schedule(&priv->napi);
658 return IRQ_HANDLED;
659 }
660 return IRQ_NONE;
661 }
662
663 static int cpsw_poll(struct napi_struct *napi, int budget)
664 {
665 struct cpsw_priv *priv = napi_to_priv(napi);
666 int num_tx, num_rx;
667
668 num_tx = cpdma_chan_process(priv->txch, 128);
669 if (num_tx)
670 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
671
672 num_rx = cpdma_chan_process(priv->rxch, budget);
673 if (num_rx < budget) {
674 struct cpsw_priv *prim_cpsw;
675
676 napi_complete(napi);
677 cpsw_intr_enable(priv);
678 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
679 prim_cpsw = cpsw_get_slave_priv(priv, 0);
680 if (prim_cpsw->irq_enabled == false) {
681 prim_cpsw->irq_enabled = true;
682 cpsw_enable_irq(priv);
683 }
684 }
685
686 if (num_rx || num_tx)
687 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
688 num_rx, num_tx);
689
690 return num_rx;
691 }
692
693 static inline void soft_reset(const char *module, void __iomem *reg)
694 {
695 unsigned long timeout = jiffies + HZ;
696
697 __raw_writel(1, reg);
698 do {
699 cpu_relax();
700 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
701
702 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
703 }
704
705 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
706 ((mac)[2] << 16) | ((mac)[3] << 24))
707 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
708
709 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
710 struct cpsw_priv *priv)
711 {
712 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
713 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
714 }
715
716 static void _cpsw_adjust_link(struct cpsw_slave *slave,
717 struct cpsw_priv *priv, bool *link)
718 {
719 struct phy_device *phy = slave->phy;
720 u32 mac_control = 0;
721 u32 slave_port;
722
723 if (!phy)
724 return;
725
726 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
727
728 if (phy->link) {
729 mac_control = priv->data.mac_control;
730
731 /* enable forwarding */
732 cpsw_ale_control_set(priv->ale, slave_port,
733 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
734
735 if (phy->speed == 1000)
736 mac_control |= BIT(7); /* GIGABITEN */
737 if (phy->duplex)
738 mac_control |= BIT(0); /* FULLDUPLEXEN */
739
740 /* set speed_in input in case RMII mode is used in 100Mbps */
741 if (phy->speed == 100)
742 mac_control |= BIT(15);
743 else if (phy->speed == 10)
744 mac_control |= BIT(18); /* In Band mode */
745
746 *link = true;
747 } else {
748 mac_control = 0;
749 /* disable forwarding */
750 cpsw_ale_control_set(priv->ale, slave_port,
751 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
752 }
753
754 if (mac_control != slave->mac_control) {
755 phy_print_status(phy);
756 __raw_writel(mac_control, &slave->sliver->mac_control);
757 }
758
759 slave->mac_control = mac_control;
760 }
761
762 static void cpsw_adjust_link(struct net_device *ndev)
763 {
764 struct cpsw_priv *priv = netdev_priv(ndev);
765 bool link = false;
766
767 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
768
769 if (link) {
770 netif_carrier_on(ndev);
771 if (netif_running(ndev))
772 netif_wake_queue(ndev);
773 } else {
774 netif_carrier_off(ndev);
775 netif_stop_queue(ndev);
776 }
777 }
778
779 static int cpsw_get_coalesce(struct net_device *ndev,
780 struct ethtool_coalesce *coal)
781 {
782 struct cpsw_priv *priv = netdev_priv(ndev);
783
784 coal->rx_coalesce_usecs = priv->coal_intvl;
785 return 0;
786 }
787
788 static int cpsw_set_coalesce(struct net_device *ndev,
789 struct ethtool_coalesce *coal)
790 {
791 struct cpsw_priv *priv = netdev_priv(ndev);
792 u32 int_ctrl;
793 u32 num_interrupts = 0;
794 u32 prescale = 0;
795 u32 addnl_dvdr = 1;
796 u32 coal_intvl = 0;
797
798 if (!coal->rx_coalesce_usecs)
799 return -EINVAL;
800
801 coal_intvl = coal->rx_coalesce_usecs;
802
803 int_ctrl = readl(&priv->wr_regs->int_control);
804 prescale = priv->bus_freq_mhz * 4;
805
806 if (coal_intvl < CPSW_CMINTMIN_INTVL)
807 coal_intvl = CPSW_CMINTMIN_INTVL;
808
809 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
810 /* Interrupt pacer works with 4us Pulse, we can
811 * throttle further by dilating the 4us pulse.
812 */
813 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
814
815 if (addnl_dvdr > 1) {
816 prescale *= addnl_dvdr;
817 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
818 coal_intvl = (CPSW_CMINTMAX_INTVL
819 * addnl_dvdr);
820 } else {
821 addnl_dvdr = 1;
822 coal_intvl = CPSW_CMINTMAX_INTVL;
823 }
824 }
825
826 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
827 writel(num_interrupts, &priv->wr_regs->rx_imax);
828 writel(num_interrupts, &priv->wr_regs->tx_imax);
829
830 int_ctrl |= CPSW_INTPACEEN;
831 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
832 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
833 writel(int_ctrl, &priv->wr_regs->int_control);
834
835 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
836 if (priv->data.dual_emac) {
837 int i;
838
839 for (i = 0; i < priv->data.slaves; i++) {
840 priv = netdev_priv(priv->slaves[i].ndev);
841 priv->coal_intvl = coal_intvl;
842 }
843 } else {
844 priv->coal_intvl = coal_intvl;
845 }
846
847 return 0;
848 }
849
850 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
851 {
852 switch (sset) {
853 case ETH_SS_STATS:
854 return CPSW_STATS_LEN;
855 default:
856 return -EOPNOTSUPP;
857 }
858 }
859
860 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
861 {
862 u8 *p = data;
863 int i;
864
865 switch (stringset) {
866 case ETH_SS_STATS:
867 for (i = 0; i < CPSW_STATS_LEN; i++) {
868 memcpy(p, cpsw_gstrings_stats[i].stat_string,
869 ETH_GSTRING_LEN);
870 p += ETH_GSTRING_LEN;
871 }
872 break;
873 }
874 }
875
876 static void cpsw_get_ethtool_stats(struct net_device *ndev,
877 struct ethtool_stats *stats, u64 *data)
878 {
879 struct cpsw_priv *priv = netdev_priv(ndev);
880 struct cpdma_chan_stats rx_stats;
881 struct cpdma_chan_stats tx_stats;
882 u32 val;
883 u8 *p;
884 int i;
885
886 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
887 cpdma_chan_get_stats(priv->rxch, &rx_stats);
888 cpdma_chan_get_stats(priv->txch, &tx_stats);
889
890 for (i = 0; i < CPSW_STATS_LEN; i++) {
891 switch (cpsw_gstrings_stats[i].type) {
892 case CPSW_STATS:
893 val = readl(priv->hw_stats +
894 cpsw_gstrings_stats[i].stat_offset);
895 data[i] = val;
896 break;
897
898 case CPDMA_RX_STATS:
899 p = (u8 *)&rx_stats +
900 cpsw_gstrings_stats[i].stat_offset;
901 data[i] = *(u32 *)p;
902 break;
903
904 case CPDMA_TX_STATS:
905 p = (u8 *)&tx_stats +
906 cpsw_gstrings_stats[i].stat_offset;
907 data[i] = *(u32 *)p;
908 break;
909 }
910 }
911 }
912
913 static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
914 {
915 static char *leader = "........................................";
916
917 if (!val)
918 return 0;
919 else
920 return snprintf(buf, maxlen, "%s %s %10d\n", name,
921 leader + strlen(name), val);
922 }
923
924 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
925 {
926 u32 i;
927 u32 usage_count = 0;
928
929 if (!priv->data.dual_emac)
930 return 0;
931
932 for (i = 0; i < priv->data.slaves; i++)
933 if (priv->slaves[i].open_stat)
934 usage_count++;
935
936 return usage_count;
937 }
938
939 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
940 struct cpsw_priv *priv, struct sk_buff *skb)
941 {
942 if (!priv->data.dual_emac)
943 return cpdma_chan_submit(priv->txch, skb, skb->data,
944 skb->len, 0);
945
946 if (ndev == cpsw_get_slave_ndev(priv, 0))
947 return cpdma_chan_submit(priv->txch, skb, skb->data,
948 skb->len, 1);
949 else
950 return cpdma_chan_submit(priv->txch, skb, skb->data,
951 skb->len, 2);
952 }
953
954 static inline void cpsw_add_dual_emac_def_ale_entries(
955 struct cpsw_priv *priv, struct cpsw_slave *slave,
956 u32 slave_port)
957 {
958 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
959
960 if (priv->version == CPSW_VERSION_1)
961 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
962 else
963 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
964 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
965 port_mask, port_mask, 0);
966 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
967 port_mask, ALE_VLAN, slave->port_vlan, 0);
968 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
969 priv->host_port, ALE_VLAN, slave->port_vlan);
970 }
971
972 static void soft_reset_slave(struct cpsw_slave *slave)
973 {
974 char name[32];
975
976 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
977 soft_reset(name, &slave->sliver->soft_reset);
978 }
979
980 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
981 {
982 u32 slave_port;
983
984 soft_reset_slave(slave);
985
986 /* setup priority mapping */
987 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
988
989 switch (priv->version) {
990 case CPSW_VERSION_1:
991 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
992 break;
993 case CPSW_VERSION_2:
994 case CPSW_VERSION_3:
995 case CPSW_VERSION_4:
996 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
997 break;
998 }
999
1000 /* setup max packet size, and mac address */
1001 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1002 cpsw_set_slave_mac(slave, priv);
1003
1004 slave->mac_control = 0; /* no link yet */
1005
1006 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1007
1008 if (priv->data.dual_emac)
1009 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1010 else
1011 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1012 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1013
1014 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1015 &cpsw_adjust_link, slave->data->phy_if);
1016 if (IS_ERR(slave->phy)) {
1017 dev_err(priv->dev, "phy %s not found on slave %d\n",
1018 slave->data->phy_id, slave->slave_num);
1019 slave->phy = NULL;
1020 } else {
1021 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1022 slave->phy->phy_id);
1023 phy_start(slave->phy);
1024
1025 /* Configure GMII_SEL register */
1026 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1027 slave->slave_num);
1028 }
1029 }
1030
1031 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1032 {
1033 const int vlan = priv->data.default_vlan;
1034 const int port = priv->host_port;
1035 u32 reg;
1036 int i;
1037
1038 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1039 CPSW2_PORT_VLAN;
1040
1041 writel(vlan, &priv->host_port_regs->port_vlan);
1042
1043 for (i = 0; i < priv->data.slaves; i++)
1044 slave_write(priv->slaves + i, vlan, reg);
1045
1046 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1047 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1048 (ALE_PORT_1 | ALE_PORT_2) << port);
1049 }
1050
1051 static void cpsw_init_host_port(struct cpsw_priv *priv)
1052 {
1053 u32 control_reg;
1054 u32 fifo_mode;
1055
1056 /* soft reset the controller and initialize ale */
1057 soft_reset("cpsw", &priv->regs->soft_reset);
1058 cpsw_ale_start(priv->ale);
1059
1060 /* switch to vlan unaware mode */
1061 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1062 CPSW_ALE_VLAN_AWARE);
1063 control_reg = readl(&priv->regs->control);
1064 control_reg |= CPSW_VLAN_AWARE;
1065 writel(control_reg, &priv->regs->control);
1066 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1067 CPSW_FIFO_NORMAL_MODE;
1068 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1069
1070 /* setup host port priority mapping */
1071 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1072 &priv->host_port_regs->cpdma_tx_pri_map);
1073 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1074
1075 cpsw_ale_control_set(priv->ale, priv->host_port,
1076 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1077
1078 if (!priv->data.dual_emac) {
1079 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1080 0, 0);
1081 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1082 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1083 }
1084 }
1085
1086 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1087 {
1088 if (!slave->phy)
1089 return;
1090 phy_stop(slave->phy);
1091 phy_disconnect(slave->phy);
1092 slave->phy = NULL;
1093 }
1094
1095 static int cpsw_ndo_open(struct net_device *ndev)
1096 {
1097 struct cpsw_priv *priv = netdev_priv(ndev);
1098 struct cpsw_priv *prim_cpsw;
1099 int i, ret;
1100 u32 reg;
1101
1102 if (!cpsw_common_res_usage_state(priv))
1103 cpsw_intr_disable(priv);
1104 netif_carrier_off(ndev);
1105
1106 pm_runtime_get_sync(&priv->pdev->dev);
1107
1108 reg = priv->version;
1109
1110 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1111 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1112 CPSW_RTL_VERSION(reg));
1113
1114 /* initialize host and slave ports */
1115 if (!cpsw_common_res_usage_state(priv))
1116 cpsw_init_host_port(priv);
1117 for_each_slave(priv, cpsw_slave_open, priv);
1118
1119 /* Add default VLAN */
1120 if (!priv->data.dual_emac)
1121 cpsw_add_default_vlan(priv);
1122
1123 if (!cpsw_common_res_usage_state(priv)) {
1124 /* setup tx dma to fixed prio and zero offset */
1125 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1126 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1127
1128 /* disable priority elevation */
1129 __raw_writel(0, &priv->regs->ptype);
1130
1131 /* enable statistics collection only on all ports */
1132 __raw_writel(0x7, &priv->regs->stat_port_en);
1133
1134 if (WARN_ON(!priv->data.rx_descs))
1135 priv->data.rx_descs = 128;
1136
1137 for (i = 0; i < priv->data.rx_descs; i++) {
1138 struct sk_buff *skb;
1139
1140 ret = -ENOMEM;
1141 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1142 priv->rx_packet_max, GFP_KERNEL);
1143 if (!skb)
1144 goto err_cleanup;
1145 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1146 skb_tailroom(skb), 0);
1147 if (ret < 0) {
1148 kfree_skb(skb);
1149 goto err_cleanup;
1150 }
1151 }
1152 /* continue even if we didn't manage to submit all
1153 * receive descs
1154 */
1155 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1156
1157 if (cpts_register(&priv->pdev->dev, priv->cpts,
1158 priv->data.cpts_clock_mult,
1159 priv->data.cpts_clock_shift))
1160 dev_err(priv->dev, "error registering cpts device\n");
1161
1162 }
1163
1164 /* Enable Interrupt pacing if configured */
1165 if (priv->coal_intvl != 0) {
1166 struct ethtool_coalesce coal;
1167
1168 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1169 cpsw_set_coalesce(ndev, &coal);
1170 }
1171
1172 prim_cpsw = cpsw_get_slave_priv(priv, 0);
1173 if (prim_cpsw->irq_enabled == false) {
1174 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1175 prim_cpsw->irq_enabled = true;
1176 cpsw_enable_irq(prim_cpsw);
1177 }
1178 }
1179
1180 napi_enable(&priv->napi);
1181 cpdma_ctlr_start(priv->dma);
1182 cpsw_intr_enable(priv);
1183 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1184 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1185
1186 if (priv->data.dual_emac)
1187 priv->slaves[priv->emac_port].open_stat = true;
1188 return 0;
1189
1190 err_cleanup:
1191 cpdma_ctlr_stop(priv->dma);
1192 for_each_slave(priv, cpsw_slave_stop, priv);
1193 pm_runtime_put_sync(&priv->pdev->dev);
1194 netif_carrier_off(priv->ndev);
1195 return ret;
1196 }
1197
1198 static int cpsw_ndo_stop(struct net_device *ndev)
1199 {
1200 struct cpsw_priv *priv = netdev_priv(ndev);
1201
1202 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1203 netif_stop_queue(priv->ndev);
1204 napi_disable(&priv->napi);
1205 netif_carrier_off(priv->ndev);
1206
1207 if (cpsw_common_res_usage_state(priv) <= 1) {
1208 cpts_unregister(priv->cpts);
1209 cpsw_intr_disable(priv);
1210 cpdma_ctlr_int_ctrl(priv->dma, false);
1211 cpdma_ctlr_stop(priv->dma);
1212 cpsw_ale_stop(priv->ale);
1213 }
1214 for_each_slave(priv, cpsw_slave_stop, priv);
1215 pm_runtime_put_sync(&priv->pdev->dev);
1216 if (priv->data.dual_emac)
1217 priv->slaves[priv->emac_port].open_stat = false;
1218 return 0;
1219 }
1220
1221 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1222 struct net_device *ndev)
1223 {
1224 struct cpsw_priv *priv = netdev_priv(ndev);
1225 int ret;
1226
1227 ndev->trans_start = jiffies;
1228
1229 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1230 cpsw_err(priv, tx_err, "packet pad failed\n");
1231 priv->stats.tx_dropped++;
1232 return NETDEV_TX_OK;
1233 }
1234
1235 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1236 priv->cpts->tx_enable)
1237 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1238
1239 skb_tx_timestamp(skb);
1240
1241 ret = cpsw_tx_packet_submit(ndev, priv, skb);
1242 if (unlikely(ret != 0)) {
1243 cpsw_err(priv, tx_err, "desc submit failed\n");
1244 goto fail;
1245 }
1246
1247 /* If there is no more tx desc left free then we need to
1248 * tell the kernel to stop sending us tx frames.
1249 */
1250 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1251 netif_stop_queue(ndev);
1252
1253 return NETDEV_TX_OK;
1254 fail:
1255 priv->stats.tx_dropped++;
1256 netif_stop_queue(ndev);
1257 return NETDEV_TX_BUSY;
1258 }
1259
1260 static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
1261 {
1262 /*
1263 * The switch cannot operate in promiscuous mode without substantial
1264 * headache. For promiscuous mode to work, we would need to put the
1265 * ALE in bypass mode and route all traffic to the host port.
1266 * Subsequently, the host will need to operate as a "bridge", learn,
1267 * and flood as needed. For now, we simply complain here and
1268 * do nothing about it :-)
1269 */
1270 if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
1271 dev_err(&ndev->dev, "promiscuity ignored!\n");
1272
1273 /*
1274 * The switch cannot filter multicast traffic unless it is configured
1275 * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a
1276 * whole bunch of additional logic that this driver does not implement
1277 * at present.
1278 */
1279 if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
1280 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
1281 }
1282
1283 #ifdef CONFIG_TI_CPTS
1284
1285 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1286 {
1287 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1288 u32 ts_en, seq_id;
1289
1290 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1291 slave_write(slave, 0, CPSW1_TS_CTL);
1292 return;
1293 }
1294
1295 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1296 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1297
1298 if (priv->cpts->tx_enable)
1299 ts_en |= CPSW_V1_TS_TX_EN;
1300
1301 if (priv->cpts->rx_enable)
1302 ts_en |= CPSW_V1_TS_RX_EN;
1303
1304 slave_write(slave, ts_en, CPSW1_TS_CTL);
1305 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1306 }
1307
1308 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1309 {
1310 struct cpsw_slave *slave;
1311 u32 ctrl, mtype;
1312
1313 if (priv->data.dual_emac)
1314 slave = &priv->slaves[priv->emac_port];
1315 else
1316 slave = &priv->slaves[priv->data.active_slave];
1317
1318 ctrl = slave_read(slave, CPSW2_CONTROL);
1319 ctrl &= ~CTRL_ALL_TS_MASK;
1320
1321 if (priv->cpts->tx_enable)
1322 ctrl |= CTRL_TX_TS_BITS;
1323
1324 if (priv->cpts->rx_enable)
1325 ctrl |= CTRL_RX_TS_BITS;
1326
1327 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1328
1329 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1330 slave_write(slave, ctrl, CPSW2_CONTROL);
1331 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1332 }
1333
1334 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1335 {
1336 struct cpsw_priv *priv = netdev_priv(dev);
1337 struct cpts *cpts = priv->cpts;
1338 struct hwtstamp_config cfg;
1339
1340 if (priv->version != CPSW_VERSION_1 &&
1341 priv->version != CPSW_VERSION_2)
1342 return -EOPNOTSUPP;
1343
1344 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1345 return -EFAULT;
1346
1347 /* reserved for future extensions */
1348 if (cfg.flags)
1349 return -EINVAL;
1350
1351 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1352 return -ERANGE;
1353
1354 switch (cfg.rx_filter) {
1355 case HWTSTAMP_FILTER_NONE:
1356 cpts->rx_enable = 0;
1357 break;
1358 case HWTSTAMP_FILTER_ALL:
1359 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1360 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1361 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1362 return -ERANGE;
1363 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1364 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1365 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1366 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1367 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1368 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1369 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1370 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1371 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1372 cpts->rx_enable = 1;
1373 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1374 break;
1375 default:
1376 return -ERANGE;
1377 }
1378
1379 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1380
1381 switch (priv->version) {
1382 case CPSW_VERSION_1:
1383 cpsw_hwtstamp_v1(priv);
1384 break;
1385 case CPSW_VERSION_2:
1386 cpsw_hwtstamp_v2(priv);
1387 break;
1388 default:
1389 WARN_ON(1);
1390 }
1391
1392 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1393 }
1394
1395 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1396 {
1397 struct cpsw_priv *priv = netdev_priv(dev);
1398 struct cpts *cpts = priv->cpts;
1399 struct hwtstamp_config cfg;
1400
1401 if (priv->version != CPSW_VERSION_1 &&
1402 priv->version != CPSW_VERSION_2)
1403 return -EOPNOTSUPP;
1404
1405 cfg.flags = 0;
1406 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1407 cfg.rx_filter = (cpts->rx_enable ?
1408 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1409
1410 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1411 }
1412
1413 #endif /*CONFIG_TI_CPTS*/
1414
1415 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1416 {
1417 struct cpsw_priv *priv = netdev_priv(dev);
1418 struct mii_ioctl_data *data = if_mii(req);
1419 int slave_no = cpsw_slave_index(priv);
1420
1421 if (!netif_running(dev))
1422 return -EINVAL;
1423
1424 switch (cmd) {
1425 #ifdef CONFIG_TI_CPTS
1426 case SIOCSHWTSTAMP:
1427 return cpsw_hwtstamp_set(dev, req);
1428 case SIOCGHWTSTAMP:
1429 return cpsw_hwtstamp_get(dev, req);
1430 #endif
1431 case SIOCGMIIPHY:
1432 data->phy_id = priv->slaves[slave_no].phy->addr;
1433 break;
1434 default:
1435 return -ENOTSUPP;
1436 }
1437
1438 return 0;
1439 }
1440
1441 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1442 {
1443 struct cpsw_priv *priv = netdev_priv(ndev);
1444
1445 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1446 priv->stats.tx_errors++;
1447 cpsw_intr_disable(priv);
1448 cpdma_ctlr_int_ctrl(priv->dma, false);
1449 cpdma_chan_stop(priv->txch);
1450 cpdma_chan_start(priv->txch);
1451 cpdma_ctlr_int_ctrl(priv->dma, true);
1452 cpsw_intr_enable(priv);
1453 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1454 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1455
1456 }
1457
1458 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1459 {
1460 struct cpsw_priv *priv = netdev_priv(ndev);
1461 struct sockaddr *addr = (struct sockaddr *)p;
1462 int flags = 0;
1463 u16 vid = 0;
1464
1465 if (!is_valid_ether_addr(addr->sa_data))
1466 return -EADDRNOTAVAIL;
1467
1468 if (priv->data.dual_emac) {
1469 vid = priv->slaves[priv->emac_port].port_vlan;
1470 flags = ALE_VLAN;
1471 }
1472
1473 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1474 flags, vid);
1475 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1476 flags, vid);
1477
1478 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1479 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1480 for_each_slave(priv, cpsw_set_slave_mac, priv);
1481
1482 return 0;
1483 }
1484
1485 static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
1486 {
1487 struct cpsw_priv *priv = netdev_priv(ndev);
1488 return &priv->stats;
1489 }
1490
1491 #ifdef CONFIG_NET_POLL_CONTROLLER
1492 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1493 {
1494 struct cpsw_priv *priv = netdev_priv(ndev);
1495
1496 cpsw_intr_disable(priv);
1497 cpdma_ctlr_int_ctrl(priv->dma, false);
1498 cpsw_interrupt(ndev->irq, priv);
1499 cpdma_ctlr_int_ctrl(priv->dma, true);
1500 cpsw_intr_enable(priv);
1501 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1502 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1503
1504 }
1505 #endif
1506
1507 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1508 unsigned short vid)
1509 {
1510 int ret;
1511
1512 ret = cpsw_ale_add_vlan(priv->ale, vid,
1513 ALE_ALL_PORTS << priv->host_port,
1514 0, ALE_ALL_PORTS << priv->host_port,
1515 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
1516 if (ret != 0)
1517 return ret;
1518
1519 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1520 priv->host_port, ALE_VLAN, vid);
1521 if (ret != 0)
1522 goto clean_vid;
1523
1524 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1525 ALE_ALL_PORTS << priv->host_port,
1526 ALE_VLAN, vid, 0);
1527 if (ret != 0)
1528 goto clean_vlan_ucast;
1529 return 0;
1530
1531 clean_vlan_ucast:
1532 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1533 priv->host_port, ALE_VLAN, vid);
1534 clean_vid:
1535 cpsw_ale_del_vlan(priv->ale, vid, 0);
1536 return ret;
1537 }
1538
1539 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1540 __be16 proto, u16 vid)
1541 {
1542 struct cpsw_priv *priv = netdev_priv(ndev);
1543
1544 if (vid == priv->data.default_vlan)
1545 return 0;
1546
1547 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1548 return cpsw_add_vlan_ale_entry(priv, vid);
1549 }
1550
1551 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1552 __be16 proto, u16 vid)
1553 {
1554 struct cpsw_priv *priv = netdev_priv(ndev);
1555 int ret;
1556
1557 if (vid == priv->data.default_vlan)
1558 return 0;
1559
1560 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1561 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1562 if (ret != 0)
1563 return ret;
1564
1565 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1566 priv->host_port, ALE_VLAN, vid);
1567 if (ret != 0)
1568 return ret;
1569
1570 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1571 0, ALE_VLAN, vid);
1572 }
1573
1574 static const struct net_device_ops cpsw_netdev_ops = {
1575 .ndo_open = cpsw_ndo_open,
1576 .ndo_stop = cpsw_ndo_stop,
1577 .ndo_start_xmit = cpsw_ndo_start_xmit,
1578 .ndo_change_rx_flags = cpsw_ndo_change_rx_flags,
1579 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
1580 .ndo_do_ioctl = cpsw_ndo_ioctl,
1581 .ndo_validate_addr = eth_validate_addr,
1582 .ndo_change_mtu = eth_change_mtu,
1583 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
1584 .ndo_get_stats = cpsw_ndo_get_stats,
1585 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
1586 #ifdef CONFIG_NET_POLL_CONTROLLER
1587 .ndo_poll_controller = cpsw_ndo_poll_controller,
1588 #endif
1589 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1590 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
1591 };
1592
1593 static void cpsw_get_drvinfo(struct net_device *ndev,
1594 struct ethtool_drvinfo *info)
1595 {
1596 struct cpsw_priv *priv = netdev_priv(ndev);
1597
1598 strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver));
1599 strlcpy(info->version, "1.0", sizeof(info->version));
1600 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1601 }
1602
1603 static u32 cpsw_get_msglevel(struct net_device *ndev)
1604 {
1605 struct cpsw_priv *priv = netdev_priv(ndev);
1606 return priv->msg_enable;
1607 }
1608
1609 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1610 {
1611 struct cpsw_priv *priv = netdev_priv(ndev);
1612 priv->msg_enable = value;
1613 }
1614
1615 static int cpsw_get_ts_info(struct net_device *ndev,
1616 struct ethtool_ts_info *info)
1617 {
1618 #ifdef CONFIG_TI_CPTS
1619 struct cpsw_priv *priv = netdev_priv(ndev);
1620
1621 info->so_timestamping =
1622 SOF_TIMESTAMPING_TX_HARDWARE |
1623 SOF_TIMESTAMPING_TX_SOFTWARE |
1624 SOF_TIMESTAMPING_RX_HARDWARE |
1625 SOF_TIMESTAMPING_RX_SOFTWARE |
1626 SOF_TIMESTAMPING_SOFTWARE |
1627 SOF_TIMESTAMPING_RAW_HARDWARE;
1628 info->phc_index = priv->cpts->phc_index;
1629 info->tx_types =
1630 (1 << HWTSTAMP_TX_OFF) |
1631 (1 << HWTSTAMP_TX_ON);
1632 info->rx_filters =
1633 (1 << HWTSTAMP_FILTER_NONE) |
1634 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1635 #else
1636 info->so_timestamping =
1637 SOF_TIMESTAMPING_TX_SOFTWARE |
1638 SOF_TIMESTAMPING_RX_SOFTWARE |
1639 SOF_TIMESTAMPING_SOFTWARE;
1640 info->phc_index = -1;
1641 info->tx_types = 0;
1642 info->rx_filters = 0;
1643 #endif
1644 return 0;
1645 }
1646
1647 static int cpsw_get_settings(struct net_device *ndev,
1648 struct ethtool_cmd *ecmd)
1649 {
1650 struct cpsw_priv *priv = netdev_priv(ndev);
1651 int slave_no = cpsw_slave_index(priv);
1652
1653 if (priv->slaves[slave_no].phy)
1654 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1655 else
1656 return -EOPNOTSUPP;
1657 }
1658
1659 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1660 {
1661 struct cpsw_priv *priv = netdev_priv(ndev);
1662 int slave_no = cpsw_slave_index(priv);
1663
1664 if (priv->slaves[slave_no].phy)
1665 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1666 else
1667 return -EOPNOTSUPP;
1668 }
1669
1670 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1671 {
1672 struct cpsw_priv *priv = netdev_priv(ndev);
1673 int slave_no = cpsw_slave_index(priv);
1674
1675 wol->supported = 0;
1676 wol->wolopts = 0;
1677
1678 if (priv->slaves[slave_no].phy)
1679 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1680 }
1681
1682 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1683 {
1684 struct cpsw_priv *priv = netdev_priv(ndev);
1685 int slave_no = cpsw_slave_index(priv);
1686
1687 if (priv->slaves[slave_no].phy)
1688 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1689 else
1690 return -EOPNOTSUPP;
1691 }
1692
1693 static const struct ethtool_ops cpsw_ethtool_ops = {
1694 .get_drvinfo = cpsw_get_drvinfo,
1695 .get_msglevel = cpsw_get_msglevel,
1696 .set_msglevel = cpsw_set_msglevel,
1697 .get_link = ethtool_op_get_link,
1698 .get_ts_info = cpsw_get_ts_info,
1699 .get_settings = cpsw_get_settings,
1700 .set_settings = cpsw_set_settings,
1701 .get_coalesce = cpsw_get_coalesce,
1702 .set_coalesce = cpsw_set_coalesce,
1703 .get_sset_count = cpsw_get_sset_count,
1704 .get_strings = cpsw_get_strings,
1705 .get_ethtool_stats = cpsw_get_ethtool_stats,
1706 .get_wol = cpsw_get_wol,
1707 .set_wol = cpsw_set_wol,
1708 };
1709
1710 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1711 u32 slave_reg_ofs, u32 sliver_reg_ofs)
1712 {
1713 void __iomem *regs = priv->regs;
1714 int slave_num = slave->slave_num;
1715 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1716
1717 slave->data = data;
1718 slave->regs = regs + slave_reg_ofs;
1719 slave->sliver = regs + sliver_reg_ofs;
1720 slave->port_vlan = data->dual_emac_res_vlan;
1721 }
1722
1723 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1724 struct platform_device *pdev)
1725 {
1726 struct device_node *node = pdev->dev.of_node;
1727 struct device_node *slave_node;
1728 int i = 0, ret;
1729 u32 prop;
1730
1731 if (!node)
1732 return -EINVAL;
1733
1734 if (of_property_read_u32(node, "slaves", &prop)) {
1735 pr_err("Missing slaves property in the DT.\n");
1736 return -EINVAL;
1737 }
1738 data->slaves = prop;
1739
1740 if (of_property_read_u32(node, "active_slave", &prop)) {
1741 pr_err("Missing active_slave property in the DT.\n");
1742 return -EINVAL;
1743 }
1744 data->active_slave = prop;
1745
1746 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1747 pr_err("Missing cpts_clock_mult property in the DT.\n");
1748 return -EINVAL;
1749 }
1750 data->cpts_clock_mult = prop;
1751
1752 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1753 pr_err("Missing cpts_clock_shift property in the DT.\n");
1754 return -EINVAL;
1755 }
1756 data->cpts_clock_shift = prop;
1757
1758 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1759 * sizeof(struct cpsw_slave_data),
1760 GFP_KERNEL);
1761 if (!data->slave_data)
1762 return -ENOMEM;
1763
1764 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1765 pr_err("Missing cpdma_channels property in the DT.\n");
1766 return -EINVAL;
1767 }
1768 data->channels = prop;
1769
1770 if (of_property_read_u32(node, "ale_entries", &prop)) {
1771 pr_err("Missing ale_entries property in the DT.\n");
1772 return -EINVAL;
1773 }
1774 data->ale_entries = prop;
1775
1776 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1777 pr_err("Missing bd_ram_size property in the DT.\n");
1778 return -EINVAL;
1779 }
1780 data->bd_ram_size = prop;
1781
1782 if (of_property_read_u32(node, "rx_descs", &prop)) {
1783 pr_err("Missing rx_descs property in the DT.\n");
1784 return -EINVAL;
1785 }
1786 data->rx_descs = prop;
1787
1788 if (of_property_read_u32(node, "mac_control", &prop)) {
1789 pr_err("Missing mac_control property in the DT.\n");
1790 return -EINVAL;
1791 }
1792 data->mac_control = prop;
1793
1794 if (of_property_read_bool(node, "dual_emac"))
1795 data->dual_emac = 1;
1796
1797 /*
1798 * Populate all the child nodes here...
1799 */
1800 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1801 /* We do not want to force this, as in some cases may not have child */
1802 if (ret)
1803 pr_warn("Doesn't have any child node\n");
1804
1805 for_each_child_of_node(node, slave_node) {
1806 struct cpsw_slave_data *slave_data = data->slave_data + i;
1807 const void *mac_addr = NULL;
1808 u32 phyid;
1809 int lenp;
1810 const __be32 *parp;
1811 struct device_node *mdio_node;
1812 struct platform_device *mdio;
1813
1814 /* This is no slave child node, continue */
1815 if (strcmp(slave_node->name, "slave"))
1816 continue;
1817
1818 parp = of_get_property(slave_node, "phy_id", &lenp);
1819 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
1820 pr_err("Missing slave[%d] phy_id property\n", i);
1821 return -EINVAL;
1822 }
1823 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1824 phyid = be32_to_cpup(parp+1);
1825 mdio = of_find_device_by_node(mdio_node);
1826 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1827 PHY_ID_FMT, mdio->name, phyid);
1828
1829 mac_addr = of_get_mac_address(slave_node);
1830 if (mac_addr)
1831 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1832
1833 slave_data->phy_if = of_get_phy_mode(slave_node);
1834
1835 if (data->dual_emac) {
1836 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
1837 &prop)) {
1838 pr_err("Missing dual_emac_res_vlan in DT.\n");
1839 slave_data->dual_emac_res_vlan = i+1;
1840 pr_err("Using %d as Reserved VLAN for %d slave\n",
1841 slave_data->dual_emac_res_vlan, i);
1842 } else {
1843 slave_data->dual_emac_res_vlan = prop;
1844 }
1845 }
1846
1847 i++;
1848 if (i == data->slaves)
1849 break;
1850 }
1851
1852 return 0;
1853 }
1854
1855 static int cpsw_probe_dual_emac(struct platform_device *pdev,
1856 struct cpsw_priv *priv)
1857 {
1858 struct cpsw_platform_data *data = &priv->data;
1859 struct net_device *ndev;
1860 struct cpsw_priv *priv_sl2;
1861 int ret = 0, i;
1862
1863 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1864 if (!ndev) {
1865 pr_err("cpsw: error allocating net_device\n");
1866 return -ENOMEM;
1867 }
1868
1869 priv_sl2 = netdev_priv(ndev);
1870 spin_lock_init(&priv_sl2->lock);
1871 priv_sl2->data = *data;
1872 priv_sl2->pdev = pdev;
1873 priv_sl2->ndev = ndev;
1874 priv_sl2->dev = &ndev->dev;
1875 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1876 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
1877
1878 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
1879 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
1880 ETH_ALEN);
1881 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
1882 } else {
1883 random_ether_addr(priv_sl2->mac_addr);
1884 pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
1885 }
1886 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
1887
1888 priv_sl2->slaves = priv->slaves;
1889 priv_sl2->clk = priv->clk;
1890
1891 priv_sl2->coal_intvl = 0;
1892 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
1893
1894 priv_sl2->regs = priv->regs;
1895 priv_sl2->host_port = priv->host_port;
1896 priv_sl2->host_port_regs = priv->host_port_regs;
1897 priv_sl2->wr_regs = priv->wr_regs;
1898 priv_sl2->hw_stats = priv->hw_stats;
1899 priv_sl2->dma = priv->dma;
1900 priv_sl2->txch = priv->txch;
1901 priv_sl2->rxch = priv->rxch;
1902 priv_sl2->ale = priv->ale;
1903 priv_sl2->emac_port = 1;
1904 priv->slaves[1].ndev = ndev;
1905 priv_sl2->cpts = priv->cpts;
1906 priv_sl2->version = priv->version;
1907
1908 for (i = 0; i < priv->num_irqs; i++) {
1909 priv_sl2->irqs_table[i] = priv->irqs_table[i];
1910 priv_sl2->num_irqs = priv->num_irqs;
1911 }
1912 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1913
1914 ndev->netdev_ops = &cpsw_netdev_ops;
1915 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1916 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1917
1918 /* register the network device */
1919 SET_NETDEV_DEV(ndev, &pdev->dev);
1920 ret = register_netdev(ndev);
1921 if (ret) {
1922 pr_err("cpsw: error registering net device\n");
1923 free_netdev(ndev);
1924 ret = -ENODEV;
1925 }
1926
1927 return ret;
1928 }
1929
1930 static int cpsw_probe(struct platform_device *pdev)
1931 {
1932 struct cpsw_platform_data *data;
1933 struct net_device *ndev;
1934 struct cpsw_priv *priv;
1935 struct cpdma_params dma_params;
1936 struct cpsw_ale_params ale_params;
1937 void __iomem *ss_regs;
1938 struct resource *res, *ss_res;
1939 u32 slave_offset, sliver_offset, slave_size;
1940 int ret = 0, i, k = 0;
1941
1942 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1943 if (!ndev) {
1944 pr_err("error allocating net_device\n");
1945 return -ENOMEM;
1946 }
1947
1948 platform_set_drvdata(pdev, ndev);
1949 priv = netdev_priv(ndev);
1950 spin_lock_init(&priv->lock);
1951 priv->pdev = pdev;
1952 priv->ndev = ndev;
1953 priv->dev = &ndev->dev;
1954 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1955 priv->rx_packet_max = max(rx_packet_max, 128);
1956 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
1957 priv->irq_enabled = true;
1958 if (!priv->cpts) {
1959 pr_err("error allocating cpts\n");
1960 goto clean_ndev_ret;
1961 }
1962
1963 /*
1964 * This may be required here for child devices.
1965 */
1966 pm_runtime_enable(&pdev->dev);
1967
1968 /* Select default pin state */
1969 pinctrl_pm_select_default_state(&pdev->dev);
1970
1971 if (cpsw_probe_dt(&priv->data, pdev)) {
1972 pr_err("cpsw: platform data missing\n");
1973 ret = -ENODEV;
1974 goto clean_runtime_disable_ret;
1975 }
1976 data = &priv->data;
1977
1978 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
1979 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
1980 pr_info("Detected MACID = %pM\n", priv->mac_addr);
1981 } else {
1982 eth_random_addr(priv->mac_addr);
1983 pr_info("Random MACID = %pM\n", priv->mac_addr);
1984 }
1985
1986 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1987
1988 priv->slaves = devm_kzalloc(&pdev->dev,
1989 sizeof(struct cpsw_slave) * data->slaves,
1990 GFP_KERNEL);
1991 if (!priv->slaves) {
1992 ret = -ENOMEM;
1993 goto clean_runtime_disable_ret;
1994 }
1995 for (i = 0; i < data->slaves; i++)
1996 priv->slaves[i].slave_num = i;
1997
1998 priv->slaves[0].ndev = ndev;
1999 priv->emac_port = 0;
2000
2001 priv->clk = devm_clk_get(&pdev->dev, "fck");
2002 if (IS_ERR(priv->clk)) {
2003 dev_err(priv->dev, "fck is not found\n");
2004 ret = -ENODEV;
2005 goto clean_runtime_disable_ret;
2006 }
2007 priv->coal_intvl = 0;
2008 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2009
2010 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2011 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2012 if (IS_ERR(ss_regs)) {
2013 ret = PTR_ERR(ss_regs);
2014 goto clean_runtime_disable_ret;
2015 }
2016 priv->regs = ss_regs;
2017 priv->host_port = HOST_PORT_NUM;
2018
2019 /* Need to enable clocks with runtime PM api to access module
2020 * registers
2021 */
2022 pm_runtime_get_sync(&pdev->dev);
2023 priv->version = readl(&priv->regs->id_ver);
2024 pm_runtime_put_sync(&pdev->dev);
2025
2026 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2027 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2028 if (IS_ERR(priv->wr_regs)) {
2029 ret = PTR_ERR(priv->wr_regs);
2030 goto clean_runtime_disable_ret;
2031 }
2032
2033 memset(&dma_params, 0, sizeof(dma_params));
2034 memset(&ale_params, 0, sizeof(ale_params));
2035
2036 switch (priv->version) {
2037 case CPSW_VERSION_1:
2038 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2039 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2040 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
2041 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2042 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2043 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2044 slave_offset = CPSW1_SLAVE_OFFSET;
2045 slave_size = CPSW1_SLAVE_SIZE;
2046 sliver_offset = CPSW1_SLIVER_OFFSET;
2047 dma_params.desc_mem_phys = 0;
2048 break;
2049 case CPSW_VERSION_2:
2050 case CPSW_VERSION_3:
2051 case CPSW_VERSION_4:
2052 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2053 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2054 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
2055 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2056 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2057 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2058 slave_offset = CPSW2_SLAVE_OFFSET;
2059 slave_size = CPSW2_SLAVE_SIZE;
2060 sliver_offset = CPSW2_SLIVER_OFFSET;
2061 dma_params.desc_mem_phys =
2062 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2063 break;
2064 default:
2065 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2066 ret = -ENODEV;
2067 goto clean_runtime_disable_ret;
2068 }
2069 for (i = 0; i < priv->data.slaves; i++) {
2070 struct cpsw_slave *slave = &priv->slaves[i];
2071 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2072 slave_offset += slave_size;
2073 sliver_offset += SLIVER_SIZE;
2074 }
2075
2076 dma_params.dev = &pdev->dev;
2077 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2078 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2079 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2080 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2081 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
2082
2083 dma_params.num_chan = data->channels;
2084 dma_params.has_soft_reset = true;
2085 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2086 dma_params.desc_mem_size = data->bd_ram_size;
2087 dma_params.desc_align = 16;
2088 dma_params.has_ext_regs = true;
2089 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
2090
2091 priv->dma = cpdma_ctlr_create(&dma_params);
2092 if (!priv->dma) {
2093 dev_err(priv->dev, "error initializing dma\n");
2094 ret = -ENOMEM;
2095 goto clean_runtime_disable_ret;
2096 }
2097
2098 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2099 cpsw_tx_handler);
2100 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2101 cpsw_rx_handler);
2102
2103 if (WARN_ON(!priv->txch || !priv->rxch)) {
2104 dev_err(priv->dev, "error initializing dma channels\n");
2105 ret = -ENOMEM;
2106 goto clean_dma_ret;
2107 }
2108
2109 ale_params.dev = &ndev->dev;
2110 ale_params.ale_ageout = ale_ageout;
2111 ale_params.ale_entries = data->ale_entries;
2112 ale_params.ale_ports = data->slaves;
2113
2114 priv->ale = cpsw_ale_create(&ale_params);
2115 if (!priv->ale) {
2116 dev_err(priv->dev, "error initializing ale engine\n");
2117 ret = -ENODEV;
2118 goto clean_dma_ret;
2119 }
2120
2121 ndev->irq = platform_get_irq(pdev, 0);
2122 if (ndev->irq < 0) {
2123 dev_err(priv->dev, "error getting irq resource\n");
2124 ret = -ENOENT;
2125 goto clean_ale_ret;
2126 }
2127
2128 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2129 for (i = res->start; i <= res->end; i++) {
2130 if (devm_request_irq(&pdev->dev, i, cpsw_interrupt, 0,
2131 dev_name(&pdev->dev), priv)) {
2132 dev_err(priv->dev, "error attaching irq\n");
2133 goto clean_ale_ret;
2134 }
2135 priv->irqs_table[k] = i;
2136 priv->num_irqs = k + 1;
2137 }
2138 k++;
2139 }
2140
2141 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2142
2143 ndev->netdev_ops = &cpsw_netdev_ops;
2144 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
2145 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2146
2147 /* register the network device */
2148 SET_NETDEV_DEV(ndev, &pdev->dev);
2149 ret = register_netdev(ndev);
2150 if (ret) {
2151 dev_err(priv->dev, "error registering net device\n");
2152 ret = -ENODEV;
2153 goto clean_ale_ret;
2154 }
2155
2156 if (cpts_register(&pdev->dev, priv->cpts,
2157 data->cpts_clock_mult, data->cpts_clock_shift))
2158 dev_err(priv->dev, "error registering cpts device\n");
2159
2160 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2161 &ss_res->start, ndev->irq);
2162
2163 if (priv->data.dual_emac) {
2164 ret = cpsw_probe_dual_emac(pdev, priv);
2165 if (ret) {
2166 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2167 goto clean_ale_ret;
2168 }
2169 }
2170
2171 return 0;
2172
2173 clean_ale_ret:
2174 cpsw_ale_destroy(priv->ale);
2175 clean_dma_ret:
2176 cpdma_chan_destroy(priv->txch);
2177 cpdma_chan_destroy(priv->rxch);
2178 cpdma_ctlr_destroy(priv->dma);
2179 clean_runtime_disable_ret:
2180 pm_runtime_disable(&pdev->dev);
2181 clean_ndev_ret:
2182 free_netdev(priv->ndev);
2183 return ret;
2184 }
2185
2186 static int cpsw_remove(struct platform_device *pdev)
2187 {
2188 struct net_device *ndev = platform_get_drvdata(pdev);
2189 struct cpsw_priv *priv = netdev_priv(ndev);
2190
2191 if (priv->data.dual_emac)
2192 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2193 unregister_netdev(ndev);
2194
2195 cpsw_ale_destroy(priv->ale);
2196 cpdma_chan_destroy(priv->txch);
2197 cpdma_chan_destroy(priv->rxch);
2198 cpdma_ctlr_destroy(priv->dma);
2199 pm_runtime_disable(&pdev->dev);
2200 if (priv->data.dual_emac)
2201 free_netdev(cpsw_get_slave_ndev(priv, 1));
2202 free_netdev(ndev);
2203 return 0;
2204 }
2205
2206 static int cpsw_suspend(struct device *dev)
2207 {
2208 struct platform_device *pdev = to_platform_device(dev);
2209 struct net_device *ndev = platform_get_drvdata(pdev);
2210 struct cpsw_priv *priv = netdev_priv(ndev);
2211
2212 if (netif_running(ndev))
2213 cpsw_ndo_stop(ndev);
2214
2215 for_each_slave(priv, soft_reset_slave);
2216
2217 pm_runtime_put_sync(&pdev->dev);
2218
2219 /* Select sleep pin state */
2220 pinctrl_pm_select_sleep_state(&pdev->dev);
2221
2222 return 0;
2223 }
2224
2225 static int cpsw_resume(struct device *dev)
2226 {
2227 struct platform_device *pdev = to_platform_device(dev);
2228 struct net_device *ndev = platform_get_drvdata(pdev);
2229
2230 pm_runtime_get_sync(&pdev->dev);
2231
2232 /* Select default pin state */
2233 pinctrl_pm_select_default_state(&pdev->dev);
2234
2235 if (netif_running(ndev))
2236 cpsw_ndo_open(ndev);
2237 return 0;
2238 }
2239
2240 static const struct dev_pm_ops cpsw_pm_ops = {
2241 .suspend = cpsw_suspend,
2242 .resume = cpsw_resume,
2243 };
2244
2245 static const struct of_device_id cpsw_of_mtable[] = {
2246 { .compatible = "ti,cpsw", },
2247 { /* sentinel */ },
2248 };
2249 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2250
2251 static struct platform_driver cpsw_driver = {
2252 .driver = {
2253 .name = "cpsw",
2254 .owner = THIS_MODULE,
2255 .pm = &cpsw_pm_ops,
2256 .of_match_table = cpsw_of_mtable,
2257 },
2258 .probe = cpsw_probe,
2259 .remove = cpsw_remove,
2260 };
2261
2262 static int __init cpsw_init(void)
2263 {
2264 return platform_driver_register(&cpsw_driver);
2265 }
2266 late_initcall(cpsw_init);
2267
2268 static void __exit cpsw_exit(void)
2269 {
2270 platform_driver_unregister(&cpsw_driver);
2271 }
2272 module_exit(cpsw_exit);
2273
2274 MODULE_LICENSE("GPL");
2275 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2276 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2277 MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux kernel - Deliverables
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