projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
net/cpsw: don't rely only on netif_running() to check which device is active
[deliverable/linux.git] / drivers / net / ethernet / ti / cpsw.c
1 /*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/of.h>
33 #include <linux/of_net.h>
34 #include <linux/of_device.h>
35 #include <linux/if_vlan.h>
36
37 #include <linux/platform_data/cpsw.h>
38
39 #include "cpsw_ale.h"
40 #include "cpts.h"
41 #include "davinci_cpdma.h"
42
43 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
44 NETIF_MSG_DRV | NETIF_MSG_LINK | \
45 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
46 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
47 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
48 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
49 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
50 NETIF_MSG_RX_STATUS)
51
52 #define cpsw_info(priv, type, format, ...) \
53 do { \
54 if (netif_msg_##type(priv) && net_ratelimit()) \
55 dev_info(priv->dev, format, ## __VA_ARGS__); \
56 } while (0)
57
58 #define cpsw_err(priv, type, format, ...) \
59 do { \
60 if (netif_msg_##type(priv) && net_ratelimit()) \
61 dev_err(priv->dev, format, ## __VA_ARGS__); \
62 } while (0)
63
64 #define cpsw_dbg(priv, type, format, ...) \
65 do { \
66 if (netif_msg_##type(priv) && net_ratelimit()) \
67 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
68 } while (0)
69
70 #define cpsw_notice(priv, type, format, ...) \
71 do { \
72 if (netif_msg_##type(priv) && net_ratelimit()) \
73 dev_notice(priv->dev, format, ## __VA_ARGS__); \
74 } while (0)
75
76 #define ALE_ALL_PORTS 0x7
77
78 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
79 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
80 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
81
82 #define CPSW_VERSION_1 0x19010a
83 #define CPSW_VERSION_2 0x19010c
84
85 #define HOST_PORT_NUM 0
86 #define SLIVER_SIZE 0x40
87
88 #define CPSW1_HOST_PORT_OFFSET 0x028
89 #define CPSW1_SLAVE_OFFSET 0x050
90 #define CPSW1_SLAVE_SIZE 0x040
91 #define CPSW1_CPDMA_OFFSET 0x100
92 #define CPSW1_STATERAM_OFFSET 0x200
93 #define CPSW1_CPTS_OFFSET 0x500
94 #define CPSW1_ALE_OFFSET 0x600
95 #define CPSW1_SLIVER_OFFSET 0x700
96
97 #define CPSW2_HOST_PORT_OFFSET 0x108
98 #define CPSW2_SLAVE_OFFSET 0x200
99 #define CPSW2_SLAVE_SIZE 0x100
100 #define CPSW2_CPDMA_OFFSET 0x800
101 #define CPSW2_STATERAM_OFFSET 0xa00
102 #define CPSW2_CPTS_OFFSET 0xc00
103 #define CPSW2_ALE_OFFSET 0xd00
104 #define CPSW2_SLIVER_OFFSET 0xd80
105 #define CPSW2_BD_OFFSET 0x2000
106
107 #define CPDMA_RXTHRESH 0x0c0
108 #define CPDMA_RXFREE 0x0e0
109 #define CPDMA_TXHDP 0x00
110 #define CPDMA_RXHDP 0x20
111 #define CPDMA_TXCP 0x40
112 #define CPDMA_RXCP 0x60
113
114 #define CPSW_POLL_WEIGHT 64
115 #define CPSW_MIN_PACKET_SIZE 60
116 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
117
118 #define RX_PRIORITY_MAPPING 0x76543210
119 #define TX_PRIORITY_MAPPING 0x33221100
120 #define CPDMA_TX_PRIORITY_MAP 0x76543210
121
122 #define CPSW_VLAN_AWARE BIT(1)
123 #define CPSW_ALE_VLAN_AWARE 1
124
125 #define CPSW_FIFO_NORMAL_MODE (0 << 15)
126 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15)
127 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15)
128
129 #define CPSW_INTPACEEN (0x3f << 16)
130 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
131 #define CPSW_CMINTMAX_CNT 63
132 #define CPSW_CMINTMIN_CNT 2
133 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
134 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
135
136 #define cpsw_enable_irq(priv) \
137 do { \
138 u32 i; \
139 for (i = 0; i < priv->num_irqs; i++) \
140 enable_irq(priv->irqs_table[i]); \
141 } while (0);
142 #define cpsw_disable_irq(priv) \
143 do { \
144 u32 i; \
145 for (i = 0; i < priv->num_irqs; i++) \
146 disable_irq_nosync(priv->irqs_table[i]); \
147 } while (0);
148
149 #define cpsw_slave_index(priv) \
150 ((priv->data.dual_emac) ? priv->emac_port : \
151 priv->data.active_slave)
152
153 static int debug_level;
154 module_param(debug_level, int, 0);
155 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
156
157 static int ale_ageout = 10;
158 module_param(ale_ageout, int, 0);
159 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
160
161 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
162 module_param(rx_packet_max, int, 0);
163 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
164
165 struct cpsw_wr_regs {
166 u32 id_ver;
167 u32 soft_reset;
168 u32 control;
169 u32 int_control;
170 u32 rx_thresh_en;
171 u32 rx_en;
172 u32 tx_en;
173 u32 misc_en;
174 u32 mem_allign1[8];
175 u32 rx_thresh_stat;
176 u32 rx_stat;
177 u32 tx_stat;
178 u32 misc_stat;
179 u32 mem_allign2[8];
180 u32 rx_imax;
181 u32 tx_imax;
182
183 };
184
185 struct cpsw_ss_regs {
186 u32 id_ver;
187 u32 control;
188 u32 soft_reset;
189 u32 stat_port_en;
190 u32 ptype;
191 u32 soft_idle;
192 u32 thru_rate;
193 u32 gap_thresh;
194 u32 tx_start_wds;
195 u32 flow_control;
196 u32 vlan_ltype;
197 u32 ts_ltype;
198 u32 dlr_ltype;
199 };
200
201 /* CPSW_PORT_V1 */
202 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
203 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
204 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
205 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
206 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
207 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
208 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
209 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
210
211 /* CPSW_PORT_V2 */
212 #define CPSW2_CONTROL 0x00 /* Control Register */
213 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
214 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
215 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
216 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
217 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
218 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
219
220 /* CPSW_PORT_V1 and V2 */
221 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
222 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
223 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
224
225 /* CPSW_PORT_V2 only */
226 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
227 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
228 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
229 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
230 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
231 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
232 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
233 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
234
235 /* Bit definitions for the CPSW2_CONTROL register */
236 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
237 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
238 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
239 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
240 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
241 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
242 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
243 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
244 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
245 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
246 #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */
247 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
248 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
249 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
250 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
251 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
252
253 #define CTRL_TS_BITS \
254 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
255 TS_ANNEX_D_EN | TS_LTYPE1_EN)
256
257 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
258 #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN)
259 #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN)
260
261 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
262 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
263 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
264 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
265 #define TS_MSG_TYPE_EN_MASK (0xffff)
266
267 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
268 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
269
270 /* Bit definitions for the CPSW1_TS_CTL register */
271 #define CPSW_V1_TS_RX_EN BIT(0)
272 #define CPSW_V1_TS_TX_EN BIT(4)
273 #define CPSW_V1_MSG_TYPE_OFS 16
274
275 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
276 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
277
278 struct cpsw_host_regs {
279 u32 max_blks;
280 u32 blk_cnt;
281 u32 tx_in_ctl;
282 u32 port_vlan;
283 u32 tx_pri_map;
284 u32 cpdma_tx_pri_map;
285 u32 cpdma_rx_chan_map;
286 };
287
288 struct cpsw_sliver_regs {
289 u32 id_ver;
290 u32 mac_control;
291 u32 mac_status;
292 u32 soft_reset;
293 u32 rx_maxlen;
294 u32 __reserved_0;
295 u32 rx_pause;
296 u32 tx_pause;
297 u32 __reserved_1;
298 u32 rx_pri_map;
299 };
300
301 struct cpsw_slave {
302 void __iomem *regs;
303 struct cpsw_sliver_regs __iomem *sliver;
304 int slave_num;
305 u32 mac_control;
306 struct cpsw_slave_data *data;
307 struct phy_device *phy;
308 struct net_device *ndev;
309 u32 port_vlan;
310 u32 open_stat;
311 };
312
313 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
314 {
315 return __raw_readl(slave->regs + offset);
316 }
317
318 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
319 {
320 __raw_writel(val, slave->regs + offset);
321 }
322
323 struct cpsw_priv {
324 spinlock_t lock;
325 struct platform_device *pdev;
326 struct net_device *ndev;
327 struct resource *cpsw_res;
328 struct resource *cpsw_wr_res;
329 struct napi_struct napi;
330 struct device *dev;
331 struct cpsw_platform_data data;
332 struct cpsw_ss_regs __iomem *regs;
333 struct cpsw_wr_regs __iomem *wr_regs;
334 struct cpsw_host_regs __iomem *host_port_regs;
335 u32 msg_enable;
336 u32 version;
337 u32 coal_intvl;
338 u32 bus_freq_mhz;
339 struct net_device_stats stats;
340 int rx_packet_max;
341 int host_port;
342 struct clk *clk;
343 u8 mac_addr[ETH_ALEN];
344 struct cpsw_slave *slaves;
345 struct cpdma_ctlr *dma;
346 struct cpdma_chan *txch, *rxch;
347 struct cpsw_ale *ale;
348 /* snapshot of IRQ numbers */
349 u32 irqs_table[4];
350 u32 num_irqs;
351 struct cpts *cpts;
352 u32 emac_port;
353 };
354
355 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
356 #define for_each_slave(priv, func, arg...) \
357 do { \
358 int idx; \
359 if (priv->data.dual_emac) \
360 (func)((priv)->slaves + priv->emac_port, ##arg);\
361 else \
362 for (idx = 0; idx < (priv)->data.slaves; idx++) \
363 (func)((priv)->slaves + idx, ##arg); \
364 } while (0)
365 #define cpsw_get_slave_ndev(priv, __slave_no__) \
366 (priv->slaves[__slave_no__].ndev)
367 #define cpsw_get_slave_priv(priv, __slave_no__) \
368 ((priv->slaves[__slave_no__].ndev) ? \
369 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
370
371 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
372 do { \
373 if (!priv->data.dual_emac) \
374 break; \
375 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
376 ndev = cpsw_get_slave_ndev(priv, 0); \
377 priv = netdev_priv(ndev); \
378 skb->dev = ndev; \
379 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
380 ndev = cpsw_get_slave_ndev(priv, 1); \
381 priv = netdev_priv(ndev); \
382 skb->dev = ndev; \
383 } \
384 } while (0)
385 #define cpsw_add_mcast(priv, addr) \
386 do { \
387 if (priv->data.dual_emac) { \
388 struct cpsw_slave *slave = priv->slaves + \
389 priv->emac_port; \
390 int slave_port = cpsw_get_slave_port(priv, \
391 slave->slave_num); \
392 cpsw_ale_add_mcast(priv->ale, addr, \
393 1 << slave_port | 1 << priv->host_port, \
394 ALE_VLAN, slave->port_vlan, 0); \
395 } else { \
396 cpsw_ale_add_mcast(priv->ale, addr, \
397 ALE_ALL_PORTS << priv->host_port, \
398 0, 0, 0); \
399 } \
400 } while (0)
401
402 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
403 {
404 if (priv->host_port == 0)
405 return slave_num + 1;
406 else
407 return slave_num;
408 }
409
410 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
411 {
412 struct cpsw_priv *priv = netdev_priv(ndev);
413
414 if (ndev->flags & IFF_PROMISC) {
415 /* Enable promiscuous mode */
416 dev_err(priv->dev, "Ignoring Promiscuous mode\n");
417 return;
418 }
419
420 /* Clear all mcast from ALE */
421 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
422
423 if (!netdev_mc_empty(ndev)) {
424 struct netdev_hw_addr *ha;
425
426 /* program multicast address list into ALE register */
427 netdev_for_each_mc_addr(ha, ndev) {
428 cpsw_add_mcast(priv, (u8 *)ha->addr);
429 }
430 }
431 }
432
433 static void cpsw_intr_enable(struct cpsw_priv *priv)
434 {
435 __raw_writel(0xFF, &priv->wr_regs->tx_en);
436 __raw_writel(0xFF, &priv->wr_regs->rx_en);
437
438 cpdma_ctlr_int_ctrl(priv->dma, true);
439 return;
440 }
441
442 static void cpsw_intr_disable(struct cpsw_priv *priv)
443 {
444 __raw_writel(0, &priv->wr_regs->tx_en);
445 __raw_writel(0, &priv->wr_regs->rx_en);
446
447 cpdma_ctlr_int_ctrl(priv->dma, false);
448 return;
449 }
450
451 void cpsw_tx_handler(void *token, int len, int status)
452 {
453 struct sk_buff *skb = token;
454 struct net_device *ndev = skb->dev;
455 struct cpsw_priv *priv = netdev_priv(ndev);
456
457 /* Check whether the queue is stopped due to stalled tx dma, if the
458 * queue is stopped then start the queue as we have free desc for tx
459 */
460 if (unlikely(netif_queue_stopped(ndev)))
461 netif_wake_queue(ndev);
462 cpts_tx_timestamp(priv->cpts, skb);
463 priv->stats.tx_packets++;
464 priv->stats.tx_bytes += len;
465 dev_kfree_skb_any(skb);
466 }
467
468 void cpsw_rx_handler(void *token, int len, int status)
469 {
470 struct sk_buff *skb = token;
471 struct net_device *ndev = skb->dev;
472 struct cpsw_priv *priv = netdev_priv(ndev);
473 int ret = 0;
474
475 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
476
477 /* free and bail if we are shutting down */
478 if (unlikely(!netif_running(ndev)) ||
479 unlikely(!netif_carrier_ok(ndev))) {
480 dev_kfree_skb_any(skb);
481 return;
482 }
483 if (likely(status >= 0)) {
484 skb_put(skb, len);
485 cpts_rx_timestamp(priv->cpts, skb);
486 skb->protocol = eth_type_trans(skb, ndev);
487 netif_receive_skb(skb);
488 priv->stats.rx_bytes += len;
489 priv->stats.rx_packets++;
490 skb = NULL;
491 }
492
493 if (unlikely(!netif_running(ndev))) {
494 if (skb)
495 dev_kfree_skb_any(skb);
496 return;
497 }
498
499 if (likely(!skb)) {
500 skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
501 if (WARN_ON(!skb))
502 return;
503
504 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
505 skb_tailroom(skb), 0, GFP_KERNEL);
506 }
507 WARN_ON(ret < 0);
508 }
509
510 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
511 {
512 struct cpsw_priv *priv = dev_id;
513 u32 rx, tx, rx_thresh;
514
515 rx_thresh = __raw_readl(&priv->wr_regs->rx_thresh_stat);
516 rx = __raw_readl(&priv->wr_regs->rx_stat);
517 tx = __raw_readl(&priv->wr_regs->tx_stat);
518 if (!rx_thresh && !rx && !tx)
519 return IRQ_NONE;
520
521 cpsw_intr_disable(priv);
522 cpsw_disable_irq(priv);
523
524 if (netif_running(priv->ndev)) {
525 napi_schedule(&priv->napi);
526 return IRQ_HANDLED;
527 }
528
529 priv = cpsw_get_slave_priv(priv, 1);
530 if (!priv)
531 return IRQ_NONE;
532
533 if (netif_running(priv->ndev)) {
534 napi_schedule(&priv->napi);
535 return IRQ_HANDLED;
536 }
537 return IRQ_NONE;
538 }
539
540 static int cpsw_poll(struct napi_struct *napi, int budget)
541 {
542 struct cpsw_priv *priv = napi_to_priv(napi);
543 int num_tx, num_rx;
544
545 num_tx = cpdma_chan_process(priv->txch, 128);
546 if (num_tx)
547 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
548
549 num_rx = cpdma_chan_process(priv->rxch, budget);
550 if (num_rx < budget) {
551 napi_complete(napi);
552 cpsw_intr_enable(priv);
553 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
554 cpsw_enable_irq(priv);
555 }
556
557 if (num_rx || num_tx)
558 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
559 num_rx, num_tx);
560
561 return num_rx;
562 }
563
564 static inline void soft_reset(const char *module, void __iomem *reg)
565 {
566 unsigned long timeout = jiffies + HZ;
567
568 __raw_writel(1, reg);
569 do {
570 cpu_relax();
571 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
572
573 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
574 }
575
576 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
577 ((mac)[2] << 16) | ((mac)[3] << 24))
578 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
579
580 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
581 struct cpsw_priv *priv)
582 {
583 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
584 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
585 }
586
587 static void _cpsw_adjust_link(struct cpsw_slave *slave,
588 struct cpsw_priv *priv, bool *link)
589 {
590 struct phy_device *phy = slave->phy;
591 u32 mac_control = 0;
592 u32 slave_port;
593
594 if (!phy)
595 return;
596
597 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
598
599 if (phy->link) {
600 mac_control = priv->data.mac_control;
601
602 /* enable forwarding */
603 cpsw_ale_control_set(priv->ale, slave_port,
604 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
605
606 if (phy->speed == 1000)
607 mac_control |= BIT(7); /* GIGABITEN */
608 if (phy->duplex)
609 mac_control |= BIT(0); /* FULLDUPLEXEN */
610
611 /* set speed_in input in case RMII mode is used in 100Mbps */
612 if (phy->speed == 100)
613 mac_control |= BIT(15);
614
615 *link = true;
616 } else {
617 mac_control = 0;
618 /* disable forwarding */
619 cpsw_ale_control_set(priv->ale, slave_port,
620 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
621 }
622
623 if (mac_control != slave->mac_control) {
624 phy_print_status(phy);
625 __raw_writel(mac_control, &slave->sliver->mac_control);
626 }
627
628 slave->mac_control = mac_control;
629 }
630
631 static void cpsw_adjust_link(struct net_device *ndev)
632 {
633 struct cpsw_priv *priv = netdev_priv(ndev);
634 bool link = false;
635
636 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
637
638 if (link) {
639 netif_carrier_on(ndev);
640 if (netif_running(ndev))
641 netif_wake_queue(ndev);
642 } else {
643 netif_carrier_off(ndev);
644 netif_stop_queue(ndev);
645 }
646 }
647
648 static int cpsw_get_coalesce(struct net_device *ndev,
649 struct ethtool_coalesce *coal)
650 {
651 struct cpsw_priv *priv = netdev_priv(ndev);
652
653 coal->rx_coalesce_usecs = priv->coal_intvl;
654 return 0;
655 }
656
657 static int cpsw_set_coalesce(struct net_device *ndev,
658 struct ethtool_coalesce *coal)
659 {
660 struct cpsw_priv *priv = netdev_priv(ndev);
661 u32 int_ctrl;
662 u32 num_interrupts = 0;
663 u32 prescale = 0;
664 u32 addnl_dvdr = 1;
665 u32 coal_intvl = 0;
666
667 if (!coal->rx_coalesce_usecs)
668 return -EINVAL;
669
670 coal_intvl = coal->rx_coalesce_usecs;
671
672 int_ctrl = readl(&priv->wr_regs->int_control);
673 prescale = priv->bus_freq_mhz * 4;
674
675 if (coal_intvl < CPSW_CMINTMIN_INTVL)
676 coal_intvl = CPSW_CMINTMIN_INTVL;
677
678 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
679 /* Interrupt pacer works with 4us Pulse, we can
680 * throttle further by dilating the 4us pulse.
681 */
682 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
683
684 if (addnl_dvdr > 1) {
685 prescale *= addnl_dvdr;
686 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
687 coal_intvl = (CPSW_CMINTMAX_INTVL
688 * addnl_dvdr);
689 } else {
690 addnl_dvdr = 1;
691 coal_intvl = CPSW_CMINTMAX_INTVL;
692 }
693 }
694
695 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
696 writel(num_interrupts, &priv->wr_regs->rx_imax);
697 writel(num_interrupts, &priv->wr_regs->tx_imax);
698
699 int_ctrl |= CPSW_INTPACEEN;
700 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
701 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
702 writel(int_ctrl, &priv->wr_regs->int_control);
703
704 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
705 if (priv->data.dual_emac) {
706 int i;
707
708 for (i = 0; i < priv->data.slaves; i++) {
709 priv = netdev_priv(priv->slaves[i].ndev);
710 priv->coal_intvl = coal_intvl;
711 }
712 } else {
713 priv->coal_intvl = coal_intvl;
714 }
715
716 return 0;
717 }
718
719 static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
720 {
721 static char *leader = "........................................";
722
723 if (!val)
724 return 0;
725 else
726 return snprintf(buf, maxlen, "%s %s %10d\n", name,
727 leader + strlen(name), val);
728 }
729
730 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
731 {
732 u32 i;
733 u32 usage_count = 0;
734
735 if (!priv->data.dual_emac)
736 return 0;
737
738 for (i = 0; i < priv->data.slaves; i++)
739 if (priv->slaves[i].open_stat)
740 usage_count++;
741
742 return usage_count;
743 }
744
745 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
746 struct cpsw_priv *priv, struct sk_buff *skb)
747 {
748 if (!priv->data.dual_emac)
749 return cpdma_chan_submit(priv->txch, skb, skb->data,
750 skb->len, 0, GFP_KERNEL);
751
752 if (ndev == cpsw_get_slave_ndev(priv, 0))
753 return cpdma_chan_submit(priv->txch, skb, skb->data,
754 skb->len, 1, GFP_KERNEL);
755 else
756 return cpdma_chan_submit(priv->txch, skb, skb->data,
757 skb->len, 2, GFP_KERNEL);
758 }
759
760 static inline void cpsw_add_dual_emac_def_ale_entries(
761 struct cpsw_priv *priv, struct cpsw_slave *slave,
762 u32 slave_port)
763 {
764 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
765
766 if (priv->version == CPSW_VERSION_1)
767 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
768 else
769 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
770 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
771 port_mask, port_mask, 0);
772 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
773 port_mask, ALE_VLAN, slave->port_vlan, 0);
774 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
775 priv->host_port, ALE_VLAN, slave->port_vlan);
776 }
777
778 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
779 {
780 char name[32];
781 u32 slave_port;
782
783 sprintf(name, "slave-%d", slave->slave_num);
784
785 soft_reset(name, &slave->sliver->soft_reset);
786
787 /* setup priority mapping */
788 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
789
790 switch (priv->version) {
791 case CPSW_VERSION_1:
792 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
793 break;
794 case CPSW_VERSION_2:
795 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
796 break;
797 }
798
799 /* setup max packet size, and mac address */
800 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
801 cpsw_set_slave_mac(slave, priv);
802
803 slave->mac_control = 0; /* no link yet */
804
805 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
806
807 if (priv->data.dual_emac)
808 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
809 else
810 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
811 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
812
813 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
814 &cpsw_adjust_link, slave->data->phy_if);
815 if (IS_ERR(slave->phy)) {
816 dev_err(priv->dev, "phy %s not found on slave %d\n",
817 slave->data->phy_id, slave->slave_num);
818 slave->phy = NULL;
819 } else {
820 dev_info(priv->dev, "phy found : id is : 0x%x\n",
821 slave->phy->phy_id);
822 phy_start(slave->phy);
823 }
824 }
825
826 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
827 {
828 const int vlan = priv->data.default_vlan;
829 const int port = priv->host_port;
830 u32 reg;
831 int i;
832
833 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
834 CPSW2_PORT_VLAN;
835
836 writel(vlan, &priv->host_port_regs->port_vlan);
837
838 for (i = 0; i < priv->data.slaves; i++)
839 slave_write(priv->slaves + i, vlan, reg);
840
841 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
842 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
843 (ALE_PORT_1 | ALE_PORT_2) << port);
844 }
845
846 static void cpsw_init_host_port(struct cpsw_priv *priv)
847 {
848 u32 control_reg;
849 u32 fifo_mode;
850
851 /* soft reset the controller and initialize ale */
852 soft_reset("cpsw", &priv->regs->soft_reset);
853 cpsw_ale_start(priv->ale);
854
855 /* switch to vlan unaware mode */
856 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
857 CPSW_ALE_VLAN_AWARE);
858 control_reg = readl(&priv->regs->control);
859 control_reg |= CPSW_VLAN_AWARE;
860 writel(control_reg, &priv->regs->control);
861 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
862 CPSW_FIFO_NORMAL_MODE;
863 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
864
865 /* setup host port priority mapping */
866 __raw_writel(CPDMA_TX_PRIORITY_MAP,
867 &priv->host_port_regs->cpdma_tx_pri_map);
868 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
869
870 cpsw_ale_control_set(priv->ale, priv->host_port,
871 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
872
873 if (!priv->data.dual_emac) {
874 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
875 0, 0);
876 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
877 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
878 }
879 }
880
881 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
882 {
883 if (!slave->phy)
884 return;
885 phy_stop(slave->phy);
886 phy_disconnect(slave->phy);
887 slave->phy = NULL;
888 }
889
890 static int cpsw_ndo_open(struct net_device *ndev)
891 {
892 struct cpsw_priv *priv = netdev_priv(ndev);
893 int i, ret;
894 u32 reg;
895
896 if (!cpsw_common_res_usage_state(priv))
897 cpsw_intr_disable(priv);
898 netif_carrier_off(ndev);
899
900 pm_runtime_get_sync(&priv->pdev->dev);
901
902 reg = priv->version;
903
904 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
905 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
906 CPSW_RTL_VERSION(reg));
907
908 /* initialize host and slave ports */
909 if (!cpsw_common_res_usage_state(priv))
910 cpsw_init_host_port(priv);
911 for_each_slave(priv, cpsw_slave_open, priv);
912
913 /* Add default VLAN */
914 if (!priv->data.dual_emac)
915 cpsw_add_default_vlan(priv);
916
917 if (!cpsw_common_res_usage_state(priv)) {
918 /* setup tx dma to fixed prio and zero offset */
919 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
920 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
921
922 /* disable priority elevation */
923 __raw_writel(0, &priv->regs->ptype);
924
925 /* enable statistics collection only on all ports */
926 __raw_writel(0x7, &priv->regs->stat_port_en);
927
928 if (WARN_ON(!priv->data.rx_descs))
929 priv->data.rx_descs = 128;
930
931 for (i = 0; i < priv->data.rx_descs; i++) {
932 struct sk_buff *skb;
933
934 ret = -ENOMEM;
935 skb = __netdev_alloc_skb_ip_align(priv->ndev,
936 priv->rx_packet_max, GFP_KERNEL);
937 if (!skb)
938 goto err_cleanup;
939 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
940 skb_tailroom(skb), 0, GFP_KERNEL);
941 if (ret < 0) {
942 kfree_skb(skb);
943 goto err_cleanup;
944 }
945 }
946 /* continue even if we didn't manage to submit all
947 * receive descs
948 */
949 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
950 }
951
952 /* Enable Interrupt pacing if configured */
953 if (priv->coal_intvl != 0) {
954 struct ethtool_coalesce coal;
955
956 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
957 cpsw_set_coalesce(ndev, &coal);
958 }
959
960 cpdma_ctlr_start(priv->dma);
961 cpsw_intr_enable(priv);
962 napi_enable(&priv->napi);
963 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
964 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
965
966 if (priv->data.dual_emac)
967 priv->slaves[priv->emac_port].open_stat = true;
968 return 0;
969
970 err_cleanup:
971 cpdma_ctlr_stop(priv->dma);
972 for_each_slave(priv, cpsw_slave_stop, priv);
973 pm_runtime_put_sync(&priv->pdev->dev);
974 netif_carrier_off(priv->ndev);
975 return ret;
976 }
977
978 static int cpsw_ndo_stop(struct net_device *ndev)
979 {
980 struct cpsw_priv *priv = netdev_priv(ndev);
981
982 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
983 netif_stop_queue(priv->ndev);
984 napi_disable(&priv->napi);
985 netif_carrier_off(priv->ndev);
986
987 if (cpsw_common_res_usage_state(priv) <= 1) {
988 cpsw_intr_disable(priv);
989 cpdma_ctlr_int_ctrl(priv->dma, false);
990 cpdma_ctlr_stop(priv->dma);
991 cpsw_ale_stop(priv->ale);
992 }
993 for_each_slave(priv, cpsw_slave_stop, priv);
994 pm_runtime_put_sync(&priv->pdev->dev);
995 if (priv->data.dual_emac)
996 priv->slaves[priv->emac_port].open_stat = false;
997 return 0;
998 }
999
1000 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1001 struct net_device *ndev)
1002 {
1003 struct cpsw_priv *priv = netdev_priv(ndev);
1004 int ret;
1005
1006 ndev->trans_start = jiffies;
1007
1008 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1009 cpsw_err(priv, tx_err, "packet pad failed\n");
1010 priv->stats.tx_dropped++;
1011 return NETDEV_TX_OK;
1012 }
1013
1014 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1015 priv->cpts->tx_enable)
1016 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1017
1018 skb_tx_timestamp(skb);
1019
1020 ret = cpsw_tx_packet_submit(ndev, priv, skb);
1021 if (unlikely(ret != 0)) {
1022 cpsw_err(priv, tx_err, "desc submit failed\n");
1023 goto fail;
1024 }
1025
1026 /* If there is no more tx desc left free then we need to
1027 * tell the kernel to stop sending us tx frames.
1028 */
1029 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1030 netif_stop_queue(ndev);
1031
1032 return NETDEV_TX_OK;
1033 fail:
1034 priv->stats.tx_dropped++;
1035 netif_stop_queue(ndev);
1036 return NETDEV_TX_BUSY;
1037 }
1038
1039 static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
1040 {
1041 /*
1042 * The switch cannot operate in promiscuous mode without substantial
1043 * headache. For promiscuous mode to work, we would need to put the
1044 * ALE in bypass mode and route all traffic to the host port.
1045 * Subsequently, the host will need to operate as a "bridge", learn,
1046 * and flood as needed. For now, we simply complain here and
1047 * do nothing about it :-)
1048 */
1049 if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
1050 dev_err(&ndev->dev, "promiscuity ignored!\n");
1051
1052 /*
1053 * The switch cannot filter multicast traffic unless it is configured
1054 * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a
1055 * whole bunch of additional logic that this driver does not implement
1056 * at present.
1057 */
1058 if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
1059 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
1060 }
1061
1062 #ifdef CONFIG_TI_CPTS
1063
1064 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1065 {
1066 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1067 u32 ts_en, seq_id;
1068
1069 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1070 slave_write(slave, 0, CPSW1_TS_CTL);
1071 return;
1072 }
1073
1074 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1075 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1076
1077 if (priv->cpts->tx_enable)
1078 ts_en |= CPSW_V1_TS_TX_EN;
1079
1080 if (priv->cpts->rx_enable)
1081 ts_en |= CPSW_V1_TS_RX_EN;
1082
1083 slave_write(slave, ts_en, CPSW1_TS_CTL);
1084 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1085 }
1086
1087 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1088 {
1089 struct cpsw_slave *slave;
1090 u32 ctrl, mtype;
1091
1092 if (priv->data.dual_emac)
1093 slave = &priv->slaves[priv->emac_port];
1094 else
1095 slave = &priv->slaves[priv->data.active_slave];
1096
1097 ctrl = slave_read(slave, CPSW2_CONTROL);
1098 ctrl &= ~CTRL_ALL_TS_MASK;
1099
1100 if (priv->cpts->tx_enable)
1101 ctrl |= CTRL_TX_TS_BITS;
1102
1103 if (priv->cpts->rx_enable)
1104 ctrl |= CTRL_RX_TS_BITS;
1105
1106 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1107
1108 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1109 slave_write(slave, ctrl, CPSW2_CONTROL);
1110 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1111 }
1112
1113 static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
1114 {
1115 struct cpsw_priv *priv = netdev_priv(dev);
1116 struct cpts *cpts = priv->cpts;
1117 struct hwtstamp_config cfg;
1118
1119 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1120 return -EFAULT;
1121
1122 /* reserved for future extensions */
1123 if (cfg.flags)
1124 return -EINVAL;
1125
1126 switch (cfg.tx_type) {
1127 case HWTSTAMP_TX_OFF:
1128 cpts->tx_enable = 0;
1129 break;
1130 case HWTSTAMP_TX_ON:
1131 cpts->tx_enable = 1;
1132 break;
1133 default:
1134 return -ERANGE;
1135 }
1136
1137 switch (cfg.rx_filter) {
1138 case HWTSTAMP_FILTER_NONE:
1139 cpts->rx_enable = 0;
1140 break;
1141 case HWTSTAMP_FILTER_ALL:
1142 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1143 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1144 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1145 return -ERANGE;
1146 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1147 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1148 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1149 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1150 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1151 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1152 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1153 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1154 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1155 cpts->rx_enable = 1;
1156 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1157 break;
1158 default:
1159 return -ERANGE;
1160 }
1161
1162 switch (priv->version) {
1163 case CPSW_VERSION_1:
1164 cpsw_hwtstamp_v1(priv);
1165 break;
1166 case CPSW_VERSION_2:
1167 cpsw_hwtstamp_v2(priv);
1168 break;
1169 default:
1170 return -ENOTSUPP;
1171 }
1172
1173 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1174 }
1175
1176 #endif /*CONFIG_TI_CPTS*/
1177
1178 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1179 {
1180 struct cpsw_priv *priv = netdev_priv(dev);
1181 struct mii_ioctl_data *data = if_mii(req);
1182 int slave_no = cpsw_slave_index(priv);
1183
1184 if (!netif_running(dev))
1185 return -EINVAL;
1186
1187 switch (cmd) {
1188 #ifdef CONFIG_TI_CPTS
1189 case SIOCSHWTSTAMP:
1190 return cpsw_hwtstamp_ioctl(dev, req);
1191 #endif
1192 case SIOCGMIIPHY:
1193 data->phy_id = priv->slaves[slave_no].phy->addr;
1194 break;
1195 default:
1196 return -ENOTSUPP;
1197 }
1198
1199 return 0;
1200 }
1201
1202 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1203 {
1204 struct cpsw_priv *priv = netdev_priv(ndev);
1205
1206 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1207 priv->stats.tx_errors++;
1208 cpsw_intr_disable(priv);
1209 cpdma_ctlr_int_ctrl(priv->dma, false);
1210 cpdma_chan_stop(priv->txch);
1211 cpdma_chan_start(priv->txch);
1212 cpdma_ctlr_int_ctrl(priv->dma, true);
1213 cpsw_intr_enable(priv);
1214 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1215 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1216
1217 }
1218
1219 static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
1220 {
1221 struct cpsw_priv *priv = netdev_priv(ndev);
1222 return &priv->stats;
1223 }
1224
1225 #ifdef CONFIG_NET_POLL_CONTROLLER
1226 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1227 {
1228 struct cpsw_priv *priv = netdev_priv(ndev);
1229
1230 cpsw_intr_disable(priv);
1231 cpdma_ctlr_int_ctrl(priv->dma, false);
1232 cpsw_interrupt(ndev->irq, priv);
1233 cpdma_ctlr_int_ctrl(priv->dma, true);
1234 cpsw_intr_enable(priv);
1235 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1236 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1237
1238 }
1239 #endif
1240
1241 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1242 unsigned short vid)
1243 {
1244 int ret;
1245
1246 ret = cpsw_ale_add_vlan(priv->ale, vid,
1247 ALE_ALL_PORTS << priv->host_port,
1248 0, ALE_ALL_PORTS << priv->host_port,
1249 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
1250 if (ret != 0)
1251 return ret;
1252
1253 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1254 priv->host_port, ALE_VLAN, vid);
1255 if (ret != 0)
1256 goto clean_vid;
1257
1258 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1259 ALE_ALL_PORTS << priv->host_port,
1260 ALE_VLAN, vid, 0);
1261 if (ret != 0)
1262 goto clean_vlan_ucast;
1263 return 0;
1264
1265 clean_vlan_ucast:
1266 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1267 priv->host_port, ALE_VLAN, vid);
1268 clean_vid:
1269 cpsw_ale_del_vlan(priv->ale, vid, 0);
1270 return ret;
1271 }
1272
1273 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1274 __be16 proto, u16 vid)
1275 {
1276 struct cpsw_priv *priv = netdev_priv(ndev);
1277
1278 if (vid == priv->data.default_vlan)
1279 return 0;
1280
1281 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1282 return cpsw_add_vlan_ale_entry(priv, vid);
1283 }
1284
1285 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1286 __be16 proto, u16 vid)
1287 {
1288 struct cpsw_priv *priv = netdev_priv(ndev);
1289 int ret;
1290
1291 if (vid == priv->data.default_vlan)
1292 return 0;
1293
1294 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1295 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1296 if (ret != 0)
1297 return ret;
1298
1299 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1300 priv->host_port, ALE_VLAN, vid);
1301 if (ret != 0)
1302 return ret;
1303
1304 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1305 0, ALE_VLAN, vid);
1306 }
1307
1308 static const struct net_device_ops cpsw_netdev_ops = {
1309 .ndo_open = cpsw_ndo_open,
1310 .ndo_stop = cpsw_ndo_stop,
1311 .ndo_start_xmit = cpsw_ndo_start_xmit,
1312 .ndo_change_rx_flags = cpsw_ndo_change_rx_flags,
1313 .ndo_do_ioctl = cpsw_ndo_ioctl,
1314 .ndo_validate_addr = eth_validate_addr,
1315 .ndo_change_mtu = eth_change_mtu,
1316 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
1317 .ndo_get_stats = cpsw_ndo_get_stats,
1318 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
1319 #ifdef CONFIG_NET_POLL_CONTROLLER
1320 .ndo_poll_controller = cpsw_ndo_poll_controller,
1321 #endif
1322 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1323 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
1324 };
1325
1326 static void cpsw_get_drvinfo(struct net_device *ndev,
1327 struct ethtool_drvinfo *info)
1328 {
1329 struct cpsw_priv *priv = netdev_priv(ndev);
1330
1331 strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver));
1332 strlcpy(info->version, "1.0", sizeof(info->version));
1333 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1334 }
1335
1336 static u32 cpsw_get_msglevel(struct net_device *ndev)
1337 {
1338 struct cpsw_priv *priv = netdev_priv(ndev);
1339 return priv->msg_enable;
1340 }
1341
1342 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1343 {
1344 struct cpsw_priv *priv = netdev_priv(ndev);
1345 priv->msg_enable = value;
1346 }
1347
1348 static int cpsw_get_ts_info(struct net_device *ndev,
1349 struct ethtool_ts_info *info)
1350 {
1351 #ifdef CONFIG_TI_CPTS
1352 struct cpsw_priv *priv = netdev_priv(ndev);
1353
1354 info->so_timestamping =
1355 SOF_TIMESTAMPING_TX_HARDWARE |
1356 SOF_TIMESTAMPING_TX_SOFTWARE |
1357 SOF_TIMESTAMPING_RX_HARDWARE |
1358 SOF_TIMESTAMPING_RX_SOFTWARE |
1359 SOF_TIMESTAMPING_SOFTWARE |
1360 SOF_TIMESTAMPING_RAW_HARDWARE;
1361 info->phc_index = priv->cpts->phc_index;
1362 info->tx_types =
1363 (1 << HWTSTAMP_TX_OFF) |
1364 (1 << HWTSTAMP_TX_ON);
1365 info->rx_filters =
1366 (1 << HWTSTAMP_FILTER_NONE) |
1367 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1368 #else
1369 info->so_timestamping =
1370 SOF_TIMESTAMPING_TX_SOFTWARE |
1371 SOF_TIMESTAMPING_RX_SOFTWARE |
1372 SOF_TIMESTAMPING_SOFTWARE;
1373 info->phc_index = -1;
1374 info->tx_types = 0;
1375 info->rx_filters = 0;
1376 #endif
1377 return 0;
1378 }
1379
1380 static int cpsw_get_settings(struct net_device *ndev,
1381 struct ethtool_cmd *ecmd)
1382 {
1383 struct cpsw_priv *priv = netdev_priv(ndev);
1384 int slave_no = cpsw_slave_index(priv);
1385
1386 if (priv->slaves[slave_no].phy)
1387 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1388 else
1389 return -EOPNOTSUPP;
1390 }
1391
1392 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1393 {
1394 struct cpsw_priv *priv = netdev_priv(ndev);
1395 int slave_no = cpsw_slave_index(priv);
1396
1397 if (priv->slaves[slave_no].phy)
1398 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1399 else
1400 return -EOPNOTSUPP;
1401 }
1402
1403 static const struct ethtool_ops cpsw_ethtool_ops = {
1404 .get_drvinfo = cpsw_get_drvinfo,
1405 .get_msglevel = cpsw_get_msglevel,
1406 .set_msglevel = cpsw_set_msglevel,
1407 .get_link = ethtool_op_get_link,
1408 .get_ts_info = cpsw_get_ts_info,
1409 .get_settings = cpsw_get_settings,
1410 .set_settings = cpsw_set_settings,
1411 .get_coalesce = cpsw_get_coalesce,
1412 .set_coalesce = cpsw_set_coalesce,
1413 };
1414
1415 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1416 u32 slave_reg_ofs, u32 sliver_reg_ofs)
1417 {
1418 void __iomem *regs = priv->regs;
1419 int slave_num = slave->slave_num;
1420 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1421
1422 slave->data = data;
1423 slave->regs = regs + slave_reg_ofs;
1424 slave->sliver = regs + sliver_reg_ofs;
1425 slave->port_vlan = data->dual_emac_res_vlan;
1426 }
1427
1428 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1429 struct platform_device *pdev)
1430 {
1431 struct device_node *node = pdev->dev.of_node;
1432 struct device_node *slave_node;
1433 int i = 0, ret;
1434 u32 prop;
1435
1436 if (!node)
1437 return -EINVAL;
1438
1439 if (of_property_read_u32(node, "slaves", &prop)) {
1440 pr_err("Missing slaves property in the DT.\n");
1441 return -EINVAL;
1442 }
1443 data->slaves = prop;
1444
1445 if (of_property_read_u32(node, "active_slave", &prop)) {
1446 pr_err("Missing active_slave property in the DT.\n");
1447 ret = -EINVAL;
1448 goto error_ret;
1449 }
1450 data->active_slave = prop;
1451
1452 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1453 pr_err("Missing cpts_clock_mult property in the DT.\n");
1454 ret = -EINVAL;
1455 goto error_ret;
1456 }
1457 data->cpts_clock_mult = prop;
1458
1459 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1460 pr_err("Missing cpts_clock_shift property in the DT.\n");
1461 ret = -EINVAL;
1462 goto error_ret;
1463 }
1464 data->cpts_clock_shift = prop;
1465
1466 data->slave_data = kcalloc(data->slaves, sizeof(struct cpsw_slave_data),
1467 GFP_KERNEL);
1468 if (!data->slave_data)
1469 return -EINVAL;
1470
1471 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1472 pr_err("Missing cpdma_channels property in the DT.\n");
1473 ret = -EINVAL;
1474 goto error_ret;
1475 }
1476 data->channels = prop;
1477
1478 if (of_property_read_u32(node, "ale_entries", &prop)) {
1479 pr_err("Missing ale_entries property in the DT.\n");
1480 ret = -EINVAL;
1481 goto error_ret;
1482 }
1483 data->ale_entries = prop;
1484
1485 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1486 pr_err("Missing bd_ram_size property in the DT.\n");
1487 ret = -EINVAL;
1488 goto error_ret;
1489 }
1490 data->bd_ram_size = prop;
1491
1492 if (of_property_read_u32(node, "rx_descs", &prop)) {
1493 pr_err("Missing rx_descs property in the DT.\n");
1494 ret = -EINVAL;
1495 goto error_ret;
1496 }
1497 data->rx_descs = prop;
1498
1499 if (of_property_read_u32(node, "mac_control", &prop)) {
1500 pr_err("Missing mac_control property in the DT.\n");
1501 ret = -EINVAL;
1502 goto error_ret;
1503 }
1504 data->mac_control = prop;
1505
1506 if (!of_property_read_u32(node, "dual_emac", &prop))
1507 data->dual_emac = prop;
1508
1509 /*
1510 * Populate all the child nodes here...
1511 */
1512 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1513 /* We do not want to force this, as in some cases may not have child */
1514 if (ret)
1515 pr_warn("Doesn't have any child node\n");
1516
1517 for_each_node_by_name(slave_node, "slave") {
1518 struct cpsw_slave_data *slave_data = data->slave_data + i;
1519 const void *mac_addr = NULL;
1520 u32 phyid;
1521 int lenp;
1522 const __be32 *parp;
1523 struct device_node *mdio_node;
1524 struct platform_device *mdio;
1525
1526 parp = of_get_property(slave_node, "phy_id", &lenp);
1527 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
1528 pr_err("Missing slave[%d] phy_id property\n", i);
1529 ret = -EINVAL;
1530 goto error_ret;
1531 }
1532 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1533 phyid = be32_to_cpup(parp+1);
1534 mdio = of_find_device_by_node(mdio_node);
1535 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1536 PHY_ID_FMT, mdio->name, phyid);
1537
1538 mac_addr = of_get_mac_address(slave_node);
1539 if (mac_addr)
1540 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1541
1542 if (data->dual_emac) {
1543 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
1544 &prop)) {
1545 pr_err("Missing dual_emac_res_vlan in DT.\n");
1546 slave_data->dual_emac_res_vlan = i+1;
1547 pr_err("Using %d as Reserved VLAN for %d slave\n",
1548 slave_data->dual_emac_res_vlan, i);
1549 } else {
1550 slave_data->dual_emac_res_vlan = prop;
1551 }
1552 }
1553
1554 i++;
1555 }
1556
1557 return 0;
1558
1559 error_ret:
1560 kfree(data->slave_data);
1561 return ret;
1562 }
1563
1564 static int cpsw_probe_dual_emac(struct platform_device *pdev,
1565 struct cpsw_priv *priv)
1566 {
1567 struct cpsw_platform_data *data = &priv->data;
1568 struct net_device *ndev;
1569 struct cpsw_priv *priv_sl2;
1570 int ret = 0, i;
1571
1572 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1573 if (!ndev) {
1574 pr_err("cpsw: error allocating net_device\n");
1575 return -ENOMEM;
1576 }
1577
1578 priv_sl2 = netdev_priv(ndev);
1579 spin_lock_init(&priv_sl2->lock);
1580 priv_sl2->data = *data;
1581 priv_sl2->pdev = pdev;
1582 priv_sl2->ndev = ndev;
1583 priv_sl2->dev = &ndev->dev;
1584 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1585 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
1586
1587 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
1588 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
1589 ETH_ALEN);
1590 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
1591 } else {
1592 random_ether_addr(priv_sl2->mac_addr);
1593 pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
1594 }
1595 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
1596
1597 priv_sl2->slaves = priv->slaves;
1598 priv_sl2->clk = priv->clk;
1599
1600 priv_sl2->coal_intvl = 0;
1601 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
1602
1603 priv_sl2->cpsw_res = priv->cpsw_res;
1604 priv_sl2->regs = priv->regs;
1605 priv_sl2->host_port = priv->host_port;
1606 priv_sl2->host_port_regs = priv->host_port_regs;
1607 priv_sl2->wr_regs = priv->wr_regs;
1608 priv_sl2->dma = priv->dma;
1609 priv_sl2->txch = priv->txch;
1610 priv_sl2->rxch = priv->rxch;
1611 priv_sl2->ale = priv->ale;
1612 priv_sl2->emac_port = 1;
1613 priv->slaves[1].ndev = ndev;
1614 priv_sl2->cpts = priv->cpts;
1615 priv_sl2->version = priv->version;
1616
1617 for (i = 0; i < priv->num_irqs; i++) {
1618 priv_sl2->irqs_table[i] = priv->irqs_table[i];
1619 priv_sl2->num_irqs = priv->num_irqs;
1620 }
1621
1622 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1623
1624 ndev->netdev_ops = &cpsw_netdev_ops;
1625 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1626 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1627
1628 /* register the network device */
1629 SET_NETDEV_DEV(ndev, &pdev->dev);
1630 ret = register_netdev(ndev);
1631 if (ret) {
1632 pr_err("cpsw: error registering net device\n");
1633 free_netdev(ndev);
1634 ret = -ENODEV;
1635 }
1636
1637 return ret;
1638 }
1639
1640 static int cpsw_probe(struct platform_device *pdev)
1641 {
1642 struct cpsw_platform_data *data = pdev->dev.platform_data;
1643 struct net_device *ndev;
1644 struct cpsw_priv *priv;
1645 struct cpdma_params dma_params;
1646 struct cpsw_ale_params ale_params;
1647 void __iomem *ss_regs, *wr_regs;
1648 struct resource *res;
1649 u32 slave_offset, sliver_offset, slave_size;
1650 int ret = 0, i, k = 0;
1651
1652 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
1653 if (!ndev) {
1654 pr_err("error allocating net_device\n");
1655 return -ENOMEM;
1656 }
1657
1658 platform_set_drvdata(pdev, ndev);
1659 priv = netdev_priv(ndev);
1660 spin_lock_init(&priv->lock);
1661 priv->pdev = pdev;
1662 priv->ndev = ndev;
1663 priv->dev = &ndev->dev;
1664 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
1665 priv->rx_packet_max = max(rx_packet_max, 128);
1666 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
1667 if (!ndev) {
1668 pr_err("error allocating cpts\n");
1669 goto clean_ndev_ret;
1670 }
1671
1672 /*
1673 * This may be required here for child devices.
1674 */
1675 pm_runtime_enable(&pdev->dev);
1676
1677 if (cpsw_probe_dt(&priv->data, pdev)) {
1678 pr_err("cpsw: platform data missing\n");
1679 ret = -ENODEV;
1680 goto clean_ndev_ret;
1681 }
1682 data = &priv->data;
1683
1684 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
1685 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
1686 pr_info("Detected MACID = %pM", priv->mac_addr);
1687 } else {
1688 eth_random_addr(priv->mac_addr);
1689 pr_info("Random MACID = %pM", priv->mac_addr);
1690 }
1691
1692 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1693
1694 priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
1695 GFP_KERNEL);
1696 if (!priv->slaves) {
1697 ret = -EBUSY;
1698 goto clean_ndev_ret;
1699 }
1700 for (i = 0; i < data->slaves; i++)
1701 priv->slaves[i].slave_num = i;
1702
1703 priv->slaves[0].ndev = ndev;
1704 priv->emac_port = 0;
1705
1706 priv->clk = clk_get(&pdev->dev, "fck");
1707 if (IS_ERR(priv->clk)) {
1708 dev_err(&pdev->dev, "fck is not found\n");
1709 ret = -ENODEV;
1710 goto clean_slave_ret;
1711 }
1712 priv->coal_intvl = 0;
1713 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
1714
1715 priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1716 if (!priv->cpsw_res) {
1717 dev_err(priv->dev, "error getting i/o resource\n");
1718 ret = -ENOENT;
1719 goto clean_clk_ret;
1720 }
1721 if (!request_mem_region(priv->cpsw_res->start,
1722 resource_size(priv->cpsw_res), ndev->name)) {
1723 dev_err(priv->dev, "failed request i/o region\n");
1724 ret = -ENXIO;
1725 goto clean_clk_ret;
1726 }
1727 ss_regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
1728 if (!ss_regs) {
1729 dev_err(priv->dev, "unable to map i/o region\n");
1730 goto clean_cpsw_iores_ret;
1731 }
1732 priv->regs = ss_regs;
1733 priv->version = __raw_readl(&priv->regs->id_ver);
1734 priv->host_port = HOST_PORT_NUM;
1735
1736 priv->cpsw_wr_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1737 if (!priv->cpsw_wr_res) {
1738 dev_err(priv->dev, "error getting i/o resource\n");
1739 ret = -ENOENT;
1740 goto clean_iomap_ret;
1741 }
1742 if (!request_mem_region(priv->cpsw_wr_res->start,
1743 resource_size(priv->cpsw_wr_res), ndev->name)) {
1744 dev_err(priv->dev, "failed request i/o region\n");
1745 ret = -ENXIO;
1746 goto clean_iomap_ret;
1747 }
1748 wr_regs = ioremap(priv->cpsw_wr_res->start,
1749 resource_size(priv->cpsw_wr_res));
1750 if (!wr_regs) {
1751 dev_err(priv->dev, "unable to map i/o region\n");
1752 goto clean_cpsw_wr_iores_ret;
1753 }
1754 priv->wr_regs = wr_regs;
1755
1756 memset(&dma_params, 0, sizeof(dma_params));
1757 memset(&ale_params, 0, sizeof(ale_params));
1758
1759 switch (priv->version) {
1760 case CPSW_VERSION_1:
1761 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
1762 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
1763 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
1764 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
1765 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
1766 slave_offset = CPSW1_SLAVE_OFFSET;
1767 slave_size = CPSW1_SLAVE_SIZE;
1768 sliver_offset = CPSW1_SLIVER_OFFSET;
1769 dma_params.desc_mem_phys = 0;
1770 break;
1771 case CPSW_VERSION_2:
1772 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
1773 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
1774 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
1775 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
1776 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
1777 slave_offset = CPSW2_SLAVE_OFFSET;
1778 slave_size = CPSW2_SLAVE_SIZE;
1779 sliver_offset = CPSW2_SLIVER_OFFSET;
1780 dma_params.desc_mem_phys =
1781 (u32 __force) priv->cpsw_res->start + CPSW2_BD_OFFSET;
1782 break;
1783 default:
1784 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
1785 ret = -ENODEV;
1786 goto clean_cpsw_wr_iores_ret;
1787 }
1788 for (i = 0; i < priv->data.slaves; i++) {
1789 struct cpsw_slave *slave = &priv->slaves[i];
1790 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
1791 slave_offset += slave_size;
1792 sliver_offset += SLIVER_SIZE;
1793 }
1794
1795 dma_params.dev = &pdev->dev;
1796 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
1797 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
1798 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
1799 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
1800 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
1801
1802 dma_params.num_chan = data->channels;
1803 dma_params.has_soft_reset = true;
1804 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
1805 dma_params.desc_mem_size = data->bd_ram_size;
1806 dma_params.desc_align = 16;
1807 dma_params.has_ext_regs = true;
1808 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
1809
1810 priv->dma = cpdma_ctlr_create(&dma_params);
1811 if (!priv->dma) {
1812 dev_err(priv->dev, "error initializing dma\n");
1813 ret = -ENOMEM;
1814 goto clean_wr_iomap_ret;
1815 }
1816
1817 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
1818 cpsw_tx_handler);
1819 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
1820 cpsw_rx_handler);
1821
1822 if (WARN_ON(!priv->txch || !priv->rxch)) {
1823 dev_err(priv->dev, "error initializing dma channels\n");
1824 ret = -ENOMEM;
1825 goto clean_dma_ret;
1826 }
1827
1828 ale_params.dev = &ndev->dev;
1829 ale_params.ale_ageout = ale_ageout;
1830 ale_params.ale_entries = data->ale_entries;
1831 ale_params.ale_ports = data->slaves;
1832
1833 priv->ale = cpsw_ale_create(&ale_params);
1834 if (!priv->ale) {
1835 dev_err(priv->dev, "error initializing ale engine\n");
1836 ret = -ENODEV;
1837 goto clean_dma_ret;
1838 }
1839
1840 ndev->irq = platform_get_irq(pdev, 0);
1841 if (ndev->irq < 0) {
1842 dev_err(priv->dev, "error getting irq resource\n");
1843 ret = -ENOENT;
1844 goto clean_ale_ret;
1845 }
1846
1847 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1848 for (i = res->start; i <= res->end; i++) {
1849 if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
1850 dev_name(&pdev->dev), priv)) {
1851 dev_err(priv->dev, "error attaching irq\n");
1852 goto clean_ale_ret;
1853 }
1854 priv->irqs_table[k] = i;
1855 priv->num_irqs = k;
1856 }
1857 k++;
1858 }
1859
1860 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1861
1862 ndev->netdev_ops = &cpsw_netdev_ops;
1863 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
1864 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
1865
1866 /* register the network device */
1867 SET_NETDEV_DEV(ndev, &pdev->dev);
1868 ret = register_netdev(ndev);
1869 if (ret) {
1870 dev_err(priv->dev, "error registering net device\n");
1871 ret = -ENODEV;
1872 goto clean_irq_ret;
1873 }
1874
1875 if (cpts_register(&pdev->dev, priv->cpts,
1876 data->cpts_clock_mult, data->cpts_clock_shift))
1877 dev_err(priv->dev, "error registering cpts device\n");
1878
1879 cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
1880 priv->cpsw_res->start, ndev->irq);
1881
1882 if (priv->data.dual_emac) {
1883 ret = cpsw_probe_dual_emac(pdev, priv);
1884 if (ret) {
1885 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
1886 goto clean_irq_ret;
1887 }
1888 }
1889
1890 return 0;
1891
1892 clean_irq_ret:
1893 free_irq(ndev->irq, priv);
1894 clean_ale_ret:
1895 cpsw_ale_destroy(priv->ale);
1896 clean_dma_ret:
1897 cpdma_chan_destroy(priv->txch);
1898 cpdma_chan_destroy(priv->rxch);
1899 cpdma_ctlr_destroy(priv->dma);
1900 clean_wr_iomap_ret:
1901 iounmap(priv->wr_regs);
1902 clean_cpsw_wr_iores_ret:
1903 release_mem_region(priv->cpsw_wr_res->start,
1904 resource_size(priv->cpsw_wr_res));
1905 clean_iomap_ret:
1906 iounmap(priv->regs);
1907 clean_cpsw_iores_ret:
1908 release_mem_region(priv->cpsw_res->start,
1909 resource_size(priv->cpsw_res));
1910 clean_clk_ret:
1911 clk_put(priv->clk);
1912 clean_slave_ret:
1913 pm_runtime_disable(&pdev->dev);
1914 kfree(priv->slaves);
1915 clean_ndev_ret:
1916 free_netdev(ndev);
1917 return ret;
1918 }
1919
1920 static int cpsw_remove(struct platform_device *pdev)
1921 {
1922 struct net_device *ndev = platform_get_drvdata(pdev);
1923 struct cpsw_priv *priv = netdev_priv(ndev);
1924
1925 pr_info("removing device");
1926 platform_set_drvdata(pdev, NULL);
1927
1928 cpts_unregister(priv->cpts);
1929 free_irq(ndev->irq, priv);
1930 cpsw_ale_destroy(priv->ale);
1931 cpdma_chan_destroy(priv->txch);
1932 cpdma_chan_destroy(priv->rxch);
1933 cpdma_ctlr_destroy(priv->dma);
1934 iounmap(priv->regs);
1935 release_mem_region(priv->cpsw_res->start,
1936 resource_size(priv->cpsw_res));
1937 iounmap(priv->wr_regs);
1938 release_mem_region(priv->cpsw_wr_res->start,
1939 resource_size(priv->cpsw_wr_res));
1940 pm_runtime_disable(&pdev->dev);
1941 clk_put(priv->clk);
1942 kfree(priv->slaves);
1943 free_netdev(ndev);
1944
1945 return 0;
1946 }
1947
1948 static int cpsw_suspend(struct device *dev)
1949 {
1950 struct platform_device *pdev = to_platform_device(dev);
1951 struct net_device *ndev = platform_get_drvdata(pdev);
1952
1953 if (netif_running(ndev))
1954 cpsw_ndo_stop(ndev);
1955 pm_runtime_put_sync(&pdev->dev);
1956
1957 return 0;
1958 }
1959
1960 static int cpsw_resume(struct device *dev)
1961 {
1962 struct platform_device *pdev = to_platform_device(dev);
1963 struct net_device *ndev = platform_get_drvdata(pdev);
1964
1965 pm_runtime_get_sync(&pdev->dev);
1966 if (netif_running(ndev))
1967 cpsw_ndo_open(ndev);
1968 return 0;
1969 }
1970
1971 static const struct dev_pm_ops cpsw_pm_ops = {
1972 .suspend = cpsw_suspend,
1973 .resume = cpsw_resume,
1974 };
1975
1976 static const struct of_device_id cpsw_of_mtable[] = {
1977 { .compatible = "ti,cpsw", },
1978 { /* sentinel */ },
1979 };
1980
1981 static struct platform_driver cpsw_driver = {
1982 .driver = {
1983 .name = "cpsw",
1984 .owner = THIS_MODULE,
1985 .pm = &cpsw_pm_ops,
1986 .of_match_table = of_match_ptr(cpsw_of_mtable),
1987 },
1988 .probe = cpsw_probe,
1989 .remove = cpsw_remove,
1990 };
1991
1992 static int __init cpsw_init(void)
1993 {
1994 return platform_driver_register(&cpsw_driver);
1995 }
1996 late_initcall(cpsw_init);
1997
1998 static void __exit cpsw_exit(void)
1999 {
2000 platform_driver_unregister(&cpsw_driver);
2001 }
2002 module_exit(cpsw_exit);
2003
2004 MODULE_LICENSE("GPL");
2005 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2006 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2007 MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux kernel - Deliverables
This page took 0.141012 seconds and 5 git commands to generate.