2 * Texas Instruments Ethernet Switch Driver
4 * Copyright (C) 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
33 #include <linux/of_mdio.h>
34 #include <linux/of_net.h>
35 #include <linux/of_device.h>
36 #include <linux/if_vlan.h>
38 #include <linux/pinctrl/consumer.h>
43 #include "davinci_cpdma.h"
45 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
46 NETIF_MSG_DRV | NETIF_MSG_LINK | \
47 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
48 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
49 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
50 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
51 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
54 #define cpsw_info(priv, type, format, ...) \
56 if (netif_msg_##type(priv) && net_ratelimit()) \
57 dev_info(priv->dev, format, ## __VA_ARGS__); \
60 #define cpsw_err(priv, type, format, ...) \
62 if (netif_msg_##type(priv) && net_ratelimit()) \
63 dev_err(priv->dev, format, ## __VA_ARGS__); \
66 #define cpsw_dbg(priv, type, format, ...) \
68 if (netif_msg_##type(priv) && net_ratelimit()) \
69 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
72 #define cpsw_notice(priv, type, format, ...) \
74 if (netif_msg_##type(priv) && net_ratelimit()) \
75 dev_notice(priv->dev, format, ## __VA_ARGS__); \
78 #define ALE_ALL_PORTS 0x7
80 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
81 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
82 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84 #define CPSW_VERSION_1 0x19010a
85 #define CPSW_VERSION_2 0x19010c
86 #define CPSW_VERSION_3 0x19010f
87 #define CPSW_VERSION_4 0x190112
89 #define HOST_PORT_NUM 0
90 #define SLIVER_SIZE 0x40
92 #define CPSW1_HOST_PORT_OFFSET 0x028
93 #define CPSW1_SLAVE_OFFSET 0x050
94 #define CPSW1_SLAVE_SIZE 0x040
95 #define CPSW1_CPDMA_OFFSET 0x100
96 #define CPSW1_STATERAM_OFFSET 0x200
97 #define CPSW1_HW_STATS 0x400
98 #define CPSW1_CPTS_OFFSET 0x500
99 #define CPSW1_ALE_OFFSET 0x600
100 #define CPSW1_SLIVER_OFFSET 0x700
102 #define CPSW2_HOST_PORT_OFFSET 0x108
103 #define CPSW2_SLAVE_OFFSET 0x200
104 #define CPSW2_SLAVE_SIZE 0x100
105 #define CPSW2_CPDMA_OFFSET 0x800
106 #define CPSW2_HW_STATS 0x900
107 #define CPSW2_STATERAM_OFFSET 0xa00
108 #define CPSW2_CPTS_OFFSET 0xc00
109 #define CPSW2_ALE_OFFSET 0xd00
110 #define CPSW2_SLIVER_OFFSET 0xd80
111 #define CPSW2_BD_OFFSET 0x2000
113 #define CPDMA_RXTHRESH 0x0c0
114 #define CPDMA_RXFREE 0x0e0
115 #define CPDMA_TXHDP 0x00
116 #define CPDMA_RXHDP 0x20
117 #define CPDMA_TXCP 0x40
118 #define CPDMA_RXCP 0x60
120 #define CPSW_POLL_WEIGHT 64
121 #define CPSW_MIN_PACKET_SIZE 60
122 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124 #define RX_PRIORITY_MAPPING 0x76543210
125 #define TX_PRIORITY_MAPPING 0x33221100
126 #define CPDMA_TX_PRIORITY_MAP 0x76543210
128 #define CPSW_VLAN_AWARE BIT(1)
129 #define CPSW_ALE_VLAN_AWARE 1
131 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
132 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
133 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
135 #define CPSW_INTPACEEN (0x3f << 16)
136 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
137 #define CPSW_CMINTMAX_CNT 63
138 #define CPSW_CMINTMIN_CNT 2
139 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
140 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142 #define cpsw_slave_index(priv) \
143 ((priv->data.dual_emac) ? priv->emac_port : \
144 priv->data.active_slave)
146 static int debug_level
;
147 module_param(debug_level
, int, 0);
148 MODULE_PARM_DESC(debug_level
, "cpsw debug level (NETIF_MSG bits)");
150 static int ale_ageout
= 10;
151 module_param(ale_ageout
, int, 0);
152 MODULE_PARM_DESC(ale_ageout
, "cpsw ale ageout interval (seconds)");
154 static int rx_packet_max
= CPSW_MAX_PACKET_SIZE
;
155 module_param(rx_packet_max
, int, 0);
156 MODULE_PARM_DESC(rx_packet_max
, "maximum receive packet size (bytes)");
158 struct cpsw_wr_regs
{
178 struct cpsw_ss_regs
{
195 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
196 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
197 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
198 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
199 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
200 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
201 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
202 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
205 #define CPSW2_CONTROL 0x00 /* Control Register */
206 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
207 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
208 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
209 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
210 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
211 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
213 /* CPSW_PORT_V1 and V2 */
214 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
215 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
216 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
218 /* CPSW_PORT_V2 only */
219 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
220 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
221 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
222 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
223 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
224 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
225 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
226 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
228 /* Bit definitions for the CPSW2_CONTROL register */
229 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
230 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
231 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
232 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
233 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
234 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
235 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
236 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
237 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
238 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
239 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
240 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
241 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
242 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
243 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
244 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
245 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
247 #define CTRL_V2_TS_BITS \
248 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
249 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
251 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
252 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
253 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
256 #define CTRL_V3_TS_BITS \
257 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
258 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
261 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
262 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
263 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
265 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
266 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
267 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
268 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
269 #define TS_MSG_TYPE_EN_MASK (0xffff)
271 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
272 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
274 /* Bit definitions for the CPSW1_TS_CTL register */
275 #define CPSW_V1_TS_RX_EN BIT(0)
276 #define CPSW_V1_TS_TX_EN BIT(4)
277 #define CPSW_V1_MSG_TYPE_OFS 16
279 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
280 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
282 struct cpsw_host_regs
{
288 u32 cpdma_tx_pri_map
;
289 u32 cpdma_rx_chan_map
;
292 struct cpsw_sliver_regs
{
305 struct cpsw_hw_stats
{
307 u32 rxbroadcastframes
;
308 u32 rxmulticastframes
;
311 u32 rxaligncodeerrors
;
312 u32 rxoversizedframes
;
314 u32 rxundersizedframes
;
319 u32 txbroadcastframes
;
320 u32 txmulticastframes
;
322 u32 txdeferredframes
;
323 u32 txcollisionframes
;
324 u32 txsinglecollframes
;
325 u32 txmultcollframes
;
326 u32 txexcessivecollisions
;
327 u32 txlatecollisions
;
329 u32 txcarriersenseerrors
;
332 u32 octetframes65t127
;
333 u32 octetframes128t255
;
334 u32 octetframes256t511
;
335 u32 octetframes512t1023
;
336 u32 octetframes1024tup
;
345 struct cpsw_sliver_regs __iomem
*sliver
;
348 struct cpsw_slave_data
*data
;
349 struct phy_device
*phy
;
350 struct net_device
*ndev
;
355 static inline u32
slave_read(struct cpsw_slave
*slave
, u32 offset
)
357 return __raw_readl(slave
->regs
+ offset
);
360 static inline void slave_write(struct cpsw_slave
*slave
, u32 val
, u32 offset
)
362 __raw_writel(val
, slave
->regs
+ offset
);
367 struct platform_device
*pdev
;
368 struct net_device
*ndev
;
369 struct device_node
*phy_node
;
370 struct napi_struct napi_rx
;
371 struct napi_struct napi_tx
;
373 struct cpsw_platform_data data
;
374 struct cpsw_ss_regs __iomem
*regs
;
375 struct cpsw_wr_regs __iomem
*wr_regs
;
376 u8 __iomem
*hw_stats
;
377 struct cpsw_host_regs __iomem
*host_port_regs
;
385 u8 mac_addr
[ETH_ALEN
];
386 struct cpsw_slave
*slaves
;
387 struct cpdma_ctlr
*dma
;
388 struct cpdma_chan
*txch
, *rxch
;
389 struct cpsw_ale
*ale
;
393 bool rx_irq_disabled
;
394 bool tx_irq_disabled
;
395 /* snapshot of IRQ numbers */
403 char stat_string
[ETH_GSTRING_LEN
];
415 #define CPSW_STAT(m) CPSW_STATS, \
416 sizeof(((struct cpsw_hw_stats *)0)->m), \
417 offsetof(struct cpsw_hw_stats, m)
418 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
419 sizeof(((struct cpdma_chan_stats *)0)->m), \
420 offsetof(struct cpdma_chan_stats, m)
421 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
422 sizeof(((struct cpdma_chan_stats *)0)->m), \
423 offsetof(struct cpdma_chan_stats, m)
425 static const struct cpsw_stats cpsw_gstrings_stats
[] = {
426 { "Good Rx Frames", CPSW_STAT(rxgoodframes
) },
427 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes
) },
428 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes
) },
429 { "Pause Rx Frames", CPSW_STAT(rxpauseframes
) },
430 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors
) },
431 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors
) },
432 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes
) },
433 { "Rx Jabbers", CPSW_STAT(rxjabberframes
) },
434 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes
) },
435 { "Rx Fragments", CPSW_STAT(rxfragments
) },
436 { "Rx Octets", CPSW_STAT(rxoctets
) },
437 { "Good Tx Frames", CPSW_STAT(txgoodframes
) },
438 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes
) },
439 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes
) },
440 { "Pause Tx Frames", CPSW_STAT(txpauseframes
) },
441 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes
) },
442 { "Collisions", CPSW_STAT(txcollisionframes
) },
443 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes
) },
444 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes
) },
445 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions
) },
446 { "Late Collisions", CPSW_STAT(txlatecollisions
) },
447 { "Tx Underrun", CPSW_STAT(txunderrun
) },
448 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors
) },
449 { "Tx Octets", CPSW_STAT(txoctets
) },
450 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64
) },
451 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127
) },
452 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255
) },
453 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511
) },
454 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023
) },
455 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup
) },
456 { "Net Octets", CPSW_STAT(netoctets
) },
457 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns
) },
458 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns
) },
459 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns
) },
460 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue
) },
461 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue
) },
462 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue
) },
463 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued
) },
464 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail
) },
465 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail
) },
466 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff
) },
467 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff
) },
468 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue
) },
469 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue
) },
470 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue
) },
471 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue
) },
472 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue
) },
473 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue
) },
474 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue
) },
475 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue
) },
476 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued
) },
477 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail
) },
478 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail
) },
479 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff
) },
480 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff
) },
481 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue
) },
482 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue
) },
483 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue
) },
484 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue
) },
485 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue
) },
488 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
490 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
491 #define for_each_slave(priv, func, arg...) \
493 struct cpsw_slave *slave; \
495 if (priv->data.dual_emac) \
496 (func)((priv)->slaves + priv->emac_port, ##arg);\
498 for (n = (priv)->data.slaves, \
499 slave = (priv)->slaves; \
501 (func)(slave++, ##arg); \
503 #define cpsw_get_slave_ndev(priv, __slave_no__) \
504 ((__slave_no__ < priv->data.slaves) ? \
505 priv->slaves[__slave_no__].ndev : NULL)
506 #define cpsw_get_slave_priv(priv, __slave_no__) \
507 (((__slave_no__ < priv->data.slaves) && \
508 (priv->slaves[__slave_no__].ndev)) ? \
509 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
511 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
513 if (!priv->data.dual_emac) \
515 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
516 ndev = cpsw_get_slave_ndev(priv, 0); \
517 priv = netdev_priv(ndev); \
519 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
520 ndev = cpsw_get_slave_ndev(priv, 1); \
521 priv = netdev_priv(ndev); \
525 #define cpsw_add_mcast(priv, addr) \
527 if (priv->data.dual_emac) { \
528 struct cpsw_slave *slave = priv->slaves + \
530 int slave_port = cpsw_get_slave_port(priv, \
532 cpsw_ale_add_mcast(priv->ale, addr, \
533 1 << slave_port | 1 << priv->host_port, \
534 ALE_VLAN, slave->port_vlan, 0); \
536 cpsw_ale_add_mcast(priv->ale, addr, \
537 ALE_ALL_PORTS << priv->host_port, \
542 static inline int cpsw_get_slave_port(struct cpsw_priv
*priv
, u32 slave_num
)
544 if (priv
->host_port
== 0)
545 return slave_num
+ 1;
550 static void cpsw_set_promiscious(struct net_device
*ndev
, bool enable
)
552 struct cpsw_priv
*priv
= netdev_priv(ndev
);
553 struct cpsw_ale
*ale
= priv
->ale
;
556 if (priv
->data
.dual_emac
) {
559 /* Enabling promiscuous mode for one interface will be
560 * common for both the interface as the interface shares
561 * the same hardware resource.
563 for (i
= 0; i
< priv
->data
.slaves
; i
++)
564 if (priv
->slaves
[i
].ndev
->flags
& IFF_PROMISC
)
567 if (!enable
&& flag
) {
569 dev_err(&ndev
->dev
, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
574 cpsw_ale_control_set(ale
, 0, ALE_BYPASS
, 1);
576 dev_dbg(&ndev
->dev
, "promiscuity enabled\n");
579 cpsw_ale_control_set(ale
, 0, ALE_BYPASS
, 0);
580 dev_dbg(&ndev
->dev
, "promiscuity disabled\n");
584 unsigned long timeout
= jiffies
+ HZ
;
586 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
587 for (i
= 0; i
<= priv
->data
.slaves
; i
++) {
588 cpsw_ale_control_set(ale
, i
,
589 ALE_PORT_NOLEARN
, 1);
590 cpsw_ale_control_set(ale
, i
,
591 ALE_PORT_NO_SA_UPDATE
, 1);
594 /* Clear All Untouched entries */
595 cpsw_ale_control_set(ale
, 0, ALE_AGEOUT
, 1);
598 if (cpsw_ale_control_get(ale
, 0, ALE_AGEOUT
))
600 } while (time_after(timeout
, jiffies
));
601 cpsw_ale_control_set(ale
, 0, ALE_AGEOUT
, 1);
603 /* Clear all mcast from ALE */
604 cpsw_ale_flush_multicast(ale
, ALE_ALL_PORTS
<<
605 priv
->host_port
, -1);
607 /* Flood All Unicast Packets to Host port */
608 cpsw_ale_control_set(ale
, 0, ALE_P0_UNI_FLOOD
, 1);
609 dev_dbg(&ndev
->dev
, "promiscuity enabled\n");
611 /* Don't Flood All Unicast Packets to Host port */
612 cpsw_ale_control_set(ale
, 0, ALE_P0_UNI_FLOOD
, 0);
614 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
615 for (i
= 0; i
<= priv
->data
.slaves
; i
++) {
616 cpsw_ale_control_set(ale
, i
,
617 ALE_PORT_NOLEARN
, 0);
618 cpsw_ale_control_set(ale
, i
,
619 ALE_PORT_NO_SA_UPDATE
, 0);
621 dev_dbg(&ndev
->dev
, "promiscuity disabled\n");
626 static void cpsw_ndo_set_rx_mode(struct net_device
*ndev
)
628 struct cpsw_priv
*priv
= netdev_priv(ndev
);
631 if (priv
->data
.dual_emac
)
632 vid
= priv
->slaves
[priv
->emac_port
].port_vlan
;
634 vid
= priv
->data
.default_vlan
;
636 if (ndev
->flags
& IFF_PROMISC
) {
637 /* Enable promiscuous mode */
638 cpsw_set_promiscious(ndev
, true);
639 cpsw_ale_set_allmulti(priv
->ale
, IFF_ALLMULTI
);
642 /* Disable promiscuous mode */
643 cpsw_set_promiscious(ndev
, false);
646 /* Restore allmulti on vlans if necessary */
647 cpsw_ale_set_allmulti(priv
->ale
, priv
->ndev
->flags
& IFF_ALLMULTI
);
649 /* Clear all mcast from ALE */
650 cpsw_ale_flush_multicast(priv
->ale
, ALE_ALL_PORTS
<< priv
->host_port
,
653 if (!netdev_mc_empty(ndev
)) {
654 struct netdev_hw_addr
*ha
;
656 /* program multicast address list into ALE register */
657 netdev_for_each_mc_addr(ha
, ndev
) {
658 cpsw_add_mcast(priv
, (u8
*)ha
->addr
);
663 static void cpsw_intr_enable(struct cpsw_priv
*priv
)
665 __raw_writel(0xFF, &priv
->wr_regs
->tx_en
);
666 __raw_writel(0xFF, &priv
->wr_regs
->rx_en
);
668 cpdma_ctlr_int_ctrl(priv
->dma
, true);
672 static void cpsw_intr_disable(struct cpsw_priv
*priv
)
674 __raw_writel(0, &priv
->wr_regs
->tx_en
);
675 __raw_writel(0, &priv
->wr_regs
->rx_en
);
677 cpdma_ctlr_int_ctrl(priv
->dma
, false);
681 static void cpsw_tx_handler(void *token
, int len
, int status
)
683 struct sk_buff
*skb
= token
;
684 struct net_device
*ndev
= skb
->dev
;
685 struct cpsw_priv
*priv
= netdev_priv(ndev
);
687 /* Check whether the queue is stopped due to stalled tx dma, if the
688 * queue is stopped then start the queue as we have free desc for tx
690 if (unlikely(netif_queue_stopped(ndev
)))
691 netif_wake_queue(ndev
);
692 cpts_tx_timestamp(priv
->cpts
, skb
);
693 ndev
->stats
.tx_packets
++;
694 ndev
->stats
.tx_bytes
+= len
;
695 dev_kfree_skb_any(skb
);
698 static void cpsw_rx_handler(void *token
, int len
, int status
)
700 struct sk_buff
*skb
= token
;
701 struct sk_buff
*new_skb
;
702 struct net_device
*ndev
= skb
->dev
;
703 struct cpsw_priv
*priv
= netdev_priv(ndev
);
706 cpsw_dual_emac_src_port_detect(status
, priv
, ndev
, skb
);
708 if (unlikely(status
< 0) || unlikely(!netif_running(ndev
))) {
709 bool ndev_status
= false;
710 struct cpsw_slave
*slave
= priv
->slaves
;
713 if (priv
->data
.dual_emac
) {
714 /* In dual emac mode check for all interfaces */
715 for (n
= priv
->data
.slaves
; n
; n
--, slave
++)
716 if (netif_running(slave
->ndev
))
720 if (ndev_status
&& (status
>= 0)) {
721 /* The packet received is for the interface which
722 * is already down and the other interface is up
723 * and running, instead of freeing which results
724 * in reducing of the number of rx descriptor in
725 * DMA engine, requeue skb back to cpdma.
731 /* the interface is going down, skbs are purged */
732 dev_kfree_skb_any(skb
);
736 new_skb
= netdev_alloc_skb_ip_align(ndev
, priv
->rx_packet_max
);
739 cpts_rx_timestamp(priv
->cpts
, skb
);
740 skb
->protocol
= eth_type_trans(skb
, ndev
);
741 netif_receive_skb(skb
);
742 ndev
->stats
.rx_bytes
+= len
;
743 ndev
->stats
.rx_packets
++;
745 ndev
->stats
.rx_dropped
++;
750 ret
= cpdma_chan_submit(priv
->rxch
, new_skb
, new_skb
->data
,
751 skb_tailroom(new_skb
), 0);
752 if (WARN_ON(ret
< 0))
753 dev_kfree_skb_any(new_skb
);
756 static irqreturn_t
cpsw_tx_interrupt(int irq
, void *dev_id
)
758 struct cpsw_priv
*priv
= dev_id
;
760 writel(0, &priv
->wr_regs
->tx_en
);
761 cpdma_ctlr_eoi(priv
->dma
, CPDMA_EOI_TX
);
763 if (priv
->quirk_irq
) {
764 disable_irq_nosync(priv
->irqs_table
[1]);
765 priv
->tx_irq_disabled
= true;
768 napi_schedule(&priv
->napi_tx
);
772 static irqreturn_t
cpsw_rx_interrupt(int irq
, void *dev_id
)
774 struct cpsw_priv
*priv
= dev_id
;
776 cpdma_ctlr_eoi(priv
->dma
, CPDMA_EOI_RX
);
777 writel(0, &priv
->wr_regs
->rx_en
);
779 if (priv
->quirk_irq
) {
780 disable_irq_nosync(priv
->irqs_table
[0]);
781 priv
->rx_irq_disabled
= true;
784 napi_schedule(&priv
->napi_rx
);
788 static int cpsw_tx_poll(struct napi_struct
*napi_tx
, int budget
)
790 struct cpsw_priv
*priv
= napi_to_priv(napi_tx
);
793 num_tx
= cpdma_chan_process(priv
->txch
, budget
);
794 if (num_tx
< budget
) {
795 napi_complete(napi_tx
);
796 writel(0xff, &priv
->wr_regs
->tx_en
);
797 if (priv
->quirk_irq
&& priv
->tx_irq_disabled
) {
798 priv
->tx_irq_disabled
= false;
799 enable_irq(priv
->irqs_table
[1]);
804 cpsw_dbg(priv
, intr
, "poll %d tx pkts\n", num_tx
);
809 static int cpsw_rx_poll(struct napi_struct
*napi_rx
, int budget
)
811 struct cpsw_priv
*priv
= napi_to_priv(napi_rx
);
814 num_rx
= cpdma_chan_process(priv
->rxch
, budget
);
815 if (num_rx
< budget
) {
816 napi_complete(napi_rx
);
817 writel(0xff, &priv
->wr_regs
->rx_en
);
818 if (priv
->quirk_irq
&& priv
->rx_irq_disabled
) {
819 priv
->rx_irq_disabled
= false;
820 enable_irq(priv
->irqs_table
[0]);
825 cpsw_dbg(priv
, intr
, "poll %d rx pkts\n", num_rx
);
830 static inline void soft_reset(const char *module
, void __iomem
*reg
)
832 unsigned long timeout
= jiffies
+ HZ
;
834 __raw_writel(1, reg
);
837 } while ((__raw_readl(reg
) & 1) && time_after(timeout
, jiffies
));
839 WARN(__raw_readl(reg
) & 1, "failed to soft-reset %s\n", module
);
842 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
843 ((mac)[2] << 16) | ((mac)[3] << 24))
844 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
846 static void cpsw_set_slave_mac(struct cpsw_slave
*slave
,
847 struct cpsw_priv
*priv
)
849 slave_write(slave
, mac_hi(priv
->mac_addr
), SA_HI
);
850 slave_write(slave
, mac_lo(priv
->mac_addr
), SA_LO
);
853 static void _cpsw_adjust_link(struct cpsw_slave
*slave
,
854 struct cpsw_priv
*priv
, bool *link
)
856 struct phy_device
*phy
= slave
->phy
;
863 slave_port
= cpsw_get_slave_port(priv
, slave
->slave_num
);
866 mac_control
= priv
->data
.mac_control
;
868 /* enable forwarding */
869 cpsw_ale_control_set(priv
->ale
, slave_port
,
870 ALE_PORT_STATE
, ALE_PORT_STATE_FORWARD
);
872 if (phy
->speed
== 1000)
873 mac_control
|= BIT(7); /* GIGABITEN */
875 mac_control
|= BIT(0); /* FULLDUPLEXEN */
877 /* set speed_in input in case RMII mode is used in 100Mbps */
878 if (phy
->speed
== 100)
879 mac_control
|= BIT(15);
880 else if (phy
->speed
== 10)
881 mac_control
|= BIT(18); /* In Band mode */
884 mac_control
|= BIT(3);
887 mac_control
|= BIT(4);
892 /* disable forwarding */
893 cpsw_ale_control_set(priv
->ale
, slave_port
,
894 ALE_PORT_STATE
, ALE_PORT_STATE_DISABLE
);
897 if (mac_control
!= slave
->mac_control
) {
898 phy_print_status(phy
);
899 __raw_writel(mac_control
, &slave
->sliver
->mac_control
);
902 slave
->mac_control
= mac_control
;
905 static void cpsw_adjust_link(struct net_device
*ndev
)
907 struct cpsw_priv
*priv
= netdev_priv(ndev
);
910 for_each_slave(priv
, _cpsw_adjust_link
, priv
, &link
);
913 netif_carrier_on(ndev
);
914 if (netif_running(ndev
))
915 netif_wake_queue(ndev
);
917 netif_carrier_off(ndev
);
918 netif_stop_queue(ndev
);
922 static int cpsw_get_coalesce(struct net_device
*ndev
,
923 struct ethtool_coalesce
*coal
)
925 struct cpsw_priv
*priv
= netdev_priv(ndev
);
927 coal
->rx_coalesce_usecs
= priv
->coal_intvl
;
931 static int cpsw_set_coalesce(struct net_device
*ndev
,
932 struct ethtool_coalesce
*coal
)
934 struct cpsw_priv
*priv
= netdev_priv(ndev
);
936 u32 num_interrupts
= 0;
941 coal_intvl
= coal
->rx_coalesce_usecs
;
943 int_ctrl
= readl(&priv
->wr_regs
->int_control
);
944 prescale
= priv
->bus_freq_mhz
* 4;
946 if (!coal
->rx_coalesce_usecs
) {
947 int_ctrl
&= ~(CPSW_INTPRESCALE_MASK
| CPSW_INTPACEEN
);
951 if (coal_intvl
< CPSW_CMINTMIN_INTVL
)
952 coal_intvl
= CPSW_CMINTMIN_INTVL
;
954 if (coal_intvl
> CPSW_CMINTMAX_INTVL
) {
955 /* Interrupt pacer works with 4us Pulse, we can
956 * throttle further by dilating the 4us pulse.
958 addnl_dvdr
= CPSW_INTPRESCALE_MASK
/ prescale
;
960 if (addnl_dvdr
> 1) {
961 prescale
*= addnl_dvdr
;
962 if (coal_intvl
> (CPSW_CMINTMAX_INTVL
* addnl_dvdr
))
963 coal_intvl
= (CPSW_CMINTMAX_INTVL
967 coal_intvl
= CPSW_CMINTMAX_INTVL
;
971 num_interrupts
= (1000 * addnl_dvdr
) / coal_intvl
;
972 writel(num_interrupts
, &priv
->wr_regs
->rx_imax
);
973 writel(num_interrupts
, &priv
->wr_regs
->tx_imax
);
975 int_ctrl
|= CPSW_INTPACEEN
;
976 int_ctrl
&= (~CPSW_INTPRESCALE_MASK
);
977 int_ctrl
|= (prescale
& CPSW_INTPRESCALE_MASK
);
980 writel(int_ctrl
, &priv
->wr_regs
->int_control
);
982 cpsw_notice(priv
, timer
, "Set coalesce to %d usecs.\n", coal_intvl
);
983 if (priv
->data
.dual_emac
) {
986 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
987 priv
= netdev_priv(priv
->slaves
[i
].ndev
);
988 priv
->coal_intvl
= coal_intvl
;
991 priv
->coal_intvl
= coal_intvl
;
997 static int cpsw_get_sset_count(struct net_device
*ndev
, int sset
)
1001 return CPSW_STATS_LEN
;
1007 static void cpsw_get_strings(struct net_device
*ndev
, u32 stringset
, u8
*data
)
1012 switch (stringset
) {
1014 for (i
= 0; i
< CPSW_STATS_LEN
; i
++) {
1015 memcpy(p
, cpsw_gstrings_stats
[i
].stat_string
,
1017 p
+= ETH_GSTRING_LEN
;
1023 static void cpsw_get_ethtool_stats(struct net_device
*ndev
,
1024 struct ethtool_stats
*stats
, u64
*data
)
1026 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1027 struct cpdma_chan_stats rx_stats
;
1028 struct cpdma_chan_stats tx_stats
;
1033 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1034 cpdma_chan_get_stats(priv
->rxch
, &rx_stats
);
1035 cpdma_chan_get_stats(priv
->txch
, &tx_stats
);
1037 for (i
= 0; i
< CPSW_STATS_LEN
; i
++) {
1038 switch (cpsw_gstrings_stats
[i
].type
) {
1040 val
= readl(priv
->hw_stats
+
1041 cpsw_gstrings_stats
[i
].stat_offset
);
1045 case CPDMA_RX_STATS
:
1046 p
= (u8
*)&rx_stats
+
1047 cpsw_gstrings_stats
[i
].stat_offset
;
1048 data
[i
] = *(u32
*)p
;
1051 case CPDMA_TX_STATS
:
1052 p
= (u8
*)&tx_stats
+
1053 cpsw_gstrings_stats
[i
].stat_offset
;
1054 data
[i
] = *(u32
*)p
;
1060 static int cpsw_common_res_usage_state(struct cpsw_priv
*priv
)
1063 u32 usage_count
= 0;
1065 if (!priv
->data
.dual_emac
)
1068 for (i
= 0; i
< priv
->data
.slaves
; i
++)
1069 if (priv
->slaves
[i
].open_stat
)
1075 static inline int cpsw_tx_packet_submit(struct net_device
*ndev
,
1076 struct cpsw_priv
*priv
, struct sk_buff
*skb
)
1078 if (!priv
->data
.dual_emac
)
1079 return cpdma_chan_submit(priv
->txch
, skb
, skb
->data
,
1082 if (ndev
== cpsw_get_slave_ndev(priv
, 0))
1083 return cpdma_chan_submit(priv
->txch
, skb
, skb
->data
,
1086 return cpdma_chan_submit(priv
->txch
, skb
, skb
->data
,
1090 static inline void cpsw_add_dual_emac_def_ale_entries(
1091 struct cpsw_priv
*priv
, struct cpsw_slave
*slave
,
1094 u32 port_mask
= 1 << slave_port
| 1 << priv
->host_port
;
1096 if (priv
->version
== CPSW_VERSION_1
)
1097 slave_write(slave
, slave
->port_vlan
, CPSW1_PORT_VLAN
);
1099 slave_write(slave
, slave
->port_vlan
, CPSW2_PORT_VLAN
);
1100 cpsw_ale_add_vlan(priv
->ale
, slave
->port_vlan
, port_mask
,
1101 port_mask
, port_mask
, 0);
1102 cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1103 port_mask
, ALE_VLAN
, slave
->port_vlan
, 0);
1104 cpsw_ale_add_ucast(priv
->ale
, priv
->mac_addr
,
1105 priv
->host_port
, ALE_VLAN
| ALE_SECURE
, slave
->port_vlan
);
1108 static void soft_reset_slave(struct cpsw_slave
*slave
)
1112 snprintf(name
, sizeof(name
), "slave-%d", slave
->slave_num
);
1113 soft_reset(name
, &slave
->sliver
->soft_reset
);
1116 static void cpsw_slave_open(struct cpsw_slave
*slave
, struct cpsw_priv
*priv
)
1120 soft_reset_slave(slave
);
1122 /* setup priority mapping */
1123 __raw_writel(RX_PRIORITY_MAPPING
, &slave
->sliver
->rx_pri_map
);
1125 switch (priv
->version
) {
1126 case CPSW_VERSION_1
:
1127 slave_write(slave
, TX_PRIORITY_MAPPING
, CPSW1_TX_PRI_MAP
);
1129 case CPSW_VERSION_2
:
1130 case CPSW_VERSION_3
:
1131 case CPSW_VERSION_4
:
1132 slave_write(slave
, TX_PRIORITY_MAPPING
, CPSW2_TX_PRI_MAP
);
1136 /* setup max packet size, and mac address */
1137 __raw_writel(priv
->rx_packet_max
, &slave
->sliver
->rx_maxlen
);
1138 cpsw_set_slave_mac(slave
, priv
);
1140 slave
->mac_control
= 0; /* no link yet */
1142 slave_port
= cpsw_get_slave_port(priv
, slave
->slave_num
);
1144 if (priv
->data
.dual_emac
)
1145 cpsw_add_dual_emac_def_ale_entries(priv
, slave
, slave_port
);
1147 cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1148 1 << slave_port
, 0, 0, ALE_MCAST_FWD_2
);
1151 slave
->phy
= of_phy_connect(priv
->ndev
, priv
->phy_node
,
1152 &cpsw_adjust_link
, 0, slave
->data
->phy_if
);
1154 slave
->phy
= phy_connect(priv
->ndev
, slave
->data
->phy_id
,
1155 &cpsw_adjust_link
, slave
->data
->phy_if
);
1156 if (IS_ERR(slave
->phy
)) {
1157 dev_err(priv
->dev
, "phy %s not found on slave %d\n",
1158 slave
->data
->phy_id
, slave
->slave_num
);
1161 dev_info(priv
->dev
, "phy found : id is : 0x%x\n",
1162 slave
->phy
->phy_id
);
1163 phy_start(slave
->phy
);
1165 /* Configure GMII_SEL register */
1166 cpsw_phy_sel(&priv
->pdev
->dev
, slave
->phy
->interface
,
1171 static inline void cpsw_add_default_vlan(struct cpsw_priv
*priv
)
1173 const int vlan
= priv
->data
.default_vlan
;
1174 const int port
= priv
->host_port
;
1177 int unreg_mcast_mask
;
1179 reg
= (priv
->version
== CPSW_VERSION_1
) ? CPSW1_PORT_VLAN
:
1182 writel(vlan
, &priv
->host_port_regs
->port_vlan
);
1184 for (i
= 0; i
< priv
->data
.slaves
; i
++)
1185 slave_write(priv
->slaves
+ i
, vlan
, reg
);
1187 if (priv
->ndev
->flags
& IFF_ALLMULTI
)
1188 unreg_mcast_mask
= ALE_ALL_PORTS
;
1190 unreg_mcast_mask
= ALE_PORT_1
| ALE_PORT_2
;
1192 cpsw_ale_add_vlan(priv
->ale
, vlan
, ALE_ALL_PORTS
<< port
,
1193 ALE_ALL_PORTS
<< port
, ALE_ALL_PORTS
<< port
,
1194 unreg_mcast_mask
<< port
);
1197 static void cpsw_init_host_port(struct cpsw_priv
*priv
)
1202 /* soft reset the controller and initialize ale */
1203 soft_reset("cpsw", &priv
->regs
->soft_reset
);
1204 cpsw_ale_start(priv
->ale
);
1206 /* switch to vlan unaware mode */
1207 cpsw_ale_control_set(priv
->ale
, priv
->host_port
, ALE_VLAN_AWARE
,
1208 CPSW_ALE_VLAN_AWARE
);
1209 control_reg
= readl(&priv
->regs
->control
);
1210 control_reg
|= CPSW_VLAN_AWARE
;
1211 writel(control_reg
, &priv
->regs
->control
);
1212 fifo_mode
= (priv
->data
.dual_emac
) ? CPSW_FIFO_DUAL_MAC_MODE
:
1213 CPSW_FIFO_NORMAL_MODE
;
1214 writel(fifo_mode
, &priv
->host_port_regs
->tx_in_ctl
);
1216 /* setup host port priority mapping */
1217 __raw_writel(CPDMA_TX_PRIORITY_MAP
,
1218 &priv
->host_port_regs
->cpdma_tx_pri_map
);
1219 __raw_writel(0, &priv
->host_port_regs
->cpdma_rx_chan_map
);
1221 cpsw_ale_control_set(priv
->ale
, priv
->host_port
,
1222 ALE_PORT_STATE
, ALE_PORT_STATE_FORWARD
);
1224 if (!priv
->data
.dual_emac
) {
1225 cpsw_ale_add_ucast(priv
->ale
, priv
->mac_addr
, priv
->host_port
,
1227 cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1228 1 << priv
->host_port
, 0, 0, ALE_MCAST_FWD_2
);
1232 static void cpsw_slave_stop(struct cpsw_slave
*slave
, struct cpsw_priv
*priv
)
1236 slave_port
= cpsw_get_slave_port(priv
, slave
->slave_num
);
1240 phy_stop(slave
->phy
);
1241 phy_disconnect(slave
->phy
);
1243 cpsw_ale_control_set(priv
->ale
, slave_port
,
1244 ALE_PORT_STATE
, ALE_PORT_STATE_DISABLE
);
1247 static int cpsw_ndo_open(struct net_device
*ndev
)
1249 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1253 if (!cpsw_common_res_usage_state(priv
))
1254 cpsw_intr_disable(priv
);
1255 netif_carrier_off(ndev
);
1257 pm_runtime_get_sync(&priv
->pdev
->dev
);
1259 reg
= priv
->version
;
1261 dev_info(priv
->dev
, "initializing cpsw version %d.%d (%d)\n",
1262 CPSW_MAJOR_VERSION(reg
), CPSW_MINOR_VERSION(reg
),
1263 CPSW_RTL_VERSION(reg
));
1265 /* initialize host and slave ports */
1266 if (!cpsw_common_res_usage_state(priv
))
1267 cpsw_init_host_port(priv
);
1268 for_each_slave(priv
, cpsw_slave_open
, priv
);
1270 /* Add default VLAN */
1271 if (!priv
->data
.dual_emac
)
1272 cpsw_add_default_vlan(priv
);
1274 cpsw_ale_add_vlan(priv
->ale
, priv
->data
.default_vlan
,
1275 ALE_ALL_PORTS
<< priv
->host_port
,
1276 ALE_ALL_PORTS
<< priv
->host_port
, 0, 0);
1278 if (!cpsw_common_res_usage_state(priv
)) {
1279 struct cpsw_priv
*priv_sl0
= cpsw_get_slave_priv(priv
, 0);
1281 /* setup tx dma to fixed prio and zero offset */
1282 cpdma_control_set(priv
->dma
, CPDMA_TX_PRIO_FIXED
, 1);
1283 cpdma_control_set(priv
->dma
, CPDMA_RX_BUFFER_OFFSET
, 0);
1285 /* disable priority elevation */
1286 __raw_writel(0, &priv
->regs
->ptype
);
1288 /* enable statistics collection only on all ports */
1289 __raw_writel(0x7, &priv
->regs
->stat_port_en
);
1291 /* Enable internal fifo flow control */
1292 writel(0x7, &priv
->regs
->flow_control
);
1294 napi_enable(&priv_sl0
->napi_rx
);
1295 napi_enable(&priv_sl0
->napi_tx
);
1297 if (priv_sl0
->tx_irq_disabled
) {
1298 priv_sl0
->tx_irq_disabled
= false;
1299 enable_irq(priv
->irqs_table
[1]);
1302 if (priv_sl0
->rx_irq_disabled
) {
1303 priv_sl0
->rx_irq_disabled
= false;
1304 enable_irq(priv
->irqs_table
[0]);
1307 if (WARN_ON(!priv
->data
.rx_descs
))
1308 priv
->data
.rx_descs
= 128;
1310 for (i
= 0; i
< priv
->data
.rx_descs
; i
++) {
1311 struct sk_buff
*skb
;
1314 skb
= __netdev_alloc_skb_ip_align(priv
->ndev
,
1315 priv
->rx_packet_max
, GFP_KERNEL
);
1318 ret
= cpdma_chan_submit(priv
->rxch
, skb
, skb
->data
,
1319 skb_tailroom(skb
), 0);
1325 /* continue even if we didn't manage to submit all
1328 cpsw_info(priv
, ifup
, "submitted %d rx descriptors\n", i
);
1330 if (cpts_register(&priv
->pdev
->dev
, priv
->cpts
,
1331 priv
->data
.cpts_clock_mult
,
1332 priv
->data
.cpts_clock_shift
))
1333 dev_err(priv
->dev
, "error registering cpts device\n");
1337 /* Enable Interrupt pacing if configured */
1338 if (priv
->coal_intvl
!= 0) {
1339 struct ethtool_coalesce coal
;
1341 coal
.rx_coalesce_usecs
= (priv
->coal_intvl
<< 4);
1342 cpsw_set_coalesce(ndev
, &coal
);
1345 cpdma_ctlr_start(priv
->dma
);
1346 cpsw_intr_enable(priv
);
1348 if (priv
->data
.dual_emac
)
1349 priv
->slaves
[priv
->emac_port
].open_stat
= true;
1353 cpdma_ctlr_stop(priv
->dma
);
1354 for_each_slave(priv
, cpsw_slave_stop
, priv
);
1355 pm_runtime_put_sync(&priv
->pdev
->dev
);
1356 netif_carrier_off(priv
->ndev
);
1360 static int cpsw_ndo_stop(struct net_device
*ndev
)
1362 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1364 cpsw_info(priv
, ifdown
, "shutting down cpsw device\n");
1365 netif_stop_queue(priv
->ndev
);
1366 netif_carrier_off(priv
->ndev
);
1368 if (cpsw_common_res_usage_state(priv
) <= 1) {
1369 struct cpsw_priv
*priv_sl0
= cpsw_get_slave_priv(priv
, 0);
1371 napi_disable(&priv_sl0
->napi_rx
);
1372 napi_disable(&priv_sl0
->napi_tx
);
1373 cpts_unregister(priv
->cpts
);
1374 cpsw_intr_disable(priv
);
1375 cpdma_ctlr_stop(priv
->dma
);
1376 cpsw_ale_stop(priv
->ale
);
1378 for_each_slave(priv
, cpsw_slave_stop
, priv
);
1379 pm_runtime_put_sync(&priv
->pdev
->dev
);
1380 if (priv
->data
.dual_emac
)
1381 priv
->slaves
[priv
->emac_port
].open_stat
= false;
1385 static netdev_tx_t
cpsw_ndo_start_xmit(struct sk_buff
*skb
,
1386 struct net_device
*ndev
)
1388 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1391 ndev
->trans_start
= jiffies
;
1393 if (skb_padto(skb
, CPSW_MIN_PACKET_SIZE
)) {
1394 cpsw_err(priv
, tx_err
, "packet pad failed\n");
1395 ndev
->stats
.tx_dropped
++;
1396 return NETDEV_TX_OK
;
1399 if (skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
&&
1400 priv
->cpts
->tx_enable
)
1401 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
1403 skb_tx_timestamp(skb
);
1405 ret
= cpsw_tx_packet_submit(ndev
, priv
, skb
);
1406 if (unlikely(ret
!= 0)) {
1407 cpsw_err(priv
, tx_err
, "desc submit failed\n");
1411 /* If there is no more tx desc left free then we need to
1412 * tell the kernel to stop sending us tx frames.
1414 if (unlikely(!cpdma_check_free_tx_desc(priv
->txch
)))
1415 netif_stop_queue(ndev
);
1417 return NETDEV_TX_OK
;
1419 ndev
->stats
.tx_dropped
++;
1420 netif_stop_queue(ndev
);
1421 return NETDEV_TX_BUSY
;
1424 #ifdef CONFIG_TI_CPTS
1426 static void cpsw_hwtstamp_v1(struct cpsw_priv
*priv
)
1428 struct cpsw_slave
*slave
= &priv
->slaves
[priv
->data
.active_slave
];
1431 if (!priv
->cpts
->tx_enable
&& !priv
->cpts
->rx_enable
) {
1432 slave_write(slave
, 0, CPSW1_TS_CTL
);
1436 seq_id
= (30 << CPSW_V1_SEQ_ID_OFS_SHIFT
) | ETH_P_1588
;
1437 ts_en
= EVENT_MSG_BITS
<< CPSW_V1_MSG_TYPE_OFS
;
1439 if (priv
->cpts
->tx_enable
)
1440 ts_en
|= CPSW_V1_TS_TX_EN
;
1442 if (priv
->cpts
->rx_enable
)
1443 ts_en
|= CPSW_V1_TS_RX_EN
;
1445 slave_write(slave
, ts_en
, CPSW1_TS_CTL
);
1446 slave_write(slave
, seq_id
, CPSW1_TS_SEQ_LTYPE
);
1449 static void cpsw_hwtstamp_v2(struct cpsw_priv
*priv
)
1451 struct cpsw_slave
*slave
;
1454 if (priv
->data
.dual_emac
)
1455 slave
= &priv
->slaves
[priv
->emac_port
];
1457 slave
= &priv
->slaves
[priv
->data
.active_slave
];
1459 ctrl
= slave_read(slave
, CPSW2_CONTROL
);
1460 switch (priv
->version
) {
1461 case CPSW_VERSION_2
:
1462 ctrl
&= ~CTRL_V2_ALL_TS_MASK
;
1464 if (priv
->cpts
->tx_enable
)
1465 ctrl
|= CTRL_V2_TX_TS_BITS
;
1467 if (priv
->cpts
->rx_enable
)
1468 ctrl
|= CTRL_V2_RX_TS_BITS
;
1470 case CPSW_VERSION_3
:
1472 ctrl
&= ~CTRL_V3_ALL_TS_MASK
;
1474 if (priv
->cpts
->tx_enable
)
1475 ctrl
|= CTRL_V3_TX_TS_BITS
;
1477 if (priv
->cpts
->rx_enable
)
1478 ctrl
|= CTRL_V3_RX_TS_BITS
;
1482 mtype
= (30 << TS_SEQ_ID_OFFSET_SHIFT
) | EVENT_MSG_BITS
;
1484 slave_write(slave
, mtype
, CPSW2_TS_SEQ_MTYPE
);
1485 slave_write(slave
, ctrl
, CPSW2_CONTROL
);
1486 __raw_writel(ETH_P_1588
, &priv
->regs
->ts_ltype
);
1489 static int cpsw_hwtstamp_set(struct net_device
*dev
, struct ifreq
*ifr
)
1491 struct cpsw_priv
*priv
= netdev_priv(dev
);
1492 struct cpts
*cpts
= priv
->cpts
;
1493 struct hwtstamp_config cfg
;
1495 if (priv
->version
!= CPSW_VERSION_1
&&
1496 priv
->version
!= CPSW_VERSION_2
&&
1497 priv
->version
!= CPSW_VERSION_3
)
1500 if (copy_from_user(&cfg
, ifr
->ifr_data
, sizeof(cfg
)))
1503 /* reserved for future extensions */
1507 if (cfg
.tx_type
!= HWTSTAMP_TX_OFF
&& cfg
.tx_type
!= HWTSTAMP_TX_ON
)
1510 switch (cfg
.rx_filter
) {
1511 case HWTSTAMP_FILTER_NONE
:
1512 cpts
->rx_enable
= 0;
1514 case HWTSTAMP_FILTER_ALL
:
1515 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
1516 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
1517 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
1519 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
1520 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
1521 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
1522 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
1523 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
1524 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
1525 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
1526 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
1527 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
1528 cpts
->rx_enable
= 1;
1529 cfg
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
1535 cpts
->tx_enable
= cfg
.tx_type
== HWTSTAMP_TX_ON
;
1537 switch (priv
->version
) {
1538 case CPSW_VERSION_1
:
1539 cpsw_hwtstamp_v1(priv
);
1541 case CPSW_VERSION_2
:
1542 case CPSW_VERSION_3
:
1543 cpsw_hwtstamp_v2(priv
);
1549 return copy_to_user(ifr
->ifr_data
, &cfg
, sizeof(cfg
)) ? -EFAULT
: 0;
1552 static int cpsw_hwtstamp_get(struct net_device
*dev
, struct ifreq
*ifr
)
1554 struct cpsw_priv
*priv
= netdev_priv(dev
);
1555 struct cpts
*cpts
= priv
->cpts
;
1556 struct hwtstamp_config cfg
;
1558 if (priv
->version
!= CPSW_VERSION_1
&&
1559 priv
->version
!= CPSW_VERSION_2
&&
1560 priv
->version
!= CPSW_VERSION_3
)
1564 cfg
.tx_type
= cpts
->tx_enable
? HWTSTAMP_TX_ON
: HWTSTAMP_TX_OFF
;
1565 cfg
.rx_filter
= (cpts
->rx_enable
?
1566 HWTSTAMP_FILTER_PTP_V2_EVENT
: HWTSTAMP_FILTER_NONE
);
1568 return copy_to_user(ifr
->ifr_data
, &cfg
, sizeof(cfg
)) ? -EFAULT
: 0;
1571 #endif /*CONFIG_TI_CPTS*/
1573 static int cpsw_ndo_ioctl(struct net_device
*dev
, struct ifreq
*req
, int cmd
)
1575 struct cpsw_priv
*priv
= netdev_priv(dev
);
1576 int slave_no
= cpsw_slave_index(priv
);
1578 if (!netif_running(dev
))
1582 #ifdef CONFIG_TI_CPTS
1584 return cpsw_hwtstamp_set(dev
, req
);
1586 return cpsw_hwtstamp_get(dev
, req
);
1590 if (!priv
->slaves
[slave_no
].phy
)
1592 return phy_mii_ioctl(priv
->slaves
[slave_no
].phy
, req
, cmd
);
1595 static void cpsw_ndo_tx_timeout(struct net_device
*ndev
)
1597 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1599 cpsw_err(priv
, tx_err
, "transmit timeout, restarting dma\n");
1600 ndev
->stats
.tx_errors
++;
1601 cpsw_intr_disable(priv
);
1602 cpdma_chan_stop(priv
->txch
);
1603 cpdma_chan_start(priv
->txch
);
1604 cpsw_intr_enable(priv
);
1607 static int cpsw_ndo_set_mac_address(struct net_device
*ndev
, void *p
)
1609 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1610 struct sockaddr
*addr
= (struct sockaddr
*)p
;
1614 if (!is_valid_ether_addr(addr
->sa_data
))
1615 return -EADDRNOTAVAIL
;
1617 if (priv
->data
.dual_emac
) {
1618 vid
= priv
->slaves
[priv
->emac_port
].port_vlan
;
1622 cpsw_ale_del_ucast(priv
->ale
, priv
->mac_addr
, priv
->host_port
,
1624 cpsw_ale_add_ucast(priv
->ale
, addr
->sa_data
, priv
->host_port
,
1627 memcpy(priv
->mac_addr
, addr
->sa_data
, ETH_ALEN
);
1628 memcpy(ndev
->dev_addr
, priv
->mac_addr
, ETH_ALEN
);
1629 for_each_slave(priv
, cpsw_set_slave_mac
, priv
);
1634 #ifdef CONFIG_NET_POLL_CONTROLLER
1635 static void cpsw_ndo_poll_controller(struct net_device
*ndev
)
1637 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1639 cpsw_intr_disable(priv
);
1640 cpsw_rx_interrupt(priv
->irqs_table
[0], priv
);
1641 cpsw_tx_interrupt(priv
->irqs_table
[1], priv
);
1642 cpsw_intr_enable(priv
);
1646 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv
*priv
,
1650 int unreg_mcast_mask
= 0;
1653 if (priv
->data
.dual_emac
) {
1654 port_mask
= (1 << (priv
->emac_port
+ 1)) | ALE_PORT_HOST
;
1656 if (priv
->ndev
->flags
& IFF_ALLMULTI
)
1657 unreg_mcast_mask
= port_mask
;
1659 port_mask
= ALE_ALL_PORTS
;
1661 if (priv
->ndev
->flags
& IFF_ALLMULTI
)
1662 unreg_mcast_mask
= ALE_ALL_PORTS
;
1664 unreg_mcast_mask
= ALE_PORT_1
| ALE_PORT_2
;
1667 ret
= cpsw_ale_add_vlan(priv
->ale
, vid
, port_mask
, 0, port_mask
,
1668 unreg_mcast_mask
<< priv
->host_port
);
1672 ret
= cpsw_ale_add_ucast(priv
->ale
, priv
->mac_addr
,
1673 priv
->host_port
, ALE_VLAN
, vid
);
1677 ret
= cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1678 port_mask
, ALE_VLAN
, vid
, 0);
1680 goto clean_vlan_ucast
;
1684 cpsw_ale_del_ucast(priv
->ale
, priv
->mac_addr
,
1685 priv
->host_port
, ALE_VLAN
, vid
);
1687 cpsw_ale_del_vlan(priv
->ale
, vid
, 0);
1691 static int cpsw_ndo_vlan_rx_add_vid(struct net_device
*ndev
,
1692 __be16 proto
, u16 vid
)
1694 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1696 if (vid
== priv
->data
.default_vlan
)
1699 if (priv
->data
.dual_emac
) {
1700 /* In dual EMAC, reserved VLAN id should not be used for
1701 * creating VLAN interfaces as this can break the dual
1702 * EMAC port separation
1706 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
1707 if (vid
== priv
->slaves
[i
].port_vlan
)
1712 dev_info(priv
->dev
, "Adding vlanid %d to vlan filter\n", vid
);
1713 return cpsw_add_vlan_ale_entry(priv
, vid
);
1716 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device
*ndev
,
1717 __be16 proto
, u16 vid
)
1719 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1722 if (vid
== priv
->data
.default_vlan
)
1725 if (priv
->data
.dual_emac
) {
1728 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
1729 if (vid
== priv
->slaves
[i
].port_vlan
)
1734 dev_info(priv
->dev
, "removing vlanid %d from vlan filter\n", vid
);
1735 ret
= cpsw_ale_del_vlan(priv
->ale
, vid
, 0);
1739 ret
= cpsw_ale_del_ucast(priv
->ale
, priv
->mac_addr
,
1740 priv
->host_port
, ALE_VLAN
, vid
);
1744 return cpsw_ale_del_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1748 static const struct net_device_ops cpsw_netdev_ops
= {
1749 .ndo_open
= cpsw_ndo_open
,
1750 .ndo_stop
= cpsw_ndo_stop
,
1751 .ndo_start_xmit
= cpsw_ndo_start_xmit
,
1752 .ndo_set_mac_address
= cpsw_ndo_set_mac_address
,
1753 .ndo_do_ioctl
= cpsw_ndo_ioctl
,
1754 .ndo_validate_addr
= eth_validate_addr
,
1755 .ndo_change_mtu
= eth_change_mtu
,
1756 .ndo_tx_timeout
= cpsw_ndo_tx_timeout
,
1757 .ndo_set_rx_mode
= cpsw_ndo_set_rx_mode
,
1758 #ifdef CONFIG_NET_POLL_CONTROLLER
1759 .ndo_poll_controller
= cpsw_ndo_poll_controller
,
1761 .ndo_vlan_rx_add_vid
= cpsw_ndo_vlan_rx_add_vid
,
1762 .ndo_vlan_rx_kill_vid
= cpsw_ndo_vlan_rx_kill_vid
,
1765 static int cpsw_get_regs_len(struct net_device
*ndev
)
1767 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1769 return priv
->data
.ale_entries
* ALE_ENTRY_WORDS
* sizeof(u32
);
1772 static void cpsw_get_regs(struct net_device
*ndev
,
1773 struct ethtool_regs
*regs
, void *p
)
1775 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1778 /* update CPSW IP version */
1779 regs
->version
= priv
->version
;
1781 cpsw_ale_dump(priv
->ale
, reg
);
1784 static void cpsw_get_drvinfo(struct net_device
*ndev
,
1785 struct ethtool_drvinfo
*info
)
1787 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1789 strlcpy(info
->driver
, "cpsw", sizeof(info
->driver
));
1790 strlcpy(info
->version
, "1.0", sizeof(info
->version
));
1791 strlcpy(info
->bus_info
, priv
->pdev
->name
, sizeof(info
->bus_info
));
1792 info
->regdump_len
= cpsw_get_regs_len(ndev
);
1795 static u32
cpsw_get_msglevel(struct net_device
*ndev
)
1797 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1798 return priv
->msg_enable
;
1801 static void cpsw_set_msglevel(struct net_device
*ndev
, u32 value
)
1803 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1804 priv
->msg_enable
= value
;
1807 static int cpsw_get_ts_info(struct net_device
*ndev
,
1808 struct ethtool_ts_info
*info
)
1810 #ifdef CONFIG_TI_CPTS
1811 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1813 info
->so_timestamping
=
1814 SOF_TIMESTAMPING_TX_HARDWARE
|
1815 SOF_TIMESTAMPING_TX_SOFTWARE
|
1816 SOF_TIMESTAMPING_RX_HARDWARE
|
1817 SOF_TIMESTAMPING_RX_SOFTWARE
|
1818 SOF_TIMESTAMPING_SOFTWARE
|
1819 SOF_TIMESTAMPING_RAW_HARDWARE
;
1820 info
->phc_index
= priv
->cpts
->phc_index
;
1822 (1 << HWTSTAMP_TX_OFF
) |
1823 (1 << HWTSTAMP_TX_ON
);
1825 (1 << HWTSTAMP_FILTER_NONE
) |
1826 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT
);
1828 info
->so_timestamping
=
1829 SOF_TIMESTAMPING_TX_SOFTWARE
|
1830 SOF_TIMESTAMPING_RX_SOFTWARE
|
1831 SOF_TIMESTAMPING_SOFTWARE
;
1832 info
->phc_index
= -1;
1834 info
->rx_filters
= 0;
1839 static int cpsw_get_settings(struct net_device
*ndev
,
1840 struct ethtool_cmd
*ecmd
)
1842 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1843 int slave_no
= cpsw_slave_index(priv
);
1845 if (priv
->slaves
[slave_no
].phy
)
1846 return phy_ethtool_gset(priv
->slaves
[slave_no
].phy
, ecmd
);
1851 static int cpsw_set_settings(struct net_device
*ndev
, struct ethtool_cmd
*ecmd
)
1853 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1854 int slave_no
= cpsw_slave_index(priv
);
1856 if (priv
->slaves
[slave_no
].phy
)
1857 return phy_ethtool_sset(priv
->slaves
[slave_no
].phy
, ecmd
);
1862 static void cpsw_get_wol(struct net_device
*ndev
, struct ethtool_wolinfo
*wol
)
1864 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1865 int slave_no
= cpsw_slave_index(priv
);
1870 if (priv
->slaves
[slave_no
].phy
)
1871 phy_ethtool_get_wol(priv
->slaves
[slave_no
].phy
, wol
);
1874 static int cpsw_set_wol(struct net_device
*ndev
, struct ethtool_wolinfo
*wol
)
1876 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1877 int slave_no
= cpsw_slave_index(priv
);
1879 if (priv
->slaves
[slave_no
].phy
)
1880 return phy_ethtool_set_wol(priv
->slaves
[slave_no
].phy
, wol
);
1885 static void cpsw_get_pauseparam(struct net_device
*ndev
,
1886 struct ethtool_pauseparam
*pause
)
1888 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1890 pause
->autoneg
= AUTONEG_DISABLE
;
1891 pause
->rx_pause
= priv
->rx_pause
? true : false;
1892 pause
->tx_pause
= priv
->tx_pause
? true : false;
1895 static int cpsw_set_pauseparam(struct net_device
*ndev
,
1896 struct ethtool_pauseparam
*pause
)
1898 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1901 priv
->rx_pause
= pause
->rx_pause
? true : false;
1902 priv
->tx_pause
= pause
->tx_pause
? true : false;
1904 for_each_slave(priv
, _cpsw_adjust_link
, priv
, &link
);
1909 static const struct ethtool_ops cpsw_ethtool_ops
= {
1910 .get_drvinfo
= cpsw_get_drvinfo
,
1911 .get_msglevel
= cpsw_get_msglevel
,
1912 .set_msglevel
= cpsw_set_msglevel
,
1913 .get_link
= ethtool_op_get_link
,
1914 .get_ts_info
= cpsw_get_ts_info
,
1915 .get_settings
= cpsw_get_settings
,
1916 .set_settings
= cpsw_set_settings
,
1917 .get_coalesce
= cpsw_get_coalesce
,
1918 .set_coalesce
= cpsw_set_coalesce
,
1919 .get_sset_count
= cpsw_get_sset_count
,
1920 .get_strings
= cpsw_get_strings
,
1921 .get_ethtool_stats
= cpsw_get_ethtool_stats
,
1922 .get_pauseparam
= cpsw_get_pauseparam
,
1923 .set_pauseparam
= cpsw_set_pauseparam
,
1924 .get_wol
= cpsw_get_wol
,
1925 .set_wol
= cpsw_set_wol
,
1926 .get_regs_len
= cpsw_get_regs_len
,
1927 .get_regs
= cpsw_get_regs
,
1930 static void cpsw_slave_init(struct cpsw_slave
*slave
, struct cpsw_priv
*priv
,
1931 u32 slave_reg_ofs
, u32 sliver_reg_ofs
)
1933 void __iomem
*regs
= priv
->regs
;
1934 int slave_num
= slave
->slave_num
;
1935 struct cpsw_slave_data
*data
= priv
->data
.slave_data
+ slave_num
;
1938 slave
->regs
= regs
+ slave_reg_ofs
;
1939 slave
->sliver
= regs
+ sliver_reg_ofs
;
1940 slave
->port_vlan
= data
->dual_emac_res_vlan
;
1943 static int cpsw_probe_dt(struct cpsw_priv
*priv
,
1944 struct platform_device
*pdev
)
1946 struct device_node
*node
= pdev
->dev
.of_node
;
1947 struct device_node
*slave_node
;
1948 struct cpsw_platform_data
*data
= &priv
->data
;
1955 if (of_property_read_u32(node
, "slaves", &prop
)) {
1956 dev_err(&pdev
->dev
, "Missing slaves property in the DT.\n");
1959 data
->slaves
= prop
;
1961 if (of_property_read_u32(node
, "active_slave", &prop
)) {
1962 dev_err(&pdev
->dev
, "Missing active_slave property in the DT.\n");
1965 data
->active_slave
= prop
;
1967 if (of_property_read_u32(node
, "cpts_clock_mult", &prop
)) {
1968 dev_err(&pdev
->dev
, "Missing cpts_clock_mult property in the DT.\n");
1971 data
->cpts_clock_mult
= prop
;
1973 if (of_property_read_u32(node
, "cpts_clock_shift", &prop
)) {
1974 dev_err(&pdev
->dev
, "Missing cpts_clock_shift property in the DT.\n");
1977 data
->cpts_clock_shift
= prop
;
1979 data
->slave_data
= devm_kzalloc(&pdev
->dev
, data
->slaves
1980 * sizeof(struct cpsw_slave_data
),
1982 if (!data
->slave_data
)
1985 if (of_property_read_u32(node
, "cpdma_channels", &prop
)) {
1986 dev_err(&pdev
->dev
, "Missing cpdma_channels property in the DT.\n");
1989 data
->channels
= prop
;
1991 if (of_property_read_u32(node
, "ale_entries", &prop
)) {
1992 dev_err(&pdev
->dev
, "Missing ale_entries property in the DT.\n");
1995 data
->ale_entries
= prop
;
1997 if (of_property_read_u32(node
, "bd_ram_size", &prop
)) {
1998 dev_err(&pdev
->dev
, "Missing bd_ram_size property in the DT.\n");
2001 data
->bd_ram_size
= prop
;
2003 if (of_property_read_u32(node
, "rx_descs", &prop
)) {
2004 dev_err(&pdev
->dev
, "Missing rx_descs property in the DT.\n");
2007 data
->rx_descs
= prop
;
2009 if (of_property_read_u32(node
, "mac_control", &prop
)) {
2010 dev_err(&pdev
->dev
, "Missing mac_control property in the DT.\n");
2013 data
->mac_control
= prop
;
2015 if (of_property_read_bool(node
, "dual_emac"))
2016 data
->dual_emac
= 1;
2019 * Populate all the child nodes here...
2021 ret
= of_platform_populate(node
, NULL
, NULL
, &pdev
->dev
);
2022 /* We do not want to force this, as in some cases may not have child */
2024 dev_warn(&pdev
->dev
, "Doesn't have any child node\n");
2026 for_each_child_of_node(node
, slave_node
) {
2027 struct cpsw_slave_data
*slave_data
= data
->slave_data
+ i
;
2028 const void *mac_addr
= NULL
;
2032 struct device_node
*mdio_node
;
2033 struct platform_device
*mdio
;
2035 /* This is no slave child node, continue */
2036 if (strcmp(slave_node
->name
, "slave"))
2039 priv
->phy_node
= of_parse_phandle(slave_node
, "phy-handle", 0);
2040 parp
= of_get_property(slave_node
, "phy_id", &lenp
);
2041 if ((parp
== NULL
) || (lenp
!= (sizeof(void *) * 2))) {
2042 dev_err(&pdev
->dev
, "Missing slave[%d] phy_id property\n", i
);
2045 mdio_node
= of_find_node_by_phandle(be32_to_cpup(parp
));
2046 phyid
= be32_to_cpup(parp
+1);
2047 mdio
= of_find_device_by_node(mdio_node
);
2048 of_node_put(mdio_node
);
2050 dev_err(&pdev
->dev
, "Missing mdio platform device\n");
2053 snprintf(slave_data
->phy_id
, sizeof(slave_data
->phy_id
),
2054 PHY_ID_FMT
, mdio
->name
, phyid
);
2055 slave_data
->phy_if
= of_get_phy_mode(slave_node
);
2056 if (slave_data
->phy_if
< 0) {
2057 dev_err(&pdev
->dev
, "Missing or malformed slave[%d] phy-mode property\n",
2059 return slave_data
->phy_if
;
2063 mac_addr
= of_get_mac_address(slave_node
);
2065 memcpy(slave_data
->mac_addr
, mac_addr
, ETH_ALEN
);
2067 if (of_machine_is_compatible("ti,am33xx")) {
2068 ret
= cpsw_am33xx_cm_get_macid(&pdev
->dev
,
2070 slave_data
->mac_addr
);
2075 if (data
->dual_emac
) {
2076 if (of_property_read_u32(slave_node
, "dual_emac_res_vlan",
2078 dev_err(&pdev
->dev
, "Missing dual_emac_res_vlan in DT.\n");
2079 slave_data
->dual_emac_res_vlan
= i
+1;
2080 dev_err(&pdev
->dev
, "Using %d as Reserved VLAN for %d slave\n",
2081 slave_data
->dual_emac_res_vlan
, i
);
2083 slave_data
->dual_emac_res_vlan
= prop
;
2088 if (i
== data
->slaves
)
2095 static int cpsw_probe_dual_emac(struct platform_device
*pdev
,
2096 struct cpsw_priv
*priv
)
2098 struct cpsw_platform_data
*data
= &priv
->data
;
2099 struct net_device
*ndev
;
2100 struct cpsw_priv
*priv_sl2
;
2103 ndev
= alloc_etherdev(sizeof(struct cpsw_priv
));
2105 dev_err(&pdev
->dev
, "cpsw: error allocating net_device\n");
2109 priv_sl2
= netdev_priv(ndev
);
2110 spin_lock_init(&priv_sl2
->lock
);
2111 priv_sl2
->data
= *data
;
2112 priv_sl2
->pdev
= pdev
;
2113 priv_sl2
->ndev
= ndev
;
2114 priv_sl2
->dev
= &ndev
->dev
;
2115 priv_sl2
->msg_enable
= netif_msg_init(debug_level
, CPSW_DEBUG
);
2116 priv_sl2
->rx_packet_max
= max(rx_packet_max
, 128);
2118 if (is_valid_ether_addr(data
->slave_data
[1].mac_addr
)) {
2119 memcpy(priv_sl2
->mac_addr
, data
->slave_data
[1].mac_addr
,
2121 dev_info(&pdev
->dev
, "cpsw: Detected MACID = %pM\n", priv_sl2
->mac_addr
);
2123 random_ether_addr(priv_sl2
->mac_addr
);
2124 dev_info(&pdev
->dev
, "cpsw: Random MACID = %pM\n", priv_sl2
->mac_addr
);
2126 memcpy(ndev
->dev_addr
, priv_sl2
->mac_addr
, ETH_ALEN
);
2128 priv_sl2
->slaves
= priv
->slaves
;
2129 priv_sl2
->clk
= priv
->clk
;
2131 priv_sl2
->coal_intvl
= 0;
2132 priv_sl2
->bus_freq_mhz
= priv
->bus_freq_mhz
;
2134 priv_sl2
->regs
= priv
->regs
;
2135 priv_sl2
->host_port
= priv
->host_port
;
2136 priv_sl2
->host_port_regs
= priv
->host_port_regs
;
2137 priv_sl2
->wr_regs
= priv
->wr_regs
;
2138 priv_sl2
->hw_stats
= priv
->hw_stats
;
2139 priv_sl2
->dma
= priv
->dma
;
2140 priv_sl2
->txch
= priv
->txch
;
2141 priv_sl2
->rxch
= priv
->rxch
;
2142 priv_sl2
->ale
= priv
->ale
;
2143 priv_sl2
->emac_port
= 1;
2144 priv
->slaves
[1].ndev
= ndev
;
2145 priv_sl2
->cpts
= priv
->cpts
;
2146 priv_sl2
->version
= priv
->version
;
2148 for (i
= 0; i
< priv
->num_irqs
; i
++) {
2149 priv_sl2
->irqs_table
[i
] = priv
->irqs_table
[i
];
2150 priv_sl2
->num_irqs
= priv
->num_irqs
;
2152 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
2154 ndev
->netdev_ops
= &cpsw_netdev_ops
;
2155 ndev
->ethtool_ops
= &cpsw_ethtool_ops
;
2157 /* register the network device */
2158 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
2159 ret
= register_netdev(ndev
);
2161 dev_err(&pdev
->dev
, "cpsw: error registering net device\n");
2169 #define CPSW_QUIRK_IRQ BIT(0)
2171 static struct platform_device_id cpsw_devtype
[] = {
2173 /* keep it for existing comaptibles */
2175 .driver_data
= CPSW_QUIRK_IRQ
,
2177 .name
= "am335x-cpsw",
2178 .driver_data
= CPSW_QUIRK_IRQ
,
2180 .name
= "am4372-cpsw",
2183 .name
= "dra7-cpsw",
2189 MODULE_DEVICE_TABLE(platform
, cpsw_devtype
);
2198 static const struct of_device_id cpsw_of_mtable
[] = {
2199 { .compatible
= "ti,cpsw", .data
= &cpsw_devtype
[CPSW
], },
2200 { .compatible
= "ti,am335x-cpsw", .data
= &cpsw_devtype
[AM335X_CPSW
], },
2201 { .compatible
= "ti,am4372-cpsw", .data
= &cpsw_devtype
[AM4372_CPSW
], },
2202 { .compatible
= "ti,dra7-cpsw", .data
= &cpsw_devtype
[DRA7_CPSW
], },
2205 MODULE_DEVICE_TABLE(of
, cpsw_of_mtable
);
2207 static int cpsw_probe(struct platform_device
*pdev
)
2209 struct cpsw_platform_data
*data
;
2210 struct net_device
*ndev
;
2211 struct cpsw_priv
*priv
;
2212 struct cpdma_params dma_params
;
2213 struct cpsw_ale_params ale_params
;
2214 void __iomem
*ss_regs
;
2215 struct resource
*res
, *ss_res
;
2216 const struct of_device_id
*of_id
;
2217 u32 slave_offset
, sliver_offset
, slave_size
;
2221 ndev
= alloc_etherdev(sizeof(struct cpsw_priv
));
2223 dev_err(&pdev
->dev
, "error allocating net_device\n");
2227 platform_set_drvdata(pdev
, ndev
);
2228 priv
= netdev_priv(ndev
);
2229 spin_lock_init(&priv
->lock
);
2232 priv
->dev
= &ndev
->dev
;
2233 priv
->msg_enable
= netif_msg_init(debug_level
, CPSW_DEBUG
);
2234 priv
->rx_packet_max
= max(rx_packet_max
, 128);
2235 priv
->cpts
= devm_kzalloc(&pdev
->dev
, sizeof(struct cpts
), GFP_KERNEL
);
2237 dev_err(&pdev
->dev
, "error allocating cpts\n");
2239 goto clean_ndev_ret
;
2243 * This may be required here for child devices.
2245 pm_runtime_enable(&pdev
->dev
);
2247 /* Select default pin state */
2248 pinctrl_pm_select_default_state(&pdev
->dev
);
2250 if (cpsw_probe_dt(priv
, pdev
)) {
2251 dev_err(&pdev
->dev
, "cpsw: platform data missing\n");
2253 goto clean_runtime_disable_ret
;
2257 if (is_valid_ether_addr(data
->slave_data
[0].mac_addr
)) {
2258 memcpy(priv
->mac_addr
, data
->slave_data
[0].mac_addr
, ETH_ALEN
);
2259 dev_info(&pdev
->dev
, "Detected MACID = %pM\n", priv
->mac_addr
);
2261 eth_random_addr(priv
->mac_addr
);
2262 dev_info(&pdev
->dev
, "Random MACID = %pM\n", priv
->mac_addr
);
2265 memcpy(ndev
->dev_addr
, priv
->mac_addr
, ETH_ALEN
);
2267 priv
->slaves
= devm_kzalloc(&pdev
->dev
,
2268 sizeof(struct cpsw_slave
) * data
->slaves
,
2270 if (!priv
->slaves
) {
2272 goto clean_runtime_disable_ret
;
2274 for (i
= 0; i
< data
->slaves
; i
++)
2275 priv
->slaves
[i
].slave_num
= i
;
2277 priv
->slaves
[0].ndev
= ndev
;
2278 priv
->emac_port
= 0;
2280 priv
->clk
= devm_clk_get(&pdev
->dev
, "fck");
2281 if (IS_ERR(priv
->clk
)) {
2282 dev_err(priv
->dev
, "fck is not found\n");
2284 goto clean_runtime_disable_ret
;
2286 priv
->coal_intvl
= 0;
2287 priv
->bus_freq_mhz
= clk_get_rate(priv
->clk
) / 1000000;
2289 ss_res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2290 ss_regs
= devm_ioremap_resource(&pdev
->dev
, ss_res
);
2291 if (IS_ERR(ss_regs
)) {
2292 ret
= PTR_ERR(ss_regs
);
2293 goto clean_runtime_disable_ret
;
2295 priv
->regs
= ss_regs
;
2296 priv
->host_port
= HOST_PORT_NUM
;
2298 /* Need to enable clocks with runtime PM api to access module
2301 pm_runtime_get_sync(&pdev
->dev
);
2302 priv
->version
= readl(&priv
->regs
->id_ver
);
2303 pm_runtime_put_sync(&pdev
->dev
);
2305 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
2306 priv
->wr_regs
= devm_ioremap_resource(&pdev
->dev
, res
);
2307 if (IS_ERR(priv
->wr_regs
)) {
2308 ret
= PTR_ERR(priv
->wr_regs
);
2309 goto clean_runtime_disable_ret
;
2312 memset(&dma_params
, 0, sizeof(dma_params
));
2313 memset(&ale_params
, 0, sizeof(ale_params
));
2315 switch (priv
->version
) {
2316 case CPSW_VERSION_1
:
2317 priv
->host_port_regs
= ss_regs
+ CPSW1_HOST_PORT_OFFSET
;
2318 priv
->cpts
->reg
= ss_regs
+ CPSW1_CPTS_OFFSET
;
2319 priv
->hw_stats
= ss_regs
+ CPSW1_HW_STATS
;
2320 dma_params
.dmaregs
= ss_regs
+ CPSW1_CPDMA_OFFSET
;
2321 dma_params
.txhdp
= ss_regs
+ CPSW1_STATERAM_OFFSET
;
2322 ale_params
.ale_regs
= ss_regs
+ CPSW1_ALE_OFFSET
;
2323 slave_offset
= CPSW1_SLAVE_OFFSET
;
2324 slave_size
= CPSW1_SLAVE_SIZE
;
2325 sliver_offset
= CPSW1_SLIVER_OFFSET
;
2326 dma_params
.desc_mem_phys
= 0;
2328 case CPSW_VERSION_2
:
2329 case CPSW_VERSION_3
:
2330 case CPSW_VERSION_4
:
2331 priv
->host_port_regs
= ss_regs
+ CPSW2_HOST_PORT_OFFSET
;
2332 priv
->cpts
->reg
= ss_regs
+ CPSW2_CPTS_OFFSET
;
2333 priv
->hw_stats
= ss_regs
+ CPSW2_HW_STATS
;
2334 dma_params
.dmaregs
= ss_regs
+ CPSW2_CPDMA_OFFSET
;
2335 dma_params
.txhdp
= ss_regs
+ CPSW2_STATERAM_OFFSET
;
2336 ale_params
.ale_regs
= ss_regs
+ CPSW2_ALE_OFFSET
;
2337 slave_offset
= CPSW2_SLAVE_OFFSET
;
2338 slave_size
= CPSW2_SLAVE_SIZE
;
2339 sliver_offset
= CPSW2_SLIVER_OFFSET
;
2340 dma_params
.desc_mem_phys
=
2341 (u32 __force
) ss_res
->start
+ CPSW2_BD_OFFSET
;
2344 dev_err(priv
->dev
, "unknown version 0x%08x\n", priv
->version
);
2346 goto clean_runtime_disable_ret
;
2348 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
2349 struct cpsw_slave
*slave
= &priv
->slaves
[i
];
2350 cpsw_slave_init(slave
, priv
, slave_offset
, sliver_offset
);
2351 slave_offset
+= slave_size
;
2352 sliver_offset
+= SLIVER_SIZE
;
2355 dma_params
.dev
= &pdev
->dev
;
2356 dma_params
.rxthresh
= dma_params
.dmaregs
+ CPDMA_RXTHRESH
;
2357 dma_params
.rxfree
= dma_params
.dmaregs
+ CPDMA_RXFREE
;
2358 dma_params
.rxhdp
= dma_params
.txhdp
+ CPDMA_RXHDP
;
2359 dma_params
.txcp
= dma_params
.txhdp
+ CPDMA_TXCP
;
2360 dma_params
.rxcp
= dma_params
.txhdp
+ CPDMA_RXCP
;
2362 dma_params
.num_chan
= data
->channels
;
2363 dma_params
.has_soft_reset
= true;
2364 dma_params
.min_packet_size
= CPSW_MIN_PACKET_SIZE
;
2365 dma_params
.desc_mem_size
= data
->bd_ram_size
;
2366 dma_params
.desc_align
= 16;
2367 dma_params
.has_ext_regs
= true;
2368 dma_params
.desc_hw_addr
= dma_params
.desc_mem_phys
;
2370 priv
->dma
= cpdma_ctlr_create(&dma_params
);
2372 dev_err(priv
->dev
, "error initializing dma\n");
2374 goto clean_runtime_disable_ret
;
2377 priv
->txch
= cpdma_chan_create(priv
->dma
, tx_chan_num(0),
2379 priv
->rxch
= cpdma_chan_create(priv
->dma
, rx_chan_num(0),
2382 if (WARN_ON(!priv
->txch
|| !priv
->rxch
)) {
2383 dev_err(priv
->dev
, "error initializing dma channels\n");
2388 ale_params
.dev
= &ndev
->dev
;
2389 ale_params
.ale_ageout
= ale_ageout
;
2390 ale_params
.ale_entries
= data
->ale_entries
;
2391 ale_params
.ale_ports
= data
->slaves
;
2393 priv
->ale
= cpsw_ale_create(&ale_params
);
2395 dev_err(priv
->dev
, "error initializing ale engine\n");
2400 ndev
->irq
= platform_get_irq(pdev
, 1);
2401 if (ndev
->irq
< 0) {
2402 dev_err(priv
->dev
, "error getting irq resource\n");
2407 of_id
= of_match_device(cpsw_of_mtable
, &pdev
->dev
);
2409 pdev
->id_entry
= of_id
->data
;
2410 if (pdev
->id_entry
->driver_data
)
2411 priv
->quirk_irq
= true;
2414 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2415 * MISC IRQs which are always kept disabled with this driver so
2416 * we will not request them.
2418 * If anyone wants to implement support for those, make sure to
2419 * first request and append them to irqs_table array.
2423 irq
= platform_get_irq(pdev
, 1);
2427 priv
->irqs_table
[0] = irq
;
2428 ret
= devm_request_irq(&pdev
->dev
, irq
, cpsw_rx_interrupt
,
2429 0, dev_name(&pdev
->dev
), priv
);
2431 dev_err(priv
->dev
, "error attaching irq (%d)\n", ret
);
2436 irq
= platform_get_irq(pdev
, 2);
2440 priv
->irqs_table
[1] = irq
;
2441 ret
= devm_request_irq(&pdev
->dev
, irq
, cpsw_tx_interrupt
,
2442 0, dev_name(&pdev
->dev
), priv
);
2444 dev_err(priv
->dev
, "error attaching irq (%d)\n", ret
);
2449 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
2451 ndev
->netdev_ops
= &cpsw_netdev_ops
;
2452 ndev
->ethtool_ops
= &cpsw_ethtool_ops
;
2453 netif_napi_add(ndev
, &priv
->napi_rx
, cpsw_rx_poll
, CPSW_POLL_WEIGHT
);
2454 netif_napi_add(ndev
, &priv
->napi_tx
, cpsw_tx_poll
, CPSW_POLL_WEIGHT
);
2456 /* register the network device */
2457 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
2458 ret
= register_netdev(ndev
);
2460 dev_err(priv
->dev
, "error registering net device\n");
2465 cpsw_notice(priv
, probe
, "initialized device (regs %pa, irq %d)\n",
2466 &ss_res
->start
, ndev
->irq
);
2468 if (priv
->data
.dual_emac
) {
2469 ret
= cpsw_probe_dual_emac(pdev
, priv
);
2471 cpsw_err(priv
, probe
, "error probe slave 2 emac interface\n");
2479 cpsw_ale_destroy(priv
->ale
);
2481 cpdma_chan_destroy(priv
->txch
);
2482 cpdma_chan_destroy(priv
->rxch
);
2483 cpdma_ctlr_destroy(priv
->dma
);
2484 clean_runtime_disable_ret
:
2485 pm_runtime_disable(&pdev
->dev
);
2487 free_netdev(priv
->ndev
);
2491 static int cpsw_remove_child_device(struct device
*dev
, void *c
)
2493 struct platform_device
*pdev
= to_platform_device(dev
);
2495 of_device_unregister(pdev
);
2500 static int cpsw_remove(struct platform_device
*pdev
)
2502 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2503 struct cpsw_priv
*priv
= netdev_priv(ndev
);
2505 if (priv
->data
.dual_emac
)
2506 unregister_netdev(cpsw_get_slave_ndev(priv
, 1));
2507 unregister_netdev(ndev
);
2509 cpsw_ale_destroy(priv
->ale
);
2510 cpdma_chan_destroy(priv
->txch
);
2511 cpdma_chan_destroy(priv
->rxch
);
2512 cpdma_ctlr_destroy(priv
->dma
);
2513 pm_runtime_disable(&pdev
->dev
);
2514 device_for_each_child(&pdev
->dev
, NULL
, cpsw_remove_child_device
);
2515 if (priv
->data
.dual_emac
)
2516 free_netdev(cpsw_get_slave_ndev(priv
, 1));
2521 #ifdef CONFIG_PM_SLEEP
2522 static int cpsw_suspend(struct device
*dev
)
2524 struct platform_device
*pdev
= to_platform_device(dev
);
2525 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2526 struct cpsw_priv
*priv
= netdev_priv(ndev
);
2528 if (priv
->data
.dual_emac
) {
2531 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
2532 if (netif_running(priv
->slaves
[i
].ndev
))
2533 cpsw_ndo_stop(priv
->slaves
[i
].ndev
);
2534 soft_reset_slave(priv
->slaves
+ i
);
2537 if (netif_running(ndev
))
2538 cpsw_ndo_stop(ndev
);
2539 for_each_slave(priv
, soft_reset_slave
);
2542 pm_runtime_put_sync(&pdev
->dev
);
2544 /* Select sleep pin state */
2545 pinctrl_pm_select_sleep_state(&pdev
->dev
);
2550 static int cpsw_resume(struct device
*dev
)
2552 struct platform_device
*pdev
= to_platform_device(dev
);
2553 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2554 struct cpsw_priv
*priv
= netdev_priv(ndev
);
2556 pm_runtime_get_sync(&pdev
->dev
);
2558 /* Select default pin state */
2559 pinctrl_pm_select_default_state(&pdev
->dev
);
2561 if (priv
->data
.dual_emac
) {
2564 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
2565 if (netif_running(priv
->slaves
[i
].ndev
))
2566 cpsw_ndo_open(priv
->slaves
[i
].ndev
);
2569 if (netif_running(ndev
))
2570 cpsw_ndo_open(ndev
);
2576 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops
, cpsw_suspend
, cpsw_resume
);
2578 static struct platform_driver cpsw_driver
= {
2582 .of_match_table
= cpsw_of_mtable
,
2584 .probe
= cpsw_probe
,
2585 .remove
= cpsw_remove
,
2588 static int __init
cpsw_init(void)
2590 return platform_driver_register(&cpsw_driver
);
2592 late_initcall(cpsw_init
);
2594 static void __exit
cpsw_exit(void)
2596 platform_driver_unregister(&cpsw_driver
);
2598 module_exit(cpsw_exit
);
2600 MODULE_LICENSE("GPL");
2601 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2602 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2603 MODULE_DESCRIPTION("TI CPSW Ethernet driver");