2 * Texas Instruments Ethernet Switch Driver
4 * Copyright (C) 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
33 #include <linux/of_net.h>
34 #include <linux/of_device.h>
35 #include <linux/if_vlan.h>
37 #include <linux/pinctrl/consumer.h>
42 #include "davinci_cpdma.h"
44 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
45 NETIF_MSG_DRV | NETIF_MSG_LINK | \
46 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
47 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
48 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
49 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
50 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 #define cpsw_info(priv, type, format, ...) \
55 if (netif_msg_##type(priv) && net_ratelimit()) \
56 dev_info(priv->dev, format, ## __VA_ARGS__); \
59 #define cpsw_err(priv, type, format, ...) \
61 if (netif_msg_##type(priv) && net_ratelimit()) \
62 dev_err(priv->dev, format, ## __VA_ARGS__); \
65 #define cpsw_dbg(priv, type, format, ...) \
67 if (netif_msg_##type(priv) && net_ratelimit()) \
68 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71 #define cpsw_notice(priv, type, format, ...) \
73 if (netif_msg_##type(priv) && net_ratelimit()) \
74 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77 #define ALE_ALL_PORTS 0x7
79 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
80 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
81 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
83 #define CPSW_VERSION_1 0x19010a
84 #define CPSW_VERSION_2 0x19010c
85 #define CPSW_VERSION_3 0x19010f
86 #define CPSW_VERSION_4 0x190112
88 #define HOST_PORT_NUM 0
89 #define SLIVER_SIZE 0x40
91 #define CPSW1_HOST_PORT_OFFSET 0x028
92 #define CPSW1_SLAVE_OFFSET 0x050
93 #define CPSW1_SLAVE_SIZE 0x040
94 #define CPSW1_CPDMA_OFFSET 0x100
95 #define CPSW1_STATERAM_OFFSET 0x200
96 #define CPSW1_HW_STATS 0x400
97 #define CPSW1_CPTS_OFFSET 0x500
98 #define CPSW1_ALE_OFFSET 0x600
99 #define CPSW1_SLIVER_OFFSET 0x700
101 #define CPSW2_HOST_PORT_OFFSET 0x108
102 #define CPSW2_SLAVE_OFFSET 0x200
103 #define CPSW2_SLAVE_SIZE 0x100
104 #define CPSW2_CPDMA_OFFSET 0x800
105 #define CPSW2_HW_STATS 0x900
106 #define CPSW2_STATERAM_OFFSET 0xa00
107 #define CPSW2_CPTS_OFFSET 0xc00
108 #define CPSW2_ALE_OFFSET 0xd00
109 #define CPSW2_SLIVER_OFFSET 0xd80
110 #define CPSW2_BD_OFFSET 0x2000
112 #define CPDMA_RXTHRESH 0x0c0
113 #define CPDMA_RXFREE 0x0e0
114 #define CPDMA_TXHDP 0x00
115 #define CPDMA_RXHDP 0x20
116 #define CPDMA_TXCP 0x40
117 #define CPDMA_RXCP 0x60
119 #define CPSW_POLL_WEIGHT 64
120 #define CPSW_MIN_PACKET_SIZE 60
121 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
123 #define RX_PRIORITY_MAPPING 0x76543210
124 #define TX_PRIORITY_MAPPING 0x33221100
125 #define CPDMA_TX_PRIORITY_MAP 0x76543210
127 #define CPSW_VLAN_AWARE BIT(1)
128 #define CPSW_ALE_VLAN_AWARE 1
130 #define CPSW_FIFO_NORMAL_MODE (0 << 15)
131 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15)
132 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15)
134 #define CPSW_INTPACEEN (0x3f << 16)
135 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
136 #define CPSW_CMINTMAX_CNT 63
137 #define CPSW_CMINTMIN_CNT 2
138 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
139 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
141 #define cpsw_enable_irq(priv) \
144 for (i = 0; i < priv->num_irqs; i++) \
145 enable_irq(priv->irqs_table[i]); \
147 #define cpsw_disable_irq(priv) \
150 for (i = 0; i < priv->num_irqs; i++) \
151 disable_irq_nosync(priv->irqs_table[i]); \
154 #define cpsw_slave_index(priv) \
155 ((priv->data.dual_emac) ? priv->emac_port : \
156 priv->data.active_slave)
158 static int debug_level
;
159 module_param(debug_level
, int, 0);
160 MODULE_PARM_DESC(debug_level
, "cpsw debug level (NETIF_MSG bits)");
162 static int ale_ageout
= 10;
163 module_param(ale_ageout
, int, 0);
164 MODULE_PARM_DESC(ale_ageout
, "cpsw ale ageout interval (seconds)");
166 static int rx_packet_max
= CPSW_MAX_PACKET_SIZE
;
167 module_param(rx_packet_max
, int, 0);
168 MODULE_PARM_DESC(rx_packet_max
, "maximum receive packet size (bytes)");
170 struct cpsw_wr_regs
{
190 struct cpsw_ss_regs
{
207 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
208 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
209 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
210 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
211 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
212 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
213 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
214 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
217 #define CPSW2_CONTROL 0x00 /* Control Register */
218 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
219 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
220 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
221 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
222 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
223 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
225 /* CPSW_PORT_V1 and V2 */
226 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
227 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
228 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
230 /* CPSW_PORT_V2 only */
231 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
232 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
233 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
234 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
235 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
236 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
237 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
238 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
240 /* Bit definitions for the CPSW2_CONTROL register */
241 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
242 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
243 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
244 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
245 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
246 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
247 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
248 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
249 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
250 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
251 #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */
252 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
253 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
254 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
255 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
256 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
258 #define CTRL_TS_BITS \
259 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
260 TS_ANNEX_D_EN | TS_LTYPE1_EN)
262 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
263 #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN)
264 #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN)
266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
269 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270 #define TS_MSG_TYPE_EN_MASK (0xffff)
272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
275 /* Bit definitions for the CPSW1_TS_CTL register */
276 #define CPSW_V1_TS_RX_EN BIT(0)
277 #define CPSW_V1_TS_TX_EN BIT(4)
278 #define CPSW_V1_MSG_TYPE_OFS 16
280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
283 struct cpsw_host_regs
{
289 u32 cpdma_tx_pri_map
;
290 u32 cpdma_rx_chan_map
;
293 struct cpsw_sliver_regs
{
306 struct cpsw_hw_stats
{
308 u32 rxbroadcastframes
;
309 u32 rxmulticastframes
;
312 u32 rxaligncodeerrors
;
313 u32 rxoversizedframes
;
315 u32 rxundersizedframes
;
320 u32 txbroadcastframes
;
321 u32 txmulticastframes
;
323 u32 txdeferredframes
;
324 u32 txcollisionframes
;
325 u32 txsinglecollframes
;
326 u32 txmultcollframes
;
327 u32 txexcessivecollisions
;
328 u32 txlatecollisions
;
330 u32 txcarriersenseerrors
;
333 u32 octetframes65t127
;
334 u32 octetframes128t255
;
335 u32 octetframes256t511
;
336 u32 octetframes512t1023
;
337 u32 octetframes1024tup
;
346 struct cpsw_sliver_regs __iomem
*sliver
;
349 struct cpsw_slave_data
*data
;
350 struct phy_device
*phy
;
351 struct net_device
*ndev
;
356 static inline u32
slave_read(struct cpsw_slave
*slave
, u32 offset
)
358 return __raw_readl(slave
->regs
+ offset
);
361 static inline void slave_write(struct cpsw_slave
*slave
, u32 val
, u32 offset
)
363 __raw_writel(val
, slave
->regs
+ offset
);
368 struct platform_device
*pdev
;
369 struct net_device
*ndev
;
370 struct napi_struct napi
;
372 struct cpsw_platform_data data
;
373 struct cpsw_ss_regs __iomem
*regs
;
374 struct cpsw_wr_regs __iomem
*wr_regs
;
375 u8 __iomem
*hw_stats
;
376 struct cpsw_host_regs __iomem
*host_port_regs
;
381 struct net_device_stats stats
;
385 u8 mac_addr
[ETH_ALEN
];
386 struct cpsw_slave
*slaves
;
387 struct cpdma_ctlr
*dma
;
388 struct cpdma_chan
*txch
, *rxch
;
389 struct cpsw_ale
*ale
;
390 /* snapshot of IRQ numbers */
399 char stat_string
[ETH_GSTRING_LEN
];
411 #define CPSW_STAT(m) CPSW_STATS, \
412 sizeof(((struct cpsw_hw_stats *)0)->m), \
413 offsetof(struct cpsw_hw_stats, m)
414 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
415 sizeof(((struct cpdma_chan_stats *)0)->m), \
416 offsetof(struct cpdma_chan_stats, m)
417 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
418 sizeof(((struct cpdma_chan_stats *)0)->m), \
419 offsetof(struct cpdma_chan_stats, m)
421 static const struct cpsw_stats cpsw_gstrings_stats
[] = {
422 { "Good Rx Frames", CPSW_STAT(rxgoodframes
) },
423 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes
) },
424 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes
) },
425 { "Pause Rx Frames", CPSW_STAT(rxpauseframes
) },
426 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors
) },
427 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors
) },
428 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes
) },
429 { "Rx Jabbers", CPSW_STAT(rxjabberframes
) },
430 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes
) },
431 { "Rx Fragments", CPSW_STAT(rxfragments
) },
432 { "Rx Octets", CPSW_STAT(rxoctets
) },
433 { "Good Tx Frames", CPSW_STAT(txgoodframes
) },
434 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes
) },
435 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes
) },
436 { "Pause Tx Frames", CPSW_STAT(txpauseframes
) },
437 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes
) },
438 { "Collisions", CPSW_STAT(txcollisionframes
) },
439 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes
) },
440 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes
) },
441 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions
) },
442 { "Late Collisions", CPSW_STAT(txlatecollisions
) },
443 { "Tx Underrun", CPSW_STAT(txunderrun
) },
444 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors
) },
445 { "Tx Octets", CPSW_STAT(txoctets
) },
446 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64
) },
447 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127
) },
448 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255
) },
449 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511
) },
450 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023
) },
451 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup
) },
452 { "Net Octets", CPSW_STAT(netoctets
) },
453 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns
) },
454 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns
) },
455 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns
) },
456 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue
) },
457 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue
) },
458 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue
) },
459 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued
) },
460 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail
) },
461 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail
) },
462 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff
) },
463 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff
) },
464 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue
) },
465 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue
) },
466 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue
) },
467 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue
) },
468 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue
) },
469 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue
) },
470 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue
) },
471 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue
) },
472 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued
) },
473 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail
) },
474 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail
) },
475 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff
) },
476 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff
) },
477 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue
) },
478 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue
) },
479 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue
) },
480 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue
) },
481 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue
) },
484 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
486 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
487 #define for_each_slave(priv, func, arg...) \
489 struct cpsw_slave *slave; \
491 if (priv->data.dual_emac) \
492 (func)((priv)->slaves + priv->emac_port, ##arg);\
494 for (n = (priv)->data.slaves, \
495 slave = (priv)->slaves; \
497 (func)(slave++, ##arg); \
499 #define cpsw_get_slave_ndev(priv, __slave_no__) \
500 (priv->slaves[__slave_no__].ndev)
501 #define cpsw_get_slave_priv(priv, __slave_no__) \
502 ((priv->slaves[__slave_no__].ndev) ? \
503 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
505 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
507 if (!priv->data.dual_emac) \
509 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
510 ndev = cpsw_get_slave_ndev(priv, 0); \
511 priv = netdev_priv(ndev); \
513 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
514 ndev = cpsw_get_slave_ndev(priv, 1); \
515 priv = netdev_priv(ndev); \
519 #define cpsw_add_mcast(priv, addr) \
521 if (priv->data.dual_emac) { \
522 struct cpsw_slave *slave = priv->slaves + \
524 int slave_port = cpsw_get_slave_port(priv, \
526 cpsw_ale_add_mcast(priv->ale, addr, \
527 1 << slave_port | 1 << priv->host_port, \
528 ALE_VLAN, slave->port_vlan, 0); \
530 cpsw_ale_add_mcast(priv->ale, addr, \
531 ALE_ALL_PORTS << priv->host_port, \
536 static inline int cpsw_get_slave_port(struct cpsw_priv
*priv
, u32 slave_num
)
538 if (priv
->host_port
== 0)
539 return slave_num
+ 1;
544 static void cpsw_set_promiscious(struct net_device
*ndev
, bool enable
)
546 struct cpsw_priv
*priv
= netdev_priv(ndev
);
547 struct cpsw_ale
*ale
= priv
->ale
;
550 if (priv
->data
.dual_emac
) {
553 /* Enabling promiscuous mode for one interface will be
554 * common for both the interface as the interface shares
555 * the same hardware resource.
557 for (i
= 0; i
< priv
->data
.slaves
; i
++)
558 if (priv
->slaves
[i
].ndev
->flags
& IFF_PROMISC
)
561 if (!enable
&& flag
) {
563 dev_err(&ndev
->dev
, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
568 cpsw_ale_control_set(ale
, 0, ALE_BYPASS
, 1);
570 dev_dbg(&ndev
->dev
, "promiscuity enabled\n");
573 cpsw_ale_control_set(ale
, 0, ALE_BYPASS
, 0);
574 dev_dbg(&ndev
->dev
, "promiscuity disabled\n");
578 unsigned long timeout
= jiffies
+ HZ
;
580 /* Disable Learn for all ports */
581 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
582 cpsw_ale_control_set(ale
, i
,
583 ALE_PORT_NOLEARN
, 1);
584 cpsw_ale_control_set(ale
, i
,
585 ALE_PORT_NO_SA_UPDATE
, 1);
588 /* Clear All Untouched entries */
589 cpsw_ale_control_set(ale
, 0, ALE_AGEOUT
, 1);
592 if (cpsw_ale_control_get(ale
, 0, ALE_AGEOUT
))
594 } while (time_after(timeout
, jiffies
));
595 cpsw_ale_control_set(ale
, 0, ALE_AGEOUT
, 1);
597 /* Clear all mcast from ALE */
598 cpsw_ale_flush_multicast(ale
, ALE_ALL_PORTS
<<
601 /* Flood All Unicast Packets to Host port */
602 cpsw_ale_control_set(ale
, 0, ALE_P0_UNI_FLOOD
, 1);
603 dev_dbg(&ndev
->dev
, "promiscuity enabled\n");
605 /* Flood All Unicast Packets to Host port */
606 cpsw_ale_control_set(ale
, 0, ALE_P0_UNI_FLOOD
, 0);
608 /* Enable Learn for all ports */
609 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
610 cpsw_ale_control_set(ale
, i
,
611 ALE_PORT_NOLEARN
, 0);
612 cpsw_ale_control_set(ale
, i
,
613 ALE_PORT_NO_SA_UPDATE
, 0);
615 dev_dbg(&ndev
->dev
, "promiscuity disabled\n");
620 static void cpsw_ndo_set_rx_mode(struct net_device
*ndev
)
622 struct cpsw_priv
*priv
= netdev_priv(ndev
);
624 if (ndev
->flags
& IFF_PROMISC
) {
625 /* Enable promiscuous mode */
626 cpsw_set_promiscious(ndev
, true);
629 /* Disable promiscuous mode */
630 cpsw_set_promiscious(ndev
, false);
633 /* Clear all mcast from ALE */
634 cpsw_ale_flush_multicast(priv
->ale
, ALE_ALL_PORTS
<< priv
->host_port
);
636 if (!netdev_mc_empty(ndev
)) {
637 struct netdev_hw_addr
*ha
;
639 /* program multicast address list into ALE register */
640 netdev_for_each_mc_addr(ha
, ndev
) {
641 cpsw_add_mcast(priv
, (u8
*)ha
->addr
);
646 static void cpsw_intr_enable(struct cpsw_priv
*priv
)
648 __raw_writel(0xFF, &priv
->wr_regs
->tx_en
);
649 __raw_writel(0xFF, &priv
->wr_regs
->rx_en
);
651 cpdma_ctlr_int_ctrl(priv
->dma
, true);
655 static void cpsw_intr_disable(struct cpsw_priv
*priv
)
657 __raw_writel(0, &priv
->wr_regs
->tx_en
);
658 __raw_writel(0, &priv
->wr_regs
->rx_en
);
660 cpdma_ctlr_int_ctrl(priv
->dma
, false);
664 static void cpsw_tx_handler(void *token
, int len
, int status
)
666 struct sk_buff
*skb
= token
;
667 struct net_device
*ndev
= skb
->dev
;
668 struct cpsw_priv
*priv
= netdev_priv(ndev
);
670 /* Check whether the queue is stopped due to stalled tx dma, if the
671 * queue is stopped then start the queue as we have free desc for tx
673 if (unlikely(netif_queue_stopped(ndev
)))
674 netif_wake_queue(ndev
);
675 cpts_tx_timestamp(priv
->cpts
, skb
);
676 priv
->stats
.tx_packets
++;
677 priv
->stats
.tx_bytes
+= len
;
678 dev_kfree_skb_any(skb
);
681 static void cpsw_rx_handler(void *token
, int len
, int status
)
683 struct sk_buff
*skb
= token
;
684 struct sk_buff
*new_skb
;
685 struct net_device
*ndev
= skb
->dev
;
686 struct cpsw_priv
*priv
= netdev_priv(ndev
);
689 cpsw_dual_emac_src_port_detect(status
, priv
, ndev
, skb
);
691 if (unlikely(status
< 0)) {
692 /* the interface is going down, skbs are purged */
693 dev_kfree_skb_any(skb
);
697 new_skb
= netdev_alloc_skb_ip_align(ndev
, priv
->rx_packet_max
);
700 cpts_rx_timestamp(priv
->cpts
, skb
);
701 skb
->protocol
= eth_type_trans(skb
, ndev
);
702 netif_receive_skb(skb
);
703 priv
->stats
.rx_bytes
+= len
;
704 priv
->stats
.rx_packets
++;
706 priv
->stats
.rx_dropped
++;
710 ret
= cpdma_chan_submit(priv
->rxch
, new_skb
, new_skb
->data
,
711 skb_tailroom(new_skb
), 0);
712 if (WARN_ON(ret
< 0))
713 dev_kfree_skb_any(new_skb
);
716 static irqreturn_t
cpsw_interrupt(int irq
, void *dev_id
)
718 struct cpsw_priv
*priv
= dev_id
;
720 cpsw_intr_disable(priv
);
721 if (priv
->irq_enabled
== true) {
722 cpsw_disable_irq(priv
);
723 priv
->irq_enabled
= false;
726 if (netif_running(priv
->ndev
)) {
727 napi_schedule(&priv
->napi
);
731 priv
= cpsw_get_slave_priv(priv
, 1);
735 if (netif_running(priv
->ndev
)) {
736 napi_schedule(&priv
->napi
);
742 static int cpsw_poll(struct napi_struct
*napi
, int budget
)
744 struct cpsw_priv
*priv
= napi_to_priv(napi
);
747 num_tx
= cpdma_chan_process(priv
->txch
, 128);
749 cpdma_ctlr_eoi(priv
->dma
, CPDMA_EOI_TX
);
751 num_rx
= cpdma_chan_process(priv
->rxch
, budget
);
752 if (num_rx
< budget
) {
753 struct cpsw_priv
*prim_cpsw
;
756 cpsw_intr_enable(priv
);
757 cpdma_ctlr_eoi(priv
->dma
, CPDMA_EOI_RX
);
758 prim_cpsw
= cpsw_get_slave_priv(priv
, 0);
759 if (prim_cpsw
->irq_enabled
== false) {
760 prim_cpsw
->irq_enabled
= true;
761 cpsw_enable_irq(priv
);
765 if (num_rx
|| num_tx
)
766 cpsw_dbg(priv
, intr
, "poll %d rx, %d tx pkts\n",
772 static inline void soft_reset(const char *module
, void __iomem
*reg
)
774 unsigned long timeout
= jiffies
+ HZ
;
776 __raw_writel(1, reg
);
779 } while ((__raw_readl(reg
) & 1) && time_after(timeout
, jiffies
));
781 WARN(__raw_readl(reg
) & 1, "failed to soft-reset %s\n", module
);
784 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
785 ((mac)[2] << 16) | ((mac)[3] << 24))
786 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
788 static void cpsw_set_slave_mac(struct cpsw_slave
*slave
,
789 struct cpsw_priv
*priv
)
791 slave_write(slave
, mac_hi(priv
->mac_addr
), SA_HI
);
792 slave_write(slave
, mac_lo(priv
->mac_addr
), SA_LO
);
795 static void _cpsw_adjust_link(struct cpsw_slave
*slave
,
796 struct cpsw_priv
*priv
, bool *link
)
798 struct phy_device
*phy
= slave
->phy
;
805 slave_port
= cpsw_get_slave_port(priv
, slave
->slave_num
);
808 mac_control
= priv
->data
.mac_control
;
810 /* enable forwarding */
811 cpsw_ale_control_set(priv
->ale
, slave_port
,
812 ALE_PORT_STATE
, ALE_PORT_STATE_FORWARD
);
814 if (phy
->speed
== 1000)
815 mac_control
|= BIT(7); /* GIGABITEN */
817 mac_control
|= BIT(0); /* FULLDUPLEXEN */
819 /* set speed_in input in case RMII mode is used in 100Mbps */
820 if (phy
->speed
== 100)
821 mac_control
|= BIT(15);
822 else if (phy
->speed
== 10)
823 mac_control
|= BIT(18); /* In Band mode */
828 /* disable forwarding */
829 cpsw_ale_control_set(priv
->ale
, slave_port
,
830 ALE_PORT_STATE
, ALE_PORT_STATE_DISABLE
);
833 if (mac_control
!= slave
->mac_control
) {
834 phy_print_status(phy
);
835 __raw_writel(mac_control
, &slave
->sliver
->mac_control
);
838 slave
->mac_control
= mac_control
;
841 static void cpsw_adjust_link(struct net_device
*ndev
)
843 struct cpsw_priv
*priv
= netdev_priv(ndev
);
846 for_each_slave(priv
, _cpsw_adjust_link
, priv
, &link
);
849 netif_carrier_on(ndev
);
850 if (netif_running(ndev
))
851 netif_wake_queue(ndev
);
853 netif_carrier_off(ndev
);
854 netif_stop_queue(ndev
);
858 static int cpsw_get_coalesce(struct net_device
*ndev
,
859 struct ethtool_coalesce
*coal
)
861 struct cpsw_priv
*priv
= netdev_priv(ndev
);
863 coal
->rx_coalesce_usecs
= priv
->coal_intvl
;
867 static int cpsw_set_coalesce(struct net_device
*ndev
,
868 struct ethtool_coalesce
*coal
)
870 struct cpsw_priv
*priv
= netdev_priv(ndev
);
872 u32 num_interrupts
= 0;
877 if (!coal
->rx_coalesce_usecs
)
880 coal_intvl
= coal
->rx_coalesce_usecs
;
882 int_ctrl
= readl(&priv
->wr_regs
->int_control
);
883 prescale
= priv
->bus_freq_mhz
* 4;
885 if (coal_intvl
< CPSW_CMINTMIN_INTVL
)
886 coal_intvl
= CPSW_CMINTMIN_INTVL
;
888 if (coal_intvl
> CPSW_CMINTMAX_INTVL
) {
889 /* Interrupt pacer works with 4us Pulse, we can
890 * throttle further by dilating the 4us pulse.
892 addnl_dvdr
= CPSW_INTPRESCALE_MASK
/ prescale
;
894 if (addnl_dvdr
> 1) {
895 prescale
*= addnl_dvdr
;
896 if (coal_intvl
> (CPSW_CMINTMAX_INTVL
* addnl_dvdr
))
897 coal_intvl
= (CPSW_CMINTMAX_INTVL
901 coal_intvl
= CPSW_CMINTMAX_INTVL
;
905 num_interrupts
= (1000 * addnl_dvdr
) / coal_intvl
;
906 writel(num_interrupts
, &priv
->wr_regs
->rx_imax
);
907 writel(num_interrupts
, &priv
->wr_regs
->tx_imax
);
909 int_ctrl
|= CPSW_INTPACEEN
;
910 int_ctrl
&= (~CPSW_INTPRESCALE_MASK
);
911 int_ctrl
|= (prescale
& CPSW_INTPRESCALE_MASK
);
912 writel(int_ctrl
, &priv
->wr_regs
->int_control
);
914 cpsw_notice(priv
, timer
, "Set coalesce to %d usecs.\n", coal_intvl
);
915 if (priv
->data
.dual_emac
) {
918 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
919 priv
= netdev_priv(priv
->slaves
[i
].ndev
);
920 priv
->coal_intvl
= coal_intvl
;
923 priv
->coal_intvl
= coal_intvl
;
929 static int cpsw_get_sset_count(struct net_device
*ndev
, int sset
)
933 return CPSW_STATS_LEN
;
939 static void cpsw_get_strings(struct net_device
*ndev
, u32 stringset
, u8
*data
)
946 for (i
= 0; i
< CPSW_STATS_LEN
; i
++) {
947 memcpy(p
, cpsw_gstrings_stats
[i
].stat_string
,
949 p
+= ETH_GSTRING_LEN
;
955 static void cpsw_get_ethtool_stats(struct net_device
*ndev
,
956 struct ethtool_stats
*stats
, u64
*data
)
958 struct cpsw_priv
*priv
= netdev_priv(ndev
);
959 struct cpdma_chan_stats rx_stats
;
960 struct cpdma_chan_stats tx_stats
;
965 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
966 cpdma_chan_get_stats(priv
->rxch
, &rx_stats
);
967 cpdma_chan_get_stats(priv
->txch
, &tx_stats
);
969 for (i
= 0; i
< CPSW_STATS_LEN
; i
++) {
970 switch (cpsw_gstrings_stats
[i
].type
) {
972 val
= readl(priv
->hw_stats
+
973 cpsw_gstrings_stats
[i
].stat_offset
);
978 p
= (u8
*)&rx_stats
+
979 cpsw_gstrings_stats
[i
].stat_offset
;
984 p
= (u8
*)&tx_stats
+
985 cpsw_gstrings_stats
[i
].stat_offset
;
992 static inline int __show_stat(char *buf
, int maxlen
, const char *name
, u32 val
)
994 static char *leader
= "........................................";
999 return snprintf(buf
, maxlen
, "%s %s %10d\n", name
,
1000 leader
+ strlen(name
), val
);
1003 static int cpsw_common_res_usage_state(struct cpsw_priv
*priv
)
1006 u32 usage_count
= 0;
1008 if (!priv
->data
.dual_emac
)
1011 for (i
= 0; i
< priv
->data
.slaves
; i
++)
1012 if (priv
->slaves
[i
].open_stat
)
1018 static inline int cpsw_tx_packet_submit(struct net_device
*ndev
,
1019 struct cpsw_priv
*priv
, struct sk_buff
*skb
)
1021 if (!priv
->data
.dual_emac
)
1022 return cpdma_chan_submit(priv
->txch
, skb
, skb
->data
,
1025 if (ndev
== cpsw_get_slave_ndev(priv
, 0))
1026 return cpdma_chan_submit(priv
->txch
, skb
, skb
->data
,
1029 return cpdma_chan_submit(priv
->txch
, skb
, skb
->data
,
1033 static inline void cpsw_add_dual_emac_def_ale_entries(
1034 struct cpsw_priv
*priv
, struct cpsw_slave
*slave
,
1037 u32 port_mask
= 1 << slave_port
| 1 << priv
->host_port
;
1039 if (priv
->version
== CPSW_VERSION_1
)
1040 slave_write(slave
, slave
->port_vlan
, CPSW1_PORT_VLAN
);
1042 slave_write(slave
, slave
->port_vlan
, CPSW2_PORT_VLAN
);
1043 cpsw_ale_add_vlan(priv
->ale
, slave
->port_vlan
, port_mask
,
1044 port_mask
, port_mask
, 0);
1045 cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1046 port_mask
, ALE_VLAN
, slave
->port_vlan
, 0);
1047 cpsw_ale_add_ucast(priv
->ale
, priv
->mac_addr
,
1048 priv
->host_port
, ALE_VLAN
, slave
->port_vlan
);
1051 static void soft_reset_slave(struct cpsw_slave
*slave
)
1055 snprintf(name
, sizeof(name
), "slave-%d", slave
->slave_num
);
1056 soft_reset(name
, &slave
->sliver
->soft_reset
);
1059 static void cpsw_slave_open(struct cpsw_slave
*slave
, struct cpsw_priv
*priv
)
1063 soft_reset_slave(slave
);
1065 /* setup priority mapping */
1066 __raw_writel(RX_PRIORITY_MAPPING
, &slave
->sliver
->rx_pri_map
);
1068 switch (priv
->version
) {
1069 case CPSW_VERSION_1
:
1070 slave_write(slave
, TX_PRIORITY_MAPPING
, CPSW1_TX_PRI_MAP
);
1072 case CPSW_VERSION_2
:
1073 case CPSW_VERSION_3
:
1074 case CPSW_VERSION_4
:
1075 slave_write(slave
, TX_PRIORITY_MAPPING
, CPSW2_TX_PRI_MAP
);
1079 /* setup max packet size, and mac address */
1080 __raw_writel(priv
->rx_packet_max
, &slave
->sliver
->rx_maxlen
);
1081 cpsw_set_slave_mac(slave
, priv
);
1083 slave
->mac_control
= 0; /* no link yet */
1085 slave_port
= cpsw_get_slave_port(priv
, slave
->slave_num
);
1087 if (priv
->data
.dual_emac
)
1088 cpsw_add_dual_emac_def_ale_entries(priv
, slave
, slave_port
);
1090 cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1091 1 << slave_port
, 0, 0, ALE_MCAST_FWD_2
);
1093 slave
->phy
= phy_connect(priv
->ndev
, slave
->data
->phy_id
,
1094 &cpsw_adjust_link
, slave
->data
->phy_if
);
1095 if (IS_ERR(slave
->phy
)) {
1096 dev_err(priv
->dev
, "phy %s not found on slave %d\n",
1097 slave
->data
->phy_id
, slave
->slave_num
);
1100 dev_info(priv
->dev
, "phy found : id is : 0x%x\n",
1101 slave
->phy
->phy_id
);
1102 phy_start(slave
->phy
);
1104 /* Configure GMII_SEL register */
1105 cpsw_phy_sel(&priv
->pdev
->dev
, slave
->phy
->interface
,
1110 static inline void cpsw_add_default_vlan(struct cpsw_priv
*priv
)
1112 const int vlan
= priv
->data
.default_vlan
;
1113 const int port
= priv
->host_port
;
1117 reg
= (priv
->version
== CPSW_VERSION_1
) ? CPSW1_PORT_VLAN
:
1120 writel(vlan
, &priv
->host_port_regs
->port_vlan
);
1122 for (i
= 0; i
< priv
->data
.slaves
; i
++)
1123 slave_write(priv
->slaves
+ i
, vlan
, reg
);
1125 cpsw_ale_add_vlan(priv
->ale
, vlan
, ALE_ALL_PORTS
<< port
,
1126 ALE_ALL_PORTS
<< port
, ALE_ALL_PORTS
<< port
,
1127 (ALE_PORT_1
| ALE_PORT_2
) << port
);
1130 static void cpsw_init_host_port(struct cpsw_priv
*priv
)
1135 /* soft reset the controller and initialize ale */
1136 soft_reset("cpsw", &priv
->regs
->soft_reset
);
1137 cpsw_ale_start(priv
->ale
);
1139 /* switch to vlan unaware mode */
1140 cpsw_ale_control_set(priv
->ale
, priv
->host_port
, ALE_VLAN_AWARE
,
1141 CPSW_ALE_VLAN_AWARE
);
1142 control_reg
= readl(&priv
->regs
->control
);
1143 control_reg
|= CPSW_VLAN_AWARE
;
1144 writel(control_reg
, &priv
->regs
->control
);
1145 fifo_mode
= (priv
->data
.dual_emac
) ? CPSW_FIFO_DUAL_MAC_MODE
:
1146 CPSW_FIFO_NORMAL_MODE
;
1147 writel(fifo_mode
, &priv
->host_port_regs
->tx_in_ctl
);
1149 /* setup host port priority mapping */
1150 __raw_writel(CPDMA_TX_PRIORITY_MAP
,
1151 &priv
->host_port_regs
->cpdma_tx_pri_map
);
1152 __raw_writel(0, &priv
->host_port_regs
->cpdma_rx_chan_map
);
1154 cpsw_ale_control_set(priv
->ale
, priv
->host_port
,
1155 ALE_PORT_STATE
, ALE_PORT_STATE_FORWARD
);
1157 if (!priv
->data
.dual_emac
) {
1158 cpsw_ale_add_ucast(priv
->ale
, priv
->mac_addr
, priv
->host_port
,
1160 cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1161 1 << priv
->host_port
, 0, 0, ALE_MCAST_FWD_2
);
1165 static void cpsw_slave_stop(struct cpsw_slave
*slave
, struct cpsw_priv
*priv
)
1169 slave_port
= cpsw_get_slave_port(priv
, slave
->slave_num
);
1173 phy_stop(slave
->phy
);
1174 phy_disconnect(slave
->phy
);
1176 cpsw_ale_control_set(priv
->ale
, slave_port
,
1177 ALE_PORT_STATE
, ALE_PORT_STATE_DISABLE
);
1180 static int cpsw_ndo_open(struct net_device
*ndev
)
1182 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1183 struct cpsw_priv
*prim_cpsw
;
1187 if (!cpsw_common_res_usage_state(priv
))
1188 cpsw_intr_disable(priv
);
1189 netif_carrier_off(ndev
);
1191 pm_runtime_get_sync(&priv
->pdev
->dev
);
1193 reg
= priv
->version
;
1195 dev_info(priv
->dev
, "initializing cpsw version %d.%d (%d)\n",
1196 CPSW_MAJOR_VERSION(reg
), CPSW_MINOR_VERSION(reg
),
1197 CPSW_RTL_VERSION(reg
));
1199 /* initialize host and slave ports */
1200 if (!cpsw_common_res_usage_state(priv
))
1201 cpsw_init_host_port(priv
);
1202 for_each_slave(priv
, cpsw_slave_open
, priv
);
1204 /* Add default VLAN */
1205 if (!priv
->data
.dual_emac
)
1206 cpsw_add_default_vlan(priv
);
1208 if (!cpsw_common_res_usage_state(priv
)) {
1209 /* setup tx dma to fixed prio and zero offset */
1210 cpdma_control_set(priv
->dma
, CPDMA_TX_PRIO_FIXED
, 1);
1211 cpdma_control_set(priv
->dma
, CPDMA_RX_BUFFER_OFFSET
, 0);
1213 /* disable priority elevation */
1214 __raw_writel(0, &priv
->regs
->ptype
);
1216 /* enable statistics collection only on all ports */
1217 __raw_writel(0x7, &priv
->regs
->stat_port_en
);
1219 if (WARN_ON(!priv
->data
.rx_descs
))
1220 priv
->data
.rx_descs
= 128;
1222 for (i
= 0; i
< priv
->data
.rx_descs
; i
++) {
1223 struct sk_buff
*skb
;
1226 skb
= __netdev_alloc_skb_ip_align(priv
->ndev
,
1227 priv
->rx_packet_max
, GFP_KERNEL
);
1230 ret
= cpdma_chan_submit(priv
->rxch
, skb
, skb
->data
,
1231 skb_tailroom(skb
), 0);
1237 /* continue even if we didn't manage to submit all
1240 cpsw_info(priv
, ifup
, "submitted %d rx descriptors\n", i
);
1242 if (cpts_register(&priv
->pdev
->dev
, priv
->cpts
,
1243 priv
->data
.cpts_clock_mult
,
1244 priv
->data
.cpts_clock_shift
))
1245 dev_err(priv
->dev
, "error registering cpts device\n");
1249 /* Enable Interrupt pacing if configured */
1250 if (priv
->coal_intvl
!= 0) {
1251 struct ethtool_coalesce coal
;
1253 coal
.rx_coalesce_usecs
= (priv
->coal_intvl
<< 4);
1254 cpsw_set_coalesce(ndev
, &coal
);
1257 prim_cpsw
= cpsw_get_slave_priv(priv
, 0);
1258 if (prim_cpsw
->irq_enabled
== false) {
1259 if ((priv
== prim_cpsw
) || !netif_running(prim_cpsw
->ndev
)) {
1260 prim_cpsw
->irq_enabled
= true;
1261 cpsw_enable_irq(prim_cpsw
);
1265 napi_enable(&priv
->napi
);
1266 cpdma_ctlr_start(priv
->dma
);
1267 cpsw_intr_enable(priv
);
1268 cpdma_ctlr_eoi(priv
->dma
, CPDMA_EOI_RX
);
1269 cpdma_ctlr_eoi(priv
->dma
, CPDMA_EOI_TX
);
1271 if (priv
->data
.dual_emac
)
1272 priv
->slaves
[priv
->emac_port
].open_stat
= true;
1276 cpdma_ctlr_stop(priv
->dma
);
1277 for_each_slave(priv
, cpsw_slave_stop
, priv
);
1278 pm_runtime_put_sync(&priv
->pdev
->dev
);
1279 netif_carrier_off(priv
->ndev
);
1283 static int cpsw_ndo_stop(struct net_device
*ndev
)
1285 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1287 cpsw_info(priv
, ifdown
, "shutting down cpsw device\n");
1288 netif_stop_queue(priv
->ndev
);
1289 napi_disable(&priv
->napi
);
1290 netif_carrier_off(priv
->ndev
);
1292 if (cpsw_common_res_usage_state(priv
) <= 1) {
1293 cpts_unregister(priv
->cpts
);
1294 cpsw_intr_disable(priv
);
1295 cpdma_ctlr_int_ctrl(priv
->dma
, false);
1296 cpdma_ctlr_stop(priv
->dma
);
1297 cpsw_ale_stop(priv
->ale
);
1299 for_each_slave(priv
, cpsw_slave_stop
, priv
);
1300 pm_runtime_put_sync(&priv
->pdev
->dev
);
1301 if (priv
->data
.dual_emac
)
1302 priv
->slaves
[priv
->emac_port
].open_stat
= false;
1306 static netdev_tx_t
cpsw_ndo_start_xmit(struct sk_buff
*skb
,
1307 struct net_device
*ndev
)
1309 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1312 ndev
->trans_start
= jiffies
;
1314 if (skb_padto(skb
, CPSW_MIN_PACKET_SIZE
)) {
1315 cpsw_err(priv
, tx_err
, "packet pad failed\n");
1316 priv
->stats
.tx_dropped
++;
1317 return NETDEV_TX_OK
;
1320 if (skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
&&
1321 priv
->cpts
->tx_enable
)
1322 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
1324 skb_tx_timestamp(skb
);
1326 ret
= cpsw_tx_packet_submit(ndev
, priv
, skb
);
1327 if (unlikely(ret
!= 0)) {
1328 cpsw_err(priv
, tx_err
, "desc submit failed\n");
1332 /* If there is no more tx desc left free then we need to
1333 * tell the kernel to stop sending us tx frames.
1335 if (unlikely(!cpdma_check_free_tx_desc(priv
->txch
)))
1336 netif_stop_queue(ndev
);
1338 return NETDEV_TX_OK
;
1340 priv
->stats
.tx_dropped
++;
1341 netif_stop_queue(ndev
);
1342 return NETDEV_TX_BUSY
;
1345 #ifdef CONFIG_TI_CPTS
1347 static void cpsw_hwtstamp_v1(struct cpsw_priv
*priv
)
1349 struct cpsw_slave
*slave
= &priv
->slaves
[priv
->data
.active_slave
];
1352 if (!priv
->cpts
->tx_enable
&& !priv
->cpts
->rx_enable
) {
1353 slave_write(slave
, 0, CPSW1_TS_CTL
);
1357 seq_id
= (30 << CPSW_V1_SEQ_ID_OFS_SHIFT
) | ETH_P_1588
;
1358 ts_en
= EVENT_MSG_BITS
<< CPSW_V1_MSG_TYPE_OFS
;
1360 if (priv
->cpts
->tx_enable
)
1361 ts_en
|= CPSW_V1_TS_TX_EN
;
1363 if (priv
->cpts
->rx_enable
)
1364 ts_en
|= CPSW_V1_TS_RX_EN
;
1366 slave_write(slave
, ts_en
, CPSW1_TS_CTL
);
1367 slave_write(slave
, seq_id
, CPSW1_TS_SEQ_LTYPE
);
1370 static void cpsw_hwtstamp_v2(struct cpsw_priv
*priv
)
1372 struct cpsw_slave
*slave
;
1375 if (priv
->data
.dual_emac
)
1376 slave
= &priv
->slaves
[priv
->emac_port
];
1378 slave
= &priv
->slaves
[priv
->data
.active_slave
];
1380 ctrl
= slave_read(slave
, CPSW2_CONTROL
);
1381 ctrl
&= ~CTRL_ALL_TS_MASK
;
1383 if (priv
->cpts
->tx_enable
)
1384 ctrl
|= CTRL_TX_TS_BITS
;
1386 if (priv
->cpts
->rx_enable
)
1387 ctrl
|= CTRL_RX_TS_BITS
;
1389 mtype
= (30 << TS_SEQ_ID_OFFSET_SHIFT
) | EVENT_MSG_BITS
;
1391 slave_write(slave
, mtype
, CPSW2_TS_SEQ_MTYPE
);
1392 slave_write(slave
, ctrl
, CPSW2_CONTROL
);
1393 __raw_writel(ETH_P_1588
, &priv
->regs
->ts_ltype
);
1396 static int cpsw_hwtstamp_set(struct net_device
*dev
, struct ifreq
*ifr
)
1398 struct cpsw_priv
*priv
= netdev_priv(dev
);
1399 struct cpts
*cpts
= priv
->cpts
;
1400 struct hwtstamp_config cfg
;
1402 if (priv
->version
!= CPSW_VERSION_1
&&
1403 priv
->version
!= CPSW_VERSION_2
)
1406 if (copy_from_user(&cfg
, ifr
->ifr_data
, sizeof(cfg
)))
1409 /* reserved for future extensions */
1413 if (cfg
.tx_type
!= HWTSTAMP_TX_OFF
&& cfg
.tx_type
!= HWTSTAMP_TX_ON
)
1416 switch (cfg
.rx_filter
) {
1417 case HWTSTAMP_FILTER_NONE
:
1418 cpts
->rx_enable
= 0;
1420 case HWTSTAMP_FILTER_ALL
:
1421 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
1422 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
1423 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
1425 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
1426 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
1427 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
1428 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
1429 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
1430 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
1431 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
1432 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
1433 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
1434 cpts
->rx_enable
= 1;
1435 cfg
.rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
1441 cpts
->tx_enable
= cfg
.tx_type
== HWTSTAMP_TX_ON
;
1443 switch (priv
->version
) {
1444 case CPSW_VERSION_1
:
1445 cpsw_hwtstamp_v1(priv
);
1447 case CPSW_VERSION_2
:
1448 cpsw_hwtstamp_v2(priv
);
1454 return copy_to_user(ifr
->ifr_data
, &cfg
, sizeof(cfg
)) ? -EFAULT
: 0;
1457 static int cpsw_hwtstamp_get(struct net_device
*dev
, struct ifreq
*ifr
)
1459 struct cpsw_priv
*priv
= netdev_priv(dev
);
1460 struct cpts
*cpts
= priv
->cpts
;
1461 struct hwtstamp_config cfg
;
1463 if (priv
->version
!= CPSW_VERSION_1
&&
1464 priv
->version
!= CPSW_VERSION_2
)
1468 cfg
.tx_type
= cpts
->tx_enable
? HWTSTAMP_TX_ON
: HWTSTAMP_TX_OFF
;
1469 cfg
.rx_filter
= (cpts
->rx_enable
?
1470 HWTSTAMP_FILTER_PTP_V2_EVENT
: HWTSTAMP_FILTER_NONE
);
1472 return copy_to_user(ifr
->ifr_data
, &cfg
, sizeof(cfg
)) ? -EFAULT
: 0;
1475 #endif /*CONFIG_TI_CPTS*/
1477 static int cpsw_ndo_ioctl(struct net_device
*dev
, struct ifreq
*req
, int cmd
)
1479 struct cpsw_priv
*priv
= netdev_priv(dev
);
1480 struct mii_ioctl_data
*data
= if_mii(req
);
1481 int slave_no
= cpsw_slave_index(priv
);
1483 if (!netif_running(dev
))
1487 #ifdef CONFIG_TI_CPTS
1489 return cpsw_hwtstamp_set(dev
, req
);
1491 return cpsw_hwtstamp_get(dev
, req
);
1494 data
->phy_id
= priv
->slaves
[slave_no
].phy
->addr
;
1503 static void cpsw_ndo_tx_timeout(struct net_device
*ndev
)
1505 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1507 cpsw_err(priv
, tx_err
, "transmit timeout, restarting dma\n");
1508 priv
->stats
.tx_errors
++;
1509 cpsw_intr_disable(priv
);
1510 cpdma_ctlr_int_ctrl(priv
->dma
, false);
1511 cpdma_chan_stop(priv
->txch
);
1512 cpdma_chan_start(priv
->txch
);
1513 cpdma_ctlr_int_ctrl(priv
->dma
, true);
1514 cpsw_intr_enable(priv
);
1515 cpdma_ctlr_eoi(priv
->dma
, CPDMA_EOI_RX
);
1516 cpdma_ctlr_eoi(priv
->dma
, CPDMA_EOI_TX
);
1520 static int cpsw_ndo_set_mac_address(struct net_device
*ndev
, void *p
)
1522 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1523 struct sockaddr
*addr
= (struct sockaddr
*)p
;
1527 if (!is_valid_ether_addr(addr
->sa_data
))
1528 return -EADDRNOTAVAIL
;
1530 if (priv
->data
.dual_emac
) {
1531 vid
= priv
->slaves
[priv
->emac_port
].port_vlan
;
1535 cpsw_ale_del_ucast(priv
->ale
, priv
->mac_addr
, priv
->host_port
,
1537 cpsw_ale_add_ucast(priv
->ale
, addr
->sa_data
, priv
->host_port
,
1540 memcpy(priv
->mac_addr
, addr
->sa_data
, ETH_ALEN
);
1541 memcpy(ndev
->dev_addr
, priv
->mac_addr
, ETH_ALEN
);
1542 for_each_slave(priv
, cpsw_set_slave_mac
, priv
);
1547 static struct net_device_stats
*cpsw_ndo_get_stats(struct net_device
*ndev
)
1549 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1550 return &priv
->stats
;
1553 #ifdef CONFIG_NET_POLL_CONTROLLER
1554 static void cpsw_ndo_poll_controller(struct net_device
*ndev
)
1556 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1558 cpsw_intr_disable(priv
);
1559 cpdma_ctlr_int_ctrl(priv
->dma
, false);
1560 cpsw_interrupt(ndev
->irq
, priv
);
1561 cpdma_ctlr_int_ctrl(priv
->dma
, true);
1562 cpsw_intr_enable(priv
);
1563 cpdma_ctlr_eoi(priv
->dma
, CPDMA_EOI_RX
);
1564 cpdma_ctlr_eoi(priv
->dma
, CPDMA_EOI_TX
);
1569 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv
*priv
,
1574 ret
= cpsw_ale_add_vlan(priv
->ale
, vid
,
1575 ALE_ALL_PORTS
<< priv
->host_port
,
1576 0, ALE_ALL_PORTS
<< priv
->host_port
,
1577 (ALE_PORT_1
| ALE_PORT_2
) << priv
->host_port
);
1581 ret
= cpsw_ale_add_ucast(priv
->ale
, priv
->mac_addr
,
1582 priv
->host_port
, ALE_VLAN
, vid
);
1586 ret
= cpsw_ale_add_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1587 ALE_ALL_PORTS
<< priv
->host_port
,
1590 goto clean_vlan_ucast
;
1594 cpsw_ale_del_ucast(priv
->ale
, priv
->mac_addr
,
1595 priv
->host_port
, ALE_VLAN
, vid
);
1597 cpsw_ale_del_vlan(priv
->ale
, vid
, 0);
1601 static int cpsw_ndo_vlan_rx_add_vid(struct net_device
*ndev
,
1602 __be16 proto
, u16 vid
)
1604 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1606 if (vid
== priv
->data
.default_vlan
)
1609 dev_info(priv
->dev
, "Adding vlanid %d to vlan filter\n", vid
);
1610 return cpsw_add_vlan_ale_entry(priv
, vid
);
1613 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device
*ndev
,
1614 __be16 proto
, u16 vid
)
1616 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1619 if (vid
== priv
->data
.default_vlan
)
1622 dev_info(priv
->dev
, "removing vlanid %d from vlan filter\n", vid
);
1623 ret
= cpsw_ale_del_vlan(priv
->ale
, vid
, 0);
1627 ret
= cpsw_ale_del_ucast(priv
->ale
, priv
->mac_addr
,
1628 priv
->host_port
, ALE_VLAN
, vid
);
1632 return cpsw_ale_del_mcast(priv
->ale
, priv
->ndev
->broadcast
,
1636 static const struct net_device_ops cpsw_netdev_ops
= {
1637 .ndo_open
= cpsw_ndo_open
,
1638 .ndo_stop
= cpsw_ndo_stop
,
1639 .ndo_start_xmit
= cpsw_ndo_start_xmit
,
1640 .ndo_set_mac_address
= cpsw_ndo_set_mac_address
,
1641 .ndo_do_ioctl
= cpsw_ndo_ioctl
,
1642 .ndo_validate_addr
= eth_validate_addr
,
1643 .ndo_change_mtu
= eth_change_mtu
,
1644 .ndo_tx_timeout
= cpsw_ndo_tx_timeout
,
1645 .ndo_get_stats
= cpsw_ndo_get_stats
,
1646 .ndo_set_rx_mode
= cpsw_ndo_set_rx_mode
,
1647 #ifdef CONFIG_NET_POLL_CONTROLLER
1648 .ndo_poll_controller
= cpsw_ndo_poll_controller
,
1650 .ndo_vlan_rx_add_vid
= cpsw_ndo_vlan_rx_add_vid
,
1651 .ndo_vlan_rx_kill_vid
= cpsw_ndo_vlan_rx_kill_vid
,
1654 static void cpsw_get_drvinfo(struct net_device
*ndev
,
1655 struct ethtool_drvinfo
*info
)
1657 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1659 strlcpy(info
->driver
, "TI CPSW Driver v1.0", sizeof(info
->driver
));
1660 strlcpy(info
->version
, "1.0", sizeof(info
->version
));
1661 strlcpy(info
->bus_info
, priv
->pdev
->name
, sizeof(info
->bus_info
));
1664 static u32
cpsw_get_msglevel(struct net_device
*ndev
)
1666 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1667 return priv
->msg_enable
;
1670 static void cpsw_set_msglevel(struct net_device
*ndev
, u32 value
)
1672 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1673 priv
->msg_enable
= value
;
1676 static int cpsw_get_ts_info(struct net_device
*ndev
,
1677 struct ethtool_ts_info
*info
)
1679 #ifdef CONFIG_TI_CPTS
1680 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1682 info
->so_timestamping
=
1683 SOF_TIMESTAMPING_TX_HARDWARE
|
1684 SOF_TIMESTAMPING_TX_SOFTWARE
|
1685 SOF_TIMESTAMPING_RX_HARDWARE
|
1686 SOF_TIMESTAMPING_RX_SOFTWARE
|
1687 SOF_TIMESTAMPING_SOFTWARE
|
1688 SOF_TIMESTAMPING_RAW_HARDWARE
;
1689 info
->phc_index
= priv
->cpts
->phc_index
;
1691 (1 << HWTSTAMP_TX_OFF
) |
1692 (1 << HWTSTAMP_TX_ON
);
1694 (1 << HWTSTAMP_FILTER_NONE
) |
1695 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT
);
1697 info
->so_timestamping
=
1698 SOF_TIMESTAMPING_TX_SOFTWARE
|
1699 SOF_TIMESTAMPING_RX_SOFTWARE
|
1700 SOF_TIMESTAMPING_SOFTWARE
;
1701 info
->phc_index
= -1;
1703 info
->rx_filters
= 0;
1708 static int cpsw_get_settings(struct net_device
*ndev
,
1709 struct ethtool_cmd
*ecmd
)
1711 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1712 int slave_no
= cpsw_slave_index(priv
);
1714 if (priv
->slaves
[slave_no
].phy
)
1715 return phy_ethtool_gset(priv
->slaves
[slave_no
].phy
, ecmd
);
1720 static int cpsw_set_settings(struct net_device
*ndev
, struct ethtool_cmd
*ecmd
)
1722 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1723 int slave_no
= cpsw_slave_index(priv
);
1725 if (priv
->slaves
[slave_no
].phy
)
1726 return phy_ethtool_sset(priv
->slaves
[slave_no
].phy
, ecmd
);
1731 static void cpsw_get_wol(struct net_device
*ndev
, struct ethtool_wolinfo
*wol
)
1733 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1734 int slave_no
= cpsw_slave_index(priv
);
1739 if (priv
->slaves
[slave_no
].phy
)
1740 phy_ethtool_get_wol(priv
->slaves
[slave_no
].phy
, wol
);
1743 static int cpsw_set_wol(struct net_device
*ndev
, struct ethtool_wolinfo
*wol
)
1745 struct cpsw_priv
*priv
= netdev_priv(ndev
);
1746 int slave_no
= cpsw_slave_index(priv
);
1748 if (priv
->slaves
[slave_no
].phy
)
1749 return phy_ethtool_set_wol(priv
->slaves
[slave_no
].phy
, wol
);
1754 static const struct ethtool_ops cpsw_ethtool_ops
= {
1755 .get_drvinfo
= cpsw_get_drvinfo
,
1756 .get_msglevel
= cpsw_get_msglevel
,
1757 .set_msglevel
= cpsw_set_msglevel
,
1758 .get_link
= ethtool_op_get_link
,
1759 .get_ts_info
= cpsw_get_ts_info
,
1760 .get_settings
= cpsw_get_settings
,
1761 .set_settings
= cpsw_set_settings
,
1762 .get_coalesce
= cpsw_get_coalesce
,
1763 .set_coalesce
= cpsw_set_coalesce
,
1764 .get_sset_count
= cpsw_get_sset_count
,
1765 .get_strings
= cpsw_get_strings
,
1766 .get_ethtool_stats
= cpsw_get_ethtool_stats
,
1767 .get_wol
= cpsw_get_wol
,
1768 .set_wol
= cpsw_set_wol
,
1771 static void cpsw_slave_init(struct cpsw_slave
*slave
, struct cpsw_priv
*priv
,
1772 u32 slave_reg_ofs
, u32 sliver_reg_ofs
)
1774 void __iomem
*regs
= priv
->regs
;
1775 int slave_num
= slave
->slave_num
;
1776 struct cpsw_slave_data
*data
= priv
->data
.slave_data
+ slave_num
;
1779 slave
->regs
= regs
+ slave_reg_ofs
;
1780 slave
->sliver
= regs
+ sliver_reg_ofs
;
1781 slave
->port_vlan
= data
->dual_emac_res_vlan
;
1784 static int cpsw_probe_dt(struct cpsw_platform_data
*data
,
1785 struct platform_device
*pdev
)
1787 struct device_node
*node
= pdev
->dev
.of_node
;
1788 struct device_node
*slave_node
;
1795 if (of_property_read_u32(node
, "slaves", &prop
)) {
1796 pr_err("Missing slaves property in the DT.\n");
1799 data
->slaves
= prop
;
1801 if (of_property_read_u32(node
, "active_slave", &prop
)) {
1802 pr_err("Missing active_slave property in the DT.\n");
1805 data
->active_slave
= prop
;
1807 if (of_property_read_u32(node
, "cpts_clock_mult", &prop
)) {
1808 pr_err("Missing cpts_clock_mult property in the DT.\n");
1811 data
->cpts_clock_mult
= prop
;
1813 if (of_property_read_u32(node
, "cpts_clock_shift", &prop
)) {
1814 pr_err("Missing cpts_clock_shift property in the DT.\n");
1817 data
->cpts_clock_shift
= prop
;
1819 data
->slave_data
= devm_kzalloc(&pdev
->dev
, data
->slaves
1820 * sizeof(struct cpsw_slave_data
),
1822 if (!data
->slave_data
)
1825 if (of_property_read_u32(node
, "cpdma_channels", &prop
)) {
1826 pr_err("Missing cpdma_channels property in the DT.\n");
1829 data
->channels
= prop
;
1831 if (of_property_read_u32(node
, "ale_entries", &prop
)) {
1832 pr_err("Missing ale_entries property in the DT.\n");
1835 data
->ale_entries
= prop
;
1837 if (of_property_read_u32(node
, "bd_ram_size", &prop
)) {
1838 pr_err("Missing bd_ram_size property in the DT.\n");
1841 data
->bd_ram_size
= prop
;
1843 if (of_property_read_u32(node
, "rx_descs", &prop
)) {
1844 pr_err("Missing rx_descs property in the DT.\n");
1847 data
->rx_descs
= prop
;
1849 if (of_property_read_u32(node
, "mac_control", &prop
)) {
1850 pr_err("Missing mac_control property in the DT.\n");
1853 data
->mac_control
= prop
;
1855 if (of_property_read_bool(node
, "dual_emac"))
1856 data
->dual_emac
= 1;
1859 * Populate all the child nodes here...
1861 ret
= of_platform_populate(node
, NULL
, NULL
, &pdev
->dev
);
1862 /* We do not want to force this, as in some cases may not have child */
1864 pr_warn("Doesn't have any child node\n");
1866 for_each_child_of_node(node
, slave_node
) {
1867 struct cpsw_slave_data
*slave_data
= data
->slave_data
+ i
;
1868 const void *mac_addr
= NULL
;
1872 struct device_node
*mdio_node
;
1873 struct platform_device
*mdio
;
1875 /* This is no slave child node, continue */
1876 if (strcmp(slave_node
->name
, "slave"))
1879 parp
= of_get_property(slave_node
, "phy_id", &lenp
);
1880 if ((parp
== NULL
) || (lenp
!= (sizeof(void *) * 2))) {
1881 pr_err("Missing slave[%d] phy_id property\n", i
);
1884 mdio_node
= of_find_node_by_phandle(be32_to_cpup(parp
));
1885 phyid
= be32_to_cpup(parp
+1);
1886 mdio
= of_find_device_by_node(mdio_node
);
1888 if (strncmp(mdio
->name
, "gpio", 4) == 0) {
1889 /* GPIO bitbang MDIO driver attached */
1890 struct mii_bus
*bus
= dev_get_drvdata(&mdio
->dev
);
1892 snprintf(slave_data
->phy_id
, sizeof(slave_data
->phy_id
),
1893 PHY_ID_FMT
, bus
->id
, phyid
);
1895 /* davinci MDIO driver attached */
1896 snprintf(slave_data
->phy_id
, sizeof(slave_data
->phy_id
),
1897 PHY_ID_FMT
, mdio
->name
, phyid
);
1900 mac_addr
= of_get_mac_address(slave_node
);
1902 memcpy(slave_data
->mac_addr
, mac_addr
, ETH_ALEN
);
1904 slave_data
->phy_if
= of_get_phy_mode(slave_node
);
1905 if (slave_data
->phy_if
< 0) {
1906 pr_err("Missing or malformed slave[%d] phy-mode property\n",
1908 return slave_data
->phy_if
;
1911 if (data
->dual_emac
) {
1912 if (of_property_read_u32(slave_node
, "dual_emac_res_vlan",
1914 pr_err("Missing dual_emac_res_vlan in DT.\n");
1915 slave_data
->dual_emac_res_vlan
= i
+1;
1916 pr_err("Using %d as Reserved VLAN for %d slave\n",
1917 slave_data
->dual_emac_res_vlan
, i
);
1919 slave_data
->dual_emac_res_vlan
= prop
;
1924 if (i
== data
->slaves
)
1931 static int cpsw_probe_dual_emac(struct platform_device
*pdev
,
1932 struct cpsw_priv
*priv
)
1934 struct cpsw_platform_data
*data
= &priv
->data
;
1935 struct net_device
*ndev
;
1936 struct cpsw_priv
*priv_sl2
;
1939 ndev
= alloc_etherdev(sizeof(struct cpsw_priv
));
1941 pr_err("cpsw: error allocating net_device\n");
1945 priv_sl2
= netdev_priv(ndev
);
1946 spin_lock_init(&priv_sl2
->lock
);
1947 priv_sl2
->data
= *data
;
1948 priv_sl2
->pdev
= pdev
;
1949 priv_sl2
->ndev
= ndev
;
1950 priv_sl2
->dev
= &ndev
->dev
;
1951 priv_sl2
->msg_enable
= netif_msg_init(debug_level
, CPSW_DEBUG
);
1952 priv_sl2
->rx_packet_max
= max(rx_packet_max
, 128);
1954 if (is_valid_ether_addr(data
->slave_data
[1].mac_addr
)) {
1955 memcpy(priv_sl2
->mac_addr
, data
->slave_data
[1].mac_addr
,
1957 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2
->mac_addr
);
1959 random_ether_addr(priv_sl2
->mac_addr
);
1960 pr_info("cpsw: Random MACID = %pM\n", priv_sl2
->mac_addr
);
1962 memcpy(ndev
->dev_addr
, priv_sl2
->mac_addr
, ETH_ALEN
);
1964 priv_sl2
->slaves
= priv
->slaves
;
1965 priv_sl2
->clk
= priv
->clk
;
1967 priv_sl2
->coal_intvl
= 0;
1968 priv_sl2
->bus_freq_mhz
= priv
->bus_freq_mhz
;
1970 priv_sl2
->regs
= priv
->regs
;
1971 priv_sl2
->host_port
= priv
->host_port
;
1972 priv_sl2
->host_port_regs
= priv
->host_port_regs
;
1973 priv_sl2
->wr_regs
= priv
->wr_regs
;
1974 priv_sl2
->hw_stats
= priv
->hw_stats
;
1975 priv_sl2
->dma
= priv
->dma
;
1976 priv_sl2
->txch
= priv
->txch
;
1977 priv_sl2
->rxch
= priv
->rxch
;
1978 priv_sl2
->ale
= priv
->ale
;
1979 priv_sl2
->emac_port
= 1;
1980 priv
->slaves
[1].ndev
= ndev
;
1981 priv_sl2
->cpts
= priv
->cpts
;
1982 priv_sl2
->version
= priv
->version
;
1984 for (i
= 0; i
< priv
->num_irqs
; i
++) {
1985 priv_sl2
->irqs_table
[i
] = priv
->irqs_table
[i
];
1986 priv_sl2
->num_irqs
= priv
->num_irqs
;
1988 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
1990 ndev
->netdev_ops
= &cpsw_netdev_ops
;
1991 SET_ETHTOOL_OPS(ndev
, &cpsw_ethtool_ops
);
1992 netif_napi_add(ndev
, &priv_sl2
->napi
, cpsw_poll
, CPSW_POLL_WEIGHT
);
1994 /* register the network device */
1995 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1996 ret
= register_netdev(ndev
);
1998 pr_err("cpsw: error registering net device\n");
2006 static int cpsw_probe(struct platform_device
*pdev
)
2008 struct cpsw_platform_data
*data
;
2009 struct net_device
*ndev
;
2010 struct cpsw_priv
*priv
;
2011 struct cpdma_params dma_params
;
2012 struct cpsw_ale_params ale_params
;
2013 void __iomem
*ss_regs
;
2014 struct resource
*res
, *ss_res
;
2015 u32 slave_offset
, sliver_offset
, slave_size
;
2016 int ret
= 0, i
, k
= 0;
2018 ndev
= alloc_etherdev(sizeof(struct cpsw_priv
));
2020 pr_err("error allocating net_device\n");
2024 platform_set_drvdata(pdev
, ndev
);
2025 priv
= netdev_priv(ndev
);
2026 spin_lock_init(&priv
->lock
);
2029 priv
->dev
= &ndev
->dev
;
2030 priv
->msg_enable
= netif_msg_init(debug_level
, CPSW_DEBUG
);
2031 priv
->rx_packet_max
= max(rx_packet_max
, 128);
2032 priv
->cpts
= devm_kzalloc(&pdev
->dev
, sizeof(struct cpts
), GFP_KERNEL
);
2033 priv
->irq_enabled
= true;
2035 pr_err("error allocating cpts\n");
2036 goto clean_ndev_ret
;
2040 * This may be required here for child devices.
2042 pm_runtime_enable(&pdev
->dev
);
2044 /* Select default pin state */
2045 pinctrl_pm_select_default_state(&pdev
->dev
);
2047 if (cpsw_probe_dt(&priv
->data
, pdev
)) {
2048 pr_err("cpsw: platform data missing\n");
2050 goto clean_runtime_disable_ret
;
2054 if (is_valid_ether_addr(data
->slave_data
[0].mac_addr
)) {
2055 memcpy(priv
->mac_addr
, data
->slave_data
[0].mac_addr
, ETH_ALEN
);
2056 pr_info("Detected MACID = %pM\n", priv
->mac_addr
);
2058 eth_random_addr(priv
->mac_addr
);
2059 pr_info("Random MACID = %pM\n", priv
->mac_addr
);
2062 memcpy(ndev
->dev_addr
, priv
->mac_addr
, ETH_ALEN
);
2064 priv
->slaves
= devm_kzalloc(&pdev
->dev
,
2065 sizeof(struct cpsw_slave
) * data
->slaves
,
2067 if (!priv
->slaves
) {
2069 goto clean_runtime_disable_ret
;
2071 for (i
= 0; i
< data
->slaves
; i
++)
2072 priv
->slaves
[i
].slave_num
= i
;
2074 priv
->slaves
[0].ndev
= ndev
;
2075 priv
->emac_port
= 0;
2077 priv
->clk
= devm_clk_get(&pdev
->dev
, "fck");
2078 if (IS_ERR(priv
->clk
)) {
2079 dev_err(priv
->dev
, "fck is not found\n");
2081 goto clean_runtime_disable_ret
;
2083 priv
->coal_intvl
= 0;
2084 priv
->bus_freq_mhz
= clk_get_rate(priv
->clk
) / 1000000;
2086 ss_res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2087 ss_regs
= devm_ioremap_resource(&pdev
->dev
, ss_res
);
2088 if (IS_ERR(ss_regs
)) {
2089 ret
= PTR_ERR(ss_regs
);
2090 goto clean_runtime_disable_ret
;
2092 priv
->regs
= ss_regs
;
2093 priv
->host_port
= HOST_PORT_NUM
;
2095 /* Need to enable clocks with runtime PM api to access module
2098 pm_runtime_get_sync(&pdev
->dev
);
2099 priv
->version
= readl(&priv
->regs
->id_ver
);
2100 pm_runtime_put_sync(&pdev
->dev
);
2102 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
2103 priv
->wr_regs
= devm_ioremap_resource(&pdev
->dev
, res
);
2104 if (IS_ERR(priv
->wr_regs
)) {
2105 ret
= PTR_ERR(priv
->wr_regs
);
2106 goto clean_runtime_disable_ret
;
2109 memset(&dma_params
, 0, sizeof(dma_params
));
2110 memset(&ale_params
, 0, sizeof(ale_params
));
2112 switch (priv
->version
) {
2113 case CPSW_VERSION_1
:
2114 priv
->host_port_regs
= ss_regs
+ CPSW1_HOST_PORT_OFFSET
;
2115 priv
->cpts
->reg
= ss_regs
+ CPSW1_CPTS_OFFSET
;
2116 priv
->hw_stats
= ss_regs
+ CPSW1_HW_STATS
;
2117 dma_params
.dmaregs
= ss_regs
+ CPSW1_CPDMA_OFFSET
;
2118 dma_params
.txhdp
= ss_regs
+ CPSW1_STATERAM_OFFSET
;
2119 ale_params
.ale_regs
= ss_regs
+ CPSW1_ALE_OFFSET
;
2120 slave_offset
= CPSW1_SLAVE_OFFSET
;
2121 slave_size
= CPSW1_SLAVE_SIZE
;
2122 sliver_offset
= CPSW1_SLIVER_OFFSET
;
2123 dma_params
.desc_mem_phys
= 0;
2125 case CPSW_VERSION_2
:
2126 case CPSW_VERSION_3
:
2127 case CPSW_VERSION_4
:
2128 priv
->host_port_regs
= ss_regs
+ CPSW2_HOST_PORT_OFFSET
;
2129 priv
->cpts
->reg
= ss_regs
+ CPSW2_CPTS_OFFSET
;
2130 priv
->hw_stats
= ss_regs
+ CPSW2_HW_STATS
;
2131 dma_params
.dmaregs
= ss_regs
+ CPSW2_CPDMA_OFFSET
;
2132 dma_params
.txhdp
= ss_regs
+ CPSW2_STATERAM_OFFSET
;
2133 ale_params
.ale_regs
= ss_regs
+ CPSW2_ALE_OFFSET
;
2134 slave_offset
= CPSW2_SLAVE_OFFSET
;
2135 slave_size
= CPSW2_SLAVE_SIZE
;
2136 sliver_offset
= CPSW2_SLIVER_OFFSET
;
2137 dma_params
.desc_mem_phys
=
2138 (u32 __force
) ss_res
->start
+ CPSW2_BD_OFFSET
;
2141 dev_err(priv
->dev
, "unknown version 0x%08x\n", priv
->version
);
2143 goto clean_runtime_disable_ret
;
2145 for (i
= 0; i
< priv
->data
.slaves
; i
++) {
2146 struct cpsw_slave
*slave
= &priv
->slaves
[i
];
2147 cpsw_slave_init(slave
, priv
, slave_offset
, sliver_offset
);
2148 slave_offset
+= slave_size
;
2149 sliver_offset
+= SLIVER_SIZE
;
2152 dma_params
.dev
= &pdev
->dev
;
2153 dma_params
.rxthresh
= dma_params
.dmaregs
+ CPDMA_RXTHRESH
;
2154 dma_params
.rxfree
= dma_params
.dmaregs
+ CPDMA_RXFREE
;
2155 dma_params
.rxhdp
= dma_params
.txhdp
+ CPDMA_RXHDP
;
2156 dma_params
.txcp
= dma_params
.txhdp
+ CPDMA_TXCP
;
2157 dma_params
.rxcp
= dma_params
.txhdp
+ CPDMA_RXCP
;
2159 dma_params
.num_chan
= data
->channels
;
2160 dma_params
.has_soft_reset
= true;
2161 dma_params
.min_packet_size
= CPSW_MIN_PACKET_SIZE
;
2162 dma_params
.desc_mem_size
= data
->bd_ram_size
;
2163 dma_params
.desc_align
= 16;
2164 dma_params
.has_ext_regs
= true;
2165 dma_params
.desc_hw_addr
= dma_params
.desc_mem_phys
;
2167 priv
->dma
= cpdma_ctlr_create(&dma_params
);
2169 dev_err(priv
->dev
, "error initializing dma\n");
2171 goto clean_runtime_disable_ret
;
2174 priv
->txch
= cpdma_chan_create(priv
->dma
, tx_chan_num(0),
2176 priv
->rxch
= cpdma_chan_create(priv
->dma
, rx_chan_num(0),
2179 if (WARN_ON(!priv
->txch
|| !priv
->rxch
)) {
2180 dev_err(priv
->dev
, "error initializing dma channels\n");
2185 ale_params
.dev
= &ndev
->dev
;
2186 ale_params
.ale_ageout
= ale_ageout
;
2187 ale_params
.ale_entries
= data
->ale_entries
;
2188 ale_params
.ale_ports
= data
->slaves
;
2190 priv
->ale
= cpsw_ale_create(&ale_params
);
2192 dev_err(priv
->dev
, "error initializing ale engine\n");
2197 ndev
->irq
= platform_get_irq(pdev
, 0);
2198 if (ndev
->irq
< 0) {
2199 dev_err(priv
->dev
, "error getting irq resource\n");
2204 while ((res
= platform_get_resource(priv
->pdev
, IORESOURCE_IRQ
, k
))) {
2205 for (i
= res
->start
; i
<= res
->end
; i
++) {
2206 if (devm_request_irq(&pdev
->dev
, i
, cpsw_interrupt
, 0,
2207 dev_name(&pdev
->dev
), priv
)) {
2208 dev_err(priv
->dev
, "error attaching irq\n");
2211 priv
->irqs_table
[k
] = i
;
2212 priv
->num_irqs
= k
+ 1;
2217 ndev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
2219 ndev
->netdev_ops
= &cpsw_netdev_ops
;
2220 SET_ETHTOOL_OPS(ndev
, &cpsw_ethtool_ops
);
2221 netif_napi_add(ndev
, &priv
->napi
, cpsw_poll
, CPSW_POLL_WEIGHT
);
2223 /* register the network device */
2224 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
2225 ret
= register_netdev(ndev
);
2227 dev_err(priv
->dev
, "error registering net device\n");
2232 cpsw_notice(priv
, probe
, "initialized device (regs %pa, irq %d)\n",
2233 &ss_res
->start
, ndev
->irq
);
2235 if (priv
->data
.dual_emac
) {
2236 ret
= cpsw_probe_dual_emac(pdev
, priv
);
2238 cpsw_err(priv
, probe
, "error probe slave 2 emac interface\n");
2246 cpsw_ale_destroy(priv
->ale
);
2248 cpdma_chan_destroy(priv
->txch
);
2249 cpdma_chan_destroy(priv
->rxch
);
2250 cpdma_ctlr_destroy(priv
->dma
);
2251 clean_runtime_disable_ret
:
2252 pm_runtime_disable(&pdev
->dev
);
2254 free_netdev(priv
->ndev
);
2258 static int cpsw_remove(struct platform_device
*pdev
)
2260 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2261 struct cpsw_priv
*priv
= netdev_priv(ndev
);
2263 if (priv
->data
.dual_emac
)
2264 unregister_netdev(cpsw_get_slave_ndev(priv
, 1));
2265 unregister_netdev(ndev
);
2267 cpsw_ale_destroy(priv
->ale
);
2268 cpdma_chan_destroy(priv
->txch
);
2269 cpdma_chan_destroy(priv
->rxch
);
2270 cpdma_ctlr_destroy(priv
->dma
);
2271 pm_runtime_disable(&pdev
->dev
);
2272 if (priv
->data
.dual_emac
)
2273 free_netdev(cpsw_get_slave_ndev(priv
, 1));
2278 static int cpsw_suspend(struct device
*dev
)
2280 struct platform_device
*pdev
= to_platform_device(dev
);
2281 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2282 struct cpsw_priv
*priv
= netdev_priv(ndev
);
2284 if (netif_running(ndev
))
2285 cpsw_ndo_stop(ndev
);
2287 for_each_slave(priv
, soft_reset_slave
);
2289 pm_runtime_put_sync(&pdev
->dev
);
2291 /* Select sleep pin state */
2292 pinctrl_pm_select_sleep_state(&pdev
->dev
);
2297 static int cpsw_resume(struct device
*dev
)
2299 struct platform_device
*pdev
= to_platform_device(dev
);
2300 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2302 pm_runtime_get_sync(&pdev
->dev
);
2304 /* Select default pin state */
2305 pinctrl_pm_select_default_state(&pdev
->dev
);
2307 if (netif_running(ndev
))
2308 cpsw_ndo_open(ndev
);
2312 static const struct dev_pm_ops cpsw_pm_ops
= {
2313 .suspend
= cpsw_suspend
,
2314 .resume
= cpsw_resume
,
2317 static const struct of_device_id cpsw_of_mtable
[] = {
2318 { .compatible
= "ti,cpsw", },
2321 MODULE_DEVICE_TABLE(of
, cpsw_of_mtable
);
2323 static struct platform_driver cpsw_driver
= {
2326 .owner
= THIS_MODULE
,
2328 .of_match_table
= cpsw_of_mtable
,
2330 .probe
= cpsw_probe
,
2331 .remove
= cpsw_remove
,
2334 static int __init
cpsw_init(void)
2336 return platform_driver_register(&cpsw_driver
);
2338 late_initcall(cpsw_init
);
2340 static void __exit
cpsw_exit(void)
2342 platform_driver_unregister(&cpsw_driver
);
2344 module_exit(cpsw_exit
);
2346 MODULE_LICENSE("GPL");
2347 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2348 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2349 MODULE_DESCRIPTION("TI CPSW Ethernet driver");