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Merge remote-tracking branch 'crypto-current/master'
[deliverable/linux.git] / drivers / net / ethernet / ti / cpsw.c
1 /*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio.h>
33 #include <linux/of.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
38
39 #include <linux/pinctrl/consumer.h>
40
41 #include "cpsw.h"
42 #include "cpsw_ale.h"
43 #include "cpts.h"
44 #include "davinci_cpdma.h"
45
46 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55 #define cpsw_info(priv, type, format, ...) \
56 do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59 } while (0)
60
61 #define cpsw_err(priv, type, format, ...) \
62 do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65 } while (0)
66
67 #define cpsw_dbg(priv, type, format, ...) \
68 do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71 } while (0)
72
73 #define cpsw_notice(priv, type, format, ...) \
74 do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77 } while (0)
78
79 #define ALE_ALL_PORTS 0x7
80
81 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
85 #define CPSW_VERSION_1 0x19010a
86 #define CPSW_VERSION_2 0x19010c
87 #define CPSW_VERSION_3 0x19010f
88 #define CPSW_VERSION_4 0x190112
89
90 #define HOST_PORT_NUM 0
91 #define SLIVER_SIZE 0x40
92
93 #define CPSW1_HOST_PORT_OFFSET 0x028
94 #define CPSW1_SLAVE_OFFSET 0x050
95 #define CPSW1_SLAVE_SIZE 0x040
96 #define CPSW1_CPDMA_OFFSET 0x100
97 #define CPSW1_STATERAM_OFFSET 0x200
98 #define CPSW1_HW_STATS 0x400
99 #define CPSW1_CPTS_OFFSET 0x500
100 #define CPSW1_ALE_OFFSET 0x600
101 #define CPSW1_SLIVER_OFFSET 0x700
102
103 #define CPSW2_HOST_PORT_OFFSET 0x108
104 #define CPSW2_SLAVE_OFFSET 0x200
105 #define CPSW2_SLAVE_SIZE 0x100
106 #define CPSW2_CPDMA_OFFSET 0x800
107 #define CPSW2_HW_STATS 0x900
108 #define CPSW2_STATERAM_OFFSET 0xa00
109 #define CPSW2_CPTS_OFFSET 0xc00
110 #define CPSW2_ALE_OFFSET 0xd00
111 #define CPSW2_SLIVER_OFFSET 0xd80
112 #define CPSW2_BD_OFFSET 0x2000
113
114 #define CPDMA_RXTHRESH 0x0c0
115 #define CPDMA_RXFREE 0x0e0
116 #define CPDMA_TXHDP 0x00
117 #define CPDMA_RXHDP 0x20
118 #define CPDMA_TXCP 0x40
119 #define CPDMA_RXCP 0x60
120
121 #define CPSW_POLL_WEIGHT 64
122 #define CPSW_MIN_PACKET_SIZE 60
123 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125 #define RX_PRIORITY_MAPPING 0x76543210
126 #define TX_PRIORITY_MAPPING 0x33221100
127 #define CPDMA_TX_PRIORITY_MAP 0x76543210
128
129 #define CPSW_VLAN_AWARE BIT(1)
130 #define CPSW_ALE_VLAN_AWARE 1
131
132 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
135
136 #define CPSW_INTPACEEN (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT 63
139 #define CPSW_CMINTMIN_CNT 2
140 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
143 #define cpsw_slave_index(priv) \
144 ((priv->data.dual_emac) ? priv->emac_port : \
145 priv->data.active_slave)
146
147 static int debug_level;
148 module_param(debug_level, int, 0);
149 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
150
151 static int ale_ageout = 10;
152 module_param(ale_ageout, int, 0);
153 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
154
155 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
156 module_param(rx_packet_max, int, 0);
157 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
158
159 struct cpsw_wr_regs {
160 u32 id_ver;
161 u32 soft_reset;
162 u32 control;
163 u32 int_control;
164 u32 rx_thresh_en;
165 u32 rx_en;
166 u32 tx_en;
167 u32 misc_en;
168 u32 mem_allign1[8];
169 u32 rx_thresh_stat;
170 u32 rx_stat;
171 u32 tx_stat;
172 u32 misc_stat;
173 u32 mem_allign2[8];
174 u32 rx_imax;
175 u32 tx_imax;
176
177 };
178
179 struct cpsw_ss_regs {
180 u32 id_ver;
181 u32 control;
182 u32 soft_reset;
183 u32 stat_port_en;
184 u32 ptype;
185 u32 soft_idle;
186 u32 thru_rate;
187 u32 gap_thresh;
188 u32 tx_start_wds;
189 u32 flow_control;
190 u32 vlan_ltype;
191 u32 ts_ltype;
192 u32 dlr_ltype;
193 };
194
195 /* CPSW_PORT_V1 */
196 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
197 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
198 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
199 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
200 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
201 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
202 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
203 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
204
205 /* CPSW_PORT_V2 */
206 #define CPSW2_CONTROL 0x00 /* Control Register */
207 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
208 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
209 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
210 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
211 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
212 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
213
214 /* CPSW_PORT_V1 and V2 */
215 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
216 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
217 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
218
219 /* CPSW_PORT_V2 only */
220 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
221 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
222 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
223 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
224 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
225 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
226 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
227 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
228
229 /* Bit definitions for the CPSW2_CONTROL register */
230 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
231 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
232 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
233 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
234 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
235 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
236 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
237 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
238 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
239 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
240 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
241 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
242 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
243 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
244 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
245 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
246 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
247
248 #define CTRL_V2_TS_BITS \
249 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
250 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
251
252 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
253 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
254 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
255
256
257 #define CTRL_V3_TS_BITS \
258 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
259 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
260 TS_LTYPE1_EN)
261
262 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
263 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
264 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
265
266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
269 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270 #define TS_MSG_TYPE_EN_MASK (0xffff)
271
272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
274
275 /* Bit definitions for the CPSW1_TS_CTL register */
276 #define CPSW_V1_TS_RX_EN BIT(0)
277 #define CPSW_V1_TS_TX_EN BIT(4)
278 #define CPSW_V1_MSG_TYPE_OFS 16
279
280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
282
283 struct cpsw_host_regs {
284 u32 max_blks;
285 u32 blk_cnt;
286 u32 tx_in_ctl;
287 u32 port_vlan;
288 u32 tx_pri_map;
289 u32 cpdma_tx_pri_map;
290 u32 cpdma_rx_chan_map;
291 };
292
293 struct cpsw_sliver_regs {
294 u32 id_ver;
295 u32 mac_control;
296 u32 mac_status;
297 u32 soft_reset;
298 u32 rx_maxlen;
299 u32 __reserved_0;
300 u32 rx_pause;
301 u32 tx_pause;
302 u32 __reserved_1;
303 u32 rx_pri_map;
304 };
305
306 struct cpsw_hw_stats {
307 u32 rxgoodframes;
308 u32 rxbroadcastframes;
309 u32 rxmulticastframes;
310 u32 rxpauseframes;
311 u32 rxcrcerrors;
312 u32 rxaligncodeerrors;
313 u32 rxoversizedframes;
314 u32 rxjabberframes;
315 u32 rxundersizedframes;
316 u32 rxfragments;
317 u32 __pad_0[2];
318 u32 rxoctets;
319 u32 txgoodframes;
320 u32 txbroadcastframes;
321 u32 txmulticastframes;
322 u32 txpauseframes;
323 u32 txdeferredframes;
324 u32 txcollisionframes;
325 u32 txsinglecollframes;
326 u32 txmultcollframes;
327 u32 txexcessivecollisions;
328 u32 txlatecollisions;
329 u32 txunderrun;
330 u32 txcarriersenseerrors;
331 u32 txoctets;
332 u32 octetframes64;
333 u32 octetframes65t127;
334 u32 octetframes128t255;
335 u32 octetframes256t511;
336 u32 octetframes512t1023;
337 u32 octetframes1024tup;
338 u32 netoctets;
339 u32 rxsofoverruns;
340 u32 rxmofoverruns;
341 u32 rxdmaoverruns;
342 };
343
344 struct cpsw_slave {
345 void __iomem *regs;
346 struct cpsw_sliver_regs __iomem *sliver;
347 int slave_num;
348 u32 mac_control;
349 struct cpsw_slave_data *data;
350 struct phy_device *phy;
351 struct net_device *ndev;
352 u32 port_vlan;
353 u32 open_stat;
354 };
355
356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
357 {
358 return __raw_readl(slave->regs + offset);
359 }
360
361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
362 {
363 __raw_writel(val, slave->regs + offset);
364 }
365
366 struct cpsw_priv {
367 struct platform_device *pdev;
368 struct net_device *ndev;
369 struct napi_struct napi_rx;
370 struct napi_struct napi_tx;
371 struct device *dev;
372 struct cpsw_platform_data data;
373 struct cpsw_ss_regs __iomem *regs;
374 struct cpsw_wr_regs __iomem *wr_regs;
375 u8 __iomem *hw_stats;
376 struct cpsw_host_regs __iomem *host_port_regs;
377 u32 msg_enable;
378 u32 version;
379 u32 coal_intvl;
380 u32 bus_freq_mhz;
381 int rx_packet_max;
382 struct clk *clk;
383 u8 mac_addr[ETH_ALEN];
384 struct cpsw_slave *slaves;
385 struct cpdma_ctlr *dma;
386 struct cpdma_chan *txch, *rxch;
387 struct cpsw_ale *ale;
388 bool rx_pause;
389 bool tx_pause;
390 bool quirk_irq;
391 bool rx_irq_disabled;
392 bool tx_irq_disabled;
393 /* snapshot of IRQ numbers */
394 u32 irqs_table[4];
395 u32 num_irqs;
396 struct cpts *cpts;
397 u32 emac_port;
398 };
399
400 struct cpsw_stats {
401 char stat_string[ETH_GSTRING_LEN];
402 int type;
403 int sizeof_stat;
404 int stat_offset;
405 };
406
407 enum {
408 CPSW_STATS,
409 CPDMA_RX_STATS,
410 CPDMA_TX_STATS,
411 };
412
413 #define CPSW_STAT(m) CPSW_STATS, \
414 sizeof(((struct cpsw_hw_stats *)0)->m), \
415 offsetof(struct cpsw_hw_stats, m)
416 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
417 sizeof(((struct cpdma_chan_stats *)0)->m), \
418 offsetof(struct cpdma_chan_stats, m)
419 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
420 sizeof(((struct cpdma_chan_stats *)0)->m), \
421 offsetof(struct cpdma_chan_stats, m)
422
423 static const struct cpsw_stats cpsw_gstrings_stats[] = {
424 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
425 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
426 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
427 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
428 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
429 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
430 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
431 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
432 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
433 { "Rx Fragments", CPSW_STAT(rxfragments) },
434 { "Rx Octets", CPSW_STAT(rxoctets) },
435 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
436 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
437 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
438 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
439 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
440 { "Collisions", CPSW_STAT(txcollisionframes) },
441 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
442 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
443 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
444 { "Late Collisions", CPSW_STAT(txlatecollisions) },
445 { "Tx Underrun", CPSW_STAT(txunderrun) },
446 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
447 { "Tx Octets", CPSW_STAT(txoctets) },
448 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
449 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
450 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
451 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
452 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
453 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
454 { "Net Octets", CPSW_STAT(netoctets) },
455 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
456 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
457 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
458 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
459 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
460 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
461 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
462 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
463 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
464 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
465 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
466 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
467 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
468 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
469 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
470 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
471 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
472 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
473 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
474 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
475 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
476 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
477 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
478 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
479 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
480 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
481 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
482 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
483 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
484 };
485
486 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
487
488 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
489 #define for_each_slave(priv, func, arg...) \
490 do { \
491 struct cpsw_slave *slave; \
492 int n; \
493 if (priv->data.dual_emac) \
494 (func)((priv)->slaves + priv->emac_port, ##arg);\
495 else \
496 for (n = (priv)->data.slaves, \
497 slave = (priv)->slaves; \
498 n; n--) \
499 (func)(slave++, ##arg); \
500 } while (0)
501 #define cpsw_get_slave_ndev(priv, __slave_no__) \
502 ((__slave_no__ < priv->data.slaves) ? \
503 priv->slaves[__slave_no__].ndev : NULL)
504 #define cpsw_get_slave_priv(priv, __slave_no__) \
505 (((__slave_no__ < priv->data.slaves) && \
506 (priv->slaves[__slave_no__].ndev)) ? \
507 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
508
509 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
510 do { \
511 if (!priv->data.dual_emac) \
512 break; \
513 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
514 ndev = cpsw_get_slave_ndev(priv, 0); \
515 priv = netdev_priv(ndev); \
516 skb->dev = ndev; \
517 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
518 ndev = cpsw_get_slave_ndev(priv, 1); \
519 priv = netdev_priv(ndev); \
520 skb->dev = ndev; \
521 } \
522 } while (0)
523 #define cpsw_add_mcast(priv, addr) \
524 do { \
525 if (priv->data.dual_emac) { \
526 struct cpsw_slave *slave = priv->slaves + \
527 priv->emac_port; \
528 int slave_port = cpsw_get_slave_port(priv, \
529 slave->slave_num); \
530 cpsw_ale_add_mcast(priv->ale, addr, \
531 1 << slave_port | ALE_PORT_HOST, \
532 ALE_VLAN, slave->port_vlan, 0); \
533 } else { \
534 cpsw_ale_add_mcast(priv->ale, addr, \
535 ALE_ALL_PORTS, \
536 0, 0, 0); \
537 } \
538 } while (0)
539
540 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
541 {
542 return slave_num + 1;
543 }
544
545 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
546 {
547 struct cpsw_priv *priv = netdev_priv(ndev);
548 struct cpsw_ale *ale = priv->ale;
549 int i;
550
551 if (priv->data.dual_emac) {
552 bool flag = false;
553
554 /* Enabling promiscuous mode for one interface will be
555 * common for both the interface as the interface shares
556 * the same hardware resource.
557 */
558 for (i = 0; i < priv->data.slaves; i++)
559 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
560 flag = true;
561
562 if (!enable && flag) {
563 enable = true;
564 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
565 }
566
567 if (enable) {
568 /* Enable Bypass */
569 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
570
571 dev_dbg(&ndev->dev, "promiscuity enabled\n");
572 } else {
573 /* Disable Bypass */
574 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
575 dev_dbg(&ndev->dev, "promiscuity disabled\n");
576 }
577 } else {
578 if (enable) {
579 unsigned long timeout = jiffies + HZ;
580
581 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
582 for (i = 0; i <= priv->data.slaves; i++) {
583 cpsw_ale_control_set(ale, i,
584 ALE_PORT_NOLEARN, 1);
585 cpsw_ale_control_set(ale, i,
586 ALE_PORT_NO_SA_UPDATE, 1);
587 }
588
589 /* Clear All Untouched entries */
590 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
591 do {
592 cpu_relax();
593 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
594 break;
595 } while (time_after(timeout, jiffies));
596 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
597
598 /* Clear all mcast from ALE */
599 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
600
601 /* Flood All Unicast Packets to Host port */
602 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
603 dev_dbg(&ndev->dev, "promiscuity enabled\n");
604 } else {
605 /* Don't Flood All Unicast Packets to Host port */
606 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
607
608 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
609 for (i = 0; i <= priv->data.slaves; i++) {
610 cpsw_ale_control_set(ale, i,
611 ALE_PORT_NOLEARN, 0);
612 cpsw_ale_control_set(ale, i,
613 ALE_PORT_NO_SA_UPDATE, 0);
614 }
615 dev_dbg(&ndev->dev, "promiscuity disabled\n");
616 }
617 }
618 }
619
620 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
621 {
622 struct cpsw_priv *priv = netdev_priv(ndev);
623 int vid;
624
625 if (priv->data.dual_emac)
626 vid = priv->slaves[priv->emac_port].port_vlan;
627 else
628 vid = priv->data.default_vlan;
629
630 if (ndev->flags & IFF_PROMISC) {
631 /* Enable promiscuous mode */
632 cpsw_set_promiscious(ndev, true);
633 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
634 return;
635 } else {
636 /* Disable promiscuous mode */
637 cpsw_set_promiscious(ndev, false);
638 }
639
640 /* Restore allmulti on vlans if necessary */
641 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
642
643 /* Clear all mcast from ALE */
644 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS, vid);
645
646 if (!netdev_mc_empty(ndev)) {
647 struct netdev_hw_addr *ha;
648
649 /* program multicast address list into ALE register */
650 netdev_for_each_mc_addr(ha, ndev) {
651 cpsw_add_mcast(priv, (u8 *)ha->addr);
652 }
653 }
654 }
655
656 static void cpsw_intr_enable(struct cpsw_priv *priv)
657 {
658 __raw_writel(0xFF, &priv->wr_regs->tx_en);
659 __raw_writel(0xFF, &priv->wr_regs->rx_en);
660
661 cpdma_ctlr_int_ctrl(priv->dma, true);
662 return;
663 }
664
665 static void cpsw_intr_disable(struct cpsw_priv *priv)
666 {
667 __raw_writel(0, &priv->wr_regs->tx_en);
668 __raw_writel(0, &priv->wr_regs->rx_en);
669
670 cpdma_ctlr_int_ctrl(priv->dma, false);
671 return;
672 }
673
674 static void cpsw_tx_handler(void *token, int len, int status)
675 {
676 struct sk_buff *skb = token;
677 struct net_device *ndev = skb->dev;
678 struct cpsw_priv *priv = netdev_priv(ndev);
679
680 /* Check whether the queue is stopped due to stalled tx dma, if the
681 * queue is stopped then start the queue as we have free desc for tx
682 */
683 if (unlikely(netif_queue_stopped(ndev)))
684 netif_wake_queue(ndev);
685 cpts_tx_timestamp(priv->cpts, skb);
686 ndev->stats.tx_packets++;
687 ndev->stats.tx_bytes += len;
688 dev_kfree_skb_any(skb);
689 }
690
691 static void cpsw_rx_handler(void *token, int len, int status)
692 {
693 struct sk_buff *skb = token;
694 struct sk_buff *new_skb;
695 struct net_device *ndev = skb->dev;
696 struct cpsw_priv *priv = netdev_priv(ndev);
697 int ret = 0;
698
699 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
700
701 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
702 bool ndev_status = false;
703 struct cpsw_slave *slave = priv->slaves;
704 int n;
705
706 if (priv->data.dual_emac) {
707 /* In dual emac mode check for all interfaces */
708 for (n = priv->data.slaves; n; n--, slave++)
709 if (netif_running(slave->ndev))
710 ndev_status = true;
711 }
712
713 if (ndev_status && (status >= 0)) {
714 /* The packet received is for the interface which
715 * is already down and the other interface is up
716 * and running, instead of freeing which results
717 * in reducing of the number of rx descriptor in
718 * DMA engine, requeue skb back to cpdma.
719 */
720 new_skb = skb;
721 goto requeue;
722 }
723
724 /* the interface is going down, skbs are purged */
725 dev_kfree_skb_any(skb);
726 return;
727 }
728
729 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
730 if (new_skb) {
731 skb_put(skb, len);
732 cpts_rx_timestamp(priv->cpts, skb);
733 skb->protocol = eth_type_trans(skb, ndev);
734 netif_receive_skb(skb);
735 ndev->stats.rx_bytes += len;
736 ndev->stats.rx_packets++;
737 kmemleak_not_leak(new_skb);
738 } else {
739 ndev->stats.rx_dropped++;
740 new_skb = skb;
741 }
742
743 requeue:
744 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
745 skb_tailroom(new_skb), 0);
746 if (WARN_ON(ret < 0))
747 dev_kfree_skb_any(new_skb);
748 }
749
750 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
751 {
752 struct cpsw_priv *priv = dev_id;
753
754 writel(0, &priv->wr_regs->tx_en);
755 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
756
757 if (priv->quirk_irq) {
758 disable_irq_nosync(priv->irqs_table[1]);
759 priv->tx_irq_disabled = true;
760 }
761
762 napi_schedule(&priv->napi_tx);
763 return IRQ_HANDLED;
764 }
765
766 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
767 {
768 struct cpsw_priv *priv = dev_id;
769
770 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
771 writel(0, &priv->wr_regs->rx_en);
772
773 if (priv->quirk_irq) {
774 disable_irq_nosync(priv->irqs_table[0]);
775 priv->rx_irq_disabled = true;
776 }
777
778 napi_schedule(&priv->napi_rx);
779 return IRQ_HANDLED;
780 }
781
782 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
783 {
784 struct cpsw_priv *priv = napi_to_priv(napi_tx);
785 int num_tx;
786
787 num_tx = cpdma_chan_process(priv->txch, budget);
788 if (num_tx < budget) {
789 napi_complete(napi_tx);
790 writel(0xff, &priv->wr_regs->tx_en);
791 if (priv->quirk_irq && priv->tx_irq_disabled) {
792 priv->tx_irq_disabled = false;
793 enable_irq(priv->irqs_table[1]);
794 }
795 }
796
797 if (num_tx)
798 cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx);
799
800 return num_tx;
801 }
802
803 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
804 {
805 struct cpsw_priv *priv = napi_to_priv(napi_rx);
806 int num_rx;
807
808 num_rx = cpdma_chan_process(priv->rxch, budget);
809 if (num_rx < budget) {
810 napi_complete(napi_rx);
811 writel(0xff, &priv->wr_regs->rx_en);
812 if (priv->quirk_irq && priv->rx_irq_disabled) {
813 priv->rx_irq_disabled = false;
814 enable_irq(priv->irqs_table[0]);
815 }
816 }
817
818 if (num_rx)
819 cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
820
821 return num_rx;
822 }
823
824 static inline void soft_reset(const char *module, void __iomem *reg)
825 {
826 unsigned long timeout = jiffies + HZ;
827
828 __raw_writel(1, reg);
829 do {
830 cpu_relax();
831 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
832
833 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
834 }
835
836 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
837 ((mac)[2] << 16) | ((mac)[3] << 24))
838 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
839
840 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
841 struct cpsw_priv *priv)
842 {
843 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
844 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
845 }
846
847 static void _cpsw_adjust_link(struct cpsw_slave *slave,
848 struct cpsw_priv *priv, bool *link)
849 {
850 struct phy_device *phy = slave->phy;
851 u32 mac_control = 0;
852 u32 slave_port;
853
854 if (!phy)
855 return;
856
857 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
858
859 if (phy->link) {
860 mac_control = priv->data.mac_control;
861
862 /* enable forwarding */
863 cpsw_ale_control_set(priv->ale, slave_port,
864 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
865
866 if (phy->speed == 1000)
867 mac_control |= BIT(7); /* GIGABITEN */
868 if (phy->duplex)
869 mac_control |= BIT(0); /* FULLDUPLEXEN */
870
871 /* set speed_in input in case RMII mode is used in 100Mbps */
872 if (phy->speed == 100)
873 mac_control |= BIT(15);
874 else if (phy->speed == 10)
875 mac_control |= BIT(18); /* In Band mode */
876
877 if (priv->rx_pause)
878 mac_control |= BIT(3);
879
880 if (priv->tx_pause)
881 mac_control |= BIT(4);
882
883 *link = true;
884 } else {
885 mac_control = 0;
886 /* disable forwarding */
887 cpsw_ale_control_set(priv->ale, slave_port,
888 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
889 }
890
891 if (mac_control != slave->mac_control) {
892 phy_print_status(phy);
893 __raw_writel(mac_control, &slave->sliver->mac_control);
894 }
895
896 slave->mac_control = mac_control;
897 }
898
899 static void cpsw_adjust_link(struct net_device *ndev)
900 {
901 struct cpsw_priv *priv = netdev_priv(ndev);
902 bool link = false;
903
904 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
905
906 if (link) {
907 netif_carrier_on(ndev);
908 if (netif_running(ndev))
909 netif_wake_queue(ndev);
910 } else {
911 netif_carrier_off(ndev);
912 netif_stop_queue(ndev);
913 }
914 }
915
916 static int cpsw_get_coalesce(struct net_device *ndev,
917 struct ethtool_coalesce *coal)
918 {
919 struct cpsw_priv *priv = netdev_priv(ndev);
920
921 coal->rx_coalesce_usecs = priv->coal_intvl;
922 return 0;
923 }
924
925 static int cpsw_set_coalesce(struct net_device *ndev,
926 struct ethtool_coalesce *coal)
927 {
928 struct cpsw_priv *priv = netdev_priv(ndev);
929 u32 int_ctrl;
930 u32 num_interrupts = 0;
931 u32 prescale = 0;
932 u32 addnl_dvdr = 1;
933 u32 coal_intvl = 0;
934
935 coal_intvl = coal->rx_coalesce_usecs;
936
937 int_ctrl = readl(&priv->wr_regs->int_control);
938 prescale = priv->bus_freq_mhz * 4;
939
940 if (!coal->rx_coalesce_usecs) {
941 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
942 goto update_return;
943 }
944
945 if (coal_intvl < CPSW_CMINTMIN_INTVL)
946 coal_intvl = CPSW_CMINTMIN_INTVL;
947
948 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
949 /* Interrupt pacer works with 4us Pulse, we can
950 * throttle further by dilating the 4us pulse.
951 */
952 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
953
954 if (addnl_dvdr > 1) {
955 prescale *= addnl_dvdr;
956 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
957 coal_intvl = (CPSW_CMINTMAX_INTVL
958 * addnl_dvdr);
959 } else {
960 addnl_dvdr = 1;
961 coal_intvl = CPSW_CMINTMAX_INTVL;
962 }
963 }
964
965 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
966 writel(num_interrupts, &priv->wr_regs->rx_imax);
967 writel(num_interrupts, &priv->wr_regs->tx_imax);
968
969 int_ctrl |= CPSW_INTPACEEN;
970 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
971 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
972
973 update_return:
974 writel(int_ctrl, &priv->wr_regs->int_control);
975
976 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
977 if (priv->data.dual_emac) {
978 int i;
979
980 for (i = 0; i < priv->data.slaves; i++) {
981 priv = netdev_priv(priv->slaves[i].ndev);
982 priv->coal_intvl = coal_intvl;
983 }
984 } else {
985 priv->coal_intvl = coal_intvl;
986 }
987
988 return 0;
989 }
990
991 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
992 {
993 switch (sset) {
994 case ETH_SS_STATS:
995 return CPSW_STATS_LEN;
996 default:
997 return -EOPNOTSUPP;
998 }
999 }
1000
1001 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1002 {
1003 u8 *p = data;
1004 int i;
1005
1006 switch (stringset) {
1007 case ETH_SS_STATS:
1008 for (i = 0; i < CPSW_STATS_LEN; i++) {
1009 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1010 ETH_GSTRING_LEN);
1011 p += ETH_GSTRING_LEN;
1012 }
1013 break;
1014 }
1015 }
1016
1017 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1018 struct ethtool_stats *stats, u64 *data)
1019 {
1020 struct cpsw_priv *priv = netdev_priv(ndev);
1021 struct cpdma_chan_stats rx_stats;
1022 struct cpdma_chan_stats tx_stats;
1023 u32 val;
1024 u8 *p;
1025 int i;
1026
1027 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1028 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1029 cpdma_chan_get_stats(priv->txch, &tx_stats);
1030
1031 for (i = 0; i < CPSW_STATS_LEN; i++) {
1032 switch (cpsw_gstrings_stats[i].type) {
1033 case CPSW_STATS:
1034 val = readl(priv->hw_stats +
1035 cpsw_gstrings_stats[i].stat_offset);
1036 data[i] = val;
1037 break;
1038
1039 case CPDMA_RX_STATS:
1040 p = (u8 *)&rx_stats +
1041 cpsw_gstrings_stats[i].stat_offset;
1042 data[i] = *(u32 *)p;
1043 break;
1044
1045 case CPDMA_TX_STATS:
1046 p = (u8 *)&tx_stats +
1047 cpsw_gstrings_stats[i].stat_offset;
1048 data[i] = *(u32 *)p;
1049 break;
1050 }
1051 }
1052 }
1053
1054 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1055 {
1056 u32 i;
1057 u32 usage_count = 0;
1058
1059 if (!priv->data.dual_emac)
1060 return 0;
1061
1062 for (i = 0; i < priv->data.slaves; i++)
1063 if (priv->slaves[i].open_stat)
1064 usage_count++;
1065
1066 return usage_count;
1067 }
1068
1069 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1070 struct cpsw_priv *priv, struct sk_buff *skb)
1071 {
1072 if (!priv->data.dual_emac)
1073 return cpdma_chan_submit(priv->txch, skb, skb->data,
1074 skb->len, 0);
1075
1076 if (ndev == cpsw_get_slave_ndev(priv, 0))
1077 return cpdma_chan_submit(priv->txch, skb, skb->data,
1078 skb->len, 1);
1079 else
1080 return cpdma_chan_submit(priv->txch, skb, skb->data,
1081 skb->len, 2);
1082 }
1083
1084 static inline void cpsw_add_dual_emac_def_ale_entries(
1085 struct cpsw_priv *priv, struct cpsw_slave *slave,
1086 u32 slave_port)
1087 {
1088 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1089
1090 if (priv->version == CPSW_VERSION_1)
1091 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1092 else
1093 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1094 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1095 port_mask, port_mask, 0);
1096 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1097 port_mask, ALE_VLAN, slave->port_vlan, 0);
1098 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1099 HOST_PORT_NUM, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1100 }
1101
1102 static void soft_reset_slave(struct cpsw_slave *slave)
1103 {
1104 char name[32];
1105
1106 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1107 soft_reset(name, &slave->sliver->soft_reset);
1108 }
1109
1110 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1111 {
1112 u32 slave_port;
1113
1114 soft_reset_slave(slave);
1115
1116 /* setup priority mapping */
1117 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1118
1119 switch (priv->version) {
1120 case CPSW_VERSION_1:
1121 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1122 break;
1123 case CPSW_VERSION_2:
1124 case CPSW_VERSION_3:
1125 case CPSW_VERSION_4:
1126 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1127 break;
1128 }
1129
1130 /* setup max packet size, and mac address */
1131 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1132 cpsw_set_slave_mac(slave, priv);
1133
1134 slave->mac_control = 0; /* no link yet */
1135
1136 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1137
1138 if (priv->data.dual_emac)
1139 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1140 else
1141 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1142 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1143
1144 if (slave->data->phy_node) {
1145 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1146 &cpsw_adjust_link, 0, slave->data->phy_if);
1147 if (!slave->phy) {
1148 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1149 slave->data->phy_node->full_name,
1150 slave->slave_num);
1151 return;
1152 }
1153 } else {
1154 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1155 &cpsw_adjust_link, slave->data->phy_if);
1156 if (IS_ERR(slave->phy)) {
1157 dev_err(priv->dev,
1158 "phy \"%s\" not found on slave %d, err %ld\n",
1159 slave->data->phy_id, slave->slave_num,
1160 PTR_ERR(slave->phy));
1161 slave->phy = NULL;
1162 return;
1163 }
1164 }
1165
1166 phy_attached_info(slave->phy);
1167
1168 phy_start(slave->phy);
1169
1170 /* Configure GMII_SEL register */
1171 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, slave->slave_num);
1172 }
1173
1174 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1175 {
1176 const int vlan = priv->data.default_vlan;
1177 u32 reg;
1178 int i;
1179 int unreg_mcast_mask;
1180
1181 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1182 CPSW2_PORT_VLAN;
1183
1184 writel(vlan, &priv->host_port_regs->port_vlan);
1185
1186 for (i = 0; i < priv->data.slaves; i++)
1187 slave_write(priv->slaves + i, vlan, reg);
1188
1189 if (priv->ndev->flags & IFF_ALLMULTI)
1190 unreg_mcast_mask = ALE_ALL_PORTS;
1191 else
1192 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1193
1194 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS,
1195 ALE_ALL_PORTS, ALE_ALL_PORTS,
1196 unreg_mcast_mask);
1197 }
1198
1199 static void cpsw_init_host_port(struct cpsw_priv *priv)
1200 {
1201 u32 control_reg;
1202 u32 fifo_mode;
1203
1204 /* soft reset the controller and initialize ale */
1205 soft_reset("cpsw", &priv->regs->soft_reset);
1206 cpsw_ale_start(priv->ale);
1207
1208 /* switch to vlan unaware mode */
1209 cpsw_ale_control_set(priv->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1210 CPSW_ALE_VLAN_AWARE);
1211 control_reg = readl(&priv->regs->control);
1212 control_reg |= CPSW_VLAN_AWARE;
1213 writel(control_reg, &priv->regs->control);
1214 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1215 CPSW_FIFO_NORMAL_MODE;
1216 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1217
1218 /* setup host port priority mapping */
1219 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1220 &priv->host_port_regs->cpdma_tx_pri_map);
1221 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1222
1223 cpsw_ale_control_set(priv->ale, HOST_PORT_NUM,
1224 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1225
1226 if (!priv->data.dual_emac) {
1227 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
1228 0, 0);
1229 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1230 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1231 }
1232 }
1233
1234 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1235 {
1236 u32 slave_port;
1237
1238 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1239
1240 if (!slave->phy)
1241 return;
1242 phy_stop(slave->phy);
1243 phy_disconnect(slave->phy);
1244 slave->phy = NULL;
1245 cpsw_ale_control_set(priv->ale, slave_port,
1246 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1247 soft_reset_slave(slave);
1248 }
1249
1250 static int cpsw_ndo_open(struct net_device *ndev)
1251 {
1252 struct cpsw_priv *priv = netdev_priv(ndev);
1253 int i, ret;
1254 u32 reg;
1255
1256 ret = pm_runtime_get_sync(&priv->pdev->dev);
1257 if (ret < 0) {
1258 pm_runtime_put_noidle(&priv->pdev->dev);
1259 return ret;
1260 }
1261
1262 if (!cpsw_common_res_usage_state(priv))
1263 cpsw_intr_disable(priv);
1264 netif_carrier_off(ndev);
1265
1266 reg = priv->version;
1267
1268 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1269 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1270 CPSW_RTL_VERSION(reg));
1271
1272 /* initialize host and slave ports */
1273 if (!cpsw_common_res_usage_state(priv))
1274 cpsw_init_host_port(priv);
1275 for_each_slave(priv, cpsw_slave_open, priv);
1276
1277 /* Add default VLAN */
1278 if (!priv->data.dual_emac)
1279 cpsw_add_default_vlan(priv);
1280 else
1281 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1282 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1283
1284 if (!cpsw_common_res_usage_state(priv)) {
1285 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1286 int buf_num;
1287
1288 /* setup tx dma to fixed prio and zero offset */
1289 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1290 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1291
1292 /* disable priority elevation */
1293 __raw_writel(0, &priv->regs->ptype);
1294
1295 /* enable statistics collection only on all ports */
1296 __raw_writel(0x7, &priv->regs->stat_port_en);
1297
1298 /* Enable internal fifo flow control */
1299 writel(0x7, &priv->regs->flow_control);
1300
1301 napi_enable(&priv_sl0->napi_rx);
1302 napi_enable(&priv_sl0->napi_tx);
1303
1304 if (priv_sl0->tx_irq_disabled) {
1305 priv_sl0->tx_irq_disabled = false;
1306 enable_irq(priv->irqs_table[1]);
1307 }
1308
1309 if (priv_sl0->rx_irq_disabled) {
1310 priv_sl0->rx_irq_disabled = false;
1311 enable_irq(priv->irqs_table[0]);
1312 }
1313
1314 buf_num = cpdma_chan_get_rx_buf_num(priv->dma);
1315 for (i = 0; i < buf_num; i++) {
1316 struct sk_buff *skb;
1317
1318 ret = -ENOMEM;
1319 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1320 priv->rx_packet_max, GFP_KERNEL);
1321 if (!skb)
1322 goto err_cleanup;
1323 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1324 skb_tailroom(skb), 0);
1325 if (ret < 0) {
1326 kfree_skb(skb);
1327 goto err_cleanup;
1328 }
1329 kmemleak_not_leak(skb);
1330 }
1331 /* continue even if we didn't manage to submit all
1332 * receive descs
1333 */
1334 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1335
1336 if (cpts_register(&priv->pdev->dev, priv->cpts,
1337 priv->data.cpts_clock_mult,
1338 priv->data.cpts_clock_shift))
1339 dev_err(priv->dev, "error registering cpts device\n");
1340
1341 }
1342
1343 /* Enable Interrupt pacing if configured */
1344 if (priv->coal_intvl != 0) {
1345 struct ethtool_coalesce coal;
1346
1347 coal.rx_coalesce_usecs = priv->coal_intvl;
1348 cpsw_set_coalesce(ndev, &coal);
1349 }
1350
1351 cpdma_ctlr_start(priv->dma);
1352 cpsw_intr_enable(priv);
1353
1354 if (priv->data.dual_emac)
1355 priv->slaves[priv->emac_port].open_stat = true;
1356 return 0;
1357
1358 err_cleanup:
1359 cpdma_ctlr_stop(priv->dma);
1360 for_each_slave(priv, cpsw_slave_stop, priv);
1361 pm_runtime_put_sync(&priv->pdev->dev);
1362 netif_carrier_off(priv->ndev);
1363 return ret;
1364 }
1365
1366 static int cpsw_ndo_stop(struct net_device *ndev)
1367 {
1368 struct cpsw_priv *priv = netdev_priv(ndev);
1369
1370 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1371 netif_stop_queue(priv->ndev);
1372 netif_carrier_off(priv->ndev);
1373
1374 if (cpsw_common_res_usage_state(priv) <= 1) {
1375 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1376
1377 napi_disable(&priv_sl0->napi_rx);
1378 napi_disable(&priv_sl0->napi_tx);
1379 cpts_unregister(priv->cpts);
1380 cpsw_intr_disable(priv);
1381 cpdma_ctlr_stop(priv->dma);
1382 cpsw_ale_stop(priv->ale);
1383 }
1384 for_each_slave(priv, cpsw_slave_stop, priv);
1385 pm_runtime_put_sync(&priv->pdev->dev);
1386 if (priv->data.dual_emac)
1387 priv->slaves[priv->emac_port].open_stat = false;
1388 return 0;
1389 }
1390
1391 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1392 struct net_device *ndev)
1393 {
1394 struct cpsw_priv *priv = netdev_priv(ndev);
1395 int ret;
1396
1397 netif_trans_update(ndev);
1398
1399 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1400 cpsw_err(priv, tx_err, "packet pad failed\n");
1401 ndev->stats.tx_dropped++;
1402 return NETDEV_TX_OK;
1403 }
1404
1405 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1406 priv->cpts->tx_enable)
1407 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1408
1409 skb_tx_timestamp(skb);
1410
1411 ret = cpsw_tx_packet_submit(ndev, priv, skb);
1412 if (unlikely(ret != 0)) {
1413 cpsw_err(priv, tx_err, "desc submit failed\n");
1414 goto fail;
1415 }
1416
1417 /* If there is no more tx desc left free then we need to
1418 * tell the kernel to stop sending us tx frames.
1419 */
1420 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1421 netif_stop_queue(ndev);
1422
1423 return NETDEV_TX_OK;
1424 fail:
1425 ndev->stats.tx_dropped++;
1426 netif_stop_queue(ndev);
1427 return NETDEV_TX_BUSY;
1428 }
1429
1430 #ifdef CONFIG_TI_CPTS
1431
1432 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1433 {
1434 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1435 u32 ts_en, seq_id;
1436
1437 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1438 slave_write(slave, 0, CPSW1_TS_CTL);
1439 return;
1440 }
1441
1442 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1443 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1444
1445 if (priv->cpts->tx_enable)
1446 ts_en |= CPSW_V1_TS_TX_EN;
1447
1448 if (priv->cpts->rx_enable)
1449 ts_en |= CPSW_V1_TS_RX_EN;
1450
1451 slave_write(slave, ts_en, CPSW1_TS_CTL);
1452 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1453 }
1454
1455 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1456 {
1457 struct cpsw_slave *slave;
1458 u32 ctrl, mtype;
1459
1460 if (priv->data.dual_emac)
1461 slave = &priv->slaves[priv->emac_port];
1462 else
1463 slave = &priv->slaves[priv->data.active_slave];
1464
1465 ctrl = slave_read(slave, CPSW2_CONTROL);
1466 switch (priv->version) {
1467 case CPSW_VERSION_2:
1468 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1469
1470 if (priv->cpts->tx_enable)
1471 ctrl |= CTRL_V2_TX_TS_BITS;
1472
1473 if (priv->cpts->rx_enable)
1474 ctrl |= CTRL_V2_RX_TS_BITS;
1475 break;
1476 case CPSW_VERSION_3:
1477 default:
1478 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1479
1480 if (priv->cpts->tx_enable)
1481 ctrl |= CTRL_V3_TX_TS_BITS;
1482
1483 if (priv->cpts->rx_enable)
1484 ctrl |= CTRL_V3_RX_TS_BITS;
1485 break;
1486 }
1487
1488 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1489
1490 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1491 slave_write(slave, ctrl, CPSW2_CONTROL);
1492 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1493 }
1494
1495 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1496 {
1497 struct cpsw_priv *priv = netdev_priv(dev);
1498 struct cpts *cpts = priv->cpts;
1499 struct hwtstamp_config cfg;
1500
1501 if (priv->version != CPSW_VERSION_1 &&
1502 priv->version != CPSW_VERSION_2 &&
1503 priv->version != CPSW_VERSION_3)
1504 return -EOPNOTSUPP;
1505
1506 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1507 return -EFAULT;
1508
1509 /* reserved for future extensions */
1510 if (cfg.flags)
1511 return -EINVAL;
1512
1513 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1514 return -ERANGE;
1515
1516 switch (cfg.rx_filter) {
1517 case HWTSTAMP_FILTER_NONE:
1518 cpts->rx_enable = 0;
1519 break;
1520 case HWTSTAMP_FILTER_ALL:
1521 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1522 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1523 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1524 return -ERANGE;
1525 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1526 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1527 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1528 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1529 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1530 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1531 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1532 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1533 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1534 cpts->rx_enable = 1;
1535 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1536 break;
1537 default:
1538 return -ERANGE;
1539 }
1540
1541 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1542
1543 switch (priv->version) {
1544 case CPSW_VERSION_1:
1545 cpsw_hwtstamp_v1(priv);
1546 break;
1547 case CPSW_VERSION_2:
1548 case CPSW_VERSION_3:
1549 cpsw_hwtstamp_v2(priv);
1550 break;
1551 default:
1552 WARN_ON(1);
1553 }
1554
1555 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1556 }
1557
1558 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1559 {
1560 struct cpsw_priv *priv = netdev_priv(dev);
1561 struct cpts *cpts = priv->cpts;
1562 struct hwtstamp_config cfg;
1563
1564 if (priv->version != CPSW_VERSION_1 &&
1565 priv->version != CPSW_VERSION_2 &&
1566 priv->version != CPSW_VERSION_3)
1567 return -EOPNOTSUPP;
1568
1569 cfg.flags = 0;
1570 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1571 cfg.rx_filter = (cpts->rx_enable ?
1572 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1573
1574 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1575 }
1576
1577 #endif /*CONFIG_TI_CPTS*/
1578
1579 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1580 {
1581 struct cpsw_priv *priv = netdev_priv(dev);
1582 int slave_no = cpsw_slave_index(priv);
1583
1584 if (!netif_running(dev))
1585 return -EINVAL;
1586
1587 switch (cmd) {
1588 #ifdef CONFIG_TI_CPTS
1589 case SIOCSHWTSTAMP:
1590 return cpsw_hwtstamp_set(dev, req);
1591 case SIOCGHWTSTAMP:
1592 return cpsw_hwtstamp_get(dev, req);
1593 #endif
1594 }
1595
1596 if (!priv->slaves[slave_no].phy)
1597 return -EOPNOTSUPP;
1598 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1599 }
1600
1601 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1602 {
1603 struct cpsw_priv *priv = netdev_priv(ndev);
1604
1605 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1606 ndev->stats.tx_errors++;
1607 cpsw_intr_disable(priv);
1608 cpdma_chan_stop(priv->txch);
1609 cpdma_chan_start(priv->txch);
1610 cpsw_intr_enable(priv);
1611 }
1612
1613 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1614 {
1615 struct cpsw_priv *priv = netdev_priv(ndev);
1616 struct sockaddr *addr = (struct sockaddr *)p;
1617 int flags = 0;
1618 u16 vid = 0;
1619 int ret;
1620
1621 if (!is_valid_ether_addr(addr->sa_data))
1622 return -EADDRNOTAVAIL;
1623
1624 ret = pm_runtime_get_sync(&priv->pdev->dev);
1625 if (ret < 0) {
1626 pm_runtime_put_noidle(&priv->pdev->dev);
1627 return ret;
1628 }
1629
1630 if (priv->data.dual_emac) {
1631 vid = priv->slaves[priv->emac_port].port_vlan;
1632 flags = ALE_VLAN;
1633 }
1634
1635 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, HOST_PORT_NUM,
1636 flags, vid);
1637 cpsw_ale_add_ucast(priv->ale, addr->sa_data, HOST_PORT_NUM,
1638 flags, vid);
1639
1640 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1641 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1642 for_each_slave(priv, cpsw_set_slave_mac, priv);
1643
1644 pm_runtime_put(&priv->pdev->dev);
1645
1646 return 0;
1647 }
1648
1649 #ifdef CONFIG_NET_POLL_CONTROLLER
1650 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1651 {
1652 struct cpsw_priv *priv = netdev_priv(ndev);
1653
1654 cpsw_intr_disable(priv);
1655 cpsw_rx_interrupt(priv->irqs_table[0], priv);
1656 cpsw_tx_interrupt(priv->irqs_table[1], priv);
1657 cpsw_intr_enable(priv);
1658 }
1659 #endif
1660
1661 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1662 unsigned short vid)
1663 {
1664 int ret;
1665 int unreg_mcast_mask = 0;
1666 u32 port_mask;
1667
1668 if (priv->data.dual_emac) {
1669 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1670
1671 if (priv->ndev->flags & IFF_ALLMULTI)
1672 unreg_mcast_mask = port_mask;
1673 } else {
1674 port_mask = ALE_ALL_PORTS;
1675
1676 if (priv->ndev->flags & IFF_ALLMULTI)
1677 unreg_mcast_mask = ALE_ALL_PORTS;
1678 else
1679 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1680 }
1681
1682 ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1683 unreg_mcast_mask);
1684 if (ret != 0)
1685 return ret;
1686
1687 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1688 HOST_PORT_NUM, ALE_VLAN, vid);
1689 if (ret != 0)
1690 goto clean_vid;
1691
1692 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1693 port_mask, ALE_VLAN, vid, 0);
1694 if (ret != 0)
1695 goto clean_vlan_ucast;
1696 return 0;
1697
1698 clean_vlan_ucast:
1699 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1700 HOST_PORT_NUM, ALE_VLAN, vid);
1701 clean_vid:
1702 cpsw_ale_del_vlan(priv->ale, vid, 0);
1703 return ret;
1704 }
1705
1706 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1707 __be16 proto, u16 vid)
1708 {
1709 struct cpsw_priv *priv = netdev_priv(ndev);
1710 int ret;
1711
1712 if (vid == priv->data.default_vlan)
1713 return 0;
1714
1715 ret = pm_runtime_get_sync(&priv->pdev->dev);
1716 if (ret < 0) {
1717 pm_runtime_put_noidle(&priv->pdev->dev);
1718 return ret;
1719 }
1720
1721 if (priv->data.dual_emac) {
1722 /* In dual EMAC, reserved VLAN id should not be used for
1723 * creating VLAN interfaces as this can break the dual
1724 * EMAC port separation
1725 */
1726 int i;
1727
1728 for (i = 0; i < priv->data.slaves; i++) {
1729 if (vid == priv->slaves[i].port_vlan)
1730 return -EINVAL;
1731 }
1732 }
1733
1734 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1735 ret = cpsw_add_vlan_ale_entry(priv, vid);
1736
1737 pm_runtime_put(&priv->pdev->dev);
1738 return ret;
1739 }
1740
1741 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1742 __be16 proto, u16 vid)
1743 {
1744 struct cpsw_priv *priv = netdev_priv(ndev);
1745 int ret;
1746
1747 if (vid == priv->data.default_vlan)
1748 return 0;
1749
1750 ret = pm_runtime_get_sync(&priv->pdev->dev);
1751 if (ret < 0) {
1752 pm_runtime_put_noidle(&priv->pdev->dev);
1753 return ret;
1754 }
1755
1756 if (priv->data.dual_emac) {
1757 int i;
1758
1759 for (i = 0; i < priv->data.slaves; i++) {
1760 if (vid == priv->slaves[i].port_vlan)
1761 return -EINVAL;
1762 }
1763 }
1764
1765 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1766 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1767 if (ret != 0)
1768 return ret;
1769
1770 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1771 HOST_PORT_NUM, ALE_VLAN, vid);
1772 if (ret != 0)
1773 return ret;
1774
1775 ret = cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1776 0, ALE_VLAN, vid);
1777 pm_runtime_put(&priv->pdev->dev);
1778 return ret;
1779 }
1780
1781 static const struct net_device_ops cpsw_netdev_ops = {
1782 .ndo_open = cpsw_ndo_open,
1783 .ndo_stop = cpsw_ndo_stop,
1784 .ndo_start_xmit = cpsw_ndo_start_xmit,
1785 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
1786 .ndo_do_ioctl = cpsw_ndo_ioctl,
1787 .ndo_validate_addr = eth_validate_addr,
1788 .ndo_change_mtu = eth_change_mtu,
1789 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
1790 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
1791 #ifdef CONFIG_NET_POLL_CONTROLLER
1792 .ndo_poll_controller = cpsw_ndo_poll_controller,
1793 #endif
1794 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1795 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
1796 };
1797
1798 static int cpsw_get_regs_len(struct net_device *ndev)
1799 {
1800 struct cpsw_priv *priv = netdev_priv(ndev);
1801
1802 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1803 }
1804
1805 static void cpsw_get_regs(struct net_device *ndev,
1806 struct ethtool_regs *regs, void *p)
1807 {
1808 struct cpsw_priv *priv = netdev_priv(ndev);
1809 u32 *reg = p;
1810
1811 /* update CPSW IP version */
1812 regs->version = priv->version;
1813
1814 cpsw_ale_dump(priv->ale, reg);
1815 }
1816
1817 static void cpsw_get_drvinfo(struct net_device *ndev,
1818 struct ethtool_drvinfo *info)
1819 {
1820 struct cpsw_priv *priv = netdev_priv(ndev);
1821
1822 strlcpy(info->driver, "cpsw", sizeof(info->driver));
1823 strlcpy(info->version, "1.0", sizeof(info->version));
1824 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1825 }
1826
1827 static u32 cpsw_get_msglevel(struct net_device *ndev)
1828 {
1829 struct cpsw_priv *priv = netdev_priv(ndev);
1830 return priv->msg_enable;
1831 }
1832
1833 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1834 {
1835 struct cpsw_priv *priv = netdev_priv(ndev);
1836 priv->msg_enable = value;
1837 }
1838
1839 static int cpsw_get_ts_info(struct net_device *ndev,
1840 struct ethtool_ts_info *info)
1841 {
1842 #ifdef CONFIG_TI_CPTS
1843 struct cpsw_priv *priv = netdev_priv(ndev);
1844
1845 info->so_timestamping =
1846 SOF_TIMESTAMPING_TX_HARDWARE |
1847 SOF_TIMESTAMPING_TX_SOFTWARE |
1848 SOF_TIMESTAMPING_RX_HARDWARE |
1849 SOF_TIMESTAMPING_RX_SOFTWARE |
1850 SOF_TIMESTAMPING_SOFTWARE |
1851 SOF_TIMESTAMPING_RAW_HARDWARE;
1852 info->phc_index = priv->cpts->phc_index;
1853 info->tx_types =
1854 (1 << HWTSTAMP_TX_OFF) |
1855 (1 << HWTSTAMP_TX_ON);
1856 info->rx_filters =
1857 (1 << HWTSTAMP_FILTER_NONE) |
1858 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1859 #else
1860 info->so_timestamping =
1861 SOF_TIMESTAMPING_TX_SOFTWARE |
1862 SOF_TIMESTAMPING_RX_SOFTWARE |
1863 SOF_TIMESTAMPING_SOFTWARE;
1864 info->phc_index = -1;
1865 info->tx_types = 0;
1866 info->rx_filters = 0;
1867 #endif
1868 return 0;
1869 }
1870
1871 static int cpsw_get_settings(struct net_device *ndev,
1872 struct ethtool_cmd *ecmd)
1873 {
1874 struct cpsw_priv *priv = netdev_priv(ndev);
1875 int slave_no = cpsw_slave_index(priv);
1876
1877 if (priv->slaves[slave_no].phy)
1878 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1879 else
1880 return -EOPNOTSUPP;
1881 }
1882
1883 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1884 {
1885 struct cpsw_priv *priv = netdev_priv(ndev);
1886 int slave_no = cpsw_slave_index(priv);
1887
1888 if (priv->slaves[slave_no].phy)
1889 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1890 else
1891 return -EOPNOTSUPP;
1892 }
1893
1894 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1895 {
1896 struct cpsw_priv *priv = netdev_priv(ndev);
1897 int slave_no = cpsw_slave_index(priv);
1898
1899 wol->supported = 0;
1900 wol->wolopts = 0;
1901
1902 if (priv->slaves[slave_no].phy)
1903 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1904 }
1905
1906 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1907 {
1908 struct cpsw_priv *priv = netdev_priv(ndev);
1909 int slave_no = cpsw_slave_index(priv);
1910
1911 if (priv->slaves[slave_no].phy)
1912 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1913 else
1914 return -EOPNOTSUPP;
1915 }
1916
1917 static void cpsw_get_pauseparam(struct net_device *ndev,
1918 struct ethtool_pauseparam *pause)
1919 {
1920 struct cpsw_priv *priv = netdev_priv(ndev);
1921
1922 pause->autoneg = AUTONEG_DISABLE;
1923 pause->rx_pause = priv->rx_pause ? true : false;
1924 pause->tx_pause = priv->tx_pause ? true : false;
1925 }
1926
1927 static int cpsw_set_pauseparam(struct net_device *ndev,
1928 struct ethtool_pauseparam *pause)
1929 {
1930 struct cpsw_priv *priv = netdev_priv(ndev);
1931 bool link;
1932
1933 priv->rx_pause = pause->rx_pause ? true : false;
1934 priv->tx_pause = pause->tx_pause ? true : false;
1935
1936 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1937 return 0;
1938 }
1939
1940 static int cpsw_ethtool_op_begin(struct net_device *ndev)
1941 {
1942 struct cpsw_priv *priv = netdev_priv(ndev);
1943 int ret;
1944
1945 ret = pm_runtime_get_sync(&priv->pdev->dev);
1946 if (ret < 0) {
1947 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
1948 pm_runtime_put_noidle(&priv->pdev->dev);
1949 }
1950
1951 return ret;
1952 }
1953
1954 static void cpsw_ethtool_op_complete(struct net_device *ndev)
1955 {
1956 struct cpsw_priv *priv = netdev_priv(ndev);
1957 int ret;
1958
1959 ret = pm_runtime_put(&priv->pdev->dev);
1960 if (ret < 0)
1961 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
1962 }
1963
1964 static const struct ethtool_ops cpsw_ethtool_ops = {
1965 .get_drvinfo = cpsw_get_drvinfo,
1966 .get_msglevel = cpsw_get_msglevel,
1967 .set_msglevel = cpsw_set_msglevel,
1968 .get_link = ethtool_op_get_link,
1969 .get_ts_info = cpsw_get_ts_info,
1970 .get_settings = cpsw_get_settings,
1971 .set_settings = cpsw_set_settings,
1972 .get_coalesce = cpsw_get_coalesce,
1973 .set_coalesce = cpsw_set_coalesce,
1974 .get_sset_count = cpsw_get_sset_count,
1975 .get_strings = cpsw_get_strings,
1976 .get_ethtool_stats = cpsw_get_ethtool_stats,
1977 .get_pauseparam = cpsw_get_pauseparam,
1978 .set_pauseparam = cpsw_set_pauseparam,
1979 .get_wol = cpsw_get_wol,
1980 .set_wol = cpsw_set_wol,
1981 .get_regs_len = cpsw_get_regs_len,
1982 .get_regs = cpsw_get_regs,
1983 .begin = cpsw_ethtool_op_begin,
1984 .complete = cpsw_ethtool_op_complete,
1985 };
1986
1987 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1988 u32 slave_reg_ofs, u32 sliver_reg_ofs)
1989 {
1990 void __iomem *regs = priv->regs;
1991 int slave_num = slave->slave_num;
1992 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1993
1994 slave->data = data;
1995 slave->regs = regs + slave_reg_ofs;
1996 slave->sliver = regs + sliver_reg_ofs;
1997 slave->port_vlan = data->dual_emac_res_vlan;
1998 }
1999
2000 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2001 struct platform_device *pdev)
2002 {
2003 struct device_node *node = pdev->dev.of_node;
2004 struct device_node *slave_node;
2005 int i = 0, ret;
2006 u32 prop;
2007
2008 if (!node)
2009 return -EINVAL;
2010
2011 if (of_property_read_u32(node, "slaves", &prop)) {
2012 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2013 return -EINVAL;
2014 }
2015 data->slaves = prop;
2016
2017 if (of_property_read_u32(node, "active_slave", &prop)) {
2018 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2019 return -EINVAL;
2020 }
2021 data->active_slave = prop;
2022
2023 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
2024 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
2025 return -EINVAL;
2026 }
2027 data->cpts_clock_mult = prop;
2028
2029 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
2030 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
2031 return -EINVAL;
2032 }
2033 data->cpts_clock_shift = prop;
2034
2035 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2036 * sizeof(struct cpsw_slave_data),
2037 GFP_KERNEL);
2038 if (!data->slave_data)
2039 return -ENOMEM;
2040
2041 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2042 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2043 return -EINVAL;
2044 }
2045 data->channels = prop;
2046
2047 if (of_property_read_u32(node, "ale_entries", &prop)) {
2048 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2049 return -EINVAL;
2050 }
2051 data->ale_entries = prop;
2052
2053 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2054 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2055 return -EINVAL;
2056 }
2057 data->bd_ram_size = prop;
2058
2059 if (of_property_read_u32(node, "mac_control", &prop)) {
2060 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2061 return -EINVAL;
2062 }
2063 data->mac_control = prop;
2064
2065 if (of_property_read_bool(node, "dual_emac"))
2066 data->dual_emac = 1;
2067
2068 /*
2069 * Populate all the child nodes here...
2070 */
2071 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2072 /* We do not want to force this, as in some cases may not have child */
2073 if (ret)
2074 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2075
2076 for_each_available_child_of_node(node, slave_node) {
2077 struct cpsw_slave_data *slave_data = data->slave_data + i;
2078 const void *mac_addr = NULL;
2079 int lenp;
2080 const __be32 *parp;
2081
2082 /* This is no slave child node, continue */
2083 if (strcmp(slave_node->name, "slave"))
2084 continue;
2085
2086 slave_data->phy_node = of_parse_phandle(slave_node,
2087 "phy-handle", 0);
2088 parp = of_get_property(slave_node, "phy_id", &lenp);
2089 if (slave_data->phy_node) {
2090 dev_dbg(&pdev->dev,
2091 "slave[%d] using phy-handle=\"%s\"\n",
2092 i, slave_data->phy_node->full_name);
2093 } else if (of_phy_is_fixed_link(slave_node)) {
2094 /* In the case of a fixed PHY, the DT node associated
2095 * to the PHY is the Ethernet MAC DT node.
2096 */
2097 ret = of_phy_register_fixed_link(slave_node);
2098 if (ret)
2099 return ret;
2100 slave_data->phy_node = of_node_get(slave_node);
2101 } else if (parp) {
2102 u32 phyid;
2103 struct device_node *mdio_node;
2104 struct platform_device *mdio;
2105
2106 if (lenp != (sizeof(__be32) * 2)) {
2107 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2108 goto no_phy_slave;
2109 }
2110 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2111 phyid = be32_to_cpup(parp+1);
2112 mdio = of_find_device_by_node(mdio_node);
2113 of_node_put(mdio_node);
2114 if (!mdio) {
2115 dev_err(&pdev->dev, "Missing mdio platform device\n");
2116 return -EINVAL;
2117 }
2118 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2119 PHY_ID_FMT, mdio->name, phyid);
2120 } else {
2121 dev_err(&pdev->dev,
2122 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2123 i);
2124 goto no_phy_slave;
2125 }
2126 slave_data->phy_if = of_get_phy_mode(slave_node);
2127 if (slave_data->phy_if < 0) {
2128 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2129 i);
2130 return slave_data->phy_if;
2131 }
2132
2133 no_phy_slave:
2134 mac_addr = of_get_mac_address(slave_node);
2135 if (mac_addr) {
2136 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2137 } else {
2138 ret = ti_cm_get_macid(&pdev->dev, i,
2139 slave_data->mac_addr);
2140 if (ret)
2141 return ret;
2142 }
2143 if (data->dual_emac) {
2144 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2145 &prop)) {
2146 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2147 slave_data->dual_emac_res_vlan = i+1;
2148 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2149 slave_data->dual_emac_res_vlan, i);
2150 } else {
2151 slave_data->dual_emac_res_vlan = prop;
2152 }
2153 }
2154
2155 i++;
2156 if (i == data->slaves)
2157 break;
2158 }
2159
2160 return 0;
2161 }
2162
2163 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2164 struct cpsw_priv *priv)
2165 {
2166 struct cpsw_platform_data *data = &priv->data;
2167 struct net_device *ndev;
2168 struct cpsw_priv *priv_sl2;
2169 int ret = 0, i;
2170
2171 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2172 if (!ndev) {
2173 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2174 return -ENOMEM;
2175 }
2176
2177 priv_sl2 = netdev_priv(ndev);
2178 priv_sl2->data = *data;
2179 priv_sl2->pdev = pdev;
2180 priv_sl2->ndev = ndev;
2181 priv_sl2->dev = &ndev->dev;
2182 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2183 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2184
2185 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2186 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2187 ETH_ALEN);
2188 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2189 } else {
2190 random_ether_addr(priv_sl2->mac_addr);
2191 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2192 }
2193 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2194
2195 priv_sl2->slaves = priv->slaves;
2196 priv_sl2->clk = priv->clk;
2197
2198 priv_sl2->coal_intvl = 0;
2199 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2200
2201 priv_sl2->regs = priv->regs;
2202 priv_sl2->host_port_regs = priv->host_port_regs;
2203 priv_sl2->wr_regs = priv->wr_regs;
2204 priv_sl2->hw_stats = priv->hw_stats;
2205 priv_sl2->dma = priv->dma;
2206 priv_sl2->txch = priv->txch;
2207 priv_sl2->rxch = priv->rxch;
2208 priv_sl2->ale = priv->ale;
2209 priv_sl2->emac_port = 1;
2210 priv->slaves[1].ndev = ndev;
2211 priv_sl2->cpts = priv->cpts;
2212 priv_sl2->version = priv->version;
2213
2214 for (i = 0; i < priv->num_irqs; i++) {
2215 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2216 priv_sl2->num_irqs = priv->num_irqs;
2217 }
2218 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2219
2220 ndev->netdev_ops = &cpsw_netdev_ops;
2221 ndev->ethtool_ops = &cpsw_ethtool_ops;
2222
2223 /* register the network device */
2224 SET_NETDEV_DEV(ndev, &pdev->dev);
2225 ret = register_netdev(ndev);
2226 if (ret) {
2227 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2228 free_netdev(ndev);
2229 ret = -ENODEV;
2230 }
2231
2232 return ret;
2233 }
2234
2235 #define CPSW_QUIRK_IRQ BIT(0)
2236
2237 static struct platform_device_id cpsw_devtype[] = {
2238 {
2239 /* keep it for existing comaptibles */
2240 .name = "cpsw",
2241 .driver_data = CPSW_QUIRK_IRQ,
2242 }, {
2243 .name = "am335x-cpsw",
2244 .driver_data = CPSW_QUIRK_IRQ,
2245 }, {
2246 .name = "am4372-cpsw",
2247 .driver_data = 0,
2248 }, {
2249 .name = "dra7-cpsw",
2250 .driver_data = 0,
2251 }, {
2252 /* sentinel */
2253 }
2254 };
2255 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2256
2257 enum ti_cpsw_type {
2258 CPSW = 0,
2259 AM335X_CPSW,
2260 AM4372_CPSW,
2261 DRA7_CPSW,
2262 };
2263
2264 static const struct of_device_id cpsw_of_mtable[] = {
2265 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2266 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2267 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2268 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2269 { /* sentinel */ },
2270 };
2271 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2272
2273 static int cpsw_probe(struct platform_device *pdev)
2274 {
2275 struct cpsw_platform_data *data;
2276 struct net_device *ndev;
2277 struct cpsw_priv *priv;
2278 struct cpdma_params dma_params;
2279 struct cpsw_ale_params ale_params;
2280 void __iomem *ss_regs;
2281 struct resource *res, *ss_res;
2282 const struct of_device_id *of_id;
2283 struct gpio_descs *mode;
2284 u32 slave_offset, sliver_offset, slave_size;
2285 int ret = 0, i;
2286 int irq;
2287
2288 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2289 if (!ndev) {
2290 dev_err(&pdev->dev, "error allocating net_device\n");
2291 return -ENOMEM;
2292 }
2293
2294 platform_set_drvdata(pdev, ndev);
2295 priv = netdev_priv(ndev);
2296 priv->pdev = pdev;
2297 priv->ndev = ndev;
2298 priv->dev = &ndev->dev;
2299 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2300 priv->rx_packet_max = max(rx_packet_max, 128);
2301 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2302 if (!priv->cpts) {
2303 dev_err(&pdev->dev, "error allocating cpts\n");
2304 ret = -ENOMEM;
2305 goto clean_ndev_ret;
2306 }
2307
2308 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2309 if (IS_ERR(mode)) {
2310 ret = PTR_ERR(mode);
2311 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2312 goto clean_ndev_ret;
2313 }
2314
2315 /*
2316 * This may be required here for child devices.
2317 */
2318 pm_runtime_enable(&pdev->dev);
2319
2320 /* Select default pin state */
2321 pinctrl_pm_select_default_state(&pdev->dev);
2322
2323 if (cpsw_probe_dt(&priv->data, pdev)) {
2324 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2325 ret = -ENODEV;
2326 goto clean_runtime_disable_ret;
2327 }
2328 data = &priv->data;
2329
2330 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2331 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2332 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2333 } else {
2334 eth_random_addr(priv->mac_addr);
2335 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2336 }
2337
2338 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2339
2340 priv->slaves = devm_kzalloc(&pdev->dev,
2341 sizeof(struct cpsw_slave) * data->slaves,
2342 GFP_KERNEL);
2343 if (!priv->slaves) {
2344 ret = -ENOMEM;
2345 goto clean_runtime_disable_ret;
2346 }
2347 for (i = 0; i < data->slaves; i++)
2348 priv->slaves[i].slave_num = i;
2349
2350 priv->slaves[0].ndev = ndev;
2351 priv->emac_port = 0;
2352
2353 priv->clk = devm_clk_get(&pdev->dev, "fck");
2354 if (IS_ERR(priv->clk)) {
2355 dev_err(priv->dev, "fck is not found\n");
2356 ret = -ENODEV;
2357 goto clean_runtime_disable_ret;
2358 }
2359 priv->coal_intvl = 0;
2360 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2361
2362 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2363 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2364 if (IS_ERR(ss_regs)) {
2365 ret = PTR_ERR(ss_regs);
2366 goto clean_runtime_disable_ret;
2367 }
2368 priv->regs = ss_regs;
2369
2370 /* Need to enable clocks with runtime PM api to access module
2371 * registers
2372 */
2373 ret = pm_runtime_get_sync(&pdev->dev);
2374 if (ret < 0) {
2375 pm_runtime_put_noidle(&pdev->dev);
2376 goto clean_runtime_disable_ret;
2377 }
2378 priv->version = readl(&priv->regs->id_ver);
2379 pm_runtime_put_sync(&pdev->dev);
2380
2381 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2382 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2383 if (IS_ERR(priv->wr_regs)) {
2384 ret = PTR_ERR(priv->wr_regs);
2385 goto clean_runtime_disable_ret;
2386 }
2387
2388 memset(&dma_params, 0, sizeof(dma_params));
2389 memset(&ale_params, 0, sizeof(ale_params));
2390
2391 switch (priv->version) {
2392 case CPSW_VERSION_1:
2393 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2394 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2395 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
2396 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2397 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2398 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2399 slave_offset = CPSW1_SLAVE_OFFSET;
2400 slave_size = CPSW1_SLAVE_SIZE;
2401 sliver_offset = CPSW1_SLIVER_OFFSET;
2402 dma_params.desc_mem_phys = 0;
2403 break;
2404 case CPSW_VERSION_2:
2405 case CPSW_VERSION_3:
2406 case CPSW_VERSION_4:
2407 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2408 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2409 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
2410 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2411 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2412 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2413 slave_offset = CPSW2_SLAVE_OFFSET;
2414 slave_size = CPSW2_SLAVE_SIZE;
2415 sliver_offset = CPSW2_SLIVER_OFFSET;
2416 dma_params.desc_mem_phys =
2417 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2418 break;
2419 default:
2420 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2421 ret = -ENODEV;
2422 goto clean_runtime_disable_ret;
2423 }
2424 for (i = 0; i < priv->data.slaves; i++) {
2425 struct cpsw_slave *slave = &priv->slaves[i];
2426 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2427 slave_offset += slave_size;
2428 sliver_offset += SLIVER_SIZE;
2429 }
2430
2431 dma_params.dev = &pdev->dev;
2432 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2433 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2434 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2435 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2436 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
2437
2438 dma_params.num_chan = data->channels;
2439 dma_params.has_soft_reset = true;
2440 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2441 dma_params.desc_mem_size = data->bd_ram_size;
2442 dma_params.desc_align = 16;
2443 dma_params.has_ext_regs = true;
2444 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
2445
2446 priv->dma = cpdma_ctlr_create(&dma_params);
2447 if (!priv->dma) {
2448 dev_err(priv->dev, "error initializing dma\n");
2449 ret = -ENOMEM;
2450 goto clean_runtime_disable_ret;
2451 }
2452
2453 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2454 cpsw_tx_handler);
2455 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2456 cpsw_rx_handler);
2457
2458 if (WARN_ON(!priv->txch || !priv->rxch)) {
2459 dev_err(priv->dev, "error initializing dma channels\n");
2460 ret = -ENOMEM;
2461 goto clean_dma_ret;
2462 }
2463
2464 ale_params.dev = &ndev->dev;
2465 ale_params.ale_ageout = ale_ageout;
2466 ale_params.ale_entries = data->ale_entries;
2467 ale_params.ale_ports = data->slaves;
2468
2469 priv->ale = cpsw_ale_create(&ale_params);
2470 if (!priv->ale) {
2471 dev_err(priv->dev, "error initializing ale engine\n");
2472 ret = -ENODEV;
2473 goto clean_dma_ret;
2474 }
2475
2476 ndev->irq = platform_get_irq(pdev, 1);
2477 if (ndev->irq < 0) {
2478 dev_err(priv->dev, "error getting irq resource\n");
2479 ret = ndev->irq;
2480 goto clean_ale_ret;
2481 }
2482
2483 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2484 if (of_id) {
2485 pdev->id_entry = of_id->data;
2486 if (pdev->id_entry->driver_data)
2487 priv->quirk_irq = true;
2488 }
2489
2490 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2491 * MISC IRQs which are always kept disabled with this driver so
2492 * we will not request them.
2493 *
2494 * If anyone wants to implement support for those, make sure to
2495 * first request and append them to irqs_table array.
2496 */
2497
2498 /* RX IRQ */
2499 irq = platform_get_irq(pdev, 1);
2500 if (irq < 0) {
2501 ret = irq;
2502 goto clean_ale_ret;
2503 }
2504
2505 priv->irqs_table[0] = irq;
2506 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2507 0, dev_name(&pdev->dev), priv);
2508 if (ret < 0) {
2509 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2510 goto clean_ale_ret;
2511 }
2512
2513 /* TX IRQ */
2514 irq = platform_get_irq(pdev, 2);
2515 if (irq < 0) {
2516 ret = irq;
2517 goto clean_ale_ret;
2518 }
2519
2520 priv->irqs_table[1] = irq;
2521 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2522 0, dev_name(&pdev->dev), priv);
2523 if (ret < 0) {
2524 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2525 goto clean_ale_ret;
2526 }
2527 priv->num_irqs = 2;
2528
2529 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2530
2531 ndev->netdev_ops = &cpsw_netdev_ops;
2532 ndev->ethtool_ops = &cpsw_ethtool_ops;
2533 netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2534 netif_tx_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2535
2536 /* register the network device */
2537 SET_NETDEV_DEV(ndev, &pdev->dev);
2538 ret = register_netdev(ndev);
2539 if (ret) {
2540 dev_err(priv->dev, "error registering net device\n");
2541 ret = -ENODEV;
2542 goto clean_ale_ret;
2543 }
2544
2545 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2546 &ss_res->start, ndev->irq);
2547
2548 if (priv->data.dual_emac) {
2549 ret = cpsw_probe_dual_emac(pdev, priv);
2550 if (ret) {
2551 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2552 goto clean_ale_ret;
2553 }
2554 }
2555
2556 return 0;
2557
2558 clean_ale_ret:
2559 cpsw_ale_destroy(priv->ale);
2560 clean_dma_ret:
2561 cpdma_ctlr_destroy(priv->dma);
2562 clean_runtime_disable_ret:
2563 pm_runtime_disable(&pdev->dev);
2564 clean_ndev_ret:
2565 free_netdev(priv->ndev);
2566 return ret;
2567 }
2568
2569 static int cpsw_remove(struct platform_device *pdev)
2570 {
2571 struct net_device *ndev = platform_get_drvdata(pdev);
2572 struct cpsw_priv *priv = netdev_priv(ndev);
2573 int ret;
2574
2575 ret = pm_runtime_get_sync(&pdev->dev);
2576 if (ret < 0) {
2577 pm_runtime_put_noidle(&pdev->dev);
2578 return ret;
2579 }
2580
2581 if (priv->data.dual_emac)
2582 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2583 unregister_netdev(ndev);
2584
2585 cpsw_ale_destroy(priv->ale);
2586 cpdma_ctlr_destroy(priv->dma);
2587 of_platform_depopulate(&pdev->dev);
2588 pm_runtime_put_sync(&pdev->dev);
2589 pm_runtime_disable(&pdev->dev);
2590 if (priv->data.dual_emac)
2591 free_netdev(cpsw_get_slave_ndev(priv, 1));
2592 free_netdev(ndev);
2593 return 0;
2594 }
2595
2596 #ifdef CONFIG_PM_SLEEP
2597 static int cpsw_suspend(struct device *dev)
2598 {
2599 struct platform_device *pdev = to_platform_device(dev);
2600 struct net_device *ndev = platform_get_drvdata(pdev);
2601 struct cpsw_priv *priv = netdev_priv(ndev);
2602
2603 if (priv->data.dual_emac) {
2604 int i;
2605
2606 for (i = 0; i < priv->data.slaves; i++) {
2607 if (netif_running(priv->slaves[i].ndev))
2608 cpsw_ndo_stop(priv->slaves[i].ndev);
2609 }
2610 } else {
2611 if (netif_running(ndev))
2612 cpsw_ndo_stop(ndev);
2613 }
2614
2615 /* Select sleep pin state */
2616 pinctrl_pm_select_sleep_state(&pdev->dev);
2617
2618 return 0;
2619 }
2620
2621 static int cpsw_resume(struct device *dev)
2622 {
2623 struct platform_device *pdev = to_platform_device(dev);
2624 struct net_device *ndev = platform_get_drvdata(pdev);
2625 struct cpsw_priv *priv = netdev_priv(ndev);
2626
2627 /* Select default pin state */
2628 pinctrl_pm_select_default_state(&pdev->dev);
2629
2630 if (priv->data.dual_emac) {
2631 int i;
2632
2633 for (i = 0; i < priv->data.slaves; i++) {
2634 if (netif_running(priv->slaves[i].ndev))
2635 cpsw_ndo_open(priv->slaves[i].ndev);
2636 }
2637 } else {
2638 if (netif_running(ndev))
2639 cpsw_ndo_open(ndev);
2640 }
2641 return 0;
2642 }
2643 #endif
2644
2645 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2646
2647 static struct platform_driver cpsw_driver = {
2648 .driver = {
2649 .name = "cpsw",
2650 .pm = &cpsw_pm_ops,
2651 .of_match_table = cpsw_of_mtable,
2652 },
2653 .probe = cpsw_probe,
2654 .remove = cpsw_remove,
2655 };
2656
2657 module_platform_driver(cpsw_driver);
2658
2659 MODULE_LICENSE("GPL");
2660 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2661 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2662 MODULE_DESCRIPTION("TI CPSW Ethernet driver");
Linux kernel - Deliverables
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