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Merge tag 'staging-3.3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
[deliverable/linux.git] / drivers / net / ethernet / ti / davinci_emac.c
1 /*
2 * DaVinci Ethernet Medium Access Controller
3 *
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
5 *
6 * Copyright (C) 2009 Texas Instruments.
7 *
8 * ---------------------------------------------------------------------------
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
24 * History:
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
29 * PHY layer usage
30 */
31
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
38 #include <linux/in.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
41 #include <linux/mm.h>
42 #include <linux/interrupt.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/ethtool.h>
48 #include <linux/highmem.h>
49 #include <linux/proc_fs.h>
50 #include <linux/ctype.h>
51 #include <linux/spinlock.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/clk.h>
54 #include <linux/platform_device.h>
55 #include <linux/semaphore.h>
56 #include <linux/phy.h>
57 #include <linux/bitops.h>
58 #include <linux/io.h>
59 #include <linux/uaccess.h>
60 #include <linux/davinci_emac.h>
61
62 #include <asm/irq.h>
63 #include <asm/page.h>
64
65 #include "davinci_cpdma.h"
66
67 static int debug_level;
68 module_param(debug_level, int, 0);
69 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
70
71 /* Netif debug messages possible */
72 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
73 NETIF_MSG_PROBE | \
74 NETIF_MSG_LINK | \
75 NETIF_MSG_TIMER | \
76 NETIF_MSG_IFDOWN | \
77 NETIF_MSG_IFUP | \
78 NETIF_MSG_RX_ERR | \
79 NETIF_MSG_TX_ERR | \
80 NETIF_MSG_TX_QUEUED | \
81 NETIF_MSG_INTR | \
82 NETIF_MSG_TX_DONE | \
83 NETIF_MSG_RX_STATUS | \
84 NETIF_MSG_PKTDATA | \
85 NETIF_MSG_HW | \
86 NETIF_MSG_WOL)
87
88 /* version info */
89 #define EMAC_MAJOR_VERSION 6
90 #define EMAC_MINOR_VERSION 1
91 #define EMAC_MODULE_VERSION "6.1"
92 MODULE_VERSION(EMAC_MODULE_VERSION);
93 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
94
95 /* Configuration items */
96 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
97 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
98 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
99 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
100 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
101 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
102 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
103 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
104 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
105 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
106 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
107 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
108
109 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
110 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
111
112 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
113 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
114 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
115 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
116 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
117 #define EMAC_DEF_RX_NUM_DESC (128)
118 #define EMAC_DEF_TX_NUM_DESC (128)
119 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
120 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
121 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
122
123 /* Buffer descriptor parameters */
124 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
125 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
126
127 /* EMAC register related defines */
128 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
129 #define EMAC_NUM_MULTICAST_BITS (64)
130 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
131 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
132 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
133 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
134 #define EMAC_INT_MASK_CLEAR (0xFF)
135
136 /* RX MBP register bit positions */
137 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
138 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
139 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
140 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
141 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
142 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
143 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
144 #define EMAC_RXMBP_PROMCH_SHIFT (16)
145 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
146 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
147 #define EMAC_RXMBP_BROADCH_SHIFT (8)
148 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
149 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
150 #define EMAC_RXMBP_MULTICH_SHIFT (0)
151 #define EMAC_RXMBP_MULTICH_MASK (0x7)
152 #define EMAC_RXMBP_CHMASK (0x7)
153
154 /* EMAC register definitions/bit maps used */
155 # define EMAC_MBP_RXPROMISC (0x00200000)
156 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
157 # define EMAC_MBP_RXBCAST (0x00002000)
158 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
159 # define EMAC_MBP_RXMCAST (0x00000020)
160 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
161
162 /* EMAC mac_control register */
163 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
164 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
165 #define EMAC_MACCONTROL_GMIIEN BIT(5)
166 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
167 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
168 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
169
170 /* GIGABIT MODE related bits */
171 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
172 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
173
174 /* EMAC mac_status register */
175 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
176 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
177 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
178 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
179 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
180 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
181 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
182 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
183
184 /* EMAC RX register masks */
185 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
186 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
187
188 /* MAC_IN_VECTOR (0x180) register bit fields */
189 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
190 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
191 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
192 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
193
194 /** NOTE:: For DM646x the IN_VECTOR has changed */
195 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
196 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
197 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
198 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
199
200 /* CPPI bit positions */
201 #define EMAC_CPPI_SOP_BIT BIT(31)
202 #define EMAC_CPPI_EOP_BIT BIT(30)
203 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
204 #define EMAC_CPPI_EOQ_BIT BIT(28)
205 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
206 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
207 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
208 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
209 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
210
211 /* Max hardware defines */
212 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
213 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
214
215 /* EMAC Peripheral Device Register Memory Layout structure */
216 #define EMAC_MACINVECTOR 0x90
217
218 #define EMAC_DM646X_MACEOIVECTOR 0x94
219
220 #define EMAC_MACINTSTATRAW 0xB0
221 #define EMAC_MACINTSTATMASKED 0xB4
222 #define EMAC_MACINTMASKSET 0xB8
223 #define EMAC_MACINTMASKCLEAR 0xBC
224
225 #define EMAC_RXMBPENABLE 0x100
226 #define EMAC_RXUNICASTSET 0x104
227 #define EMAC_RXUNICASTCLEAR 0x108
228 #define EMAC_RXMAXLEN 0x10C
229 #define EMAC_RXBUFFEROFFSET 0x110
230 #define EMAC_RXFILTERLOWTHRESH 0x114
231
232 #define EMAC_MACCONTROL 0x160
233 #define EMAC_MACSTATUS 0x164
234 #define EMAC_EMCONTROL 0x168
235 #define EMAC_FIFOCONTROL 0x16C
236 #define EMAC_MACCONFIG 0x170
237 #define EMAC_SOFTRESET 0x174
238 #define EMAC_MACSRCADDRLO 0x1D0
239 #define EMAC_MACSRCADDRHI 0x1D4
240 #define EMAC_MACHASH1 0x1D8
241 #define EMAC_MACHASH2 0x1DC
242 #define EMAC_MACADDRLO 0x500
243 #define EMAC_MACADDRHI 0x504
244 #define EMAC_MACINDEX 0x508
245
246 /* EMAC statistics registers */
247 #define EMAC_RXGOODFRAMES 0x200
248 #define EMAC_RXBCASTFRAMES 0x204
249 #define EMAC_RXMCASTFRAMES 0x208
250 #define EMAC_RXPAUSEFRAMES 0x20C
251 #define EMAC_RXCRCERRORS 0x210
252 #define EMAC_RXALIGNCODEERRORS 0x214
253 #define EMAC_RXOVERSIZED 0x218
254 #define EMAC_RXJABBER 0x21C
255 #define EMAC_RXUNDERSIZED 0x220
256 #define EMAC_RXFRAGMENTS 0x224
257 #define EMAC_RXFILTERED 0x228
258 #define EMAC_RXQOSFILTERED 0x22C
259 #define EMAC_RXOCTETS 0x230
260 #define EMAC_TXGOODFRAMES 0x234
261 #define EMAC_TXBCASTFRAMES 0x238
262 #define EMAC_TXMCASTFRAMES 0x23C
263 #define EMAC_TXPAUSEFRAMES 0x240
264 #define EMAC_TXDEFERRED 0x244
265 #define EMAC_TXCOLLISION 0x248
266 #define EMAC_TXSINGLECOLL 0x24C
267 #define EMAC_TXMULTICOLL 0x250
268 #define EMAC_TXEXCESSIVECOLL 0x254
269 #define EMAC_TXLATECOLL 0x258
270 #define EMAC_TXUNDERRUN 0x25C
271 #define EMAC_TXCARRIERSENSE 0x260
272 #define EMAC_TXOCTETS 0x264
273 #define EMAC_NETOCTETS 0x280
274 #define EMAC_RXSOFOVERRUNS 0x284
275 #define EMAC_RXMOFOVERRUNS 0x288
276 #define EMAC_RXDMAOVERRUNS 0x28C
277
278 /* EMAC DM644x control registers */
279 #define EMAC_CTRL_EWCTL (0x4)
280 #define EMAC_CTRL_EWINTTCNT (0x8)
281
282 /* EMAC DM644x control module masks */
283 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
284 #define EMAC_DM644X_INTMIN_INTVL 0x1
285 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
286
287 /* EMAC DM646X control module registers */
288 #define EMAC_DM646X_CMINTCTRL 0x0C
289 #define EMAC_DM646X_CMRXINTEN 0x14
290 #define EMAC_DM646X_CMTXINTEN 0x18
291 #define EMAC_DM646X_CMRXINTMAX 0x70
292 #define EMAC_DM646X_CMTXINTMAX 0x74
293
294 /* EMAC DM646X control module masks */
295 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
296 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
297 #define EMAC_DM646X_CMINTMAX_CNT 63
298 #define EMAC_DM646X_CMINTMIN_CNT 2
299 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
300 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
301
302
303 /* EMAC EOI codes for C0 */
304 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
305 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
306
307 /* EMAC Stats Clear Mask */
308 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
309
310 /* emac_priv: EMAC private data structure
311 *
312 * EMAC adapter private data structure
313 */
314 struct emac_priv {
315 u32 msg_enable;
316 struct net_device *ndev;
317 struct platform_device *pdev;
318 struct napi_struct napi;
319 char mac_addr[6];
320 void __iomem *remap_addr;
321 u32 emac_base_phys;
322 void __iomem *emac_base;
323 void __iomem *ctrl_base;
324 struct cpdma_ctlr *dma;
325 struct cpdma_chan *txchan;
326 struct cpdma_chan *rxchan;
327 u32 link; /* 1=link on, 0=link off */
328 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
329 u32 duplex; /* Link duplex: 0=Half, 1=Full */
330 u32 rx_buf_size;
331 u32 isr_count;
332 u32 coal_intvl;
333 u32 bus_freq_mhz;
334 u8 rmii_en;
335 u8 version;
336 u32 mac_hash1;
337 u32 mac_hash2;
338 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
339 u32 rx_addr_type;
340 atomic_t cur_tx;
341 const char *phy_id;
342 struct phy_device *phydev;
343 spinlock_t lock;
344 /*platform specific members*/
345 void (*int_enable) (void);
346 void (*int_disable) (void);
347 };
348
349 /* clock frequency for EMAC */
350 static struct clk *emac_clk;
351 static unsigned long emac_bus_frequency;
352
353 /* EMAC TX Host Error description strings */
354 static char *emac_txhost_errcodes[16] = {
355 "No error", "SOP error", "Ownership bit not set in SOP buffer",
356 "Zero Next Buffer Descriptor Pointer Without EOP",
357 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
358 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
359 "Reserved", "Reserved", "Reserved", "Reserved"
360 };
361
362 /* EMAC RX Host Error description strings */
363 static char *emac_rxhost_errcodes[16] = {
364 "No error", "Reserved", "Ownership bit not set in input buffer",
365 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
366 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
367 "Reserved", "Reserved", "Reserved", "Reserved"
368 };
369
370 /* Helper macros */
371 #define emac_read(reg) ioread32(priv->emac_base + (reg))
372 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
373
374 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
375 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
376
377 /**
378 * emac_dump_regs: Dump important EMAC registers to debug terminal
379 * @priv: The DaVinci EMAC private adapter structure
380 *
381 * Executes ethtool set cmd & sets phy mode
382 *
383 */
384 static void emac_dump_regs(struct emac_priv *priv)
385 {
386 struct device *emac_dev = &priv->ndev->dev;
387
388 /* Print important registers in EMAC */
389 dev_info(emac_dev, "EMAC Basic registers\n");
390 if (priv->version == EMAC_VERSION_1) {
391 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
392 emac_ctrl_read(EMAC_CTRL_EWCTL),
393 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
394 }
395 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
396 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
397 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
398 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
399 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
400 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
401 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
402 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
403 dev_info(emac_dev, "EMAC Statistics\n");
404 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
405 emac_read(EMAC_RXGOODFRAMES));
406 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
407 emac_read(EMAC_RXBCASTFRAMES));
408 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
409 emac_read(EMAC_RXMCASTFRAMES));
410 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
411 emac_read(EMAC_RXPAUSEFRAMES));
412 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
413 emac_read(EMAC_RXCRCERRORS));
414 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
415 emac_read(EMAC_RXALIGNCODEERRORS));
416 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
417 emac_read(EMAC_RXOVERSIZED));
418 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
419 emac_read(EMAC_RXJABBER));
420 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
421 emac_read(EMAC_RXUNDERSIZED));
422 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
423 emac_read(EMAC_RXFRAGMENTS));
424 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
425 emac_read(EMAC_RXFILTERED));
426 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
427 emac_read(EMAC_RXQOSFILTERED));
428 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
429 emac_read(EMAC_RXOCTETS));
430 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
431 emac_read(EMAC_TXGOODFRAMES));
432 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
433 emac_read(EMAC_TXBCASTFRAMES));
434 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
435 emac_read(EMAC_TXMCASTFRAMES));
436 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
437 emac_read(EMAC_TXPAUSEFRAMES));
438 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
439 emac_read(EMAC_TXDEFERRED));
440 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
441 emac_read(EMAC_TXCOLLISION));
442 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
443 emac_read(EMAC_TXSINGLECOLL));
444 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
445 emac_read(EMAC_TXMULTICOLL));
446 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
447 emac_read(EMAC_TXEXCESSIVECOLL));
448 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
449 emac_read(EMAC_TXLATECOLL));
450 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
451 emac_read(EMAC_TXUNDERRUN));
452 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
453 emac_read(EMAC_TXCARRIERSENSE));
454 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
455 emac_read(EMAC_TXOCTETS));
456 dev_info(emac_dev, "EMAC: net_octets:%d\n",
457 emac_read(EMAC_NETOCTETS));
458 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
459 emac_read(EMAC_RXSOFOVERRUNS));
460 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
461 emac_read(EMAC_RXMOFOVERRUNS));
462 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
463 emac_read(EMAC_RXDMAOVERRUNS));
464
465 cpdma_ctlr_dump(priv->dma);
466 }
467
468 /**
469 * emac_get_drvinfo: Get EMAC driver information
470 * @ndev: The DaVinci EMAC network adapter
471 * @info: ethtool info structure containing name and version
472 *
473 * Returns EMAC driver information (name and version)
474 *
475 */
476 static void emac_get_drvinfo(struct net_device *ndev,
477 struct ethtool_drvinfo *info)
478 {
479 strcpy(info->driver, emac_version_string);
480 strcpy(info->version, EMAC_MODULE_VERSION);
481 }
482
483 /**
484 * emac_get_settings: Get EMAC settings
485 * @ndev: The DaVinci EMAC network adapter
486 * @ecmd: ethtool command
487 *
488 * Executes ethool get command
489 *
490 */
491 static int emac_get_settings(struct net_device *ndev,
492 struct ethtool_cmd *ecmd)
493 {
494 struct emac_priv *priv = netdev_priv(ndev);
495 if (priv->phydev)
496 return phy_ethtool_gset(priv->phydev, ecmd);
497 else
498 return -EOPNOTSUPP;
499
500 }
501
502 /**
503 * emac_set_settings: Set EMAC settings
504 * @ndev: The DaVinci EMAC network adapter
505 * @ecmd: ethtool command
506 *
507 * Executes ethool set command
508 *
509 */
510 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
511 {
512 struct emac_priv *priv = netdev_priv(ndev);
513 if (priv->phydev)
514 return phy_ethtool_sset(priv->phydev, ecmd);
515 else
516 return -EOPNOTSUPP;
517
518 }
519
520 /**
521 * emac_get_coalesce : Get interrupt coalesce settings for this device
522 * @ndev : The DaVinci EMAC network adapter
523 * @coal : ethtool coalesce settings structure
524 *
525 * Fetch the current interrupt coalesce settings
526 *
527 */
528 static int emac_get_coalesce(struct net_device *ndev,
529 struct ethtool_coalesce *coal)
530 {
531 struct emac_priv *priv = netdev_priv(ndev);
532
533 coal->rx_coalesce_usecs = priv->coal_intvl;
534 return 0;
535
536 }
537
538 /**
539 * emac_set_coalesce : Set interrupt coalesce settings for this device
540 * @ndev : The DaVinci EMAC network adapter
541 * @coal : ethtool coalesce settings structure
542 *
543 * Set interrupt coalesce parameters
544 *
545 */
546 static int emac_set_coalesce(struct net_device *ndev,
547 struct ethtool_coalesce *coal)
548 {
549 struct emac_priv *priv = netdev_priv(ndev);
550 u32 int_ctrl, num_interrupts = 0;
551 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
552
553 if (!coal->rx_coalesce_usecs)
554 return -EINVAL;
555
556 coal_intvl = coal->rx_coalesce_usecs;
557
558 switch (priv->version) {
559 case EMAC_VERSION_2:
560 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
561 prescale = priv->bus_freq_mhz * 4;
562
563 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
564 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
565
566 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
567 /*
568 * Interrupt pacer works with 4us Pulse, we can
569 * throttle further by dilating the 4us pulse.
570 */
571 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
572
573 if (addnl_dvdr > 1) {
574 prescale *= addnl_dvdr;
575 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
576 * addnl_dvdr))
577 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
578 * addnl_dvdr);
579 } else {
580 addnl_dvdr = 1;
581 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
582 }
583 }
584
585 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
586
587 int_ctrl |= EMAC_DM646X_INTPACEEN;
588 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
589 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
590 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
591
592 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
593 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
594
595 break;
596 default:
597 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
598 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
599 prescale = coal_intvl * priv->bus_freq_mhz;
600 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
601 prescale = EMAC_DM644X_EWINTCNT_MASK;
602 coal_intvl = prescale / priv->bus_freq_mhz;
603 }
604 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
605
606 break;
607 }
608
609 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
610 priv->coal_intvl = coal_intvl;
611
612 return 0;
613
614 }
615
616
617 /**
618 * ethtool_ops: DaVinci EMAC Ethtool structure
619 *
620 * Ethtool support for EMAC adapter
621 *
622 */
623 static const struct ethtool_ops ethtool_ops = {
624 .get_drvinfo = emac_get_drvinfo,
625 .get_settings = emac_get_settings,
626 .set_settings = emac_set_settings,
627 .get_link = ethtool_op_get_link,
628 .get_coalesce = emac_get_coalesce,
629 .set_coalesce = emac_set_coalesce,
630 };
631
632 /**
633 * emac_update_phystatus: Update Phy status
634 * @priv: The DaVinci EMAC private adapter structure
635 *
636 * Updates phy status and takes action for network queue if required
637 * based upon link status
638 *
639 */
640 static void emac_update_phystatus(struct emac_priv *priv)
641 {
642 u32 mac_control;
643 u32 new_duplex;
644 u32 cur_duplex;
645 struct net_device *ndev = priv->ndev;
646
647 mac_control = emac_read(EMAC_MACCONTROL);
648 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
649 DUPLEX_FULL : DUPLEX_HALF;
650 if (priv->phydev)
651 new_duplex = priv->phydev->duplex;
652 else
653 new_duplex = DUPLEX_FULL;
654
655 /* We get called only if link has changed (speed/duplex/status) */
656 if ((priv->link) && (new_duplex != cur_duplex)) {
657 priv->duplex = new_duplex;
658 if (DUPLEX_FULL == priv->duplex)
659 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
660 else
661 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
662 }
663
664 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
665 mac_control = emac_read(EMAC_MACCONTROL);
666 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
667 EMAC_DM646X_MACCONTORL_GIGFORCE);
668 } else {
669 /* Clear the GIG bit and GIGFORCE bit */
670 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
671 EMAC_DM646X_MACCONTORL_GIG);
672
673 if (priv->rmii_en && (priv->speed == SPEED_100))
674 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
675 else
676 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
677 }
678
679 /* Update mac_control if changed */
680 emac_write(EMAC_MACCONTROL, mac_control);
681
682 if (priv->link) {
683 /* link ON */
684 if (!netif_carrier_ok(ndev))
685 netif_carrier_on(ndev);
686 /* reactivate the transmit queue if it is stopped */
687 if (netif_running(ndev) && netif_queue_stopped(ndev))
688 netif_wake_queue(ndev);
689 } else {
690 /* link OFF */
691 if (netif_carrier_ok(ndev))
692 netif_carrier_off(ndev);
693 if (!netif_queue_stopped(ndev))
694 netif_stop_queue(ndev);
695 }
696 }
697
698 /**
699 * hash_get: Calculate hash value from mac address
700 * @addr: mac address to delete from hash table
701 *
702 * Calculates hash value from mac address
703 *
704 */
705 static u32 hash_get(u8 *addr)
706 {
707 u32 hash;
708 u8 tmpval;
709 int cnt;
710 hash = 0;
711
712 for (cnt = 0; cnt < 2; cnt++) {
713 tmpval = *addr++;
714 hash ^= (tmpval >> 2) ^ (tmpval << 4);
715 tmpval = *addr++;
716 hash ^= (tmpval >> 4) ^ (tmpval << 2);
717 tmpval = *addr++;
718 hash ^= (tmpval >> 6) ^ (tmpval);
719 }
720
721 return hash & 0x3F;
722 }
723
724 /**
725 * hash_add: Hash function to add mac addr from hash table
726 * @priv: The DaVinci EMAC private adapter structure
727 * mac_addr: mac address to delete from hash table
728 *
729 * Adds mac address to the internal hash table
730 *
731 */
732 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
733 {
734 struct device *emac_dev = &priv->ndev->dev;
735 u32 rc = 0;
736 u32 hash_bit;
737 u32 hash_value = hash_get(mac_addr);
738
739 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
740 if (netif_msg_drv(priv)) {
741 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
742 "Hash %08x, should not be greater than %08x",
743 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
744 }
745 return -1;
746 }
747
748 /* set the hash bit only if not previously set */
749 if (priv->multicast_hash_cnt[hash_value] == 0) {
750 rc = 1; /* hash value changed */
751 if (hash_value < 32) {
752 hash_bit = BIT(hash_value);
753 priv->mac_hash1 |= hash_bit;
754 } else {
755 hash_bit = BIT((hash_value - 32));
756 priv->mac_hash2 |= hash_bit;
757 }
758 }
759
760 /* incr counter for num of mcast addr's mapped to "this" hash bit */
761 ++priv->multicast_hash_cnt[hash_value];
762
763 return rc;
764 }
765
766 /**
767 * hash_del: Hash function to delete mac addr from hash table
768 * @priv: The DaVinci EMAC private adapter structure
769 * mac_addr: mac address to delete from hash table
770 *
771 * Removes mac address from the internal hash table
772 *
773 */
774 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
775 {
776 u32 hash_value;
777 u32 hash_bit;
778
779 hash_value = hash_get(mac_addr);
780 if (priv->multicast_hash_cnt[hash_value] > 0) {
781 /* dec cntr for num of mcast addr's mapped to this hash bit */
782 --priv->multicast_hash_cnt[hash_value];
783 }
784
785 /* if counter still > 0, at least one multicast address refers
786 * to this hash bit. so return 0 */
787 if (priv->multicast_hash_cnt[hash_value] > 0)
788 return 0;
789
790 if (hash_value < 32) {
791 hash_bit = BIT(hash_value);
792 priv->mac_hash1 &= ~hash_bit;
793 } else {
794 hash_bit = BIT((hash_value - 32));
795 priv->mac_hash2 &= ~hash_bit;
796 }
797
798 /* return 1 to indicate change in mac_hash registers reqd */
799 return 1;
800 }
801
802 /* EMAC multicast operation */
803 #define EMAC_MULTICAST_ADD 0
804 #define EMAC_MULTICAST_DEL 1
805 #define EMAC_ALL_MULTI_SET 2
806 #define EMAC_ALL_MULTI_CLR 3
807
808 /**
809 * emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
810 * @priv: The DaVinci EMAC private adapter structure
811 * @action: multicast operation to perform
812 * mac_addr: mac address to set
813 *
814 * Set multicast addresses in EMAC adapter - internal function
815 *
816 */
817 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
818 {
819 struct device *emac_dev = &priv->ndev->dev;
820 int update = -1;
821
822 switch (action) {
823 case EMAC_MULTICAST_ADD:
824 update = hash_add(priv, mac_addr);
825 break;
826 case EMAC_MULTICAST_DEL:
827 update = hash_del(priv, mac_addr);
828 break;
829 case EMAC_ALL_MULTI_SET:
830 update = 1;
831 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
832 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
833 break;
834 case EMAC_ALL_MULTI_CLR:
835 update = 1;
836 priv->mac_hash1 = 0;
837 priv->mac_hash2 = 0;
838 memset(&(priv->multicast_hash_cnt[0]), 0,
839 sizeof(priv->multicast_hash_cnt[0]) *
840 EMAC_NUM_MULTICAST_BITS);
841 break;
842 default:
843 if (netif_msg_drv(priv))
844 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
845 ": bad operation %d", action);
846 break;
847 }
848
849 /* write to the hardware only if the register status chances */
850 if (update > 0) {
851 emac_write(EMAC_MACHASH1, priv->mac_hash1);
852 emac_write(EMAC_MACHASH2, priv->mac_hash2);
853 }
854 }
855
856 /**
857 * emac_dev_mcast_set: Set multicast address in the EMAC adapter
858 * @ndev: The DaVinci EMAC network adapter
859 *
860 * Set multicast addresses in EMAC adapter
861 *
862 */
863 static void emac_dev_mcast_set(struct net_device *ndev)
864 {
865 u32 mbp_enable;
866 struct emac_priv *priv = netdev_priv(ndev);
867
868 mbp_enable = emac_read(EMAC_RXMBPENABLE);
869 if (ndev->flags & IFF_PROMISC) {
870 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
871 mbp_enable |= (EMAC_MBP_RXPROMISC);
872 } else {
873 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
874 if ((ndev->flags & IFF_ALLMULTI) ||
875 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
876 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
877 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
878 }
879 if (!netdev_mc_empty(ndev)) {
880 struct netdev_hw_addr *ha;
881
882 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
883 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
884 /* program multicast address list into EMAC hardware */
885 netdev_for_each_mc_addr(ha, ndev) {
886 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
887 (u8 *) ha->addr);
888 }
889 } else {
890 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
891 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
892 }
893 }
894 /* Set mbp config register */
895 emac_write(EMAC_RXMBPENABLE, mbp_enable);
896 }
897
898 /*************************************************************************
899 * EMAC Hardware manipulation
900 *************************************************************************/
901
902 /**
903 * emac_int_disable: Disable EMAC module interrupt (from adapter)
904 * @priv: The DaVinci EMAC private adapter structure
905 *
906 * Disable EMAC interrupt on the adapter
907 *
908 */
909 static void emac_int_disable(struct emac_priv *priv)
910 {
911 if (priv->version == EMAC_VERSION_2) {
912 unsigned long flags;
913
914 local_irq_save(flags);
915
916 /* Program C0_Int_En to zero to turn off
917 * interrupts to the CPU */
918 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
919 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
920 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
921 if (priv->int_disable)
922 priv->int_disable();
923
924 local_irq_restore(flags);
925
926 } else {
927 /* Set DM644x control registers for interrupt control */
928 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
929 }
930 }
931
932 /**
933 * emac_int_enable: Enable EMAC module interrupt (from adapter)
934 * @priv: The DaVinci EMAC private adapter structure
935 *
936 * Enable EMAC interrupt on the adapter
937 *
938 */
939 static void emac_int_enable(struct emac_priv *priv)
940 {
941 if (priv->version == EMAC_VERSION_2) {
942 if (priv->int_enable)
943 priv->int_enable();
944
945 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
946 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
947
948 /* In addition to turning on interrupt Enable, we need
949 * ack by writing appropriate values to the EOI
950 * register */
951
952 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
953
954 /* ack rxen only then a new pulse will be generated */
955 emac_write(EMAC_DM646X_MACEOIVECTOR,
956 EMAC_DM646X_MAC_EOI_C0_RXEN);
957
958 /* ack txen- only then a new pulse will be generated */
959 emac_write(EMAC_DM646X_MACEOIVECTOR,
960 EMAC_DM646X_MAC_EOI_C0_TXEN);
961
962 } else {
963 /* Set DM644x control registers for interrupt control */
964 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
965 }
966 }
967
968 /**
969 * emac_irq: EMAC interrupt handler
970 * @irq: interrupt number
971 * @dev_id: EMAC network adapter data structure ptr
972 *
973 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
974 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
975 *
976 * Returns interrupt handled condition
977 */
978 static irqreturn_t emac_irq(int irq, void *dev_id)
979 {
980 struct net_device *ndev = (struct net_device *)dev_id;
981 struct emac_priv *priv = netdev_priv(ndev);
982
983 ++priv->isr_count;
984 if (likely(netif_running(priv->ndev))) {
985 emac_int_disable(priv);
986 napi_schedule(&priv->napi);
987 } else {
988 /* we are closing down, so dont process anything */
989 }
990 return IRQ_HANDLED;
991 }
992
993 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
994 {
995 struct sk_buff *skb = dev_alloc_skb(priv->rx_buf_size);
996 if (WARN_ON(!skb))
997 return NULL;
998 skb->dev = priv->ndev;
999 skb_reserve(skb, NET_IP_ALIGN);
1000 return skb;
1001 }
1002
1003 static void emac_rx_handler(void *token, int len, int status)
1004 {
1005 struct sk_buff *skb = token;
1006 struct net_device *ndev = skb->dev;
1007 struct emac_priv *priv = netdev_priv(ndev);
1008 struct device *emac_dev = &ndev->dev;
1009 int ret;
1010
1011 /* free and bail if we are shutting down */
1012 if (unlikely(!netif_running(ndev))) {
1013 dev_kfree_skb_any(skb);
1014 return;
1015 }
1016
1017 /* recycle on receive error */
1018 if (status < 0) {
1019 ndev->stats.rx_errors++;
1020 goto recycle;
1021 }
1022
1023 /* feed received packet up the stack */
1024 skb_put(skb, len);
1025 skb->protocol = eth_type_trans(skb, ndev);
1026 netif_receive_skb(skb);
1027 ndev->stats.rx_bytes += len;
1028 ndev->stats.rx_packets++;
1029
1030 /* alloc a new packet for receive */
1031 skb = emac_rx_alloc(priv);
1032 if (!skb) {
1033 if (netif_msg_rx_err(priv) && net_ratelimit())
1034 dev_err(emac_dev, "failed rx buffer alloc\n");
1035 return;
1036 }
1037
1038 recycle:
1039 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1040 skb_tailroom(skb), GFP_KERNEL);
1041
1042 WARN_ON(ret == -ENOMEM);
1043 if (unlikely(ret < 0))
1044 dev_kfree_skb_any(skb);
1045 }
1046
1047 static void emac_tx_handler(void *token, int len, int status)
1048 {
1049 struct sk_buff *skb = token;
1050 struct net_device *ndev = skb->dev;
1051 struct emac_priv *priv = netdev_priv(ndev);
1052
1053 atomic_dec(&priv->cur_tx);
1054
1055 if (unlikely(netif_queue_stopped(ndev)))
1056 netif_start_queue(ndev);
1057 ndev->stats.tx_packets++;
1058 ndev->stats.tx_bytes += len;
1059 dev_kfree_skb_any(skb);
1060 }
1061
1062 /**
1063 * emac_dev_xmit: EMAC Transmit function
1064 * @skb: SKB pointer
1065 * @ndev: The DaVinci EMAC network adapter
1066 *
1067 * Called by the system to transmit a packet - we queue the packet in
1068 * EMAC hardware transmit queue
1069 *
1070 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1071 */
1072 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1073 {
1074 struct device *emac_dev = &ndev->dev;
1075 int ret_code;
1076 struct emac_priv *priv = netdev_priv(ndev);
1077
1078 /* If no link, return */
1079 if (unlikely(!priv->link)) {
1080 if (netif_msg_tx_err(priv) && net_ratelimit())
1081 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1082 goto fail_tx;
1083 }
1084
1085 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
1086 if (unlikely(ret_code < 0)) {
1087 if (netif_msg_tx_err(priv) && net_ratelimit())
1088 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
1089 goto fail_tx;
1090 }
1091
1092 skb_tx_timestamp(skb);
1093
1094 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
1095 GFP_KERNEL);
1096 if (unlikely(ret_code != 0)) {
1097 if (netif_msg_tx_err(priv) && net_ratelimit())
1098 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
1099 goto fail_tx;
1100 }
1101
1102 if (atomic_inc_return(&priv->cur_tx) >= EMAC_DEF_TX_NUM_DESC)
1103 netif_stop_queue(ndev);
1104
1105 return NETDEV_TX_OK;
1106
1107 fail_tx:
1108 ndev->stats.tx_dropped++;
1109 netif_stop_queue(ndev);
1110 return NETDEV_TX_BUSY;
1111 }
1112
1113 /**
1114 * emac_dev_tx_timeout: EMAC Transmit timeout function
1115 * @ndev: The DaVinci EMAC network adapter
1116 *
1117 * Called when system detects that a skb timeout period has expired
1118 * potentially due to a fault in the adapter in not being able to send
1119 * it out on the wire. We teardown the TX channel assuming a hardware
1120 * error and re-initialize the TX channel for hardware operation
1121 *
1122 */
1123 static void emac_dev_tx_timeout(struct net_device *ndev)
1124 {
1125 struct emac_priv *priv = netdev_priv(ndev);
1126 struct device *emac_dev = &ndev->dev;
1127
1128 if (netif_msg_tx_err(priv))
1129 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1130
1131 emac_dump_regs(priv);
1132
1133 ndev->stats.tx_errors++;
1134 emac_int_disable(priv);
1135 cpdma_chan_stop(priv->txchan);
1136 cpdma_chan_start(priv->txchan);
1137 emac_int_enable(priv);
1138 }
1139
1140 /**
1141 * emac_set_type0addr: Set EMAC Type0 mac address
1142 * @priv: The DaVinci EMAC private adapter structure
1143 * @ch: RX channel number
1144 * @mac_addr: MAC address to set in device
1145 *
1146 * Called internally to set Type0 mac address of the adapter (Device)
1147 *
1148 * Returns success (0) or appropriate error code (none as of now)
1149 */
1150 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1151 {
1152 u32 val;
1153 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1154 emac_write(EMAC_MACSRCADDRLO, val);
1155
1156 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1157 (mac_addr[1] << 8) | (mac_addr[0]));
1158 emac_write(EMAC_MACSRCADDRHI, val);
1159 val = emac_read(EMAC_RXUNICASTSET);
1160 val |= BIT(ch);
1161 emac_write(EMAC_RXUNICASTSET, val);
1162 val = emac_read(EMAC_RXUNICASTCLEAR);
1163 val &= ~BIT(ch);
1164 emac_write(EMAC_RXUNICASTCLEAR, val);
1165 }
1166
1167 /**
1168 * emac_set_type1addr: Set EMAC Type1 mac address
1169 * @priv: The DaVinci EMAC private adapter structure
1170 * @ch: RX channel number
1171 * @mac_addr: MAC address to set in device
1172 *
1173 * Called internally to set Type1 mac address of the adapter (Device)
1174 *
1175 * Returns success (0) or appropriate error code (none as of now)
1176 */
1177 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1178 {
1179 u32 val;
1180 emac_write(EMAC_MACINDEX, ch);
1181 val = ((mac_addr[5] << 8) | mac_addr[4]);
1182 emac_write(EMAC_MACADDRLO, val);
1183 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1184 (mac_addr[1] << 8) | (mac_addr[0]));
1185 emac_write(EMAC_MACADDRHI, val);
1186 emac_set_type0addr(priv, ch, mac_addr);
1187 }
1188
1189 /**
1190 * emac_set_type2addr: Set EMAC Type2 mac address
1191 * @priv: The DaVinci EMAC private adapter structure
1192 * @ch: RX channel number
1193 * @mac_addr: MAC address to set in device
1194 * @index: index into RX address entries
1195 * @match: match parameter for RX address matching logic
1196 *
1197 * Called internally to set Type2 mac address of the adapter (Device)
1198 *
1199 * Returns success (0) or appropriate error code (none as of now)
1200 */
1201 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1202 char *mac_addr, int index, int match)
1203 {
1204 u32 val;
1205 emac_write(EMAC_MACINDEX, index);
1206 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1207 (mac_addr[1] << 8) | (mac_addr[0]));
1208 emac_write(EMAC_MACADDRHI, val);
1209 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1210 (match << 19) | BIT(20));
1211 emac_write(EMAC_MACADDRLO, val);
1212 emac_set_type0addr(priv, ch, mac_addr);
1213 }
1214
1215 /**
1216 * emac_setmac: Set mac address in the adapter (internal function)
1217 * @priv: The DaVinci EMAC private adapter structure
1218 * @ch: RX channel number
1219 * @mac_addr: MAC address to set in device
1220 *
1221 * Called internally to set the mac address of the adapter (Device)
1222 *
1223 * Returns success (0) or appropriate error code (none as of now)
1224 */
1225 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1226 {
1227 struct device *emac_dev = &priv->ndev->dev;
1228
1229 if (priv->rx_addr_type == 0) {
1230 emac_set_type0addr(priv, ch, mac_addr);
1231 } else if (priv->rx_addr_type == 1) {
1232 u32 cnt;
1233 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1234 emac_set_type1addr(priv, ch, mac_addr);
1235 } else if (priv->rx_addr_type == 2) {
1236 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1237 emac_set_type0addr(priv, ch, mac_addr);
1238 } else {
1239 if (netif_msg_drv(priv))
1240 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1241 }
1242 }
1243
1244 /**
1245 * emac_dev_setmac_addr: Set mac address in the adapter
1246 * @ndev: The DaVinci EMAC network adapter
1247 * @addr: MAC address to set in device
1248 *
1249 * Called by the system to set the mac address of the adapter (Device)
1250 *
1251 * Returns success (0) or appropriate error code (none as of now)
1252 */
1253 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1254 {
1255 struct emac_priv *priv = netdev_priv(ndev);
1256 struct device *emac_dev = &priv->ndev->dev;
1257 struct sockaddr *sa = addr;
1258
1259 if (!is_valid_ether_addr(sa->sa_data))
1260 return -EINVAL;
1261
1262 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1263 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1264 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1265
1266 /* MAC address is configured only after the interface is enabled. */
1267 if (netif_running(ndev)) {
1268 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1269 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1270 }
1271
1272 if (netif_msg_drv(priv))
1273 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1274 priv->mac_addr);
1275
1276 return 0;
1277 }
1278
1279 /**
1280 * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
1281 * @priv: The DaVinci EMAC private adapter structure
1282 *
1283 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1284 * for packet reception and enables device interrupts and then NAPI
1285 *
1286 * Returns success (0) or appropriate error code (none right now)
1287 */
1288 static int emac_hw_enable(struct emac_priv *priv)
1289 {
1290 u32 val, mbp_enable, mac_control;
1291
1292 /* Soft reset */
1293 emac_write(EMAC_SOFTRESET, 1);
1294 while (emac_read(EMAC_SOFTRESET))
1295 cpu_relax();
1296
1297 /* Disable interrupt & Set pacing for more interrupts initially */
1298 emac_int_disable(priv);
1299
1300 /* Full duplex enable bit set when auto negotiation happens */
1301 mac_control =
1302 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1303 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1304 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1305 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1306 emac_write(EMAC_MACCONTROL, mac_control);
1307
1308 mbp_enable =
1309 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1310 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1311 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1312 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1313 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1314 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1315 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1316 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1317 EMAC_RXMBP_PROMCH_SHIFT) |
1318 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1319 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1320 EMAC_RXMBP_BROADCH_SHIFT) |
1321 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1322 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1323 EMAC_RXMBP_MULTICH_SHIFT));
1324 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1325 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1326 EMAC_RX_MAX_LEN_MASK));
1327 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1328 EMAC_RX_BUFFER_OFFSET_MASK));
1329 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1330 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1331 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1332
1333 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1334
1335 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1336
1337 /* Enable MII */
1338 val = emac_read(EMAC_MACCONTROL);
1339 val |= (EMAC_MACCONTROL_GMIIEN);
1340 emac_write(EMAC_MACCONTROL, val);
1341
1342 /* Enable NAPI and interrupts */
1343 napi_enable(&priv->napi);
1344 emac_int_enable(priv);
1345 return 0;
1346
1347 }
1348
1349 /**
1350 * emac_poll: EMAC NAPI Poll function
1351 * @ndev: The DaVinci EMAC network adapter
1352 * @budget: Number of receive packets to process (as told by NAPI layer)
1353 *
1354 * NAPI Poll function implemented to process packets as per budget. We check
1355 * the type of interrupt on the device and accordingly call the TX or RX
1356 * packet processing functions. We follow the budget for RX processing and
1357 * also put a cap on number of TX pkts processed through config param. The
1358 * NAPI schedule function is called if more packets pending.
1359 *
1360 * Returns number of packets received (in most cases; else TX pkts - rarely)
1361 */
1362 static int emac_poll(struct napi_struct *napi, int budget)
1363 {
1364 unsigned int mask;
1365 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1366 struct net_device *ndev = priv->ndev;
1367 struct device *emac_dev = &ndev->dev;
1368 u32 status = 0;
1369 u32 num_tx_pkts = 0, num_rx_pkts = 0;
1370
1371 /* Check interrupt vectors and call packet processing */
1372 status = emac_read(EMAC_MACINVECTOR);
1373
1374 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1375
1376 if (priv->version == EMAC_VERSION_2)
1377 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1378
1379 if (status & mask) {
1380 num_tx_pkts = cpdma_chan_process(priv->txchan,
1381 EMAC_DEF_TX_MAX_SERVICE);
1382 } /* TX processing */
1383
1384 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1385
1386 if (priv->version == EMAC_VERSION_2)
1387 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1388
1389 if (status & mask) {
1390 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1391 } /* RX processing */
1392
1393 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1394 if (priv->version == EMAC_VERSION_2)
1395 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1396
1397 if (unlikely(status & mask)) {
1398 u32 ch, cause;
1399 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1400 netif_stop_queue(ndev);
1401 napi_disable(&priv->napi);
1402
1403 status = emac_read(EMAC_MACSTATUS);
1404 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1405 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1406 if (cause) {
1407 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1408 EMAC_MACSTATUS_TXERRCH_SHIFT);
1409 if (net_ratelimit()) {
1410 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1411 &emac_txhost_errcodes[cause][0], ch);
1412 }
1413 }
1414 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1415 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1416 if (cause) {
1417 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1418 EMAC_MACSTATUS_RXERRCH_SHIFT);
1419 if (netif_msg_hw(priv) && net_ratelimit())
1420 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1421 &emac_rxhost_errcodes[cause][0], ch);
1422 }
1423 } else if (num_rx_pkts < budget) {
1424 napi_complete(napi);
1425 emac_int_enable(priv);
1426 }
1427
1428 return num_rx_pkts;
1429 }
1430
1431 #ifdef CONFIG_NET_POLL_CONTROLLER
1432 /**
1433 * emac_poll_controller: EMAC Poll controller function
1434 * @ndev: The DaVinci EMAC network adapter
1435 *
1436 * Polled functionality used by netconsole and others in non interrupt mode
1437 *
1438 */
1439 void emac_poll_controller(struct net_device *ndev)
1440 {
1441 struct emac_priv *priv = netdev_priv(ndev);
1442
1443 emac_int_disable(priv);
1444 emac_irq(ndev->irq, ndev);
1445 emac_int_enable(priv);
1446 }
1447 #endif
1448
1449 static void emac_adjust_link(struct net_device *ndev)
1450 {
1451 struct emac_priv *priv = netdev_priv(ndev);
1452 struct phy_device *phydev = priv->phydev;
1453 unsigned long flags;
1454 int new_state = 0;
1455
1456 spin_lock_irqsave(&priv->lock, flags);
1457
1458 if (phydev->link) {
1459 /* check the mode of operation - full/half duplex */
1460 if (phydev->duplex != priv->duplex) {
1461 new_state = 1;
1462 priv->duplex = phydev->duplex;
1463 }
1464 if (phydev->speed != priv->speed) {
1465 new_state = 1;
1466 priv->speed = phydev->speed;
1467 }
1468 if (!priv->link) {
1469 new_state = 1;
1470 priv->link = 1;
1471 }
1472
1473 } else if (priv->link) {
1474 new_state = 1;
1475 priv->link = 0;
1476 priv->speed = 0;
1477 priv->duplex = ~0;
1478 }
1479 if (new_state) {
1480 emac_update_phystatus(priv);
1481 phy_print_status(priv->phydev);
1482 }
1483
1484 spin_unlock_irqrestore(&priv->lock, flags);
1485 }
1486
1487 /*************************************************************************
1488 * Linux Driver Model
1489 *************************************************************************/
1490
1491 /**
1492 * emac_devioctl: EMAC adapter ioctl
1493 * @ndev: The DaVinci EMAC network adapter
1494 * @ifrq: request parameter
1495 * @cmd: command parameter
1496 *
1497 * EMAC driver ioctl function
1498 *
1499 * Returns success(0) or appropriate error code
1500 */
1501 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1502 {
1503 struct emac_priv *priv = netdev_priv(ndev);
1504
1505 if (!(netif_running(ndev)))
1506 return -EINVAL;
1507
1508 /* TODO: Add phy read and write and private statistics get feature */
1509
1510 return phy_mii_ioctl(priv->phydev, ifrq, cmd);
1511 }
1512
1513 static int match_first_device(struct device *dev, void *data)
1514 {
1515 return 1;
1516 }
1517
1518 /**
1519 * emac_dev_open: EMAC device open
1520 * @ndev: The DaVinci EMAC network adapter
1521 *
1522 * Called when system wants to start the interface. We init TX/RX channels
1523 * and enable the hardware for packet reception/transmission and start the
1524 * network queue.
1525 *
1526 * Returns 0 for a successful open, or appropriate error code
1527 */
1528 static int emac_dev_open(struct net_device *ndev)
1529 {
1530 struct device *emac_dev = &ndev->dev;
1531 u32 cnt;
1532 struct resource *res;
1533 int q, m, ret;
1534 int i = 0;
1535 int k = 0;
1536 struct emac_priv *priv = netdev_priv(ndev);
1537
1538 netif_carrier_off(ndev);
1539 for (cnt = 0; cnt < ETH_ALEN; cnt++)
1540 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1541
1542 /* Configuration items */
1543 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1544
1545 priv->mac_hash1 = 0;
1546 priv->mac_hash2 = 0;
1547 emac_write(EMAC_MACHASH1, 0);
1548 emac_write(EMAC_MACHASH2, 0);
1549
1550 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1551 struct sk_buff *skb = emac_rx_alloc(priv);
1552
1553 if (!skb)
1554 break;
1555
1556 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1557 skb_tailroom(skb), GFP_KERNEL);
1558 if (WARN_ON(ret < 0))
1559 break;
1560 }
1561
1562 /* Request IRQ */
1563
1564 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1565 for (i = res->start; i <= res->end; i++) {
1566 if (request_irq(i, emac_irq, IRQF_DISABLED,
1567 ndev->name, ndev))
1568 goto rollback;
1569 }
1570 k++;
1571 }
1572
1573 /* Start/Enable EMAC hardware */
1574 emac_hw_enable(priv);
1575
1576 /* Enable Interrupt pacing if configured */
1577 if (priv->coal_intvl != 0) {
1578 struct ethtool_coalesce coal;
1579
1580 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1581 emac_set_coalesce(ndev, &coal);
1582 }
1583
1584 cpdma_ctlr_start(priv->dma);
1585
1586 priv->phydev = NULL;
1587 /* use the first phy on the bus if pdata did not give us a phy id */
1588 if (!priv->phy_id) {
1589 struct device *phy;
1590
1591 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1592 match_first_device);
1593 if (phy)
1594 priv->phy_id = dev_name(phy);
1595 }
1596
1597 if (priv->phy_id && *priv->phy_id) {
1598 priv->phydev = phy_connect(ndev, priv->phy_id,
1599 &emac_adjust_link, 0,
1600 PHY_INTERFACE_MODE_MII);
1601
1602 if (IS_ERR(priv->phydev)) {
1603 dev_err(emac_dev, "could not connect to phy %s\n",
1604 priv->phy_id);
1605 ret = PTR_ERR(priv->phydev);
1606 priv->phydev = NULL;
1607 return ret;
1608 }
1609
1610 priv->link = 0;
1611 priv->speed = 0;
1612 priv->duplex = ~0;
1613
1614 dev_info(emac_dev, "attached PHY driver [%s] "
1615 "(mii_bus:phy_addr=%s, id=%x)\n",
1616 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
1617 priv->phydev->phy_id);
1618 } else {
1619 /* No PHY , fix the link, speed and duplex settings */
1620 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1621 priv->link = 1;
1622 priv->speed = SPEED_100;
1623 priv->duplex = DUPLEX_FULL;
1624 emac_update_phystatus(priv);
1625 }
1626
1627 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
1628 emac_dump_regs(priv);
1629
1630 if (netif_msg_drv(priv))
1631 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1632
1633 if (priv->phydev)
1634 phy_start(priv->phydev);
1635
1636 return 0;
1637
1638 rollback:
1639
1640 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
1641
1642 for (q = k; k >= 0; k--) {
1643 for (m = i; m >= res->start; m--)
1644 free_irq(m, ndev);
1645 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
1646 m = res->end;
1647 }
1648 return -EBUSY;
1649 }
1650
1651 /**
1652 * emac_dev_stop: EMAC device stop
1653 * @ndev: The DaVinci EMAC network adapter
1654 *
1655 * Called when system wants to stop or down the interface. We stop the network
1656 * queue, disable interrupts and cleanup TX/RX channels.
1657 *
1658 * We return the statistics in net_device_stats structure pulled from emac
1659 */
1660 static int emac_dev_stop(struct net_device *ndev)
1661 {
1662 struct resource *res;
1663 int i = 0;
1664 int irq_num;
1665 struct emac_priv *priv = netdev_priv(ndev);
1666 struct device *emac_dev = &ndev->dev;
1667
1668 /* inform the upper layers. */
1669 netif_stop_queue(ndev);
1670 napi_disable(&priv->napi);
1671
1672 netif_carrier_off(ndev);
1673 emac_int_disable(priv);
1674 cpdma_ctlr_stop(priv->dma);
1675 emac_write(EMAC_SOFTRESET, 1);
1676
1677 if (priv->phydev)
1678 phy_disconnect(priv->phydev);
1679
1680 /* Free IRQ */
1681 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1682 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1683 free_irq(irq_num, priv->ndev);
1684 i++;
1685 }
1686
1687 if (netif_msg_drv(priv))
1688 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1689
1690 return 0;
1691 }
1692
1693 /**
1694 * emac_dev_getnetstats: EMAC get statistics function
1695 * @ndev: The DaVinci EMAC network adapter
1696 *
1697 * Called when system wants to get statistics from the device.
1698 *
1699 * We return the statistics in net_device_stats structure pulled from emac
1700 */
1701 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1702 {
1703 struct emac_priv *priv = netdev_priv(ndev);
1704 u32 mac_control;
1705 u32 stats_clear_mask;
1706
1707 /* update emac hardware stats and reset the registers*/
1708
1709 mac_control = emac_read(EMAC_MACCONTROL);
1710
1711 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1712 stats_clear_mask = EMAC_STATS_CLR_MASK;
1713 else
1714 stats_clear_mask = 0;
1715
1716 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1717 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1718
1719 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1720 emac_read(EMAC_TXSINGLECOLL) +
1721 emac_read(EMAC_TXMULTICOLL));
1722 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1723 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1724 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1725
1726 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1727 emac_read(EMAC_RXJABBER) +
1728 emac_read(EMAC_RXUNDERSIZED));
1729 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1730 emac_write(EMAC_RXJABBER, stats_clear_mask);
1731 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1732
1733 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1734 emac_read(EMAC_RXMOFOVERRUNS));
1735 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1736 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1737
1738 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1739 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1740
1741 ndev->stats.tx_carrier_errors +=
1742 emac_read(EMAC_TXCARRIERSENSE);
1743 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1744
1745 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1746 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1747
1748 return &ndev->stats;
1749 }
1750
1751 static const struct net_device_ops emac_netdev_ops = {
1752 .ndo_open = emac_dev_open,
1753 .ndo_stop = emac_dev_stop,
1754 .ndo_start_xmit = emac_dev_xmit,
1755 .ndo_set_rx_mode = emac_dev_mcast_set,
1756 .ndo_set_mac_address = emac_dev_setmac_addr,
1757 .ndo_do_ioctl = emac_devioctl,
1758 .ndo_tx_timeout = emac_dev_tx_timeout,
1759 .ndo_get_stats = emac_dev_getnetstats,
1760 #ifdef CONFIG_NET_POLL_CONTROLLER
1761 .ndo_poll_controller = emac_poll_controller,
1762 #endif
1763 };
1764
1765 /**
1766 * davinci_emac_probe: EMAC device probe
1767 * @pdev: The DaVinci EMAC device that we are removing
1768 *
1769 * Called when probing for emac devicesr. We get details of instances and
1770 * resource information from platform init and register a network device
1771 * and allocate resources necessary for driver to perform
1772 */
1773 static int __devinit davinci_emac_probe(struct platform_device *pdev)
1774 {
1775 int rc = 0;
1776 struct resource *res;
1777 struct net_device *ndev;
1778 struct emac_priv *priv;
1779 unsigned long size, hw_ram_addr;
1780 struct emac_platform_data *pdata;
1781 struct device *emac_dev;
1782 struct cpdma_params dma_params;
1783
1784 /* obtain emac clock from kernel */
1785 emac_clk = clk_get(&pdev->dev, NULL);
1786 if (IS_ERR(emac_clk)) {
1787 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1788 return -EBUSY;
1789 }
1790 emac_bus_frequency = clk_get_rate(emac_clk);
1791 /* TODO: Probe PHY here if possible */
1792
1793 ndev = alloc_etherdev(sizeof(struct emac_priv));
1794 if (!ndev) {
1795 dev_err(&pdev->dev, "error allocating net_device\n");
1796 rc = -ENOMEM;
1797 goto free_clk;
1798 }
1799
1800 platform_set_drvdata(pdev, ndev);
1801 priv = netdev_priv(ndev);
1802 priv->pdev = pdev;
1803 priv->ndev = ndev;
1804 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1805
1806 spin_lock_init(&priv->lock);
1807
1808 pdata = pdev->dev.platform_data;
1809 if (!pdata) {
1810 dev_err(&pdev->dev, "no platform data\n");
1811 rc = -ENODEV;
1812 goto probe_quit;
1813 }
1814
1815 /* MAC addr and PHY mask , RMII enable info from platform_data */
1816 memcpy(priv->mac_addr, pdata->mac_addr, 6);
1817 priv->phy_id = pdata->phy_id;
1818 priv->rmii_en = pdata->rmii_en;
1819 priv->version = pdata->version;
1820 priv->int_enable = pdata->interrupt_enable;
1821 priv->int_disable = pdata->interrupt_disable;
1822
1823 priv->coal_intvl = 0;
1824 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1825
1826 emac_dev = &ndev->dev;
1827 /* Get EMAC platform data */
1828 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1829 if (!res) {
1830 dev_err(&pdev->dev,"error getting res\n");
1831 rc = -ENOENT;
1832 goto probe_quit;
1833 }
1834
1835 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1836 size = resource_size(res);
1837 if (!request_mem_region(res->start, size, ndev->name)) {
1838 dev_err(&pdev->dev, "failed request_mem_region() for regs\n");
1839 rc = -ENXIO;
1840 goto probe_quit;
1841 }
1842
1843 priv->remap_addr = ioremap(res->start, size);
1844 if (!priv->remap_addr) {
1845 dev_err(&pdev->dev, "unable to map IO\n");
1846 rc = -ENOMEM;
1847 release_mem_region(res->start, size);
1848 goto probe_quit;
1849 }
1850 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1851 ndev->base_addr = (unsigned long)priv->remap_addr;
1852
1853 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1854
1855 hw_ram_addr = pdata->hw_ram_addr;
1856 if (!hw_ram_addr)
1857 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1858
1859 memset(&dma_params, 0, sizeof(dma_params));
1860 dma_params.dev = emac_dev;
1861 dma_params.dmaregs = priv->emac_base;
1862 dma_params.rxthresh = priv->emac_base + 0x120;
1863 dma_params.rxfree = priv->emac_base + 0x140;
1864 dma_params.txhdp = priv->emac_base + 0x600;
1865 dma_params.rxhdp = priv->emac_base + 0x620;
1866 dma_params.txcp = priv->emac_base + 0x640;
1867 dma_params.rxcp = priv->emac_base + 0x660;
1868 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1869 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1870 dma_params.desc_hw_addr = hw_ram_addr;
1871 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1872 dma_params.desc_align = 16;
1873
1874 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1875 (u32 __force)res->start + pdata->ctrl_ram_offset;
1876
1877 priv->dma = cpdma_ctlr_create(&dma_params);
1878 if (!priv->dma) {
1879 dev_err(&pdev->dev, "error initializing DMA\n");
1880 rc = -ENOMEM;
1881 goto no_dma;
1882 }
1883
1884 priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
1885 emac_tx_handler);
1886 priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
1887 emac_rx_handler);
1888 if (WARN_ON(!priv->txchan || !priv->rxchan)) {
1889 rc = -ENOMEM;
1890 goto no_irq_res;
1891 }
1892
1893 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1894 if (!res) {
1895 dev_err(&pdev->dev, "error getting irq res\n");
1896 rc = -ENOENT;
1897 goto no_irq_res;
1898 }
1899 ndev->irq = res->start;
1900
1901 if (!is_valid_ether_addr(priv->mac_addr)) {
1902 /* Use random MAC if none passed */
1903 random_ether_addr(priv->mac_addr);
1904 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
1905 priv->mac_addr);
1906 }
1907
1908 ndev->netdev_ops = &emac_netdev_ops;
1909 SET_ETHTOOL_OPS(ndev, &ethtool_ops);
1910 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
1911
1912 clk_enable(emac_clk);
1913
1914 /* register the network device */
1915 SET_NETDEV_DEV(ndev, &pdev->dev);
1916 rc = register_netdev(ndev);
1917 if (rc) {
1918 dev_err(&pdev->dev, "error in register_netdev\n");
1919 rc = -ENODEV;
1920 goto netdev_reg_err;
1921 }
1922
1923
1924 if (netif_msg_probe(priv)) {
1925 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
1926 "(regs: %p, irq: %d)\n",
1927 (void *)priv->emac_base_phys, ndev->irq);
1928 }
1929 return 0;
1930
1931 netdev_reg_err:
1932 clk_disable(emac_clk);
1933 no_irq_res:
1934 if (priv->txchan)
1935 cpdma_chan_destroy(priv->txchan);
1936 if (priv->rxchan)
1937 cpdma_chan_destroy(priv->rxchan);
1938 cpdma_ctlr_destroy(priv->dma);
1939 no_dma:
1940 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1941 release_mem_region(res->start, resource_size(res));
1942 iounmap(priv->remap_addr);
1943
1944 probe_quit:
1945 free_netdev(ndev);
1946 free_clk:
1947 clk_put(emac_clk);
1948 return rc;
1949 }
1950
1951 /**
1952 * davinci_emac_remove: EMAC device remove
1953 * @pdev: The DaVinci EMAC device that we are removing
1954 *
1955 * Called when removing the device driver. We disable clock usage and release
1956 * the resources taken up by the driver and unregister network device
1957 */
1958 static int __devexit davinci_emac_remove(struct platform_device *pdev)
1959 {
1960 struct resource *res;
1961 struct net_device *ndev = platform_get_drvdata(pdev);
1962 struct emac_priv *priv = netdev_priv(ndev);
1963
1964 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
1965
1966 platform_set_drvdata(pdev, NULL);
1967 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1968
1969 if (priv->txchan)
1970 cpdma_chan_destroy(priv->txchan);
1971 if (priv->rxchan)
1972 cpdma_chan_destroy(priv->rxchan);
1973 cpdma_ctlr_destroy(priv->dma);
1974
1975 release_mem_region(res->start, resource_size(res));
1976
1977 unregister_netdev(ndev);
1978 iounmap(priv->remap_addr);
1979 free_netdev(ndev);
1980
1981 clk_disable(emac_clk);
1982 clk_put(emac_clk);
1983
1984 return 0;
1985 }
1986
1987 static int davinci_emac_suspend(struct device *dev)
1988 {
1989 struct platform_device *pdev = to_platform_device(dev);
1990 struct net_device *ndev = platform_get_drvdata(pdev);
1991
1992 if (netif_running(ndev))
1993 emac_dev_stop(ndev);
1994
1995 clk_disable(emac_clk);
1996
1997 return 0;
1998 }
1999
2000 static int davinci_emac_resume(struct device *dev)
2001 {
2002 struct platform_device *pdev = to_platform_device(dev);
2003 struct net_device *ndev = platform_get_drvdata(pdev);
2004
2005 clk_enable(emac_clk);
2006
2007 if (netif_running(ndev))
2008 emac_dev_open(ndev);
2009
2010 return 0;
2011 }
2012
2013 static const struct dev_pm_ops davinci_emac_pm_ops = {
2014 .suspend = davinci_emac_suspend,
2015 .resume = davinci_emac_resume,
2016 };
2017
2018 /**
2019 * davinci_emac_driver: EMAC platform driver structure
2020 */
2021 static struct platform_driver davinci_emac_driver = {
2022 .driver = {
2023 .name = "davinci_emac",
2024 .owner = THIS_MODULE,
2025 .pm = &davinci_emac_pm_ops,
2026 },
2027 .probe = davinci_emac_probe,
2028 .remove = __devexit_p(davinci_emac_remove),
2029 };
2030
2031 /**
2032 * davinci_emac_init: EMAC driver module init
2033 *
2034 * Called when initializing the driver. We register the driver with
2035 * the platform.
2036 */
2037 static int __init davinci_emac_init(void)
2038 {
2039 return platform_driver_register(&davinci_emac_driver);
2040 }
2041 late_initcall(davinci_emac_init);
2042
2043 /**
2044 * davinci_emac_exit: EMAC driver module exit
2045 *
2046 * Called when exiting the driver completely. We unregister the driver with
2047 * the platform and exit
2048 */
2049 static void __exit davinci_emac_exit(void)
2050 {
2051 platform_driver_unregister(&davinci_emac_driver);
2052 }
2053 module_exit(davinci_emac_exit);
2054
2055 MODULE_LICENSE("GPL");
2056 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2057 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2058 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");
Linux kernel - Deliverables
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