2 * DaVinci Ethernet Medium Access Controller
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 * Copyright (C) 2009 Texas Instruments.
8 * ---------------------------------------------------------------------------
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/ethtool.h>
48 #include <linux/highmem.h>
49 #include <linux/proc_fs.h>
50 #include <linux/ctype.h>
51 #include <linux/spinlock.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/clk.h>
54 #include <linux/platform_device.h>
55 #include <linux/semaphore.h>
56 #include <linux/phy.h>
57 #include <linux/bitops.h>
59 #include <linux/uaccess.h>
60 #include <linux/davinci_emac.h>
65 #include "davinci_cpdma.h"
67 static int debug_level
;
68 module_param(debug_level
, int, 0);
69 MODULE_PARM_DESC(debug_level
, "DaVinci EMAC debug level (NETIF_MSG bits)");
71 /* Netif debug messages possible */
72 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
80 NETIF_MSG_TX_QUEUED | \
83 NETIF_MSG_RX_STATUS | \
89 #define EMAC_MAJOR_VERSION 6
90 #define EMAC_MINOR_VERSION 1
91 #define EMAC_MODULE_VERSION "6.1"
92 MODULE_VERSION(EMAC_MODULE_VERSION
);
93 static const char emac_version_string
[] = "TI DaVinci EMAC Linux v6.1";
95 /* Configuration items */
96 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
97 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
98 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
99 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
100 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
101 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
102 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
103 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
104 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
105 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
106 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
107 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
109 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
110 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
112 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
113 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
114 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
115 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
116 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
117 #define EMAC_DEF_RX_NUM_DESC (128)
118 #define EMAC_DEF_TX_NUM_DESC (128)
119 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
120 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
121 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
123 /* Buffer descriptor parameters */
124 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
125 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
127 /* EMAC register related defines */
128 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
129 #define EMAC_NUM_MULTICAST_BITS (64)
130 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
131 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
132 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
133 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
134 #define EMAC_INT_MASK_CLEAR (0xFF)
136 /* RX MBP register bit positions */
137 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
138 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
139 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
140 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
141 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
142 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
143 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
144 #define EMAC_RXMBP_PROMCH_SHIFT (16)
145 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
146 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
147 #define EMAC_RXMBP_BROADCH_SHIFT (8)
148 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
149 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
150 #define EMAC_RXMBP_MULTICH_SHIFT (0)
151 #define EMAC_RXMBP_MULTICH_MASK (0x7)
152 #define EMAC_RXMBP_CHMASK (0x7)
154 /* EMAC register definitions/bit maps used */
155 # define EMAC_MBP_RXPROMISC (0x00200000)
156 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
157 # define EMAC_MBP_RXBCAST (0x00002000)
158 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
159 # define EMAC_MBP_RXMCAST (0x00000020)
160 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
162 /* EMAC mac_control register */
163 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
164 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
165 #define EMAC_MACCONTROL_GMIIEN BIT(5)
166 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
167 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
168 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
170 /* GIGABIT MODE related bits */
171 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
172 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
174 /* EMAC mac_status register */
175 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
176 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
177 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
178 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
179 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
180 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
181 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
182 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
184 /* EMAC RX register masks */
185 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
186 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
188 /* MAC_IN_VECTOR (0x180) register bit fields */
189 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
190 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
191 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
192 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
194 /** NOTE:: For DM646x the IN_VECTOR has changed */
195 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
196 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
197 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
198 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
200 /* CPPI bit positions */
201 #define EMAC_CPPI_SOP_BIT BIT(31)
202 #define EMAC_CPPI_EOP_BIT BIT(30)
203 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
204 #define EMAC_CPPI_EOQ_BIT BIT(28)
205 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
206 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
207 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
208 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
209 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
211 /* Max hardware defines */
212 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
213 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
215 /* EMAC Peripheral Device Register Memory Layout structure */
216 #define EMAC_MACINVECTOR 0x90
218 #define EMAC_DM646X_MACEOIVECTOR 0x94
220 #define EMAC_MACINTSTATRAW 0xB0
221 #define EMAC_MACINTSTATMASKED 0xB4
222 #define EMAC_MACINTMASKSET 0xB8
223 #define EMAC_MACINTMASKCLEAR 0xBC
225 #define EMAC_RXMBPENABLE 0x100
226 #define EMAC_RXUNICASTSET 0x104
227 #define EMAC_RXUNICASTCLEAR 0x108
228 #define EMAC_RXMAXLEN 0x10C
229 #define EMAC_RXBUFFEROFFSET 0x110
230 #define EMAC_RXFILTERLOWTHRESH 0x114
232 #define EMAC_MACCONTROL 0x160
233 #define EMAC_MACSTATUS 0x164
234 #define EMAC_EMCONTROL 0x168
235 #define EMAC_FIFOCONTROL 0x16C
236 #define EMAC_MACCONFIG 0x170
237 #define EMAC_SOFTRESET 0x174
238 #define EMAC_MACSRCADDRLO 0x1D0
239 #define EMAC_MACSRCADDRHI 0x1D4
240 #define EMAC_MACHASH1 0x1D8
241 #define EMAC_MACHASH2 0x1DC
242 #define EMAC_MACADDRLO 0x500
243 #define EMAC_MACADDRHI 0x504
244 #define EMAC_MACINDEX 0x508
246 /* EMAC statistics registers */
247 #define EMAC_RXGOODFRAMES 0x200
248 #define EMAC_RXBCASTFRAMES 0x204
249 #define EMAC_RXMCASTFRAMES 0x208
250 #define EMAC_RXPAUSEFRAMES 0x20C
251 #define EMAC_RXCRCERRORS 0x210
252 #define EMAC_RXALIGNCODEERRORS 0x214
253 #define EMAC_RXOVERSIZED 0x218
254 #define EMAC_RXJABBER 0x21C
255 #define EMAC_RXUNDERSIZED 0x220
256 #define EMAC_RXFRAGMENTS 0x224
257 #define EMAC_RXFILTERED 0x228
258 #define EMAC_RXQOSFILTERED 0x22C
259 #define EMAC_RXOCTETS 0x230
260 #define EMAC_TXGOODFRAMES 0x234
261 #define EMAC_TXBCASTFRAMES 0x238
262 #define EMAC_TXMCASTFRAMES 0x23C
263 #define EMAC_TXPAUSEFRAMES 0x240
264 #define EMAC_TXDEFERRED 0x244
265 #define EMAC_TXCOLLISION 0x248
266 #define EMAC_TXSINGLECOLL 0x24C
267 #define EMAC_TXMULTICOLL 0x250
268 #define EMAC_TXEXCESSIVECOLL 0x254
269 #define EMAC_TXLATECOLL 0x258
270 #define EMAC_TXUNDERRUN 0x25C
271 #define EMAC_TXCARRIERSENSE 0x260
272 #define EMAC_TXOCTETS 0x264
273 #define EMAC_NETOCTETS 0x280
274 #define EMAC_RXSOFOVERRUNS 0x284
275 #define EMAC_RXMOFOVERRUNS 0x288
276 #define EMAC_RXDMAOVERRUNS 0x28C
278 /* EMAC DM644x control registers */
279 #define EMAC_CTRL_EWCTL (0x4)
280 #define EMAC_CTRL_EWINTTCNT (0x8)
282 /* EMAC DM644x control module masks */
283 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
284 #define EMAC_DM644X_INTMIN_INTVL 0x1
285 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
287 /* EMAC DM646X control module registers */
288 #define EMAC_DM646X_CMINTCTRL 0x0C
289 #define EMAC_DM646X_CMRXINTEN 0x14
290 #define EMAC_DM646X_CMTXINTEN 0x18
291 #define EMAC_DM646X_CMRXINTMAX 0x70
292 #define EMAC_DM646X_CMTXINTMAX 0x74
294 /* EMAC DM646X control module masks */
295 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
296 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
297 #define EMAC_DM646X_CMINTMAX_CNT 63
298 #define EMAC_DM646X_CMINTMIN_CNT 2
299 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
300 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
303 /* EMAC EOI codes for C0 */
304 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
305 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
307 /* EMAC Stats Clear Mask */
308 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
310 /* emac_priv: EMAC private data structure
312 * EMAC adapter private data structure
316 struct net_device
*ndev
;
317 struct platform_device
*pdev
;
318 struct napi_struct napi
;
320 void __iomem
*remap_addr
;
322 void __iomem
*emac_base
;
323 void __iomem
*ctrl_base
;
324 struct cpdma_ctlr
*dma
;
325 struct cpdma_chan
*txchan
;
326 struct cpdma_chan
*rxchan
;
327 u32 link
; /* 1=link on, 0=link off */
328 u32 speed
; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
329 u32 duplex
; /* Link duplex: 0=Half, 1=Full */
338 u32 multicast_hash_cnt
[EMAC_NUM_MULTICAST_BITS
];
342 struct phy_device
*phydev
;
344 /*platform specific members*/
345 void (*int_enable
) (void);
346 void (*int_disable
) (void);
349 /* clock frequency for EMAC */
350 static struct clk
*emac_clk
;
351 static unsigned long emac_bus_frequency
;
353 /* EMAC TX Host Error description strings */
354 static char *emac_txhost_errcodes
[16] = {
355 "No error", "SOP error", "Ownership bit not set in SOP buffer",
356 "Zero Next Buffer Descriptor Pointer Without EOP",
357 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
358 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
359 "Reserved", "Reserved", "Reserved", "Reserved"
362 /* EMAC RX Host Error description strings */
363 static char *emac_rxhost_errcodes
[16] = {
364 "No error", "Reserved", "Ownership bit not set in input buffer",
365 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
366 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
367 "Reserved", "Reserved", "Reserved", "Reserved"
371 #define emac_read(reg) ioread32(priv->emac_base + (reg))
372 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
374 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
375 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
378 * emac_dump_regs: Dump important EMAC registers to debug terminal
379 * @priv: The DaVinci EMAC private adapter structure
381 * Executes ethtool set cmd & sets phy mode
384 static void emac_dump_regs(struct emac_priv
*priv
)
386 struct device
*emac_dev
= &priv
->ndev
->dev
;
388 /* Print important registers in EMAC */
389 dev_info(emac_dev
, "EMAC Basic registers\n");
390 if (priv
->version
== EMAC_VERSION_1
) {
391 dev_info(emac_dev
, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
392 emac_ctrl_read(EMAC_CTRL_EWCTL
),
393 emac_ctrl_read(EMAC_CTRL_EWINTTCNT
));
395 dev_info(emac_dev
, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
396 emac_read(EMAC_EMCONTROL
), emac_read(EMAC_FIFOCONTROL
));
397 dev_info(emac_dev
, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
398 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE
),
399 emac_read(EMAC_RXUNICASTSET
), emac_read(EMAC_RXMAXLEN
));
400 dev_info(emac_dev
, "EMAC: MacControl:%08X, MacStatus: %08X, "\
401 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL
),
402 emac_read(EMAC_MACSTATUS
), emac_read(EMAC_MACCONFIG
));
403 dev_info(emac_dev
, "EMAC Statistics\n");
404 dev_info(emac_dev
, "EMAC: rx_good_frames:%d\n",
405 emac_read(EMAC_RXGOODFRAMES
));
406 dev_info(emac_dev
, "EMAC: rx_broadcast_frames:%d\n",
407 emac_read(EMAC_RXBCASTFRAMES
));
408 dev_info(emac_dev
, "EMAC: rx_multicast_frames:%d\n",
409 emac_read(EMAC_RXMCASTFRAMES
));
410 dev_info(emac_dev
, "EMAC: rx_pause_frames:%d\n",
411 emac_read(EMAC_RXPAUSEFRAMES
));
412 dev_info(emac_dev
, "EMAC: rx_crcerrors:%d\n",
413 emac_read(EMAC_RXCRCERRORS
));
414 dev_info(emac_dev
, "EMAC: rx_align_code_errors:%d\n",
415 emac_read(EMAC_RXALIGNCODEERRORS
));
416 dev_info(emac_dev
, "EMAC: rx_oversized_frames:%d\n",
417 emac_read(EMAC_RXOVERSIZED
));
418 dev_info(emac_dev
, "EMAC: rx_jabber_frames:%d\n",
419 emac_read(EMAC_RXJABBER
));
420 dev_info(emac_dev
, "EMAC: rx_undersized_frames:%d\n",
421 emac_read(EMAC_RXUNDERSIZED
));
422 dev_info(emac_dev
, "EMAC: rx_fragments:%d\n",
423 emac_read(EMAC_RXFRAGMENTS
));
424 dev_info(emac_dev
, "EMAC: rx_filtered_frames:%d\n",
425 emac_read(EMAC_RXFILTERED
));
426 dev_info(emac_dev
, "EMAC: rx_qos_filtered_frames:%d\n",
427 emac_read(EMAC_RXQOSFILTERED
));
428 dev_info(emac_dev
, "EMAC: rx_octets:%d\n",
429 emac_read(EMAC_RXOCTETS
));
430 dev_info(emac_dev
, "EMAC: tx_goodframes:%d\n",
431 emac_read(EMAC_TXGOODFRAMES
));
432 dev_info(emac_dev
, "EMAC: tx_bcastframes:%d\n",
433 emac_read(EMAC_TXBCASTFRAMES
));
434 dev_info(emac_dev
, "EMAC: tx_mcastframes:%d\n",
435 emac_read(EMAC_TXMCASTFRAMES
));
436 dev_info(emac_dev
, "EMAC: tx_pause_frames:%d\n",
437 emac_read(EMAC_TXPAUSEFRAMES
));
438 dev_info(emac_dev
, "EMAC: tx_deferred_frames:%d\n",
439 emac_read(EMAC_TXDEFERRED
));
440 dev_info(emac_dev
, "EMAC: tx_collision_frames:%d\n",
441 emac_read(EMAC_TXCOLLISION
));
442 dev_info(emac_dev
, "EMAC: tx_single_coll_frames:%d\n",
443 emac_read(EMAC_TXSINGLECOLL
));
444 dev_info(emac_dev
, "EMAC: tx_mult_coll_frames:%d\n",
445 emac_read(EMAC_TXMULTICOLL
));
446 dev_info(emac_dev
, "EMAC: tx_excessive_collisions:%d\n",
447 emac_read(EMAC_TXEXCESSIVECOLL
));
448 dev_info(emac_dev
, "EMAC: tx_late_collisions:%d\n",
449 emac_read(EMAC_TXLATECOLL
));
450 dev_info(emac_dev
, "EMAC: tx_underrun:%d\n",
451 emac_read(EMAC_TXUNDERRUN
));
452 dev_info(emac_dev
, "EMAC: tx_carrier_sense_errors:%d\n",
453 emac_read(EMAC_TXCARRIERSENSE
));
454 dev_info(emac_dev
, "EMAC: tx_octets:%d\n",
455 emac_read(EMAC_TXOCTETS
));
456 dev_info(emac_dev
, "EMAC: net_octets:%d\n",
457 emac_read(EMAC_NETOCTETS
));
458 dev_info(emac_dev
, "EMAC: rx_sof_overruns:%d\n",
459 emac_read(EMAC_RXSOFOVERRUNS
));
460 dev_info(emac_dev
, "EMAC: rx_mof_overruns:%d\n",
461 emac_read(EMAC_RXMOFOVERRUNS
));
462 dev_info(emac_dev
, "EMAC: rx_dma_overruns:%d\n",
463 emac_read(EMAC_RXDMAOVERRUNS
));
465 cpdma_ctlr_dump(priv
->dma
);
469 * emac_get_drvinfo: Get EMAC driver information
470 * @ndev: The DaVinci EMAC network adapter
471 * @info: ethtool info structure containing name and version
473 * Returns EMAC driver information (name and version)
476 static void emac_get_drvinfo(struct net_device
*ndev
,
477 struct ethtool_drvinfo
*info
)
479 strcpy(info
->driver
, emac_version_string
);
480 strcpy(info
->version
, EMAC_MODULE_VERSION
);
484 * emac_get_settings: Get EMAC settings
485 * @ndev: The DaVinci EMAC network adapter
486 * @ecmd: ethtool command
488 * Executes ethool get command
491 static int emac_get_settings(struct net_device
*ndev
,
492 struct ethtool_cmd
*ecmd
)
494 struct emac_priv
*priv
= netdev_priv(ndev
);
496 return phy_ethtool_gset(priv
->phydev
, ecmd
);
503 * emac_set_settings: Set EMAC settings
504 * @ndev: The DaVinci EMAC network adapter
505 * @ecmd: ethtool command
507 * Executes ethool set command
510 static int emac_set_settings(struct net_device
*ndev
, struct ethtool_cmd
*ecmd
)
512 struct emac_priv
*priv
= netdev_priv(ndev
);
514 return phy_ethtool_sset(priv
->phydev
, ecmd
);
521 * emac_get_coalesce : Get interrupt coalesce settings for this device
522 * @ndev : The DaVinci EMAC network adapter
523 * @coal : ethtool coalesce settings structure
525 * Fetch the current interrupt coalesce settings
528 static int emac_get_coalesce(struct net_device
*ndev
,
529 struct ethtool_coalesce
*coal
)
531 struct emac_priv
*priv
= netdev_priv(ndev
);
533 coal
->rx_coalesce_usecs
= priv
->coal_intvl
;
539 * emac_set_coalesce : Set interrupt coalesce settings for this device
540 * @ndev : The DaVinci EMAC network adapter
541 * @coal : ethtool coalesce settings structure
543 * Set interrupt coalesce parameters
546 static int emac_set_coalesce(struct net_device
*ndev
,
547 struct ethtool_coalesce
*coal
)
549 struct emac_priv
*priv
= netdev_priv(ndev
);
550 u32 int_ctrl
, num_interrupts
= 0;
551 u32 prescale
= 0, addnl_dvdr
= 1, coal_intvl
= 0;
553 if (!coal
->rx_coalesce_usecs
)
556 coal_intvl
= coal
->rx_coalesce_usecs
;
558 switch (priv
->version
) {
560 int_ctrl
= emac_ctrl_read(EMAC_DM646X_CMINTCTRL
);
561 prescale
= priv
->bus_freq_mhz
* 4;
563 if (coal_intvl
< EMAC_DM646X_CMINTMIN_INTVL
)
564 coal_intvl
= EMAC_DM646X_CMINTMIN_INTVL
;
566 if (coal_intvl
> EMAC_DM646X_CMINTMAX_INTVL
) {
568 * Interrupt pacer works with 4us Pulse, we can
569 * throttle further by dilating the 4us pulse.
571 addnl_dvdr
= EMAC_DM646X_INTPRESCALE_MASK
/ prescale
;
573 if (addnl_dvdr
> 1) {
574 prescale
*= addnl_dvdr
;
575 if (coal_intvl
> (EMAC_DM646X_CMINTMAX_INTVL
577 coal_intvl
= (EMAC_DM646X_CMINTMAX_INTVL
581 coal_intvl
= EMAC_DM646X_CMINTMAX_INTVL
;
585 num_interrupts
= (1000 * addnl_dvdr
) / coal_intvl
;
587 int_ctrl
|= EMAC_DM646X_INTPACEEN
;
588 int_ctrl
&= (~EMAC_DM646X_INTPRESCALE_MASK
);
589 int_ctrl
|= (prescale
& EMAC_DM646X_INTPRESCALE_MASK
);
590 emac_ctrl_write(EMAC_DM646X_CMINTCTRL
, int_ctrl
);
592 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX
, num_interrupts
);
593 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX
, num_interrupts
);
597 int_ctrl
= emac_ctrl_read(EMAC_CTRL_EWINTTCNT
);
598 int_ctrl
&= (~EMAC_DM644X_EWINTCNT_MASK
);
599 prescale
= coal_intvl
* priv
->bus_freq_mhz
;
600 if (prescale
> EMAC_DM644X_EWINTCNT_MASK
) {
601 prescale
= EMAC_DM644X_EWINTCNT_MASK
;
602 coal_intvl
= prescale
/ priv
->bus_freq_mhz
;
604 emac_ctrl_write(EMAC_CTRL_EWINTTCNT
, (int_ctrl
| prescale
));
609 printk(KERN_INFO
"Set coalesce to %d usecs.\n", coal_intvl
);
610 priv
->coal_intvl
= coal_intvl
;
618 * ethtool_ops: DaVinci EMAC Ethtool structure
620 * Ethtool support for EMAC adapter
623 static const struct ethtool_ops ethtool_ops
= {
624 .get_drvinfo
= emac_get_drvinfo
,
625 .get_settings
= emac_get_settings
,
626 .set_settings
= emac_set_settings
,
627 .get_link
= ethtool_op_get_link
,
628 .get_coalesce
= emac_get_coalesce
,
629 .set_coalesce
= emac_set_coalesce
,
633 * emac_update_phystatus: Update Phy status
634 * @priv: The DaVinci EMAC private adapter structure
636 * Updates phy status and takes action for network queue if required
637 * based upon link status
640 static void emac_update_phystatus(struct emac_priv
*priv
)
645 struct net_device
*ndev
= priv
->ndev
;
647 mac_control
= emac_read(EMAC_MACCONTROL
);
648 cur_duplex
= (mac_control
& EMAC_MACCONTROL_FULLDUPLEXEN
) ?
649 DUPLEX_FULL
: DUPLEX_HALF
;
651 new_duplex
= priv
->phydev
->duplex
;
653 new_duplex
= DUPLEX_FULL
;
655 /* We get called only if link has changed (speed/duplex/status) */
656 if ((priv
->link
) && (new_duplex
!= cur_duplex
)) {
657 priv
->duplex
= new_duplex
;
658 if (DUPLEX_FULL
== priv
->duplex
)
659 mac_control
|= (EMAC_MACCONTROL_FULLDUPLEXEN
);
661 mac_control
&= ~(EMAC_MACCONTROL_FULLDUPLEXEN
);
664 if (priv
->speed
== SPEED_1000
&& (priv
->version
== EMAC_VERSION_2
)) {
665 mac_control
= emac_read(EMAC_MACCONTROL
);
666 mac_control
|= (EMAC_DM646X_MACCONTORL_GIG
|
667 EMAC_DM646X_MACCONTORL_GIGFORCE
);
669 /* Clear the GIG bit and GIGFORCE bit */
670 mac_control
&= ~(EMAC_DM646X_MACCONTORL_GIGFORCE
|
671 EMAC_DM646X_MACCONTORL_GIG
);
673 if (priv
->rmii_en
&& (priv
->speed
== SPEED_100
))
674 mac_control
|= EMAC_MACCONTROL_RMIISPEED_MASK
;
676 mac_control
&= ~EMAC_MACCONTROL_RMIISPEED_MASK
;
679 /* Update mac_control if changed */
680 emac_write(EMAC_MACCONTROL
, mac_control
);
684 if (!netif_carrier_ok(ndev
))
685 netif_carrier_on(ndev
);
686 /* reactivate the transmit queue if it is stopped */
687 if (netif_running(ndev
) && netif_queue_stopped(ndev
))
688 netif_wake_queue(ndev
);
691 if (netif_carrier_ok(ndev
))
692 netif_carrier_off(ndev
);
693 if (!netif_queue_stopped(ndev
))
694 netif_stop_queue(ndev
);
699 * hash_get: Calculate hash value from mac address
700 * @addr: mac address to delete from hash table
702 * Calculates hash value from mac address
705 static u32
hash_get(u8
*addr
)
712 for (cnt
= 0; cnt
< 2; cnt
++) {
714 hash
^= (tmpval
>> 2) ^ (tmpval
<< 4);
716 hash
^= (tmpval
>> 4) ^ (tmpval
<< 2);
718 hash
^= (tmpval
>> 6) ^ (tmpval
);
725 * hash_add: Hash function to add mac addr from hash table
726 * @priv: The DaVinci EMAC private adapter structure
727 * mac_addr: mac address to delete from hash table
729 * Adds mac address to the internal hash table
732 static int hash_add(struct emac_priv
*priv
, u8
*mac_addr
)
734 struct device
*emac_dev
= &priv
->ndev
->dev
;
737 u32 hash_value
= hash_get(mac_addr
);
739 if (hash_value
>= EMAC_NUM_MULTICAST_BITS
) {
740 if (netif_msg_drv(priv
)) {
741 dev_err(emac_dev
, "DaVinci EMAC: hash_add(): Invalid "\
742 "Hash %08x, should not be greater than %08x",
743 hash_value
, (EMAC_NUM_MULTICAST_BITS
- 1));
748 /* set the hash bit only if not previously set */
749 if (priv
->multicast_hash_cnt
[hash_value
] == 0) {
750 rc
= 1; /* hash value changed */
751 if (hash_value
< 32) {
752 hash_bit
= BIT(hash_value
);
753 priv
->mac_hash1
|= hash_bit
;
755 hash_bit
= BIT((hash_value
- 32));
756 priv
->mac_hash2
|= hash_bit
;
760 /* incr counter for num of mcast addr's mapped to "this" hash bit */
761 ++priv
->multicast_hash_cnt
[hash_value
];
767 * hash_del: Hash function to delete mac addr from hash table
768 * @priv: The DaVinci EMAC private adapter structure
769 * mac_addr: mac address to delete from hash table
771 * Removes mac address from the internal hash table
774 static int hash_del(struct emac_priv
*priv
, u8
*mac_addr
)
779 hash_value
= hash_get(mac_addr
);
780 if (priv
->multicast_hash_cnt
[hash_value
] > 0) {
781 /* dec cntr for num of mcast addr's mapped to this hash bit */
782 --priv
->multicast_hash_cnt
[hash_value
];
785 /* if counter still > 0, at least one multicast address refers
786 * to this hash bit. so return 0 */
787 if (priv
->multicast_hash_cnt
[hash_value
] > 0)
790 if (hash_value
< 32) {
791 hash_bit
= BIT(hash_value
);
792 priv
->mac_hash1
&= ~hash_bit
;
794 hash_bit
= BIT((hash_value
- 32));
795 priv
->mac_hash2
&= ~hash_bit
;
798 /* return 1 to indicate change in mac_hash registers reqd */
802 /* EMAC multicast operation */
803 #define EMAC_MULTICAST_ADD 0
804 #define EMAC_MULTICAST_DEL 1
805 #define EMAC_ALL_MULTI_SET 2
806 #define EMAC_ALL_MULTI_CLR 3
809 * emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
810 * @priv: The DaVinci EMAC private adapter structure
811 * @action: multicast operation to perform
812 * mac_addr: mac address to set
814 * Set multicast addresses in EMAC adapter - internal function
817 static void emac_add_mcast(struct emac_priv
*priv
, u32 action
, u8
*mac_addr
)
819 struct device
*emac_dev
= &priv
->ndev
->dev
;
823 case EMAC_MULTICAST_ADD
:
824 update
= hash_add(priv
, mac_addr
);
826 case EMAC_MULTICAST_DEL
:
827 update
= hash_del(priv
, mac_addr
);
829 case EMAC_ALL_MULTI_SET
:
831 priv
->mac_hash1
= EMAC_ALL_MULTI_REG_VALUE
;
832 priv
->mac_hash2
= EMAC_ALL_MULTI_REG_VALUE
;
834 case EMAC_ALL_MULTI_CLR
:
838 memset(&(priv
->multicast_hash_cnt
[0]), 0,
839 sizeof(priv
->multicast_hash_cnt
[0]) *
840 EMAC_NUM_MULTICAST_BITS
);
843 if (netif_msg_drv(priv
))
844 dev_err(emac_dev
, "DaVinci EMAC: add_mcast"\
845 ": bad operation %d", action
);
849 /* write to the hardware only if the register status chances */
851 emac_write(EMAC_MACHASH1
, priv
->mac_hash1
);
852 emac_write(EMAC_MACHASH2
, priv
->mac_hash2
);
857 * emac_dev_mcast_set: Set multicast address in the EMAC adapter
858 * @ndev: The DaVinci EMAC network adapter
860 * Set multicast addresses in EMAC adapter
863 static void emac_dev_mcast_set(struct net_device
*ndev
)
866 struct emac_priv
*priv
= netdev_priv(ndev
);
868 mbp_enable
= emac_read(EMAC_RXMBPENABLE
);
869 if (ndev
->flags
& IFF_PROMISC
) {
870 mbp_enable
&= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH
));
871 mbp_enable
|= (EMAC_MBP_RXPROMISC
);
873 mbp_enable
= (mbp_enable
& ~EMAC_MBP_RXPROMISC
);
874 if ((ndev
->flags
& IFF_ALLMULTI
) ||
875 netdev_mc_count(ndev
) > EMAC_DEF_MAX_MULTICAST_ADDRESSES
) {
876 mbp_enable
= (mbp_enable
| EMAC_MBP_RXMCAST
);
877 emac_add_mcast(priv
, EMAC_ALL_MULTI_SET
, NULL
);
879 if (!netdev_mc_empty(ndev
)) {
880 struct netdev_hw_addr
*ha
;
882 mbp_enable
= (mbp_enable
| EMAC_MBP_RXMCAST
);
883 emac_add_mcast(priv
, EMAC_ALL_MULTI_CLR
, NULL
);
884 /* program multicast address list into EMAC hardware */
885 netdev_for_each_mc_addr(ha
, ndev
) {
886 emac_add_mcast(priv
, EMAC_MULTICAST_ADD
,
890 mbp_enable
= (mbp_enable
& ~EMAC_MBP_RXMCAST
);
891 emac_add_mcast(priv
, EMAC_ALL_MULTI_CLR
, NULL
);
894 /* Set mbp config register */
895 emac_write(EMAC_RXMBPENABLE
, mbp_enable
);
898 /*************************************************************************
899 * EMAC Hardware manipulation
900 *************************************************************************/
903 * emac_int_disable: Disable EMAC module interrupt (from adapter)
904 * @priv: The DaVinci EMAC private adapter structure
906 * Disable EMAC interrupt on the adapter
909 static void emac_int_disable(struct emac_priv
*priv
)
911 if (priv
->version
== EMAC_VERSION_2
) {
914 local_irq_save(flags
);
916 /* Program C0_Int_En to zero to turn off
917 * interrupts to the CPU */
918 emac_ctrl_write(EMAC_DM646X_CMRXINTEN
, 0x0);
919 emac_ctrl_write(EMAC_DM646X_CMTXINTEN
, 0x0);
920 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
921 if (priv
->int_disable
)
924 local_irq_restore(flags
);
927 /* Set DM644x control registers for interrupt control */
928 emac_ctrl_write(EMAC_CTRL_EWCTL
, 0x0);
933 * emac_int_enable: Enable EMAC module interrupt (from adapter)
934 * @priv: The DaVinci EMAC private adapter structure
936 * Enable EMAC interrupt on the adapter
939 static void emac_int_enable(struct emac_priv
*priv
)
941 if (priv
->version
== EMAC_VERSION_2
) {
942 if (priv
->int_enable
)
945 emac_ctrl_write(EMAC_DM646X_CMRXINTEN
, 0xff);
946 emac_ctrl_write(EMAC_DM646X_CMTXINTEN
, 0xff);
948 /* In addition to turning on interrupt Enable, we need
949 * ack by writing appropriate values to the EOI
952 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
954 /* ack rxen only then a new pulse will be generated */
955 emac_write(EMAC_DM646X_MACEOIVECTOR
,
956 EMAC_DM646X_MAC_EOI_C0_RXEN
);
958 /* ack txen- only then a new pulse will be generated */
959 emac_write(EMAC_DM646X_MACEOIVECTOR
,
960 EMAC_DM646X_MAC_EOI_C0_TXEN
);
963 /* Set DM644x control registers for interrupt control */
964 emac_ctrl_write(EMAC_CTRL_EWCTL
, 0x1);
969 * emac_irq: EMAC interrupt handler
970 * @irq: interrupt number
971 * @dev_id: EMAC network adapter data structure ptr
973 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
974 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
976 * Returns interrupt handled condition
978 static irqreturn_t
emac_irq(int irq
, void *dev_id
)
980 struct net_device
*ndev
= (struct net_device
*)dev_id
;
981 struct emac_priv
*priv
= netdev_priv(ndev
);
984 if (likely(netif_running(priv
->ndev
))) {
985 emac_int_disable(priv
);
986 napi_schedule(&priv
->napi
);
988 /* we are closing down, so dont process anything */
993 static struct sk_buff
*emac_rx_alloc(struct emac_priv
*priv
)
995 struct sk_buff
*skb
= netdev_alloc_skb(priv
->ndev
, priv
->rx_buf_size
);
998 skb_reserve(skb
, NET_IP_ALIGN
);
1002 static void emac_rx_handler(void *token
, int len
, int status
)
1004 struct sk_buff
*skb
= token
;
1005 struct net_device
*ndev
= skb
->dev
;
1006 struct emac_priv
*priv
= netdev_priv(ndev
);
1007 struct device
*emac_dev
= &ndev
->dev
;
1010 /* free and bail if we are shutting down */
1011 if (unlikely(!netif_running(ndev
))) {
1012 dev_kfree_skb_any(skb
);
1016 /* recycle on receive error */
1018 ndev
->stats
.rx_errors
++;
1022 /* feed received packet up the stack */
1024 skb
->protocol
= eth_type_trans(skb
, ndev
);
1025 netif_receive_skb(skb
);
1026 ndev
->stats
.rx_bytes
+= len
;
1027 ndev
->stats
.rx_packets
++;
1029 /* alloc a new packet for receive */
1030 skb
= emac_rx_alloc(priv
);
1032 if (netif_msg_rx_err(priv
) && net_ratelimit())
1033 dev_err(emac_dev
, "failed rx buffer alloc\n");
1038 ret
= cpdma_chan_submit(priv
->rxchan
, skb
, skb
->data
,
1039 skb_tailroom(skb
), GFP_KERNEL
);
1041 WARN_ON(ret
== -ENOMEM
);
1042 if (unlikely(ret
< 0))
1043 dev_kfree_skb_any(skb
);
1046 static void emac_tx_handler(void *token
, int len
, int status
)
1048 struct sk_buff
*skb
= token
;
1049 struct net_device
*ndev
= skb
->dev
;
1050 struct emac_priv
*priv
= netdev_priv(ndev
);
1052 atomic_dec(&priv
->cur_tx
);
1054 if (unlikely(netif_queue_stopped(ndev
)))
1055 netif_start_queue(ndev
);
1056 ndev
->stats
.tx_packets
++;
1057 ndev
->stats
.tx_bytes
+= len
;
1058 dev_kfree_skb_any(skb
);
1062 * emac_dev_xmit: EMAC Transmit function
1064 * @ndev: The DaVinci EMAC network adapter
1066 * Called by the system to transmit a packet - we queue the packet in
1067 * EMAC hardware transmit queue
1069 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1071 static int emac_dev_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
1073 struct device
*emac_dev
= &ndev
->dev
;
1075 struct emac_priv
*priv
= netdev_priv(ndev
);
1077 /* If no link, return */
1078 if (unlikely(!priv
->link
)) {
1079 if (netif_msg_tx_err(priv
) && net_ratelimit())
1080 dev_err(emac_dev
, "DaVinci EMAC: No link to transmit");
1084 ret_code
= skb_padto(skb
, EMAC_DEF_MIN_ETHPKTSIZE
);
1085 if (unlikely(ret_code
< 0)) {
1086 if (netif_msg_tx_err(priv
) && net_ratelimit())
1087 dev_err(emac_dev
, "DaVinci EMAC: packet pad failed");
1091 skb_tx_timestamp(skb
);
1093 ret_code
= cpdma_chan_submit(priv
->txchan
, skb
, skb
->data
, skb
->len
,
1095 if (unlikely(ret_code
!= 0)) {
1096 if (netif_msg_tx_err(priv
) && net_ratelimit())
1097 dev_err(emac_dev
, "DaVinci EMAC: desc submit failed");
1101 if (atomic_inc_return(&priv
->cur_tx
) >= EMAC_DEF_TX_NUM_DESC
)
1102 netif_stop_queue(ndev
);
1104 return NETDEV_TX_OK
;
1107 ndev
->stats
.tx_dropped
++;
1108 netif_stop_queue(ndev
);
1109 return NETDEV_TX_BUSY
;
1113 * emac_dev_tx_timeout: EMAC Transmit timeout function
1114 * @ndev: The DaVinci EMAC network adapter
1116 * Called when system detects that a skb timeout period has expired
1117 * potentially due to a fault in the adapter in not being able to send
1118 * it out on the wire. We teardown the TX channel assuming a hardware
1119 * error and re-initialize the TX channel for hardware operation
1122 static void emac_dev_tx_timeout(struct net_device
*ndev
)
1124 struct emac_priv
*priv
= netdev_priv(ndev
);
1125 struct device
*emac_dev
= &ndev
->dev
;
1127 if (netif_msg_tx_err(priv
))
1128 dev_err(emac_dev
, "DaVinci EMAC: xmit timeout, restarting TX");
1130 emac_dump_regs(priv
);
1132 ndev
->stats
.tx_errors
++;
1133 emac_int_disable(priv
);
1134 cpdma_chan_stop(priv
->txchan
);
1135 cpdma_chan_start(priv
->txchan
);
1136 emac_int_enable(priv
);
1140 * emac_set_type0addr: Set EMAC Type0 mac address
1141 * @priv: The DaVinci EMAC private adapter structure
1142 * @ch: RX channel number
1143 * @mac_addr: MAC address to set in device
1145 * Called internally to set Type0 mac address of the adapter (Device)
1147 * Returns success (0) or appropriate error code (none as of now)
1149 static void emac_set_type0addr(struct emac_priv
*priv
, u32 ch
, char *mac_addr
)
1152 val
= ((mac_addr
[5] << 8) | (mac_addr
[4]));
1153 emac_write(EMAC_MACSRCADDRLO
, val
);
1155 val
= ((mac_addr
[3] << 24) | (mac_addr
[2] << 16) | \
1156 (mac_addr
[1] << 8) | (mac_addr
[0]));
1157 emac_write(EMAC_MACSRCADDRHI
, val
);
1158 val
= emac_read(EMAC_RXUNICASTSET
);
1160 emac_write(EMAC_RXUNICASTSET
, val
);
1161 val
= emac_read(EMAC_RXUNICASTCLEAR
);
1163 emac_write(EMAC_RXUNICASTCLEAR
, val
);
1167 * emac_set_type1addr: Set EMAC Type1 mac address
1168 * @priv: The DaVinci EMAC private adapter structure
1169 * @ch: RX channel number
1170 * @mac_addr: MAC address to set in device
1172 * Called internally to set Type1 mac address of the adapter (Device)
1174 * Returns success (0) or appropriate error code (none as of now)
1176 static void emac_set_type1addr(struct emac_priv
*priv
, u32 ch
, char *mac_addr
)
1179 emac_write(EMAC_MACINDEX
, ch
);
1180 val
= ((mac_addr
[5] << 8) | mac_addr
[4]);
1181 emac_write(EMAC_MACADDRLO
, val
);
1182 val
= ((mac_addr
[3] << 24) | (mac_addr
[2] << 16) | \
1183 (mac_addr
[1] << 8) | (mac_addr
[0]));
1184 emac_write(EMAC_MACADDRHI
, val
);
1185 emac_set_type0addr(priv
, ch
, mac_addr
);
1189 * emac_set_type2addr: Set EMAC Type2 mac address
1190 * @priv: The DaVinci EMAC private adapter structure
1191 * @ch: RX channel number
1192 * @mac_addr: MAC address to set in device
1193 * @index: index into RX address entries
1194 * @match: match parameter for RX address matching logic
1196 * Called internally to set Type2 mac address of the adapter (Device)
1198 * Returns success (0) or appropriate error code (none as of now)
1200 static void emac_set_type2addr(struct emac_priv
*priv
, u32 ch
,
1201 char *mac_addr
, int index
, int match
)
1204 emac_write(EMAC_MACINDEX
, index
);
1205 val
= ((mac_addr
[3] << 24) | (mac_addr
[2] << 16) | \
1206 (mac_addr
[1] << 8) | (mac_addr
[0]));
1207 emac_write(EMAC_MACADDRHI
, val
);
1208 val
= ((mac_addr
[5] << 8) | mac_addr
[4] | ((ch
& 0x7) << 16) | \
1209 (match
<< 19) | BIT(20));
1210 emac_write(EMAC_MACADDRLO
, val
);
1211 emac_set_type0addr(priv
, ch
, mac_addr
);
1215 * emac_setmac: Set mac address in the adapter (internal function)
1216 * @priv: The DaVinci EMAC private adapter structure
1217 * @ch: RX channel number
1218 * @mac_addr: MAC address to set in device
1220 * Called internally to set the mac address of the adapter (Device)
1222 * Returns success (0) or appropriate error code (none as of now)
1224 static void emac_setmac(struct emac_priv
*priv
, u32 ch
, char *mac_addr
)
1226 struct device
*emac_dev
= &priv
->ndev
->dev
;
1228 if (priv
->rx_addr_type
== 0) {
1229 emac_set_type0addr(priv
, ch
, mac_addr
);
1230 } else if (priv
->rx_addr_type
== 1) {
1232 for (cnt
= 0; cnt
< EMAC_MAX_TXRX_CHANNELS
; cnt
++)
1233 emac_set_type1addr(priv
, ch
, mac_addr
);
1234 } else if (priv
->rx_addr_type
== 2) {
1235 emac_set_type2addr(priv
, ch
, mac_addr
, ch
, 1);
1236 emac_set_type0addr(priv
, ch
, mac_addr
);
1238 if (netif_msg_drv(priv
))
1239 dev_err(emac_dev
, "DaVinci EMAC: Wrong addressing\n");
1244 * emac_dev_setmac_addr: Set mac address in the adapter
1245 * @ndev: The DaVinci EMAC network adapter
1246 * @addr: MAC address to set in device
1248 * Called by the system to set the mac address of the adapter (Device)
1250 * Returns success (0) or appropriate error code (none as of now)
1252 static int emac_dev_setmac_addr(struct net_device
*ndev
, void *addr
)
1254 struct emac_priv
*priv
= netdev_priv(ndev
);
1255 struct device
*emac_dev
= &priv
->ndev
->dev
;
1256 struct sockaddr
*sa
= addr
;
1258 if (!is_valid_ether_addr(sa
->sa_data
))
1259 return -EADDRNOTAVAIL
;
1261 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1262 memcpy(priv
->mac_addr
, sa
->sa_data
, ndev
->addr_len
);
1263 memcpy(ndev
->dev_addr
, sa
->sa_data
, ndev
->addr_len
);
1264 ndev
->addr_assign_type
&= ~NET_ADDR_RANDOM
;
1266 /* MAC address is configured only after the interface is enabled. */
1267 if (netif_running(ndev
)) {
1268 emac_setmac(priv
, EMAC_DEF_RX_CH
, priv
->mac_addr
);
1271 if (netif_msg_drv(priv
))
1272 dev_notice(emac_dev
, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1279 * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
1280 * @priv: The DaVinci EMAC private adapter structure
1282 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1283 * for packet reception and enables device interrupts and then NAPI
1285 * Returns success (0) or appropriate error code (none right now)
1287 static int emac_hw_enable(struct emac_priv
*priv
)
1289 u32 val
, mbp_enable
, mac_control
;
1292 emac_write(EMAC_SOFTRESET
, 1);
1293 while (emac_read(EMAC_SOFTRESET
))
1296 /* Disable interrupt & Set pacing for more interrupts initially */
1297 emac_int_disable(priv
);
1299 /* Full duplex enable bit set when auto negotiation happens */
1301 (((EMAC_DEF_TXPRIO_FIXED
) ? (EMAC_MACCONTROL_TXPTYPE
) : 0x0) |
1302 ((priv
->speed
== 1000) ? EMAC_MACCONTROL_GIGABITEN
: 0x0) |
1303 ((EMAC_DEF_TXPACING_EN
) ? (EMAC_MACCONTROL_TXPACEEN
) : 0x0) |
1304 ((priv
->duplex
== DUPLEX_FULL
) ? 0x1 : 0));
1305 emac_write(EMAC_MACCONTROL
, mac_control
);
1308 (((EMAC_DEF_PASS_CRC
) ? (EMAC_RXMBP_PASSCRC_MASK
) : 0x0) |
1309 ((EMAC_DEF_QOS_EN
) ? (EMAC_RXMBP_QOSEN_MASK
) : 0x0) |
1310 ((EMAC_DEF_NO_BUFF_CHAIN
) ? (EMAC_RXMBP_NOCHAIN_MASK
) : 0x0) |
1311 ((EMAC_DEF_MACCTRL_FRAME_EN
) ? (EMAC_RXMBP_CMFEN_MASK
) : 0x0) |
1312 ((EMAC_DEF_SHORT_FRAME_EN
) ? (EMAC_RXMBP_CSFEN_MASK
) : 0x0) |
1313 ((EMAC_DEF_ERROR_FRAME_EN
) ? (EMAC_RXMBP_CEFEN_MASK
) : 0x0) |
1314 ((EMAC_DEF_PROM_EN
) ? (EMAC_RXMBP_CAFEN_MASK
) : 0x0) |
1315 ((EMAC_DEF_PROM_CH
& EMAC_RXMBP_CHMASK
) << \
1316 EMAC_RXMBP_PROMCH_SHIFT
) |
1317 ((EMAC_DEF_BCAST_EN
) ? (EMAC_RXMBP_BROADEN_MASK
) : 0x0) |
1318 ((EMAC_DEF_BCAST_CH
& EMAC_RXMBP_CHMASK
) << \
1319 EMAC_RXMBP_BROADCH_SHIFT
) |
1320 ((EMAC_DEF_MCAST_EN
) ? (EMAC_RXMBP_MULTIEN_MASK
) : 0x0) |
1321 ((EMAC_DEF_MCAST_CH
& EMAC_RXMBP_CHMASK
) << \
1322 EMAC_RXMBP_MULTICH_SHIFT
));
1323 emac_write(EMAC_RXMBPENABLE
, mbp_enable
);
1324 emac_write(EMAC_RXMAXLEN
, (EMAC_DEF_MAX_FRAME_SIZE
&
1325 EMAC_RX_MAX_LEN_MASK
));
1326 emac_write(EMAC_RXBUFFEROFFSET
, (EMAC_DEF_BUFFER_OFFSET
&
1327 EMAC_RX_BUFFER_OFFSET_MASK
));
1328 emac_write(EMAC_RXFILTERLOWTHRESH
, 0);
1329 emac_write(EMAC_RXUNICASTCLEAR
, EMAC_RX_UNICAST_CLEAR_ALL
);
1330 priv
->rx_addr_type
= (emac_read(EMAC_MACCONFIG
) >> 8) & 0xFF;
1332 emac_write(EMAC_MACINTMASKSET
, EMAC_MAC_HOST_ERR_INTMASK_VAL
);
1334 emac_setmac(priv
, EMAC_DEF_RX_CH
, priv
->mac_addr
);
1337 val
= emac_read(EMAC_MACCONTROL
);
1338 val
|= (EMAC_MACCONTROL_GMIIEN
);
1339 emac_write(EMAC_MACCONTROL
, val
);
1341 /* Enable NAPI and interrupts */
1342 napi_enable(&priv
->napi
);
1343 emac_int_enable(priv
);
1349 * emac_poll: EMAC NAPI Poll function
1350 * @ndev: The DaVinci EMAC network adapter
1351 * @budget: Number of receive packets to process (as told by NAPI layer)
1353 * NAPI Poll function implemented to process packets as per budget. We check
1354 * the type of interrupt on the device and accordingly call the TX or RX
1355 * packet processing functions. We follow the budget for RX processing and
1356 * also put a cap on number of TX pkts processed through config param. The
1357 * NAPI schedule function is called if more packets pending.
1359 * Returns number of packets received (in most cases; else TX pkts - rarely)
1361 static int emac_poll(struct napi_struct
*napi
, int budget
)
1364 struct emac_priv
*priv
= container_of(napi
, struct emac_priv
, napi
);
1365 struct net_device
*ndev
= priv
->ndev
;
1366 struct device
*emac_dev
= &ndev
->dev
;
1368 u32 num_tx_pkts
= 0, num_rx_pkts
= 0;
1370 /* Check interrupt vectors and call packet processing */
1371 status
= emac_read(EMAC_MACINVECTOR
);
1373 mask
= EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC
;
1375 if (priv
->version
== EMAC_VERSION_2
)
1376 mask
= EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC
;
1378 if (status
& mask
) {
1379 num_tx_pkts
= cpdma_chan_process(priv
->txchan
,
1380 EMAC_DEF_TX_MAX_SERVICE
);
1381 } /* TX processing */
1383 mask
= EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC
;
1385 if (priv
->version
== EMAC_VERSION_2
)
1386 mask
= EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC
;
1388 if (status
& mask
) {
1389 num_rx_pkts
= cpdma_chan_process(priv
->rxchan
, budget
);
1390 } /* RX processing */
1392 mask
= EMAC_DM644X_MAC_IN_VECTOR_HOST_INT
;
1393 if (priv
->version
== EMAC_VERSION_2
)
1394 mask
= EMAC_DM646X_MAC_IN_VECTOR_HOST_INT
;
1396 if (unlikely(status
& mask
)) {
1398 dev_err(emac_dev
, "DaVinci EMAC: Fatal Hardware Error\n");
1399 netif_stop_queue(ndev
);
1400 napi_disable(&priv
->napi
);
1402 status
= emac_read(EMAC_MACSTATUS
);
1403 cause
= ((status
& EMAC_MACSTATUS_TXERRCODE_MASK
) >>
1404 EMAC_MACSTATUS_TXERRCODE_SHIFT
);
1406 ch
= ((status
& EMAC_MACSTATUS_TXERRCH_MASK
) >>
1407 EMAC_MACSTATUS_TXERRCH_SHIFT
);
1408 if (net_ratelimit()) {
1409 dev_err(emac_dev
, "TX Host error %s on ch=%d\n",
1410 &emac_txhost_errcodes
[cause
][0], ch
);
1413 cause
= ((status
& EMAC_MACSTATUS_RXERRCODE_MASK
) >>
1414 EMAC_MACSTATUS_RXERRCODE_SHIFT
);
1416 ch
= ((status
& EMAC_MACSTATUS_RXERRCH_MASK
) >>
1417 EMAC_MACSTATUS_RXERRCH_SHIFT
);
1418 if (netif_msg_hw(priv
) && net_ratelimit())
1419 dev_err(emac_dev
, "RX Host error %s on ch=%d\n",
1420 &emac_rxhost_errcodes
[cause
][0], ch
);
1422 } else if (num_rx_pkts
< budget
) {
1423 napi_complete(napi
);
1424 emac_int_enable(priv
);
1430 #ifdef CONFIG_NET_POLL_CONTROLLER
1432 * emac_poll_controller: EMAC Poll controller function
1433 * @ndev: The DaVinci EMAC network adapter
1435 * Polled functionality used by netconsole and others in non interrupt mode
1438 void emac_poll_controller(struct net_device
*ndev
)
1440 struct emac_priv
*priv
= netdev_priv(ndev
);
1442 emac_int_disable(priv
);
1443 emac_irq(ndev
->irq
, ndev
);
1444 emac_int_enable(priv
);
1448 static void emac_adjust_link(struct net_device
*ndev
)
1450 struct emac_priv
*priv
= netdev_priv(ndev
);
1451 struct phy_device
*phydev
= priv
->phydev
;
1452 unsigned long flags
;
1455 spin_lock_irqsave(&priv
->lock
, flags
);
1458 /* check the mode of operation - full/half duplex */
1459 if (phydev
->duplex
!= priv
->duplex
) {
1461 priv
->duplex
= phydev
->duplex
;
1463 if (phydev
->speed
!= priv
->speed
) {
1465 priv
->speed
= phydev
->speed
;
1472 } else if (priv
->link
) {
1479 emac_update_phystatus(priv
);
1480 phy_print_status(priv
->phydev
);
1483 spin_unlock_irqrestore(&priv
->lock
, flags
);
1486 /*************************************************************************
1487 * Linux Driver Model
1488 *************************************************************************/
1491 * emac_devioctl: EMAC adapter ioctl
1492 * @ndev: The DaVinci EMAC network adapter
1493 * @ifrq: request parameter
1494 * @cmd: command parameter
1496 * EMAC driver ioctl function
1498 * Returns success(0) or appropriate error code
1500 static int emac_devioctl(struct net_device
*ndev
, struct ifreq
*ifrq
, int cmd
)
1502 struct emac_priv
*priv
= netdev_priv(ndev
);
1504 if (!(netif_running(ndev
)))
1507 /* TODO: Add phy read and write and private statistics get feature */
1509 return phy_mii_ioctl(priv
->phydev
, ifrq
, cmd
);
1512 static int match_first_device(struct device
*dev
, void *data
)
1518 * emac_dev_open: EMAC device open
1519 * @ndev: The DaVinci EMAC network adapter
1521 * Called when system wants to start the interface. We init TX/RX channels
1522 * and enable the hardware for packet reception/transmission and start the
1525 * Returns 0 for a successful open, or appropriate error code
1527 static int emac_dev_open(struct net_device
*ndev
)
1529 struct device
*emac_dev
= &ndev
->dev
;
1531 struct resource
*res
;
1535 struct emac_priv
*priv
= netdev_priv(ndev
);
1537 netif_carrier_off(ndev
);
1538 for (cnt
= 0; cnt
< ETH_ALEN
; cnt
++)
1539 ndev
->dev_addr
[cnt
] = priv
->mac_addr
[cnt
];
1541 /* Configuration items */
1542 priv
->rx_buf_size
= EMAC_DEF_MAX_FRAME_SIZE
+ NET_IP_ALIGN
;
1544 priv
->mac_hash1
= 0;
1545 priv
->mac_hash2
= 0;
1546 emac_write(EMAC_MACHASH1
, 0);
1547 emac_write(EMAC_MACHASH2
, 0);
1549 for (i
= 0; i
< EMAC_DEF_RX_NUM_DESC
; i
++) {
1550 struct sk_buff
*skb
= emac_rx_alloc(priv
);
1555 ret
= cpdma_chan_submit(priv
->rxchan
, skb
, skb
->data
,
1556 skb_tailroom(skb
), GFP_KERNEL
);
1557 if (WARN_ON(ret
< 0))
1563 while ((res
= platform_get_resource(priv
->pdev
, IORESOURCE_IRQ
, k
))) {
1564 for (i
= res
->start
; i
<= res
->end
; i
++) {
1565 if (request_irq(i
, emac_irq
, IRQF_DISABLED
,
1572 /* Start/Enable EMAC hardware */
1573 emac_hw_enable(priv
);
1575 /* Enable Interrupt pacing if configured */
1576 if (priv
->coal_intvl
!= 0) {
1577 struct ethtool_coalesce coal
;
1579 coal
.rx_coalesce_usecs
= (priv
->coal_intvl
<< 4);
1580 emac_set_coalesce(ndev
, &coal
);
1583 cpdma_ctlr_start(priv
->dma
);
1585 priv
->phydev
= NULL
;
1586 /* use the first phy on the bus if pdata did not give us a phy id */
1587 if (!priv
->phy_id
) {
1590 phy
= bus_find_device(&mdio_bus_type
, NULL
, NULL
,
1591 match_first_device
);
1593 priv
->phy_id
= dev_name(phy
);
1596 if (priv
->phy_id
&& *priv
->phy_id
) {
1597 priv
->phydev
= phy_connect(ndev
, priv
->phy_id
,
1598 &emac_adjust_link
, 0,
1599 PHY_INTERFACE_MODE_MII
);
1601 if (IS_ERR(priv
->phydev
)) {
1602 dev_err(emac_dev
, "could not connect to phy %s\n",
1604 ret
= PTR_ERR(priv
->phydev
);
1605 priv
->phydev
= NULL
;
1613 dev_info(emac_dev
, "attached PHY driver [%s] "
1614 "(mii_bus:phy_addr=%s, id=%x)\n",
1615 priv
->phydev
->drv
->name
, dev_name(&priv
->phydev
->dev
),
1616 priv
->phydev
->phy_id
);
1618 /* No PHY , fix the link, speed and duplex settings */
1619 dev_notice(emac_dev
, "no phy, defaulting to 100/full\n");
1621 priv
->speed
= SPEED_100
;
1622 priv
->duplex
= DUPLEX_FULL
;
1623 emac_update_phystatus(priv
);
1626 if (!netif_running(ndev
)) /* debug only - to avoid compiler warning */
1627 emac_dump_regs(priv
);
1629 if (netif_msg_drv(priv
))
1630 dev_notice(emac_dev
, "DaVinci EMAC: Opened %s\n", ndev
->name
);
1633 phy_start(priv
->phydev
);
1639 dev_err(emac_dev
, "DaVinci EMAC: request_irq() failed");
1641 for (q
= k
; k
>= 0; k
--) {
1642 for (m
= i
; m
>= res
->start
; m
--)
1644 res
= platform_get_resource(priv
->pdev
, IORESOURCE_IRQ
, k
-1);
1651 * emac_dev_stop: EMAC device stop
1652 * @ndev: The DaVinci EMAC network adapter
1654 * Called when system wants to stop or down the interface. We stop the network
1655 * queue, disable interrupts and cleanup TX/RX channels.
1657 * We return the statistics in net_device_stats structure pulled from emac
1659 static int emac_dev_stop(struct net_device
*ndev
)
1661 struct resource
*res
;
1664 struct emac_priv
*priv
= netdev_priv(ndev
);
1665 struct device
*emac_dev
= &ndev
->dev
;
1667 /* inform the upper layers. */
1668 netif_stop_queue(ndev
);
1669 napi_disable(&priv
->napi
);
1671 netif_carrier_off(ndev
);
1672 emac_int_disable(priv
);
1673 cpdma_ctlr_stop(priv
->dma
);
1674 emac_write(EMAC_SOFTRESET
, 1);
1677 phy_disconnect(priv
->phydev
);
1680 while ((res
= platform_get_resource(priv
->pdev
, IORESOURCE_IRQ
, i
))) {
1681 for (irq_num
= res
->start
; irq_num
<= res
->end
; irq_num
++)
1682 free_irq(irq_num
, priv
->ndev
);
1686 if (netif_msg_drv(priv
))
1687 dev_notice(emac_dev
, "DaVinci EMAC: %s stopped\n", ndev
->name
);
1693 * emac_dev_getnetstats: EMAC get statistics function
1694 * @ndev: The DaVinci EMAC network adapter
1696 * Called when system wants to get statistics from the device.
1698 * We return the statistics in net_device_stats structure pulled from emac
1700 static struct net_device_stats
*emac_dev_getnetstats(struct net_device
*ndev
)
1702 struct emac_priv
*priv
= netdev_priv(ndev
);
1704 u32 stats_clear_mask
;
1706 /* update emac hardware stats and reset the registers*/
1708 mac_control
= emac_read(EMAC_MACCONTROL
);
1710 if (mac_control
& EMAC_MACCONTROL_GMIIEN
)
1711 stats_clear_mask
= EMAC_STATS_CLR_MASK
;
1713 stats_clear_mask
= 0;
1715 ndev
->stats
.multicast
+= emac_read(EMAC_RXMCASTFRAMES
);
1716 emac_write(EMAC_RXMCASTFRAMES
, stats_clear_mask
);
1718 ndev
->stats
.collisions
+= (emac_read(EMAC_TXCOLLISION
) +
1719 emac_read(EMAC_TXSINGLECOLL
) +
1720 emac_read(EMAC_TXMULTICOLL
));
1721 emac_write(EMAC_TXCOLLISION
, stats_clear_mask
);
1722 emac_write(EMAC_TXSINGLECOLL
, stats_clear_mask
);
1723 emac_write(EMAC_TXMULTICOLL
, stats_clear_mask
);
1725 ndev
->stats
.rx_length_errors
+= (emac_read(EMAC_RXOVERSIZED
) +
1726 emac_read(EMAC_RXJABBER
) +
1727 emac_read(EMAC_RXUNDERSIZED
));
1728 emac_write(EMAC_RXOVERSIZED
, stats_clear_mask
);
1729 emac_write(EMAC_RXJABBER
, stats_clear_mask
);
1730 emac_write(EMAC_RXUNDERSIZED
, stats_clear_mask
);
1732 ndev
->stats
.rx_over_errors
+= (emac_read(EMAC_RXSOFOVERRUNS
) +
1733 emac_read(EMAC_RXMOFOVERRUNS
));
1734 emac_write(EMAC_RXSOFOVERRUNS
, stats_clear_mask
);
1735 emac_write(EMAC_RXMOFOVERRUNS
, stats_clear_mask
);
1737 ndev
->stats
.rx_fifo_errors
+= emac_read(EMAC_RXDMAOVERRUNS
);
1738 emac_write(EMAC_RXDMAOVERRUNS
, stats_clear_mask
);
1740 ndev
->stats
.tx_carrier_errors
+=
1741 emac_read(EMAC_TXCARRIERSENSE
);
1742 emac_write(EMAC_TXCARRIERSENSE
, stats_clear_mask
);
1744 ndev
->stats
.tx_fifo_errors
+= emac_read(EMAC_TXUNDERRUN
);
1745 emac_write(EMAC_TXUNDERRUN
, stats_clear_mask
);
1747 return &ndev
->stats
;
1750 static const struct net_device_ops emac_netdev_ops
= {
1751 .ndo_open
= emac_dev_open
,
1752 .ndo_stop
= emac_dev_stop
,
1753 .ndo_start_xmit
= emac_dev_xmit
,
1754 .ndo_set_rx_mode
= emac_dev_mcast_set
,
1755 .ndo_set_mac_address
= emac_dev_setmac_addr
,
1756 .ndo_do_ioctl
= emac_devioctl
,
1757 .ndo_tx_timeout
= emac_dev_tx_timeout
,
1758 .ndo_get_stats
= emac_dev_getnetstats
,
1759 #ifdef CONFIG_NET_POLL_CONTROLLER
1760 .ndo_poll_controller
= emac_poll_controller
,
1765 * davinci_emac_probe: EMAC device probe
1766 * @pdev: The DaVinci EMAC device that we are removing
1768 * Called when probing for emac devicesr. We get details of instances and
1769 * resource information from platform init and register a network device
1770 * and allocate resources necessary for driver to perform
1772 static int __devinit
davinci_emac_probe(struct platform_device
*pdev
)
1775 struct resource
*res
;
1776 struct net_device
*ndev
;
1777 struct emac_priv
*priv
;
1778 unsigned long size
, hw_ram_addr
;
1779 struct emac_platform_data
*pdata
;
1780 struct device
*emac_dev
;
1781 struct cpdma_params dma_params
;
1783 /* obtain emac clock from kernel */
1784 emac_clk
= clk_get(&pdev
->dev
, NULL
);
1785 if (IS_ERR(emac_clk
)) {
1786 dev_err(&pdev
->dev
, "failed to get EMAC clock\n");
1789 emac_bus_frequency
= clk_get_rate(emac_clk
);
1790 /* TODO: Probe PHY here if possible */
1792 ndev
= alloc_etherdev(sizeof(struct emac_priv
));
1798 platform_set_drvdata(pdev
, ndev
);
1799 priv
= netdev_priv(ndev
);
1802 priv
->msg_enable
= netif_msg_init(debug_level
, DAVINCI_EMAC_DEBUG
);
1804 spin_lock_init(&priv
->lock
);
1806 pdata
= pdev
->dev
.platform_data
;
1808 dev_err(&pdev
->dev
, "no platform data\n");
1813 /* MAC addr and PHY mask , RMII enable info from platform_data */
1814 memcpy(priv
->mac_addr
, pdata
->mac_addr
, 6);
1815 priv
->phy_id
= pdata
->phy_id
;
1816 priv
->rmii_en
= pdata
->rmii_en
;
1817 priv
->version
= pdata
->version
;
1818 priv
->int_enable
= pdata
->interrupt_enable
;
1819 priv
->int_disable
= pdata
->interrupt_disable
;
1821 priv
->coal_intvl
= 0;
1822 priv
->bus_freq_mhz
= (u32
)(emac_bus_frequency
/ 1000000);
1824 emac_dev
= &ndev
->dev
;
1825 /* Get EMAC platform data */
1826 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1828 dev_err(&pdev
->dev
,"error getting res\n");
1833 priv
->emac_base_phys
= res
->start
+ pdata
->ctrl_reg_offset
;
1834 size
= resource_size(res
);
1835 if (!request_mem_region(res
->start
, size
, ndev
->name
)) {
1836 dev_err(&pdev
->dev
, "failed request_mem_region() for regs\n");
1841 priv
->remap_addr
= ioremap(res
->start
, size
);
1842 if (!priv
->remap_addr
) {
1843 dev_err(&pdev
->dev
, "unable to map IO\n");
1845 release_mem_region(res
->start
, size
);
1848 priv
->emac_base
= priv
->remap_addr
+ pdata
->ctrl_reg_offset
;
1849 ndev
->base_addr
= (unsigned long)priv
->remap_addr
;
1851 priv
->ctrl_base
= priv
->remap_addr
+ pdata
->ctrl_mod_reg_offset
;
1853 hw_ram_addr
= pdata
->hw_ram_addr
;
1855 hw_ram_addr
= (u32 __force
)res
->start
+ pdata
->ctrl_ram_offset
;
1857 memset(&dma_params
, 0, sizeof(dma_params
));
1858 dma_params
.dev
= emac_dev
;
1859 dma_params
.dmaregs
= priv
->emac_base
;
1860 dma_params
.rxthresh
= priv
->emac_base
+ 0x120;
1861 dma_params
.rxfree
= priv
->emac_base
+ 0x140;
1862 dma_params
.txhdp
= priv
->emac_base
+ 0x600;
1863 dma_params
.rxhdp
= priv
->emac_base
+ 0x620;
1864 dma_params
.txcp
= priv
->emac_base
+ 0x640;
1865 dma_params
.rxcp
= priv
->emac_base
+ 0x660;
1866 dma_params
.num_chan
= EMAC_MAX_TXRX_CHANNELS
;
1867 dma_params
.min_packet_size
= EMAC_DEF_MIN_ETHPKTSIZE
;
1868 dma_params
.desc_hw_addr
= hw_ram_addr
;
1869 dma_params
.desc_mem_size
= pdata
->ctrl_ram_size
;
1870 dma_params
.desc_align
= 16;
1872 dma_params
.desc_mem_phys
= pdata
->no_bd_ram
? 0 :
1873 (u32 __force
)res
->start
+ pdata
->ctrl_ram_offset
;
1875 priv
->dma
= cpdma_ctlr_create(&dma_params
);
1877 dev_err(&pdev
->dev
, "error initializing DMA\n");
1882 priv
->txchan
= cpdma_chan_create(priv
->dma
, tx_chan_num(EMAC_DEF_TX_CH
),
1884 priv
->rxchan
= cpdma_chan_create(priv
->dma
, rx_chan_num(EMAC_DEF_RX_CH
),
1886 if (WARN_ON(!priv
->txchan
|| !priv
->rxchan
)) {
1891 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1893 dev_err(&pdev
->dev
, "error getting irq res\n");
1897 ndev
->irq
= res
->start
;
1899 if (!is_valid_ether_addr(priv
->mac_addr
)) {
1900 /* Use random MAC if none passed */
1901 eth_hw_addr_random(ndev
);
1902 memcpy(priv
->mac_addr
, ndev
->dev_addr
, ndev
->addr_len
);
1903 dev_warn(&pdev
->dev
, "using random MAC addr: %pM\n",
1907 ndev
->netdev_ops
= &emac_netdev_ops
;
1908 SET_ETHTOOL_OPS(ndev
, ðtool_ops
);
1909 netif_napi_add(ndev
, &priv
->napi
, emac_poll
, EMAC_POLL_WEIGHT
);
1911 clk_enable(emac_clk
);
1913 /* register the network device */
1914 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1915 rc
= register_netdev(ndev
);
1917 dev_err(&pdev
->dev
, "error in register_netdev\n");
1919 goto netdev_reg_err
;
1923 if (netif_msg_probe(priv
)) {
1924 dev_notice(emac_dev
, "DaVinci EMAC Probe found device "\
1925 "(regs: %p, irq: %d)\n",
1926 (void *)priv
->emac_base_phys
, ndev
->irq
);
1931 clk_disable(emac_clk
);
1934 cpdma_chan_destroy(priv
->txchan
);
1936 cpdma_chan_destroy(priv
->rxchan
);
1937 cpdma_ctlr_destroy(priv
->dma
);
1939 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1940 release_mem_region(res
->start
, resource_size(res
));
1941 iounmap(priv
->remap_addr
);
1951 * davinci_emac_remove: EMAC device remove
1952 * @pdev: The DaVinci EMAC device that we are removing
1954 * Called when removing the device driver. We disable clock usage and release
1955 * the resources taken up by the driver and unregister network device
1957 static int __devexit
davinci_emac_remove(struct platform_device
*pdev
)
1959 struct resource
*res
;
1960 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1961 struct emac_priv
*priv
= netdev_priv(ndev
);
1963 dev_notice(&ndev
->dev
, "DaVinci EMAC: davinci_emac_remove()\n");
1965 platform_set_drvdata(pdev
, NULL
);
1966 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1969 cpdma_chan_destroy(priv
->txchan
);
1971 cpdma_chan_destroy(priv
->rxchan
);
1972 cpdma_ctlr_destroy(priv
->dma
);
1974 release_mem_region(res
->start
, resource_size(res
));
1976 unregister_netdev(ndev
);
1977 iounmap(priv
->remap_addr
);
1980 clk_disable(emac_clk
);
1986 static int davinci_emac_suspend(struct device
*dev
)
1988 struct platform_device
*pdev
= to_platform_device(dev
);
1989 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1991 if (netif_running(ndev
))
1992 emac_dev_stop(ndev
);
1994 clk_disable(emac_clk
);
1999 static int davinci_emac_resume(struct device
*dev
)
2001 struct platform_device
*pdev
= to_platform_device(dev
);
2002 struct net_device
*ndev
= platform_get_drvdata(pdev
);
2004 clk_enable(emac_clk
);
2006 if (netif_running(ndev
))
2007 emac_dev_open(ndev
);
2012 static const struct dev_pm_ops davinci_emac_pm_ops
= {
2013 .suspend
= davinci_emac_suspend
,
2014 .resume
= davinci_emac_resume
,
2018 * davinci_emac_driver: EMAC platform driver structure
2020 static struct platform_driver davinci_emac_driver
= {
2022 .name
= "davinci_emac",
2023 .owner
= THIS_MODULE
,
2024 .pm
= &davinci_emac_pm_ops
,
2026 .probe
= davinci_emac_probe
,
2027 .remove
= __devexit_p(davinci_emac_remove
),
2031 * davinci_emac_init: EMAC driver module init
2033 * Called when initializing the driver. We register the driver with
2036 static int __init
davinci_emac_init(void)
2038 return platform_driver_register(&davinci_emac_driver
);
2040 late_initcall(davinci_emac_init
);
2043 * davinci_emac_exit: EMAC driver module exit
2045 * Called when exiting the driver completely. We unregister the driver with
2046 * the platform and exit
2048 static void __exit
davinci_emac_exit(void)
2050 platform_driver_unregister(&davinci_emac_driver
);
2052 module_exit(davinci_emac_exit
);
2054 MODULE_LICENSE("GPL");
2055 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2056 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2057 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");