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[deliverable/linux.git] / drivers / net / ethernet / ti / davinci_mdio.c
1 /*
2 * DaVinci MDIO Module driver
3 *
4 * Copyright (C) 2010 Texas Instruments.
5 *
6 * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
7 *
8 * Copyright (C) 2009 Texas Instruments.
9 *
10 * ---------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ---------------------------------------------------------------------------
26 */
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/platform_device.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <linux/phy.h>
34 #include <linux/clk.h>
35 #include <linux/err.h>
36 #include <linux/io.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/davinci_emac.h>
39 #include <linux/of.h>
40 #include <linux/of_device.h>
41 #include <linux/of_mdio.h>
42 #include <linux/pinctrl/consumer.h>
43
44 /*
45 * This timeout definition is a worst-case ultra defensive measure against
46 * unexpected controller lock ups. Ideally, we should never ever hit this
47 * scenario in practice.
48 */
49 #define MDIO_TIMEOUT 100 /* msecs */
50
51 #define PHY_REG_MASK 0x1f
52 #define PHY_ID_MASK 0x1f
53
54 #define DEF_OUT_FREQ 2200000 /* 2.2 MHz */
55
56 struct davinci_mdio_regs {
57 u32 version;
58 u32 control;
59 #define CONTROL_IDLE BIT(31)
60 #define CONTROL_ENABLE BIT(30)
61 #define CONTROL_MAX_DIV (0xffff)
62
63 u32 alive;
64 u32 link;
65 u32 linkintraw;
66 u32 linkintmasked;
67 u32 __reserved_0[2];
68 u32 userintraw;
69 u32 userintmasked;
70 u32 userintmaskset;
71 u32 userintmaskclr;
72 u32 __reserved_1[20];
73
74 struct {
75 u32 access;
76 #define USERACCESS_GO BIT(31)
77 #define USERACCESS_WRITE BIT(30)
78 #define USERACCESS_ACK BIT(29)
79 #define USERACCESS_READ (0)
80 #define USERACCESS_DATA (0xffff)
81
82 u32 physel;
83 } user[0];
84 };
85
86 static const struct mdio_platform_data default_pdata = {
87 .bus_freq = DEF_OUT_FREQ,
88 };
89
90 struct davinci_mdio_data {
91 struct mdio_platform_data pdata;
92 struct davinci_mdio_regs __iomem *regs;
93 struct clk *clk;
94 struct device *dev;
95 struct mii_bus *bus;
96 unsigned long access_time; /* jiffies */
97 /* Indicates that driver shouldn't modify phy_mask in case
98 * if MDIO bus is registered from DT.
99 */
100 bool skip_scan;
101 };
102
103 static void __davinci_mdio_reset(struct davinci_mdio_data *data)
104 {
105 u32 mdio_in, div, mdio_out_khz, access_time;
106
107 mdio_in = clk_get_rate(data->clk);
108 div = (mdio_in / data->pdata.bus_freq) - 1;
109 if (div > CONTROL_MAX_DIV)
110 div = CONTROL_MAX_DIV;
111
112 /* set enable and clock divider */
113 __raw_writel(div | CONTROL_ENABLE, &data->regs->control);
114
115 /*
116 * One mdio transaction consists of:
117 * 32 bits of preamble
118 * 32 bits of transferred data
119 * 24 bits of bus yield (not needed unless shared?)
120 */
121 mdio_out_khz = mdio_in / (1000 * (div + 1));
122 access_time = (88 * 1000) / mdio_out_khz;
123
124 /*
125 * In the worst case, we could be kicking off a user-access immediately
126 * after the mdio bus scan state-machine triggered its own read. If
127 * so, our request could get deferred by one access cycle. We
128 * defensively allow for 4 access cycles.
129 */
130 data->access_time = usecs_to_jiffies(access_time * 4);
131 if (!data->access_time)
132 data->access_time = 1;
133 }
134
135 static int davinci_mdio_reset(struct mii_bus *bus)
136 {
137 struct davinci_mdio_data *data = bus->priv;
138 u32 phy_mask, ver;
139
140 __davinci_mdio_reset(data);
141
142 /* wait for scan logic to settle */
143 msleep(PHY_MAX_ADDR * data->access_time);
144
145 /* dump hardware version info */
146 ver = __raw_readl(&data->regs->version);
147 dev_info(data->dev, "davinci mdio revision %d.%d\n",
148 (ver >> 8) & 0xff, ver & 0xff);
149
150 if (data->skip_scan)
151 return 0;
152
153 /* get phy mask from the alive register */
154 phy_mask = __raw_readl(&data->regs->alive);
155 if (phy_mask) {
156 /* restrict mdio bus to live phys only */
157 dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
158 phy_mask = ~phy_mask;
159 } else {
160 /* desperately scan all phys */
161 dev_warn(data->dev, "no live phy, scanning all\n");
162 phy_mask = 0;
163 }
164 data->bus->phy_mask = phy_mask;
165
166 return 0;
167 }
168
169 /* wait until hardware is ready for another user access */
170 static inline int wait_for_user_access(struct davinci_mdio_data *data)
171 {
172 struct davinci_mdio_regs __iomem *regs = data->regs;
173 unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
174 u32 reg;
175
176 while (time_after(timeout, jiffies)) {
177 reg = __raw_readl(&regs->user[0].access);
178 if ((reg & USERACCESS_GO) == 0)
179 return 0;
180
181 reg = __raw_readl(&regs->control);
182 if ((reg & CONTROL_IDLE) == 0)
183 continue;
184
185 /*
186 * An emac soft_reset may have clobbered the mdio controller's
187 * state machine. We need to reset and retry the current
188 * operation
189 */
190 dev_warn(data->dev, "resetting idled controller\n");
191 __davinci_mdio_reset(data);
192 return -EAGAIN;
193 }
194
195 reg = __raw_readl(&regs->user[0].access);
196 if ((reg & USERACCESS_GO) == 0)
197 return 0;
198
199 dev_err(data->dev, "timed out waiting for user access\n");
200 return -ETIMEDOUT;
201 }
202
203 /* wait until hardware state machine is idle */
204 static inline int wait_for_idle(struct davinci_mdio_data *data)
205 {
206 struct davinci_mdio_regs __iomem *regs = data->regs;
207 unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
208
209 while (time_after(timeout, jiffies)) {
210 if (__raw_readl(&regs->control) & CONTROL_IDLE)
211 return 0;
212 }
213 dev_err(data->dev, "timed out waiting for idle\n");
214 return -ETIMEDOUT;
215 }
216
217 static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
218 {
219 struct davinci_mdio_data *data = bus->priv;
220 u32 reg;
221 int ret;
222
223 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
224 return -EINVAL;
225
226 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
227 (phy_id << 16));
228
229 while (1) {
230 ret = wait_for_user_access(data);
231 if (ret == -EAGAIN)
232 continue;
233 if (ret < 0)
234 break;
235
236 __raw_writel(reg, &data->regs->user[0].access);
237
238 ret = wait_for_user_access(data);
239 if (ret == -EAGAIN)
240 continue;
241 if (ret < 0)
242 break;
243
244 reg = __raw_readl(&data->regs->user[0].access);
245 ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
246 break;
247 }
248
249 return ret;
250 }
251
252 static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
253 int phy_reg, u16 phy_data)
254 {
255 struct davinci_mdio_data *data = bus->priv;
256 u32 reg;
257 int ret;
258
259 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
260 return -EINVAL;
261
262 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
263 (phy_id << 16) | (phy_data & USERACCESS_DATA));
264
265 while (1) {
266 ret = wait_for_user_access(data);
267 if (ret == -EAGAIN)
268 continue;
269 if (ret < 0)
270 break;
271
272 __raw_writel(reg, &data->regs->user[0].access);
273
274 ret = wait_for_user_access(data);
275 if (ret == -EAGAIN)
276 continue;
277 break;
278 }
279
280 return 0;
281 }
282
283 #if IS_ENABLED(CONFIG_OF)
284 static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
285 struct platform_device *pdev)
286 {
287 struct device_node *node = pdev->dev.of_node;
288 u32 prop;
289
290 if (!node)
291 return -EINVAL;
292
293 if (of_property_read_u32(node, "bus_freq", &prop)) {
294 dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n");
295 return -EINVAL;
296 }
297 data->bus_freq = prop;
298
299 return 0;
300 }
301 #endif
302
303 static int davinci_mdio_probe(struct platform_device *pdev)
304 {
305 struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
306 struct device *dev = &pdev->dev;
307 struct davinci_mdio_data *data;
308 struct resource *res;
309 struct phy_device *phy;
310 int ret, addr;
311
312 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
313 if (!data)
314 return -ENOMEM;
315
316 data->bus = devm_mdiobus_alloc(dev);
317 if (!data->bus) {
318 dev_err(dev, "failed to alloc mii bus\n");
319 return -ENOMEM;
320 }
321
322 if (dev->of_node) {
323 if (davinci_mdio_probe_dt(&data->pdata, pdev))
324 data->pdata = default_pdata;
325 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
326 } else {
327 data->pdata = pdata ? (*pdata) : default_pdata;
328 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
329 pdev->name, pdev->id);
330 }
331
332 data->bus->name = dev_name(dev);
333 data->bus->read = davinci_mdio_read,
334 data->bus->write = davinci_mdio_write,
335 data->bus->reset = davinci_mdio_reset,
336 data->bus->parent = dev;
337 data->bus->priv = data;
338
339 data->clk = devm_clk_get(dev, "fck");
340 if (IS_ERR(data->clk)) {
341 dev_err(dev, "failed to get device clock\n");
342 return PTR_ERR(data->clk);
343 }
344
345 dev_set_drvdata(dev, data);
346 data->dev = dev;
347
348 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
349 data->regs = devm_ioremap_resource(dev, res);
350 if (IS_ERR(data->regs))
351 return PTR_ERR(data->regs);
352
353 pm_runtime_enable(&pdev->dev);
354 pm_runtime_get_sync(&pdev->dev);
355
356 /* register the mii bus
357 * Create PHYs from DT only in case if PHY child nodes are explicitly
358 * defined to support backward compatibility with DTs which assume that
359 * Davinci MDIO will always scan the bus for PHYs detection.
360 */
361 if (dev->of_node && of_get_child_count(dev->of_node)) {
362 data->skip_scan = true;
363 ret = of_mdiobus_register(data->bus, dev->of_node);
364 } else {
365 ret = mdiobus_register(data->bus);
366 }
367 if (ret)
368 goto bail_out;
369
370 /* scan and dump the bus */
371 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
372 phy = mdiobus_get_phy(data->bus, addr);
373 if (phy) {
374 dev_info(dev, "phy[%d]: device %s, driver %s\n",
375 phy->mdio.addr, phydev_name(phy),
376 phy->drv ? phy->drv->name : "unknown");
377 }
378 }
379
380 return 0;
381
382 bail_out:
383 pm_runtime_put_sync(&pdev->dev);
384 pm_runtime_disable(&pdev->dev);
385
386 return ret;
387 }
388
389 static int davinci_mdio_remove(struct platform_device *pdev)
390 {
391 struct davinci_mdio_data *data = platform_get_drvdata(pdev);
392
393 if (data->bus)
394 mdiobus_unregister(data->bus);
395
396 pm_runtime_put_sync(&pdev->dev);
397 pm_runtime_disable(&pdev->dev);
398
399 return 0;
400 }
401
402 #ifdef CONFIG_PM_SLEEP
403 static int davinci_mdio_suspend(struct device *dev)
404 {
405 struct davinci_mdio_data *data = dev_get_drvdata(dev);
406 u32 ctrl;
407
408 /* shutdown the scan state machine */
409 ctrl = __raw_readl(&data->regs->control);
410 ctrl &= ~CONTROL_ENABLE;
411 __raw_writel(ctrl, &data->regs->control);
412 wait_for_idle(data);
413
414 /* Select sleep pin state */
415 pinctrl_pm_select_sleep_state(dev);
416
417 return 0;
418 }
419
420 static int davinci_mdio_resume(struct device *dev)
421 {
422 struct davinci_mdio_data *data = dev_get_drvdata(dev);
423
424 /* Select default pin state */
425 pinctrl_pm_select_default_state(dev);
426
427 /* restart the scan state machine */
428 __davinci_mdio_reset(data);
429
430 return 0;
431 }
432 #endif
433
434 static const struct dev_pm_ops davinci_mdio_pm_ops = {
435 SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume)
436 };
437
438 #if IS_ENABLED(CONFIG_OF)
439 static const struct of_device_id davinci_mdio_of_mtable[] = {
440 { .compatible = "ti,davinci_mdio", },
441 { /* sentinel */ },
442 };
443 MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
444 #endif
445
446 static struct platform_driver davinci_mdio_driver = {
447 .driver = {
448 .name = "davinci_mdio",
449 .pm = &davinci_mdio_pm_ops,
450 .of_match_table = of_match_ptr(davinci_mdio_of_mtable),
451 },
452 .probe = davinci_mdio_probe,
453 .remove = davinci_mdio_remove,
454 };
455
456 static int __init davinci_mdio_init(void)
457 {
458 return platform_driver_register(&davinci_mdio_driver);
459 }
460 device_initcall(davinci_mdio_init);
461
462 static void __exit davinci_mdio_exit(void)
463 {
464 platform_driver_unregister(&davinci_mdio_driver);
465 }
466 module_exit(davinci_mdio_exit);
467
468 MODULE_LICENSE("GPL");
469 MODULE_DESCRIPTION("DaVinci MDIO driver");
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