5d2a719fc68824c3b77ee5519406f4f9df31d42f
[deliverable/linux.git] / drivers / net / ethernet / tile / tilegx.c
1 /*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/moduleparam.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h> /* printk() */
20 #include <linux/slab.h> /* kmalloc() */
21 #include <linux/errno.h> /* error codes */
22 #include <linux/types.h> /* size_t */
23 #include <linux/interrupt.h>
24 #include <linux/in.h>
25 #include <linux/irq.h>
26 #include <linux/netdevice.h> /* struct device, and other headers */
27 #include <linux/etherdevice.h> /* eth_type_trans */
28 #include <linux/skbuff.h>
29 #include <linux/ioctl.h>
30 #include <linux/cdev.h>
31 #include <linux/hugetlb.h>
32 #include <linux/in6.h>
33 #include <linux/timer.h>
34 #include <linux/hrtimer.h>
35 #include <linux/ktime.h>
36 #include <linux/io.h>
37 #include <linux/ctype.h>
38 #include <linux/ip.h>
39 #include <linux/ipv6.h>
40 #include <linux/tcp.h>
41 #include <linux/net_tstamp.h>
42 #include <linux/ptp_clock_kernel.h>
43
44 #include <asm/checksum.h>
45 #include <asm/homecache.h>
46 #include <gxio/mpipe.h>
47 #include <arch/sim.h>
48
49 /* Default transmit lockup timeout period, in jiffies. */
50 #define TILE_NET_TIMEOUT (5 * HZ)
51
52 /* The maximum number of distinct channels (idesc.channel is 5 bits). */
53 #define TILE_NET_CHANNELS 32
54
55 /* Maximum number of idescs to handle per "poll". */
56 #define TILE_NET_BATCH 128
57
58 /* Maximum number of packets to handle per "poll". */
59 #define TILE_NET_WEIGHT 64
60
61 /* Number of entries in each iqueue. */
62 #define IQUEUE_ENTRIES 512
63
64 /* Number of entries in each equeue. */
65 #define EQUEUE_ENTRIES 2048
66
67 /* Total header bytes per equeue slot. Must be big enough for 2 bytes
68 * of NET_IP_ALIGN alignment, plus 14 bytes (?) of L2 header, plus up to
69 * 60 bytes of actual TCP header. We round up to align to cache lines.
70 */
71 #define HEADER_BYTES 128
72
73 /* Maximum completions per cpu per device (must be a power of two).
74 * ISSUE: What is the right number here? If this is too small, then
75 * egress might block waiting for free space in a completions array.
76 * ISSUE: At the least, allocate these only for initialized echannels.
77 */
78 #define TILE_NET_MAX_COMPS 64
79
80 #define MAX_FRAGS (MAX_SKB_FRAGS + 1)
81
82 /* The "kinds" of buffer stacks (small/large/jumbo). */
83 #define MAX_KINDS 3
84
85 /* Size of completions data to allocate.
86 * ISSUE: Probably more than needed since we don't use all the channels.
87 */
88 #define COMPS_SIZE (TILE_NET_CHANNELS * sizeof(struct tile_net_comps))
89
90 /* Size of NotifRing data to allocate. */
91 #define NOTIF_RING_SIZE (IQUEUE_ENTRIES * sizeof(gxio_mpipe_idesc_t))
92
93 /* Timeout to wake the per-device TX timer after we stop the queue.
94 * We don't want the timeout too short (adds overhead, and might end
95 * up causing stop/wake/stop/wake cycles) or too long (affects performance).
96 * For the 10 Gb NIC, 30 usec means roughly 30+ 1500-byte packets.
97 */
98 #define TX_TIMER_DELAY_USEC 30
99
100 /* Timeout to wake the per-cpu egress timer to free completions. */
101 #define EGRESS_TIMER_DELAY_USEC 1000
102
103 MODULE_AUTHOR("Tilera Corporation");
104 MODULE_LICENSE("GPL");
105
106 /* A "packet fragment" (a chunk of memory). */
107 struct frag {
108 void *buf;
109 size_t length;
110 };
111
112 /* A single completion. */
113 struct tile_net_comp {
114 /* The "complete_count" when the completion will be complete. */
115 s64 when;
116 /* The buffer to be freed when the completion is complete. */
117 struct sk_buff *skb;
118 };
119
120 /* The completions for a given cpu and echannel. */
121 struct tile_net_comps {
122 /* The completions. */
123 struct tile_net_comp comp_queue[TILE_NET_MAX_COMPS];
124 /* The number of completions used. */
125 unsigned long comp_next;
126 /* The number of completions freed. */
127 unsigned long comp_last;
128 };
129
130 /* The transmit wake timer for a given cpu and echannel. */
131 struct tile_net_tx_wake {
132 int tx_queue_idx;
133 struct hrtimer timer;
134 struct net_device *dev;
135 };
136
137 /* Info for a specific cpu. */
138 struct tile_net_info {
139 /* Our cpu. */
140 int my_cpu;
141 /* A timer for handling egress completions. */
142 struct hrtimer egress_timer;
143 /* True if "egress_timer" is scheduled. */
144 bool egress_timer_scheduled;
145 struct info_mpipe {
146 /* Packet queue. */
147 gxio_mpipe_iqueue_t iqueue;
148 /* The NAPI struct. */
149 struct napi_struct napi;
150 /* Number of buffers (by kind) which must still be provided. */
151 unsigned int num_needed_buffers[MAX_KINDS];
152 /* instance id. */
153 int instance;
154 /* True if iqueue is valid. */
155 bool has_iqueue;
156 /* NAPI flags. */
157 bool napi_added;
158 bool napi_enabled;
159 /* Comps for each egress channel. */
160 struct tile_net_comps *comps_for_echannel[TILE_NET_CHANNELS];
161 /* Transmit wake timer for each egress channel. */
162 struct tile_net_tx_wake tx_wake[TILE_NET_CHANNELS];
163 } mpipe[NR_MPIPE_MAX];
164 };
165
166 /* Info for egress on a particular egress channel. */
167 struct tile_net_egress {
168 /* The "equeue". */
169 gxio_mpipe_equeue_t *equeue;
170 /* The headers for TSO. */
171 unsigned char *headers;
172 };
173
174 /* Info for a specific device. */
175 struct tile_net_priv {
176 /* Our network device. */
177 struct net_device *dev;
178 /* The primary link. */
179 gxio_mpipe_link_t link;
180 /* The primary channel, if open, else -1. */
181 int channel;
182 /* The "loopify" egress link, if needed. */
183 gxio_mpipe_link_t loopify_link;
184 /* The "loopify" egress channel, if open, else -1. */
185 int loopify_channel;
186 /* The egress channel (channel or loopify_channel). */
187 int echannel;
188 /* mPIPE instance, 0 or 1. */
189 int instance;
190 #ifdef CONFIG_PTP_1588_CLOCK_TILEGX
191 /* The timestamp config. */
192 struct hwtstamp_config stamp_cfg;
193 #endif
194 };
195
196 static struct mpipe_data {
197 /* The ingress irq. */
198 int ingress_irq;
199
200 /* The "context" for all devices. */
201 gxio_mpipe_context_t context;
202
203 /* Egress info, indexed by "priv->echannel"
204 * (lazily created as needed).
205 */
206 struct tile_net_egress
207 egress_for_echannel[TILE_NET_CHANNELS];
208
209 /* Devices currently associated with each channel.
210 * NOTE: The array entry can become NULL after ifconfig down, but
211 * we do not free the underlying net_device structures, so it is
212 * safe to use a pointer after reading it from this array.
213 */
214 struct net_device
215 *tile_net_devs_for_channel[TILE_NET_CHANNELS];
216
217 /* The actual memory allocated for the buffer stacks. */
218 void *buffer_stack_vas[MAX_KINDS];
219
220 /* The amount of memory allocated for each buffer stack. */
221 size_t buffer_stack_bytes[MAX_KINDS];
222
223 /* The first buffer stack index
224 * (small = +0, large = +1, jumbo = +2).
225 */
226 int first_buffer_stack;
227
228 /* The buckets. */
229 int first_bucket;
230 int num_buckets;
231
232 #ifdef CONFIG_PTP_1588_CLOCK_TILEGX
233 /* PTP-specific data. */
234 struct ptp_clock *ptp_clock;
235 struct ptp_clock_info caps;
236
237 /* Lock for ptp accessors. */
238 struct mutex ptp_lock;
239 #endif
240
241 } mpipe_data[NR_MPIPE_MAX] = {
242 [0 ... (NR_MPIPE_MAX - 1)] {
243 .ingress_irq = -1,
244 .first_buffer_stack = -1,
245 .first_bucket = -1,
246 .num_buckets = 1
247 }
248 };
249
250 /* A mutex for "tile_net_devs_for_channel". */
251 static DEFINE_MUTEX(tile_net_devs_for_channel_mutex);
252
253 /* The per-cpu info. */
254 static DEFINE_PER_CPU(struct tile_net_info, per_cpu_info);
255
256
257 /* The buffer size enums for each buffer stack.
258 * See arch/tile/include/gxio/mpipe.h for the set of possible values.
259 * We avoid the "10384" size because it can induce "false chaining"
260 * on "cut-through" jumbo packets.
261 */
262 static gxio_mpipe_buffer_size_enum_t buffer_size_enums[MAX_KINDS] = {
263 GXIO_MPIPE_BUFFER_SIZE_128,
264 GXIO_MPIPE_BUFFER_SIZE_1664,
265 GXIO_MPIPE_BUFFER_SIZE_16384
266 };
267
268 /* Text value of tile_net.cpus if passed as a module parameter. */
269 static char *network_cpus_string;
270
271 /* The actual cpus in "network_cpus". */
272 static struct cpumask network_cpus_map;
273
274 /* If "tile_net.loopify=LINK" was specified, this is "LINK". */
275 static char *loopify_link_name;
276
277 /* If "tile_net.custom" was specified, this is true. */
278 static bool custom_flag;
279
280 /* If "tile_net.jumbo=NUM" was specified, this is "NUM". */
281 static uint jumbo_num;
282
283 /* Obtain mpipe instance from struct tile_net_priv given struct net_device. */
284 static inline int mpipe_instance(struct net_device *dev)
285 {
286 struct tile_net_priv *priv = netdev_priv(dev);
287 return priv->instance;
288 }
289
290 /* The "tile_net.cpus" argument specifies the cpus that are dedicated
291 * to handle ingress packets.
292 *
293 * The parameter should be in the form "tile_net.cpus=m-n[,x-y]", where
294 * m, n, x, y are integer numbers that represent the cpus that can be
295 * neither a dedicated cpu nor a dataplane cpu.
296 */
297 static bool network_cpus_init(void)
298 {
299 char buf[1024];
300 int rc;
301
302 if (network_cpus_string == NULL)
303 return false;
304
305 rc = cpulist_parse_crop(network_cpus_string, &network_cpus_map);
306 if (rc != 0) {
307 pr_warn("tile_net.cpus=%s: malformed cpu list\n",
308 network_cpus_string);
309 return false;
310 }
311
312 /* Remove dedicated cpus. */
313 cpumask_and(&network_cpus_map, &network_cpus_map, cpu_possible_mask);
314
315 if (cpumask_empty(&network_cpus_map)) {
316 pr_warn("Ignoring empty tile_net.cpus='%s'.\n",
317 network_cpus_string);
318 return false;
319 }
320
321 cpulist_scnprintf(buf, sizeof(buf), &network_cpus_map);
322 pr_info("Linux network CPUs: %s\n", buf);
323 return true;
324 }
325
326 module_param_named(cpus, network_cpus_string, charp, 0444);
327 MODULE_PARM_DESC(cpus, "cpulist of cores that handle network interrupts");
328
329 /* The "tile_net.loopify=LINK" argument causes the named device to
330 * actually use "loop0" for ingress, and "loop1" for egress. This
331 * allows an app to sit between the actual link and linux, passing
332 * (some) packets along to linux, and forwarding (some) packets sent
333 * out by linux.
334 */
335 module_param_named(loopify, loopify_link_name, charp, 0444);
336 MODULE_PARM_DESC(loopify, "name the device to use loop0/1 for ingress/egress");
337
338 /* The "tile_net.custom" argument causes us to ignore the "conventional"
339 * classifier metadata, in particular, the "l2_offset".
340 */
341 module_param_named(custom, custom_flag, bool, 0444);
342 MODULE_PARM_DESC(custom, "indicates a (heavily) customized classifier");
343
344 /* The "tile_net.jumbo" argument causes us to support "jumbo" packets,
345 * and to allocate the given number of "jumbo" buffers.
346 */
347 module_param_named(jumbo, jumbo_num, uint, 0444);
348 MODULE_PARM_DESC(jumbo, "the number of buffers to support jumbo packets");
349
350 /* Atomically update a statistics field.
351 * Note that on TILE-Gx, this operation is fire-and-forget on the
352 * issuing core (single-cycle dispatch) and takes only a few cycles
353 * longer than a regular store when the request reaches the home cache.
354 * No expensive bus management overhead is required.
355 */
356 static void tile_net_stats_add(unsigned long value, unsigned long *field)
357 {
358 BUILD_BUG_ON(sizeof(atomic_long_t) != sizeof(unsigned long));
359 atomic_long_add(value, (atomic_long_t *)field);
360 }
361
362 /* Allocate and push a buffer. */
363 static bool tile_net_provide_buffer(int instance, int kind)
364 {
365 struct mpipe_data *md = &mpipe_data[instance];
366 gxio_mpipe_buffer_size_enum_t bse = buffer_size_enums[kind];
367 size_t bs = gxio_mpipe_buffer_size_enum_to_buffer_size(bse);
368 const unsigned long buffer_alignment = 128;
369 struct sk_buff *skb;
370 int len;
371
372 len = sizeof(struct sk_buff **) + buffer_alignment + bs;
373 skb = dev_alloc_skb(len);
374 if (skb == NULL)
375 return false;
376
377 /* Make room for a back-pointer to 'skb' and guarantee alignment. */
378 skb_reserve(skb, sizeof(struct sk_buff **));
379 skb_reserve(skb, -(long)skb->data & (buffer_alignment - 1));
380
381 /* Save a back-pointer to 'skb'. */
382 *(struct sk_buff **)(skb->data - sizeof(struct sk_buff **)) = skb;
383
384 /* Make sure "skb" and the back-pointer have been flushed. */
385 wmb();
386
387 gxio_mpipe_push_buffer(&md->context, md->first_buffer_stack + kind,
388 (void *)va_to_tile_io_addr(skb->data));
389
390 return true;
391 }
392
393 /* Convert a raw mpipe buffer to its matching skb pointer. */
394 static struct sk_buff *mpipe_buf_to_skb(void *va)
395 {
396 /* Acquire the associated "skb". */
397 struct sk_buff **skb_ptr = va - sizeof(*skb_ptr);
398 struct sk_buff *skb = *skb_ptr;
399
400 /* Paranoia. */
401 if (skb->data != va) {
402 /* Panic here since there's a reasonable chance
403 * that corrupt buffers means generic memory
404 * corruption, with unpredictable system effects.
405 */
406 panic("Corrupt linux buffer! va=%p, skb=%p, skb->data=%p",
407 va, skb, skb->data);
408 }
409
410 return skb;
411 }
412
413 static void tile_net_pop_all_buffers(int instance, int stack)
414 {
415 struct mpipe_data *md = &mpipe_data[instance];
416
417 for (;;) {
418 tile_io_addr_t addr =
419 (tile_io_addr_t)gxio_mpipe_pop_buffer(&md->context,
420 stack);
421 if (addr == 0)
422 break;
423 dev_kfree_skb_irq(mpipe_buf_to_skb(tile_io_addr_to_va(addr)));
424 }
425 }
426
427 /* Provide linux buffers to mPIPE. */
428 static void tile_net_provide_needed_buffers(void)
429 {
430 struct tile_net_info *info = &__get_cpu_var(per_cpu_info);
431 int instance, kind;
432 for (instance = 0; instance < NR_MPIPE_MAX &&
433 info->mpipe[instance].has_iqueue; instance++) {
434 for (kind = 0; kind < MAX_KINDS; kind++) {
435 while (info->mpipe[instance].num_needed_buffers[kind]
436 != 0) {
437 if (!tile_net_provide_buffer(instance, kind)) {
438 pr_notice("Tile %d still needs"
439 " some buffers\n",
440 info->my_cpu);
441 return;
442 }
443 info->mpipe[instance].
444 num_needed_buffers[kind]--;
445 }
446 }
447 }
448 }
449
450 /* Get RX timestamp, and store it in the skb. */
451 static void tile_rx_timestamp(struct tile_net_priv *priv, struct sk_buff *skb,
452 gxio_mpipe_idesc_t *idesc)
453 {
454 #ifdef CONFIG_PTP_1588_CLOCK_TILEGX
455 if (unlikely(priv->stamp_cfg.rx_filter != HWTSTAMP_FILTER_NONE)) {
456 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
457 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
458 shhwtstamps->hwtstamp = ktime_set(idesc->time_stamp_sec,
459 idesc->time_stamp_ns);
460 }
461 #endif
462 }
463
464 /* Get TX timestamp, and store it in the skb. */
465 static void tile_tx_timestamp(struct sk_buff *skb, int instance)
466 {
467 #ifdef CONFIG_PTP_1588_CLOCK_TILEGX
468 struct skb_shared_info *shtx = skb_shinfo(skb);
469 if (unlikely((shtx->tx_flags & SKBTX_HW_TSTAMP) != 0)) {
470 struct mpipe_data *md = &mpipe_data[instance];
471 struct skb_shared_hwtstamps shhwtstamps;
472 struct timespec ts;
473
474 shtx->tx_flags |= SKBTX_IN_PROGRESS;
475 gxio_mpipe_get_timestamp(&md->context, &ts);
476 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
477 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
478 skb_tstamp_tx(skb, &shhwtstamps);
479 }
480 #endif
481 }
482
483 /* Use ioctl() to enable or disable TX or RX timestamping. */
484 static int tile_hwtstamp_ioctl(struct net_device *dev, struct ifreq *rq,
485 int cmd)
486 {
487 #ifdef CONFIG_PTP_1588_CLOCK_TILEGX
488 struct hwtstamp_config config;
489 struct tile_net_priv *priv = netdev_priv(dev);
490
491 if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
492 return -EFAULT;
493
494 if (config.flags) /* reserved for future extensions */
495 return -EINVAL;
496
497 switch (config.tx_type) {
498 case HWTSTAMP_TX_OFF:
499 case HWTSTAMP_TX_ON:
500 break;
501 default:
502 return -ERANGE;
503 }
504
505 switch (config.rx_filter) {
506 case HWTSTAMP_FILTER_NONE:
507 break;
508 case HWTSTAMP_FILTER_ALL:
509 case HWTSTAMP_FILTER_SOME:
510 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
511 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
512 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
513 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
514 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
515 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
516 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
517 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
518 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
519 case HWTSTAMP_FILTER_PTP_V2_EVENT:
520 case HWTSTAMP_FILTER_PTP_V2_SYNC:
521 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
522 config.rx_filter = HWTSTAMP_FILTER_ALL;
523 break;
524 default:
525 return -ERANGE;
526 }
527
528 if (copy_to_user(rq->ifr_data, &config, sizeof(config)))
529 return -EFAULT;
530
531 priv->stamp_cfg = config;
532 return 0;
533 #else
534 return -EOPNOTSUPP;
535 #endif
536 }
537
538 static inline bool filter_packet(struct net_device *dev, void *buf)
539 {
540 /* Filter packets received before we're up. */
541 if (dev == NULL || !(dev->flags & IFF_UP))
542 return true;
543
544 /* Filter out packets that aren't for us. */
545 if (!(dev->flags & IFF_PROMISC) &&
546 !is_multicast_ether_addr(buf) &&
547 compare_ether_addr(dev->dev_addr, buf) != 0)
548 return true;
549
550 return false;
551 }
552
553 static void tile_net_receive_skb(struct net_device *dev, struct sk_buff *skb,
554 gxio_mpipe_idesc_t *idesc, unsigned long len)
555 {
556 struct tile_net_info *info = &__get_cpu_var(per_cpu_info);
557 struct tile_net_priv *priv = netdev_priv(dev);
558 int instance = priv->instance;
559
560 /* Encode the actual packet length. */
561 skb_put(skb, len);
562
563 skb->protocol = eth_type_trans(skb, dev);
564
565 /* Acknowledge "good" hardware checksums. */
566 if (idesc->cs && idesc->csum_seed_val == 0xFFFF)
567 skb->ip_summed = CHECKSUM_UNNECESSARY;
568
569 /* Get RX timestamp from idesc. */
570 tile_rx_timestamp(priv, skb, idesc);
571
572 napi_gro_receive(&info->mpipe[instance].napi, skb);
573
574 /* Update stats. */
575 tile_net_stats_add(1, &dev->stats.rx_packets);
576 tile_net_stats_add(len, &dev->stats.rx_bytes);
577
578 /* Need a new buffer. */
579 if (idesc->size == buffer_size_enums[0])
580 info->mpipe[instance].num_needed_buffers[0]++;
581 else if (idesc->size == buffer_size_enums[1])
582 info->mpipe[instance].num_needed_buffers[1]++;
583 else
584 info->mpipe[instance].num_needed_buffers[2]++;
585 }
586
587 /* Handle a packet. Return true if "processed", false if "filtered". */
588 static bool tile_net_handle_packet(int instance, gxio_mpipe_idesc_t *idesc)
589 {
590 struct tile_net_info *info = &__get_cpu_var(per_cpu_info);
591 struct mpipe_data *md = &mpipe_data[instance];
592 struct net_device *dev = md->tile_net_devs_for_channel[idesc->channel];
593 uint8_t l2_offset;
594 void *va;
595 void *buf;
596 unsigned long len;
597 bool filter;
598
599 /* Drop packets for which no buffer was available (which can
600 * happen under heavy load), or for which the me/tr/ce flags
601 * are set (which can happen for jumbo cut-through packets,
602 * or with a customized classifier).
603 */
604 if (idesc->be || idesc->me || idesc->tr || idesc->ce) {
605 if (dev)
606 tile_net_stats_add(1, &dev->stats.rx_errors);
607 goto drop;
608 }
609
610 /* Get the "l2_offset", if allowed. */
611 l2_offset = custom_flag ? 0 : gxio_mpipe_idesc_get_l2_offset(idesc);
612
613 /* Get the VA (including NET_IP_ALIGN bytes of "headroom"). */
614 va = tile_io_addr_to_va((unsigned long)idesc->va);
615
616 /* Get the actual packet start/length. */
617 buf = va + l2_offset;
618 len = idesc->l2_size - l2_offset;
619
620 /* Point "va" at the raw buffer. */
621 va -= NET_IP_ALIGN;
622
623 filter = filter_packet(dev, buf);
624 if (filter) {
625 if (dev)
626 tile_net_stats_add(1, &dev->stats.rx_dropped);
627 drop:
628 gxio_mpipe_iqueue_drop(&info->mpipe[instance].iqueue, idesc);
629 } else {
630 struct sk_buff *skb = mpipe_buf_to_skb(va);
631
632 /* Skip headroom, and any custom header. */
633 skb_reserve(skb, NET_IP_ALIGN + l2_offset);
634
635 tile_net_receive_skb(dev, skb, idesc, len);
636 }
637
638 gxio_mpipe_iqueue_consume(&info->mpipe[instance].iqueue, idesc);
639 return !filter;
640 }
641
642 /* Handle some packets for the current CPU.
643 *
644 * This function handles up to TILE_NET_BATCH idescs per call.
645 *
646 * ISSUE: Since we do not provide new buffers until this function is
647 * complete, we must initially provide enough buffers for each network
648 * cpu to fill its iqueue and also its batched idescs.
649 *
650 * ISSUE: The "rotting packet" race condition occurs if a packet
651 * arrives after the queue appears to be empty, and before the
652 * hypervisor interrupt is re-enabled.
653 */
654 static int tile_net_poll(struct napi_struct *napi, int budget)
655 {
656 struct tile_net_info *info = &__get_cpu_var(per_cpu_info);
657 unsigned int work = 0;
658 gxio_mpipe_idesc_t *idesc;
659 int instance, i, n;
660 struct mpipe_data *md;
661 struct info_mpipe *info_mpipe =
662 container_of(napi, struct info_mpipe, napi);
663
664 instance = info_mpipe->instance;
665 while ((n = gxio_mpipe_iqueue_try_peek(
666 &info_mpipe->iqueue,
667 &idesc)) > 0) {
668 for (i = 0; i < n; i++) {
669 if (i == TILE_NET_BATCH)
670 goto done;
671 if (tile_net_handle_packet(instance,
672 idesc + i)) {
673 if (++work >= budget)
674 goto done;
675 }
676 }
677 }
678
679 /* There are no packets left. */
680 napi_complete(&info_mpipe->napi);
681
682 md = &mpipe_data[instance];
683 /* Re-enable hypervisor interrupts. */
684 gxio_mpipe_enable_notif_ring_interrupt(
685 &md->context, info->mpipe[instance].iqueue.ring);
686
687 /* HACK: Avoid the "rotting packet" problem. */
688 if (gxio_mpipe_iqueue_try_peek(&info_mpipe->iqueue, &idesc) > 0)
689 napi_schedule(&info_mpipe->napi);
690
691 /* ISSUE: Handle completions? */
692
693 done:
694 tile_net_provide_needed_buffers();
695
696 return work;
697 }
698
699 /* Handle an ingress interrupt from an instance on the current cpu. */
700 static irqreturn_t tile_net_handle_ingress_irq(int irq, void *id)
701 {
702 struct tile_net_info *info = &__get_cpu_var(per_cpu_info);
703 napi_schedule(&info->mpipe[(uint64_t)id].napi);
704 return IRQ_HANDLED;
705 }
706
707 /* Free some completions. This must be called with interrupts blocked. */
708 static int tile_net_free_comps(gxio_mpipe_equeue_t *equeue,
709 struct tile_net_comps *comps,
710 int limit, bool force_update)
711 {
712 int n = 0;
713 while (comps->comp_last < comps->comp_next) {
714 unsigned int cid = comps->comp_last % TILE_NET_MAX_COMPS;
715 struct tile_net_comp *comp = &comps->comp_queue[cid];
716 if (!gxio_mpipe_equeue_is_complete(equeue, comp->when,
717 force_update || n == 0))
718 break;
719 dev_kfree_skb_irq(comp->skb);
720 comps->comp_last++;
721 if (++n == limit)
722 break;
723 }
724 return n;
725 }
726
727 /* Add a completion. This must be called with interrupts blocked.
728 * tile_net_equeue_try_reserve() will have ensured a free completion entry.
729 */
730 static void add_comp(gxio_mpipe_equeue_t *equeue,
731 struct tile_net_comps *comps,
732 uint64_t when, struct sk_buff *skb)
733 {
734 int cid = comps->comp_next % TILE_NET_MAX_COMPS;
735 comps->comp_queue[cid].when = when;
736 comps->comp_queue[cid].skb = skb;
737 comps->comp_next++;
738 }
739
740 static void tile_net_schedule_tx_wake_timer(struct net_device *dev,
741 int tx_queue_idx)
742 {
743 struct tile_net_info *info = &per_cpu(per_cpu_info, tx_queue_idx);
744 struct tile_net_priv *priv = netdev_priv(dev);
745 int instance = priv->instance;
746 struct tile_net_tx_wake *tx_wake =
747 &info->mpipe[instance].tx_wake[priv->echannel];
748
749 hrtimer_start(&tx_wake->timer,
750 ktime_set(0, TX_TIMER_DELAY_USEC * 1000UL),
751 HRTIMER_MODE_REL_PINNED);
752 }
753
754 static enum hrtimer_restart tile_net_handle_tx_wake_timer(struct hrtimer *t)
755 {
756 struct tile_net_tx_wake *tx_wake =
757 container_of(t, struct tile_net_tx_wake, timer);
758 netif_wake_subqueue(tx_wake->dev, tx_wake->tx_queue_idx);
759 return HRTIMER_NORESTART;
760 }
761
762 /* Make sure the egress timer is scheduled. */
763 static void tile_net_schedule_egress_timer(void)
764 {
765 struct tile_net_info *info = &__get_cpu_var(per_cpu_info);
766
767 if (!info->egress_timer_scheduled) {
768 hrtimer_start(&info->egress_timer,
769 ktime_set(0, EGRESS_TIMER_DELAY_USEC * 1000UL),
770 HRTIMER_MODE_REL_PINNED);
771 info->egress_timer_scheduled = true;
772 }
773 }
774
775 /* The "function" for "info->egress_timer".
776 *
777 * This timer will reschedule itself as long as there are any pending
778 * completions expected for this tile.
779 */
780 static enum hrtimer_restart tile_net_handle_egress_timer(struct hrtimer *t)
781 {
782 struct tile_net_info *info = &__get_cpu_var(per_cpu_info);
783 unsigned long irqflags;
784 bool pending = false;
785 int i, instance;
786
787 local_irq_save(irqflags);
788
789 /* The timer is no longer scheduled. */
790 info->egress_timer_scheduled = false;
791
792 /* Free all possible comps for this tile. */
793 for (instance = 0; instance < NR_MPIPE_MAX &&
794 info->mpipe[instance].has_iqueue; instance++) {
795 for (i = 0; i < TILE_NET_CHANNELS; i++) {
796 struct tile_net_egress *egress =
797 &mpipe_data[instance].egress_for_echannel[i];
798 struct tile_net_comps *comps =
799 info->mpipe[instance].comps_for_echannel[i];
800 if (!egress || comps->comp_last >= comps->comp_next)
801 continue;
802 tile_net_free_comps(egress->equeue, comps, -1, true);
803 pending = pending ||
804 (comps->comp_last < comps->comp_next);
805 }
806 }
807
808 /* Reschedule timer if needed. */
809 if (pending)
810 tile_net_schedule_egress_timer();
811
812 local_irq_restore(irqflags);
813
814 return HRTIMER_NORESTART;
815 }
816
817 #ifdef CONFIG_PTP_1588_CLOCK_TILEGX
818
819 /* PTP clock operations. */
820
821 static int ptp_mpipe_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
822 {
823 int ret = 0;
824 struct mpipe_data *md = container_of(ptp, struct mpipe_data, caps);
825 mutex_lock(&md->ptp_lock);
826 if (gxio_mpipe_adjust_timestamp_freq(&md->context, ppb))
827 ret = -EINVAL;
828 mutex_unlock(&md->ptp_lock);
829 return ret;
830 }
831
832 static int ptp_mpipe_adjtime(struct ptp_clock_info *ptp, s64 delta)
833 {
834 int ret = 0;
835 struct mpipe_data *md = container_of(ptp, struct mpipe_data, caps);
836 mutex_lock(&md->ptp_lock);
837 if (gxio_mpipe_adjust_timestamp(&md->context, delta))
838 ret = -EBUSY;
839 mutex_unlock(&md->ptp_lock);
840 return ret;
841 }
842
843 static int ptp_mpipe_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
844 {
845 int ret = 0;
846 struct mpipe_data *md = container_of(ptp, struct mpipe_data, caps);
847 mutex_lock(&md->ptp_lock);
848 if (gxio_mpipe_get_timestamp(&md->context, ts))
849 ret = -EBUSY;
850 mutex_unlock(&md->ptp_lock);
851 return ret;
852 }
853
854 static int ptp_mpipe_settime(struct ptp_clock_info *ptp,
855 const struct timespec *ts)
856 {
857 int ret = 0;
858 struct mpipe_data *md = container_of(ptp, struct mpipe_data, caps);
859 mutex_lock(&md->ptp_lock);
860 if (gxio_mpipe_set_timestamp(&md->context, ts))
861 ret = -EBUSY;
862 mutex_unlock(&md->ptp_lock);
863 return ret;
864 }
865
866 static int ptp_mpipe_enable(struct ptp_clock_info *ptp,
867 struct ptp_clock_request *request, int on)
868 {
869 return -EOPNOTSUPP;
870 }
871
872 static struct ptp_clock_info ptp_mpipe_caps = {
873 .owner = THIS_MODULE,
874 .name = "mPIPE clock",
875 .max_adj = 999999999,
876 .n_ext_ts = 0,
877 .pps = 0,
878 .adjfreq = ptp_mpipe_adjfreq,
879 .adjtime = ptp_mpipe_adjtime,
880 .gettime = ptp_mpipe_gettime,
881 .settime = ptp_mpipe_settime,
882 .enable = ptp_mpipe_enable,
883 };
884
885 #endif /* CONFIG_PTP_1588_CLOCK_TILEGX */
886
887 /* Sync mPIPE's timestamp up with Linux system time and register PTP clock. */
888 static void register_ptp_clock(struct net_device *dev, struct mpipe_data *md)
889 {
890 #ifdef CONFIG_PTP_1588_CLOCK_TILEGX
891 struct timespec ts;
892
893 getnstimeofday(&ts);
894 gxio_mpipe_set_timestamp(&md->context, &ts);
895
896 mutex_init(&md->ptp_lock);
897 md->caps = ptp_mpipe_caps;
898 md->ptp_clock = ptp_clock_register(&md->caps, NULL);
899 if (IS_ERR(md->ptp_clock))
900 netdev_err(dev, "ptp_clock_register failed %ld\n",
901 PTR_ERR(md->ptp_clock));
902 #endif
903 }
904
905 /* Initialize PTP fields in a new device. */
906 static void init_ptp_dev(struct tile_net_priv *priv)
907 {
908 #ifdef CONFIG_PTP_1588_CLOCK_TILEGX
909 priv->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
910 priv->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
911 #endif
912 }
913
914 /* Helper functions for "tile_net_update()". */
915 static void enable_ingress_irq(void *irq)
916 {
917 enable_percpu_irq((long)irq, 0);
918 }
919
920 static void disable_ingress_irq(void *irq)
921 {
922 disable_percpu_irq((long)irq);
923 }
924
925 /* Helper function for tile_net_open() and tile_net_stop().
926 * Always called under tile_net_devs_for_channel_mutex.
927 */
928 static int tile_net_update(struct net_device *dev)
929 {
930 static gxio_mpipe_rules_t rules; /* too big to fit on the stack */
931 bool saw_channel = false;
932 int instance = mpipe_instance(dev);
933 struct mpipe_data *md = &mpipe_data[instance];
934 int channel;
935 int rc;
936 int cpu;
937
938 saw_channel = false;
939 gxio_mpipe_rules_init(&rules, &md->context);
940
941 for (channel = 0; channel < TILE_NET_CHANNELS; channel++) {
942 if (md->tile_net_devs_for_channel[channel] == NULL)
943 continue;
944 if (!saw_channel) {
945 saw_channel = true;
946 gxio_mpipe_rules_begin(&rules, md->first_bucket,
947 md->num_buckets, NULL);
948 gxio_mpipe_rules_set_headroom(&rules, NET_IP_ALIGN);
949 }
950 gxio_mpipe_rules_add_channel(&rules, channel);
951 }
952
953 /* NOTE: This can fail if there is no classifier.
954 * ISSUE: Can anything else cause it to fail?
955 */
956 rc = gxio_mpipe_rules_commit(&rules);
957 if (rc != 0) {
958 netdev_warn(dev, "gxio_mpipe_rules_commit: mpipe[%d] %d\n",
959 instance, rc);
960 return -EIO;
961 }
962
963 /* Update all cpus, sequentially (to protect "netif_napi_add()").
964 * We use on_each_cpu to handle the IPI mask or unmask.
965 */
966 if (!saw_channel)
967 on_each_cpu(disable_ingress_irq,
968 (void *)(long)(md->ingress_irq), 1);
969 for_each_online_cpu(cpu) {
970 struct tile_net_info *info = &per_cpu(per_cpu_info, cpu);
971
972 if (!info->mpipe[instance].has_iqueue)
973 continue;
974 if (saw_channel) {
975 if (!info->mpipe[instance].napi_added) {
976 netif_napi_add(dev, &info->mpipe[instance].napi,
977 tile_net_poll, TILE_NET_WEIGHT);
978 info->mpipe[instance].napi_added = true;
979 }
980 if (!info->mpipe[instance].napi_enabled) {
981 napi_enable(&info->mpipe[instance].napi);
982 info->mpipe[instance].napi_enabled = true;
983 }
984 } else {
985 if (info->mpipe[instance].napi_enabled) {
986 napi_disable(&info->mpipe[instance].napi);
987 info->mpipe[instance].napi_enabled = false;
988 }
989 /* FIXME: Drain the iqueue. */
990 }
991 }
992 if (saw_channel)
993 on_each_cpu(enable_ingress_irq,
994 (void *)(long)(md->ingress_irq), 1);
995
996 /* HACK: Allow packets to flow in the simulator. */
997 if (saw_channel)
998 sim_enable_mpipe_links(instance, -1);
999
1000 return 0;
1001 }
1002
1003 /* Initialize a buffer stack. */
1004 static int create_buffer_stack(struct net_device *dev,
1005 int kind, size_t num_buffers)
1006 {
1007 pte_t hash_pte = pte_set_home((pte_t) { 0 }, PAGE_HOME_HASH);
1008 int instance = mpipe_instance(dev);
1009 struct mpipe_data *md = &mpipe_data[instance];
1010 size_t needed = gxio_mpipe_calc_buffer_stack_bytes(num_buffers);
1011 int stack_idx = md->first_buffer_stack + kind;
1012 void *va;
1013 int i, rc;
1014
1015 /* Round up to 64KB and then use alloc_pages() so we get the
1016 * required 64KB alignment.
1017 */
1018 md->buffer_stack_bytes[kind] =
1019 ALIGN(needed, 64 * 1024);
1020
1021 va = alloc_pages_exact(md->buffer_stack_bytes[kind], GFP_KERNEL);
1022 if (va == NULL) {
1023 netdev_err(dev,
1024 "Could not alloc %zd bytes for buffer stack %d\n",
1025 md->buffer_stack_bytes[kind], kind);
1026 return -ENOMEM;
1027 }
1028
1029 /* Initialize the buffer stack. */
1030 rc = gxio_mpipe_init_buffer_stack(&md->context, stack_idx,
1031 buffer_size_enums[kind], va,
1032 md->buffer_stack_bytes[kind], 0);
1033 if (rc != 0) {
1034 netdev_err(dev, "gxio_mpipe_init_buffer_stack: mpipe[%d] %d\n",
1035 instance, rc);
1036 free_pages_exact(va, md->buffer_stack_bytes[kind]);
1037 return rc;
1038 }
1039
1040 md->buffer_stack_vas[kind] = va;
1041
1042 rc = gxio_mpipe_register_client_memory(&md->context, stack_idx,
1043 hash_pte, 0);
1044 if (rc != 0) {
1045 netdev_err(dev,
1046 "gxio_mpipe_register_client_memory: mpipe[%d] %d\n",
1047 instance, rc);
1048 return rc;
1049 }
1050
1051 /* Provide initial buffers. */
1052 for (i = 0; i < num_buffers; i++) {
1053 if (!tile_net_provide_buffer(instance, kind)) {
1054 netdev_err(dev, "Cannot allocate initial sk_bufs!\n");
1055 return -ENOMEM;
1056 }
1057 }
1058
1059 return 0;
1060 }
1061
1062 /* Allocate and initialize mpipe buffer stacks, and register them in
1063 * the mPIPE TLBs, for small, large, and (possibly) jumbo packet sizes.
1064 * This routine supports tile_net_init_mpipe(), below.
1065 */
1066 static int init_buffer_stacks(struct net_device *dev,
1067 int network_cpus_count)
1068 {
1069 int num_kinds = MAX_KINDS - (jumbo_num == 0);
1070 size_t num_buffers;
1071 int rc;
1072 int instance = mpipe_instance(dev);
1073 struct mpipe_data *md = &mpipe_data[instance];
1074
1075 /* Allocate the buffer stacks. */
1076 rc = gxio_mpipe_alloc_buffer_stacks(&md->context, num_kinds, 0, 0);
1077 if (rc < 0) {
1078 netdev_err(dev,
1079 "gxio_mpipe_alloc_buffer_stacks: mpipe[%d] %d\n",
1080 instance, rc);
1081 return rc;
1082 }
1083 md->first_buffer_stack = rc;
1084
1085 /* Enough small/large buffers to (normally) avoid buffer errors. */
1086 num_buffers =
1087 network_cpus_count * (IQUEUE_ENTRIES + TILE_NET_BATCH);
1088
1089 /* Allocate the small memory stack. */
1090 if (rc >= 0)
1091 rc = create_buffer_stack(dev, 0, num_buffers);
1092
1093 /* Allocate the large buffer stack. */
1094 if (rc >= 0)
1095 rc = create_buffer_stack(dev, 1, num_buffers);
1096
1097 /* Allocate the jumbo buffer stack if needed. */
1098 if (rc >= 0 && jumbo_num != 0)
1099 rc = create_buffer_stack(dev, 2, jumbo_num);
1100
1101 return rc;
1102 }
1103
1104 /* Allocate per-cpu resources (memory for completions and idescs).
1105 * This routine supports tile_net_init_mpipe(), below.
1106 */
1107 static int alloc_percpu_mpipe_resources(struct net_device *dev,
1108 int cpu, int ring)
1109 {
1110 struct tile_net_info *info = &per_cpu(per_cpu_info, cpu);
1111 int order, i, rc;
1112 int instance = mpipe_instance(dev);
1113 struct mpipe_data *md = &mpipe_data[instance];
1114 struct page *page;
1115 void *addr;
1116
1117 /* Allocate the "comps". */
1118 order = get_order(COMPS_SIZE);
1119 page = homecache_alloc_pages(GFP_KERNEL, order, cpu);
1120 if (page == NULL) {
1121 netdev_err(dev, "Failed to alloc %zd bytes comps memory\n",
1122 COMPS_SIZE);
1123 return -ENOMEM;
1124 }
1125 addr = pfn_to_kaddr(page_to_pfn(page));
1126 memset(addr, 0, COMPS_SIZE);
1127 for (i = 0; i < TILE_NET_CHANNELS; i++)
1128 info->mpipe[instance].comps_for_echannel[i] =
1129 addr + i * sizeof(struct tile_net_comps);
1130
1131 /* If this is a network cpu, create an iqueue. */
1132 if (cpu_isset(cpu, network_cpus_map)) {
1133 order = get_order(NOTIF_RING_SIZE);
1134 page = homecache_alloc_pages(GFP_KERNEL, order, cpu);
1135 if (page == NULL) {
1136 netdev_err(dev,
1137 "Failed to alloc %zd bytes iqueue memory\n",
1138 NOTIF_RING_SIZE);
1139 return -ENOMEM;
1140 }
1141 addr = pfn_to_kaddr(page_to_pfn(page));
1142 rc = gxio_mpipe_iqueue_init(&info->mpipe[instance].iqueue,
1143 &md->context, ring++, addr,
1144 NOTIF_RING_SIZE, 0);
1145 if (rc < 0) {
1146 netdev_err(dev,
1147 "gxio_mpipe_iqueue_init failed: %d\n", rc);
1148 return rc;
1149 }
1150 info->mpipe[instance].has_iqueue = true;
1151 }
1152
1153 return ring;
1154 }
1155
1156 /* Initialize NotifGroup and buckets.
1157 * This routine supports tile_net_init_mpipe(), below.
1158 */
1159 static int init_notif_group_and_buckets(struct net_device *dev,
1160 int ring, int network_cpus_count)
1161 {
1162 int group, rc;
1163 int instance = mpipe_instance(dev);
1164 struct mpipe_data *md = &mpipe_data[instance];
1165
1166 /* Allocate one NotifGroup. */
1167 rc = gxio_mpipe_alloc_notif_groups(&md->context, 1, 0, 0);
1168 if (rc < 0) {
1169 netdev_err(dev, "gxio_mpipe_alloc_notif_groups: mpipe[%d] %d\n",
1170 instance, rc);
1171 return rc;
1172 }
1173 group = rc;
1174
1175 /* Initialize global num_buckets value. */
1176 if (network_cpus_count > 4)
1177 md->num_buckets = 256;
1178 else if (network_cpus_count > 1)
1179 md->num_buckets = 16;
1180
1181 /* Allocate some buckets, and set global first_bucket value. */
1182 rc = gxio_mpipe_alloc_buckets(&md->context, md->num_buckets, 0, 0);
1183 if (rc < 0) {
1184 netdev_err(dev, "gxio_mpipe_alloc_buckets: mpipe[%d] %d\n",
1185 instance, rc);
1186 return rc;
1187 }
1188 md->first_bucket = rc;
1189
1190 /* Init group and buckets. */
1191 rc = gxio_mpipe_init_notif_group_and_buckets(
1192 &md->context, group, ring, network_cpus_count,
1193 md->first_bucket, md->num_buckets,
1194 GXIO_MPIPE_BUCKET_STICKY_FLOW_LOCALITY);
1195 if (rc != 0) {
1196 netdev_err(dev, "gxio_mpipe_init_notif_group_and_buckets: "
1197 "mpipe[%d] %d\n", instance, rc);
1198 return rc;
1199 }
1200
1201 return 0;
1202 }
1203
1204 /* Create an irq and register it, then activate the irq and request
1205 * interrupts on all cores. Note that "ingress_irq" being initialized
1206 * is how we know not to call tile_net_init_mpipe() again.
1207 * This routine supports tile_net_init_mpipe(), below.
1208 */
1209 static int tile_net_setup_interrupts(struct net_device *dev)
1210 {
1211 int cpu, rc, irq;
1212 int instance = mpipe_instance(dev);
1213 struct mpipe_data *md = &mpipe_data[instance];
1214
1215 irq = md->ingress_irq;
1216 if (irq < 0) {
1217 irq = create_irq();
1218 if (irq < 0) {
1219 netdev_err(dev,
1220 "create_irq failed: mpipe[%d] %d\n",
1221 instance, irq);
1222 return irq;
1223 }
1224 tile_irq_activate(irq, TILE_IRQ_PERCPU);
1225
1226 rc = request_irq(irq, tile_net_handle_ingress_irq,
1227 0, "tile_net", (void *)((uint64_t)instance));
1228
1229 if (rc != 0) {
1230 netdev_err(dev, "request_irq failed: mpipe[%d] %d\n",
1231 instance, rc);
1232 destroy_irq(irq);
1233 return rc;
1234 }
1235 md->ingress_irq = irq;
1236 }
1237
1238 for_each_online_cpu(cpu) {
1239 struct tile_net_info *info = &per_cpu(per_cpu_info, cpu);
1240 if (info->mpipe[instance].has_iqueue) {
1241 gxio_mpipe_request_notif_ring_interrupt(&md->context,
1242 cpu_x(cpu), cpu_y(cpu), KERNEL_PL, irq,
1243 info->mpipe[instance].iqueue.ring);
1244 }
1245 }
1246
1247 return 0;
1248 }
1249
1250 /* Undo any state set up partially by a failed call to tile_net_init_mpipe. */
1251 static void tile_net_init_mpipe_fail(int instance)
1252 {
1253 int kind, cpu;
1254 struct mpipe_data *md = &mpipe_data[instance];
1255
1256 /* Do cleanups that require the mpipe context first. */
1257 for (kind = 0; kind < MAX_KINDS; kind++) {
1258 if (md->buffer_stack_vas[kind] != NULL) {
1259 tile_net_pop_all_buffers(instance,
1260 md->first_buffer_stack +
1261 kind);
1262 }
1263 }
1264
1265 /* Destroy mpipe context so the hardware no longer owns any memory. */
1266 gxio_mpipe_destroy(&md->context);
1267
1268 for_each_online_cpu(cpu) {
1269 struct tile_net_info *info = &per_cpu(per_cpu_info, cpu);
1270 free_pages(
1271 (unsigned long)(
1272 info->mpipe[instance].comps_for_echannel[0]),
1273 get_order(COMPS_SIZE));
1274 info->mpipe[instance].comps_for_echannel[0] = NULL;
1275 free_pages((unsigned long)(info->mpipe[instance].iqueue.idescs),
1276 get_order(NOTIF_RING_SIZE));
1277 info->mpipe[instance].iqueue.idescs = NULL;
1278 }
1279
1280 for (kind = 0; kind < MAX_KINDS; kind++) {
1281 if (md->buffer_stack_vas[kind] != NULL) {
1282 free_pages_exact(md->buffer_stack_vas[kind],
1283 md->buffer_stack_bytes[kind]);
1284 md->buffer_stack_vas[kind] = NULL;
1285 }
1286 }
1287
1288 md->first_buffer_stack = -1;
1289 md->first_bucket = -1;
1290 }
1291
1292 /* The first time any tilegx network device is opened, we initialize
1293 * the global mpipe state. If this step fails, we fail to open the
1294 * device, but if it succeeds, we never need to do it again, and since
1295 * tile_net can't be unloaded, we never undo it.
1296 *
1297 * Note that some resources in this path (buffer stack indices,
1298 * bindings from init_buffer_stack, etc.) are hypervisor resources
1299 * that are freed implicitly by gxio_mpipe_destroy().
1300 */
1301 static int tile_net_init_mpipe(struct net_device *dev)
1302 {
1303 int rc;
1304 int cpu;
1305 int first_ring, ring;
1306 int instance = mpipe_instance(dev);
1307 struct mpipe_data *md = &mpipe_data[instance];
1308 int network_cpus_count = cpus_weight(network_cpus_map);
1309
1310 if (!hash_default) {
1311 netdev_err(dev, "Networking requires hash_default!\n");
1312 return -EIO;
1313 }
1314
1315 rc = gxio_mpipe_init(&md->context, instance);
1316 if (rc != 0) {
1317 netdev_err(dev, "gxio_mpipe_init: mpipe[%d] %d\n",
1318 instance, rc);
1319 return -EIO;
1320 }
1321
1322 /* Set up the buffer stacks. */
1323 rc = init_buffer_stacks(dev, network_cpus_count);
1324 if (rc != 0)
1325 goto fail;
1326
1327 /* Allocate one NotifRing for each network cpu. */
1328 rc = gxio_mpipe_alloc_notif_rings(&md->context,
1329 network_cpus_count, 0, 0);
1330 if (rc < 0) {
1331 netdev_err(dev, "gxio_mpipe_alloc_notif_rings failed %d\n",
1332 rc);
1333 goto fail;
1334 }
1335
1336 /* Init NotifRings per-cpu. */
1337 first_ring = rc;
1338 ring = first_ring;
1339 for_each_online_cpu(cpu) {
1340 rc = alloc_percpu_mpipe_resources(dev, cpu, ring);
1341 if (rc < 0)
1342 goto fail;
1343 ring = rc;
1344 }
1345
1346 /* Initialize NotifGroup and buckets. */
1347 rc = init_notif_group_and_buckets(dev, first_ring, network_cpus_count);
1348 if (rc != 0)
1349 goto fail;
1350
1351 /* Create and enable interrupts. */
1352 rc = tile_net_setup_interrupts(dev);
1353 if (rc != 0)
1354 goto fail;
1355
1356 /* Register PTP clock and set mPIPE timestamp, if configured. */
1357 register_ptp_clock(dev, md);
1358
1359 return 0;
1360
1361 fail:
1362 tile_net_init_mpipe_fail(instance);
1363 return rc;
1364 }
1365
1366 /* Create persistent egress info for a given egress channel.
1367 * Note that this may be shared between, say, "gbe0" and "xgbe0".
1368 * ISSUE: Defer header allocation until TSO is actually needed?
1369 */
1370 static int tile_net_init_egress(struct net_device *dev, int echannel)
1371 {
1372 static int ering = -1;
1373 struct page *headers_page, *edescs_page, *equeue_page;
1374 gxio_mpipe_edesc_t *edescs;
1375 gxio_mpipe_equeue_t *equeue;
1376 unsigned char *headers;
1377 int headers_order, edescs_order, equeue_order;
1378 size_t edescs_size;
1379 int rc = -ENOMEM;
1380 int instance = mpipe_instance(dev);
1381 struct mpipe_data *md = &mpipe_data[instance];
1382
1383 /* Only initialize once. */
1384 if (md->egress_for_echannel[echannel].equeue != NULL)
1385 return 0;
1386
1387 /* Allocate memory for the "headers". */
1388 headers_order = get_order(EQUEUE_ENTRIES * HEADER_BYTES);
1389 headers_page = alloc_pages(GFP_KERNEL, headers_order);
1390 if (headers_page == NULL) {
1391 netdev_warn(dev,
1392 "Could not alloc %zd bytes for TSO headers.\n",
1393 PAGE_SIZE << headers_order);
1394 goto fail;
1395 }
1396 headers = pfn_to_kaddr(page_to_pfn(headers_page));
1397
1398 /* Allocate memory for the "edescs". */
1399 edescs_size = EQUEUE_ENTRIES * sizeof(*edescs);
1400 edescs_order = get_order(edescs_size);
1401 edescs_page = alloc_pages(GFP_KERNEL, edescs_order);
1402 if (edescs_page == NULL) {
1403 netdev_warn(dev,
1404 "Could not alloc %zd bytes for eDMA ring.\n",
1405 edescs_size);
1406 goto fail_headers;
1407 }
1408 edescs = pfn_to_kaddr(page_to_pfn(edescs_page));
1409
1410 /* Allocate memory for the "equeue". */
1411 equeue_order = get_order(sizeof(*equeue));
1412 equeue_page = alloc_pages(GFP_KERNEL, equeue_order);
1413 if (equeue_page == NULL) {
1414 netdev_warn(dev,
1415 "Could not alloc %zd bytes for equeue info.\n",
1416 PAGE_SIZE << equeue_order);
1417 goto fail_edescs;
1418 }
1419 equeue = pfn_to_kaddr(page_to_pfn(equeue_page));
1420
1421 /* Allocate an edma ring (using a one entry "free list"). */
1422 if (ering < 0) {
1423 rc = gxio_mpipe_alloc_edma_rings(&md->context, 1, 0, 0);
1424 if (rc < 0) {
1425 netdev_warn(dev, "gxio_mpipe_alloc_edma_rings: "
1426 "mpipe[%d] %d\n", instance, rc);
1427 goto fail_equeue;
1428 }
1429 ering = rc;
1430 }
1431
1432 /* Initialize the equeue. */
1433 rc = gxio_mpipe_equeue_init(equeue, &md->context, ering, echannel,
1434 edescs, edescs_size, 0);
1435 if (rc != 0) {
1436 netdev_err(dev, "gxio_mpipe_equeue_init: mpipe[%d] %d\n",
1437 instance, rc);
1438 goto fail_equeue;
1439 }
1440
1441 /* Don't reuse the ering later. */
1442 ering = -1;
1443
1444 if (jumbo_num != 0) {
1445 /* Make sure "jumbo" packets can be egressed safely. */
1446 if (gxio_mpipe_equeue_set_snf_size(equeue, 10368) < 0) {
1447 /* ISSUE: There is no "gxio_mpipe_equeue_destroy()". */
1448 netdev_warn(dev, "Jumbo packets may not be egressed"
1449 " properly on channel %d\n", echannel);
1450 }
1451 }
1452
1453 /* Done. */
1454 md->egress_for_echannel[echannel].equeue = equeue;
1455 md->egress_for_echannel[echannel].headers = headers;
1456 return 0;
1457
1458 fail_equeue:
1459 __free_pages(equeue_page, equeue_order);
1460
1461 fail_edescs:
1462 __free_pages(edescs_page, edescs_order);
1463
1464 fail_headers:
1465 __free_pages(headers_page, headers_order);
1466
1467 fail:
1468 return rc;
1469 }
1470
1471 /* Return channel number for a newly-opened link. */
1472 static int tile_net_link_open(struct net_device *dev, gxio_mpipe_link_t *link,
1473 const char *link_name)
1474 {
1475 int instance = mpipe_instance(dev);
1476 struct mpipe_data *md = &mpipe_data[instance];
1477 int rc = gxio_mpipe_link_open(link, &md->context, link_name, 0);
1478 if (rc < 0) {
1479 netdev_err(dev, "Failed to open '%s', mpipe[%d], %d\n",
1480 link_name, instance, rc);
1481 return rc;
1482 }
1483 if (jumbo_num != 0) {
1484 u32 attr = GXIO_MPIPE_LINK_RECEIVE_JUMBO;
1485 rc = gxio_mpipe_link_set_attr(link, attr, 1);
1486 if (rc != 0) {
1487 netdev_err(dev,
1488 "Cannot receive jumbo packets on '%s'\n",
1489 link_name);
1490 gxio_mpipe_link_close(link);
1491 return rc;
1492 }
1493 }
1494 rc = gxio_mpipe_link_channel(link);
1495 if (rc < 0 || rc >= TILE_NET_CHANNELS) {
1496 netdev_err(dev, "gxio_mpipe_link_channel bad value: %d\n", rc);
1497 gxio_mpipe_link_close(link);
1498 return -EINVAL;
1499 }
1500 return rc;
1501 }
1502
1503 /* Help the kernel activate the given network interface. */
1504 static int tile_net_open(struct net_device *dev)
1505 {
1506 struct tile_net_priv *priv = netdev_priv(dev);
1507 int cpu, rc, instance;
1508
1509 mutex_lock(&tile_net_devs_for_channel_mutex);
1510
1511 /* Get the instance info. */
1512 rc = gxio_mpipe_link_instance(dev->name);
1513 if (rc < 0 || rc >= NR_MPIPE_MAX) {
1514 mutex_unlock(&tile_net_devs_for_channel_mutex);
1515 return -EIO;
1516 }
1517
1518 priv->instance = rc;
1519 instance = rc;
1520 if (!mpipe_data[rc].context.mmio_fast_base) {
1521 /* Do one-time initialization per instance the first time
1522 * any device is opened.
1523 */
1524 rc = tile_net_init_mpipe(dev);
1525 if (rc != 0)
1526 goto fail;
1527 }
1528
1529 /* Determine if this is the "loopify" device. */
1530 if (unlikely((loopify_link_name != NULL) &&
1531 !strcmp(dev->name, loopify_link_name))) {
1532 rc = tile_net_link_open(dev, &priv->link, "loop0");
1533 if (rc < 0)
1534 goto fail;
1535 priv->channel = rc;
1536 rc = tile_net_link_open(dev, &priv->loopify_link, "loop1");
1537 if (rc < 0)
1538 goto fail;
1539 priv->loopify_channel = rc;
1540 priv->echannel = rc;
1541 } else {
1542 rc = tile_net_link_open(dev, &priv->link, dev->name);
1543 if (rc < 0)
1544 goto fail;
1545 priv->channel = rc;
1546 priv->echannel = rc;
1547 }
1548
1549 /* Initialize egress info (if needed). Once ever, per echannel. */
1550 rc = tile_net_init_egress(dev, priv->echannel);
1551 if (rc != 0)
1552 goto fail;
1553
1554 mpipe_data[instance].tile_net_devs_for_channel[priv->channel] = dev;
1555
1556 rc = tile_net_update(dev);
1557 if (rc != 0)
1558 goto fail;
1559
1560 mutex_unlock(&tile_net_devs_for_channel_mutex);
1561
1562 /* Initialize the transmit wake timer for this device for each cpu. */
1563 for_each_online_cpu(cpu) {
1564 struct tile_net_info *info = &per_cpu(per_cpu_info, cpu);
1565 struct tile_net_tx_wake *tx_wake =
1566 &info->mpipe[instance].tx_wake[priv->echannel];
1567
1568 hrtimer_init(&tx_wake->timer, CLOCK_MONOTONIC,
1569 HRTIMER_MODE_REL);
1570 tx_wake->tx_queue_idx = cpu;
1571 tx_wake->timer.function = tile_net_handle_tx_wake_timer;
1572 tx_wake->dev = dev;
1573 }
1574
1575 for_each_online_cpu(cpu)
1576 netif_start_subqueue(dev, cpu);
1577 netif_carrier_on(dev);
1578 return 0;
1579
1580 fail:
1581 if (priv->loopify_channel >= 0) {
1582 if (gxio_mpipe_link_close(&priv->loopify_link) != 0)
1583 netdev_warn(dev, "Failed to close loopify link!\n");
1584 priv->loopify_channel = -1;
1585 }
1586 if (priv->channel >= 0) {
1587 if (gxio_mpipe_link_close(&priv->link) != 0)
1588 netdev_warn(dev, "Failed to close link!\n");
1589 priv->channel = -1;
1590 }
1591 priv->echannel = -1;
1592 mpipe_data[instance].tile_net_devs_for_channel[priv->channel] = NULL;
1593 mutex_unlock(&tile_net_devs_for_channel_mutex);
1594
1595 /* Don't return raw gxio error codes to generic Linux. */
1596 return (rc > -512) ? rc : -EIO;
1597 }
1598
1599 /* Help the kernel deactivate the given network interface. */
1600 static int tile_net_stop(struct net_device *dev)
1601 {
1602 struct tile_net_priv *priv = netdev_priv(dev);
1603 int cpu;
1604 int instance = priv->instance;
1605 struct mpipe_data *md = &mpipe_data[instance];
1606
1607 for_each_online_cpu(cpu) {
1608 struct tile_net_info *info = &per_cpu(per_cpu_info, cpu);
1609 struct tile_net_tx_wake *tx_wake =
1610 &info->mpipe[instance].tx_wake[priv->echannel];
1611
1612 hrtimer_cancel(&tx_wake->timer);
1613 netif_stop_subqueue(dev, cpu);
1614 }
1615
1616 mutex_lock(&tile_net_devs_for_channel_mutex);
1617 md->tile_net_devs_for_channel[priv->channel] = NULL;
1618 (void)tile_net_update(dev);
1619 if (priv->loopify_channel >= 0) {
1620 if (gxio_mpipe_link_close(&priv->loopify_link) != 0)
1621 netdev_warn(dev, "Failed to close loopify link!\n");
1622 priv->loopify_channel = -1;
1623 }
1624 if (priv->channel >= 0) {
1625 if (gxio_mpipe_link_close(&priv->link) != 0)
1626 netdev_warn(dev, "Failed to close link!\n");
1627 priv->channel = -1;
1628 }
1629 priv->echannel = -1;
1630 mutex_unlock(&tile_net_devs_for_channel_mutex);
1631
1632 return 0;
1633 }
1634
1635 /* Determine the VA for a fragment. */
1636 static inline void *tile_net_frag_buf(skb_frag_t *f)
1637 {
1638 unsigned long pfn = page_to_pfn(skb_frag_page(f));
1639 return pfn_to_kaddr(pfn) + f->page_offset;
1640 }
1641
1642 /* Acquire a completion entry and an egress slot, or if we can't,
1643 * stop the queue and schedule the tx_wake timer.
1644 */
1645 static s64 tile_net_equeue_try_reserve(struct net_device *dev,
1646 int tx_queue_idx,
1647 struct tile_net_comps *comps,
1648 gxio_mpipe_equeue_t *equeue,
1649 int num_edescs)
1650 {
1651 /* Try to acquire a completion entry. */
1652 if (comps->comp_next - comps->comp_last < TILE_NET_MAX_COMPS - 1 ||
1653 tile_net_free_comps(equeue, comps, 32, false) != 0) {
1654
1655 /* Try to acquire an egress slot. */
1656 s64 slot = gxio_mpipe_equeue_try_reserve(equeue, num_edescs);
1657 if (slot >= 0)
1658 return slot;
1659
1660 /* Freeing some completions gives the equeue time to drain. */
1661 tile_net_free_comps(equeue, comps, TILE_NET_MAX_COMPS, false);
1662
1663 slot = gxio_mpipe_equeue_try_reserve(equeue, num_edescs);
1664 if (slot >= 0)
1665 return slot;
1666 }
1667
1668 /* Still nothing; give up and stop the queue for a short while. */
1669 netif_stop_subqueue(dev, tx_queue_idx);
1670 tile_net_schedule_tx_wake_timer(dev, tx_queue_idx);
1671 return -1;
1672 }
1673
1674 /* Determine how many edesc's are needed for TSO.
1675 *
1676 * Sometimes, if "sendfile()" requires copying, we will be called with
1677 * "data" containing the header and payload, with "frags" being empty.
1678 * Sometimes, for example when using NFS over TCP, a single segment can
1679 * span 3 fragments. This requires special care.
1680 */
1681 static int tso_count_edescs(struct sk_buff *skb)
1682 {
1683 struct skb_shared_info *sh = skb_shinfo(skb);
1684 unsigned int sh_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1685 unsigned int data_len = skb->len - sh_len;
1686 unsigned int p_len = sh->gso_size;
1687 long f_id = -1; /* id of the current fragment */
1688 long f_size = skb_headlen(skb) - sh_len; /* current fragment size */
1689 long f_used = 0; /* bytes used from the current fragment */
1690 long n; /* size of the current piece of payload */
1691 int num_edescs = 0;
1692 int segment;
1693
1694 for (segment = 0; segment < sh->gso_segs; segment++) {
1695
1696 unsigned int p_used = 0;
1697
1698 /* One edesc for header and for each piece of the payload. */
1699 for (num_edescs++; p_used < p_len; num_edescs++) {
1700
1701 /* Advance as needed. */
1702 while (f_used >= f_size) {
1703 f_id++;
1704 f_size = skb_frag_size(&sh->frags[f_id]);
1705 f_used = 0;
1706 }
1707
1708 /* Use bytes from the current fragment. */
1709 n = p_len - p_used;
1710 if (n > f_size - f_used)
1711 n = f_size - f_used;
1712 f_used += n;
1713 p_used += n;
1714 }
1715
1716 /* The last segment may be less than gso_size. */
1717 data_len -= p_len;
1718 if (data_len < p_len)
1719 p_len = data_len;
1720 }
1721
1722 return num_edescs;
1723 }
1724
1725 /* Prepare modified copies of the skbuff headers. */
1726 static void tso_headers_prepare(struct sk_buff *skb, unsigned char *headers,
1727 s64 slot)
1728 {
1729 struct skb_shared_info *sh = skb_shinfo(skb);
1730 struct iphdr *ih;
1731 struct ipv6hdr *ih6;
1732 struct tcphdr *th;
1733 unsigned int sh_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1734 unsigned int data_len = skb->len - sh_len;
1735 unsigned char *data = skb->data;
1736 unsigned int ih_off, th_off, p_len;
1737 unsigned int isum_seed, tsum_seed, id, seq;
1738 int is_ipv6;
1739 long f_id = -1; /* id of the current fragment */
1740 long f_size = skb_headlen(skb) - sh_len; /* current fragment size */
1741 long f_used = 0; /* bytes used from the current fragment */
1742 long n; /* size of the current piece of payload */
1743 int segment;
1744
1745 /* Locate original headers and compute various lengths. */
1746 is_ipv6 = skb_is_gso_v6(skb);
1747 if (is_ipv6) {
1748 ih6 = ipv6_hdr(skb);
1749 ih_off = skb_network_offset(skb);
1750 } else {
1751 ih = ip_hdr(skb);
1752 ih_off = skb_network_offset(skb);
1753 isum_seed = ((0xFFFF - ih->check) +
1754 (0xFFFF - ih->tot_len) +
1755 (0xFFFF - ih->id));
1756 id = ntohs(ih->id);
1757 }
1758
1759 th = tcp_hdr(skb);
1760 th_off = skb_transport_offset(skb);
1761 p_len = sh->gso_size;
1762
1763 tsum_seed = th->check + (0xFFFF ^ htons(skb->len));
1764 seq = ntohl(th->seq);
1765
1766 /* Prepare all the headers. */
1767 for (segment = 0; segment < sh->gso_segs; segment++) {
1768 unsigned char *buf;
1769 unsigned int p_used = 0;
1770
1771 /* Copy to the header memory for this segment. */
1772 buf = headers + (slot % EQUEUE_ENTRIES) * HEADER_BYTES +
1773 NET_IP_ALIGN;
1774 memcpy(buf, data, sh_len);
1775
1776 /* Update copied ip header. */
1777 if (is_ipv6) {
1778 ih6 = (struct ipv6hdr *)(buf + ih_off);
1779 ih6->payload_len = htons(sh_len + p_len - ih_off -
1780 sizeof(*ih6));
1781 } else {
1782 ih = (struct iphdr *)(buf + ih_off);
1783 ih->tot_len = htons(sh_len + p_len - ih_off);
1784 ih->id = htons(id);
1785 ih->check = csum_long(isum_seed + ih->tot_len +
1786 ih->id) ^ 0xffff;
1787 }
1788
1789 /* Update copied tcp header. */
1790 th = (struct tcphdr *)(buf + th_off);
1791 th->seq = htonl(seq);
1792 th->check = csum_long(tsum_seed + htons(sh_len + p_len));
1793 if (segment != sh->gso_segs - 1) {
1794 th->fin = 0;
1795 th->psh = 0;
1796 }
1797
1798 /* Skip past the header. */
1799 slot++;
1800
1801 /* Skip past the payload. */
1802 while (p_used < p_len) {
1803
1804 /* Advance as needed. */
1805 while (f_used >= f_size) {
1806 f_id++;
1807 f_size = skb_frag_size(&sh->frags[f_id]);
1808 f_used = 0;
1809 }
1810
1811 /* Use bytes from the current fragment. */
1812 n = p_len - p_used;
1813 if (n > f_size - f_used)
1814 n = f_size - f_used;
1815 f_used += n;
1816 p_used += n;
1817
1818 slot++;
1819 }
1820
1821 id++;
1822 seq += p_len;
1823
1824 /* The last segment may be less than gso_size. */
1825 data_len -= p_len;
1826 if (data_len < p_len)
1827 p_len = data_len;
1828 }
1829
1830 /* Flush the headers so they are ready for hardware DMA. */
1831 wmb();
1832 }
1833
1834 /* Pass all the data to mpipe for egress. */
1835 static void tso_egress(struct net_device *dev, gxio_mpipe_equeue_t *equeue,
1836 struct sk_buff *skb, unsigned char *headers, s64 slot)
1837 {
1838 struct skb_shared_info *sh = skb_shinfo(skb);
1839 int instance = mpipe_instance(dev);
1840 struct mpipe_data *md = &mpipe_data[instance];
1841 unsigned int sh_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1842 unsigned int data_len = skb->len - sh_len;
1843 unsigned int p_len = sh->gso_size;
1844 gxio_mpipe_edesc_t edesc_head = { { 0 } };
1845 gxio_mpipe_edesc_t edesc_body = { { 0 } };
1846 long f_id = -1; /* id of the current fragment */
1847 long f_size = skb_headlen(skb) - sh_len; /* current fragment size */
1848 long f_used = 0; /* bytes used from the current fragment */
1849 void *f_data = skb->data + sh_len;
1850 long n; /* size of the current piece of payload */
1851 unsigned long tx_packets = 0, tx_bytes = 0;
1852 unsigned int csum_start;
1853 int segment;
1854
1855 /* Prepare to egress the headers: set up header edesc. */
1856 csum_start = skb_checksum_start_offset(skb);
1857 edesc_head.csum = 1;
1858 edesc_head.csum_start = csum_start;
1859 edesc_head.csum_dest = csum_start + skb->csum_offset;
1860 edesc_head.xfer_size = sh_len;
1861
1862 /* This is only used to specify the TLB. */
1863 edesc_head.stack_idx = md->first_buffer_stack;
1864 edesc_body.stack_idx = md->first_buffer_stack;
1865
1866 /* Egress all the edescs. */
1867 for (segment = 0; segment < sh->gso_segs; segment++) {
1868 unsigned char *buf;
1869 unsigned int p_used = 0;
1870
1871 /* Egress the header. */
1872 buf = headers + (slot % EQUEUE_ENTRIES) * HEADER_BYTES +
1873 NET_IP_ALIGN;
1874 edesc_head.va = va_to_tile_io_addr(buf);
1875 gxio_mpipe_equeue_put_at(equeue, edesc_head, slot);
1876 slot++;
1877
1878 /* Egress the payload. */
1879 while (p_used < p_len) {
1880 void *va;
1881
1882 /* Advance as needed. */
1883 while (f_used >= f_size) {
1884 f_id++;
1885 f_size = skb_frag_size(&sh->frags[f_id]);
1886 f_data = tile_net_frag_buf(&sh->frags[f_id]);
1887 f_used = 0;
1888 }
1889
1890 va = f_data + f_used;
1891
1892 /* Use bytes from the current fragment. */
1893 n = p_len - p_used;
1894 if (n > f_size - f_used)
1895 n = f_size - f_used;
1896 f_used += n;
1897 p_used += n;
1898
1899 /* Egress a piece of the payload. */
1900 edesc_body.va = va_to_tile_io_addr(va);
1901 edesc_body.xfer_size = n;
1902 edesc_body.bound = !(p_used < p_len);
1903 gxio_mpipe_equeue_put_at(equeue, edesc_body, slot);
1904 slot++;
1905 }
1906
1907 tx_packets++;
1908 tx_bytes += sh_len + p_len;
1909
1910 /* The last segment may be less than gso_size. */
1911 data_len -= p_len;
1912 if (data_len < p_len)
1913 p_len = data_len;
1914 }
1915
1916 /* Update stats. */
1917 tile_net_stats_add(tx_packets, &dev->stats.tx_packets);
1918 tile_net_stats_add(tx_bytes, &dev->stats.tx_bytes);
1919 }
1920
1921 /* Do "TSO" handling for egress.
1922 *
1923 * Normally drivers set NETIF_F_TSO only to support hardware TSO;
1924 * otherwise the stack uses scatter-gather to implement GSO in software.
1925 * On our testing, enabling GSO support (via NETIF_F_SG) drops network
1926 * performance down to around 7.5 Gbps on the 10G interfaces, although
1927 * also dropping cpu utilization way down, to under 8%. But
1928 * implementing "TSO" in the driver brings performance back up to line
1929 * rate, while dropping cpu usage even further, to less than 4%. In
1930 * practice, profiling of GSO shows that skb_segment() is what causes
1931 * the performance overheads; we benefit in the driver from using
1932 * preallocated memory to duplicate the TCP/IP headers.
1933 */
1934 static int tile_net_tx_tso(struct sk_buff *skb, struct net_device *dev)
1935 {
1936 struct tile_net_info *info = &__get_cpu_var(per_cpu_info);
1937 struct tile_net_priv *priv = netdev_priv(dev);
1938 int channel = priv->echannel;
1939 int instance = priv->instance;
1940 struct mpipe_data *md = &mpipe_data[instance];
1941 struct tile_net_egress *egress = &md->egress_for_echannel[channel];
1942 struct tile_net_comps *comps =
1943 info->mpipe[instance].comps_for_echannel[channel];
1944 gxio_mpipe_equeue_t *equeue = egress->equeue;
1945 unsigned long irqflags;
1946 int num_edescs;
1947 s64 slot;
1948
1949 /* Determine how many mpipe edesc's are needed. */
1950 num_edescs = tso_count_edescs(skb);
1951
1952 local_irq_save(irqflags);
1953
1954 /* Try to acquire a completion entry and an egress slot. */
1955 slot = tile_net_equeue_try_reserve(dev, skb->queue_mapping, comps,
1956 equeue, num_edescs);
1957 if (slot < 0) {
1958 local_irq_restore(irqflags);
1959 return NETDEV_TX_BUSY;
1960 }
1961
1962 /* Set up copies of header data properly. */
1963 tso_headers_prepare(skb, egress->headers, slot);
1964
1965 /* Actually pass the data to the network hardware. */
1966 tso_egress(dev, equeue, skb, egress->headers, slot);
1967
1968 /* Add a completion record. */
1969 add_comp(equeue, comps, slot + num_edescs - 1, skb);
1970
1971 local_irq_restore(irqflags);
1972
1973 /* Make sure the egress timer is scheduled. */
1974 tile_net_schedule_egress_timer();
1975
1976 return NETDEV_TX_OK;
1977 }
1978
1979 /* Analyze the body and frags for a transmit request. */
1980 static unsigned int tile_net_tx_frags(struct frag *frags,
1981 struct sk_buff *skb,
1982 void *b_data, unsigned int b_len)
1983 {
1984 unsigned int i, n = 0;
1985
1986 struct skb_shared_info *sh = skb_shinfo(skb);
1987
1988 if (b_len != 0) {
1989 frags[n].buf = b_data;
1990 frags[n++].length = b_len;
1991 }
1992
1993 for (i = 0; i < sh->nr_frags; i++) {
1994 skb_frag_t *f = &sh->frags[i];
1995 frags[n].buf = tile_net_frag_buf(f);
1996 frags[n++].length = skb_frag_size(f);
1997 }
1998
1999 return n;
2000 }
2001
2002 /* Help the kernel transmit a packet. */
2003 static int tile_net_tx(struct sk_buff *skb, struct net_device *dev)
2004 {
2005 struct tile_net_info *info = &__get_cpu_var(per_cpu_info);
2006 struct tile_net_priv *priv = netdev_priv(dev);
2007 int instance = priv->instance;
2008 struct mpipe_data *md = &mpipe_data[instance];
2009 struct tile_net_egress *egress =
2010 &md->egress_for_echannel[priv->echannel];
2011 gxio_mpipe_equeue_t *equeue = egress->equeue;
2012 struct tile_net_comps *comps =
2013 info->mpipe[instance].comps_for_echannel[priv->echannel];
2014 unsigned int len = skb->len;
2015 unsigned char *data = skb->data;
2016 unsigned int num_edescs;
2017 struct frag frags[MAX_FRAGS];
2018 gxio_mpipe_edesc_t edescs[MAX_FRAGS];
2019 unsigned long irqflags;
2020 gxio_mpipe_edesc_t edesc = { { 0 } };
2021 unsigned int i;
2022 s64 slot;
2023
2024 if (skb_is_gso(skb))
2025 return tile_net_tx_tso(skb, dev);
2026
2027 num_edescs = tile_net_tx_frags(frags, skb, data, skb_headlen(skb));
2028
2029 /* This is only used to specify the TLB. */
2030 edesc.stack_idx = md->first_buffer_stack;
2031
2032 /* Prepare the edescs. */
2033 for (i = 0; i < num_edescs; i++) {
2034 edesc.xfer_size = frags[i].length;
2035 edesc.va = va_to_tile_io_addr(frags[i].buf);
2036 edescs[i] = edesc;
2037 }
2038
2039 /* Mark the final edesc. */
2040 edescs[num_edescs - 1].bound = 1;
2041
2042 /* Add checksum info to the initial edesc, if needed. */
2043 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2044 unsigned int csum_start = skb_checksum_start_offset(skb);
2045 edescs[0].csum = 1;
2046 edescs[0].csum_start = csum_start;
2047 edescs[0].csum_dest = csum_start + skb->csum_offset;
2048 }
2049
2050 local_irq_save(irqflags);
2051
2052 /* Try to acquire a completion entry and an egress slot. */
2053 slot = tile_net_equeue_try_reserve(dev, skb->queue_mapping, comps,
2054 equeue, num_edescs);
2055 if (slot < 0) {
2056 local_irq_restore(irqflags);
2057 return NETDEV_TX_BUSY;
2058 }
2059
2060 for (i = 0; i < num_edescs; i++)
2061 gxio_mpipe_equeue_put_at(equeue, edescs[i], slot++);
2062
2063 /* Store TX timestamp if needed. */
2064 tile_tx_timestamp(skb, instance);
2065
2066 /* Add a completion record. */
2067 add_comp(equeue, comps, slot - 1, skb);
2068
2069 /* NOTE: Use ETH_ZLEN for short packets (e.g. 42 < 60). */
2070 tile_net_stats_add(1, &dev->stats.tx_packets);
2071 tile_net_stats_add(max_t(unsigned int, len, ETH_ZLEN),
2072 &dev->stats.tx_bytes);
2073
2074 local_irq_restore(irqflags);
2075
2076 /* Make sure the egress timer is scheduled. */
2077 tile_net_schedule_egress_timer();
2078
2079 return NETDEV_TX_OK;
2080 }
2081
2082 /* Return subqueue id on this core (one per core). */
2083 static u16 tile_net_select_queue(struct net_device *dev, struct sk_buff *skb)
2084 {
2085 return smp_processor_id();
2086 }
2087
2088 /* Deal with a transmit timeout. */
2089 static void tile_net_tx_timeout(struct net_device *dev)
2090 {
2091 int cpu;
2092
2093 for_each_online_cpu(cpu)
2094 netif_wake_subqueue(dev, cpu);
2095 }
2096
2097 /* Ioctl commands. */
2098 static int tile_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2099 {
2100 if (cmd == SIOCSHWTSTAMP)
2101 return tile_hwtstamp_ioctl(dev, rq, cmd);
2102
2103 return -EOPNOTSUPP;
2104 }
2105
2106 /* Change the MTU. */
2107 static int tile_net_change_mtu(struct net_device *dev, int new_mtu)
2108 {
2109 if (new_mtu < 68)
2110 return -EINVAL;
2111 if (new_mtu > ((jumbo_num != 0) ? 9000 : 1500))
2112 return -EINVAL;
2113 dev->mtu = new_mtu;
2114 return 0;
2115 }
2116
2117 /* Change the Ethernet address of the NIC.
2118 *
2119 * The hypervisor driver does not support changing MAC address. However,
2120 * the hardware does not do anything with the MAC address, so the address
2121 * which gets used on outgoing packets, and which is accepted on incoming
2122 * packets, is completely up to us.
2123 *
2124 * Returns 0 on success, negative on failure.
2125 */
2126 static int tile_net_set_mac_address(struct net_device *dev, void *p)
2127 {
2128 struct sockaddr *addr = p;
2129
2130 if (!is_valid_ether_addr(addr->sa_data))
2131 return -EINVAL;
2132 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2133 return 0;
2134 }
2135
2136 #ifdef CONFIG_NET_POLL_CONTROLLER
2137 /* Polling 'interrupt' - used by things like netconsole to send skbs
2138 * without having to re-enable interrupts. It's not called while
2139 * the interrupt routine is executing.
2140 */
2141 static void tile_net_netpoll(struct net_device *dev)
2142 {
2143 int instance = mpipe_instance(dev);
2144 struct tile_net_info *info = &__get_cpu_var(per_cpu_info);
2145 struct mpipe_data *md = &mpipe_data[instance];
2146
2147 disable_percpu_irq(md->ingress_irq);
2148 napi_schedule(&info->mpipe[instance].napi);
2149 enable_percpu_irq(md->ingress_irq, 0);
2150 }
2151 #endif
2152
2153 static const struct net_device_ops tile_net_ops = {
2154 .ndo_open = tile_net_open,
2155 .ndo_stop = tile_net_stop,
2156 .ndo_start_xmit = tile_net_tx,
2157 .ndo_select_queue = tile_net_select_queue,
2158 .ndo_do_ioctl = tile_net_ioctl,
2159 .ndo_change_mtu = tile_net_change_mtu,
2160 .ndo_tx_timeout = tile_net_tx_timeout,
2161 .ndo_set_mac_address = tile_net_set_mac_address,
2162 #ifdef CONFIG_NET_POLL_CONTROLLER
2163 .ndo_poll_controller = tile_net_netpoll,
2164 #endif
2165 };
2166
2167 /* The setup function.
2168 *
2169 * This uses ether_setup() to assign various fields in dev, including
2170 * setting IFF_BROADCAST and IFF_MULTICAST, then sets some extra fields.
2171 */
2172 static void tile_net_setup(struct net_device *dev)
2173 {
2174 netdev_features_t features = 0;
2175
2176 ether_setup(dev);
2177 dev->netdev_ops = &tile_net_ops;
2178 dev->watchdog_timeo = TILE_NET_TIMEOUT;
2179 dev->mtu = 1500;
2180
2181 features |= NETIF_F_HW_CSUM;
2182 features |= NETIF_F_SG;
2183 features |= NETIF_F_TSO;
2184 features |= NETIF_F_TSO6;
2185
2186 dev->hw_features |= features;
2187 dev->vlan_features |= features;
2188 dev->features |= features;
2189 }
2190
2191 /* Allocate the device structure, register the device, and obtain the
2192 * MAC address from the hypervisor.
2193 */
2194 static void tile_net_dev_init(const char *name, const uint8_t *mac)
2195 {
2196 int ret;
2197 int i;
2198 int nz_addr = 0;
2199 struct net_device *dev;
2200 struct tile_net_priv *priv;
2201
2202 /* HACK: Ignore "loop" links. */
2203 if (strncmp(name, "loop", 4) == 0)
2204 return;
2205
2206 /* Allocate the device structure. Normally, "name" is a
2207 * template, instantiated by register_netdev(), but not for us.
2208 */
2209 dev = alloc_netdev_mqs(sizeof(*priv), name, tile_net_setup,
2210 NR_CPUS, 1);
2211 if (!dev) {
2212 pr_err("alloc_netdev_mqs(%s) failed\n", name);
2213 return;
2214 }
2215
2216 /* Initialize "priv". */
2217 priv = netdev_priv(dev);
2218 memset(priv, 0, sizeof(*priv));
2219 priv->dev = dev;
2220 priv->channel = -1;
2221 priv->loopify_channel = -1;
2222 priv->echannel = -1;
2223 init_ptp_dev(priv);
2224
2225 /* Get the MAC address and set it in the device struct; this must
2226 * be done before the device is opened. If the MAC is all zeroes,
2227 * we use a random address, since we're probably on the simulator.
2228 */
2229 for (i = 0; i < 6; i++)
2230 nz_addr |= mac[i];
2231
2232 if (nz_addr) {
2233 memcpy(dev->dev_addr, mac, 6);
2234 dev->addr_len = 6;
2235 } else {
2236 eth_hw_addr_random(dev);
2237 }
2238
2239 /* Register the network device. */
2240 ret = register_netdev(dev);
2241 if (ret) {
2242 netdev_err(dev, "register_netdev failed %d\n", ret);
2243 free_netdev(dev);
2244 return;
2245 }
2246 }
2247
2248 /* Per-cpu module initialization. */
2249 static void tile_net_init_module_percpu(void *unused)
2250 {
2251 struct tile_net_info *info = &__get_cpu_var(per_cpu_info);
2252 int my_cpu = smp_processor_id();
2253 int instance;
2254
2255 for (instance = 0; instance < NR_MPIPE_MAX; instance++) {
2256 info->mpipe[instance].has_iqueue = false;
2257 info->mpipe[instance].instance = instance;
2258 }
2259 info->my_cpu = my_cpu;
2260
2261 /* Initialize the egress timer. */
2262 hrtimer_init(&info->egress_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2263 info->egress_timer.function = tile_net_handle_egress_timer;
2264 }
2265
2266 /* Module initialization. */
2267 static int __init tile_net_init_module(void)
2268 {
2269 int i;
2270 char name[GXIO_MPIPE_LINK_NAME_LEN];
2271 uint8_t mac[6];
2272
2273 pr_info("Tilera Network Driver\n");
2274
2275 BUILD_BUG_ON(NR_MPIPE_MAX != 2);
2276
2277 mutex_init(&tile_net_devs_for_channel_mutex);
2278
2279 /* Initialize each CPU. */
2280 on_each_cpu(tile_net_init_module_percpu, NULL, 1);
2281
2282 /* Find out what devices we have, and initialize them. */
2283 for (i = 0; gxio_mpipe_link_enumerate_mac(i, name, mac) >= 0; i++)
2284 tile_net_dev_init(name, mac);
2285
2286 if (!network_cpus_init())
2287 network_cpus_map = *cpu_online_mask;
2288
2289 return 0;
2290 }
2291
2292 module_init(tile_net_init_module);
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