drivers/net/ethernet/tundra/tsi108_eth.h

   1 /*
   2  * (C) Copyright 2005 Tundra Semiconductor Corp.
   3  * Kong Lai, <kong.lai@tundra.com).
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 /*
  23  * net/tsi108_eth.h - definitions for Tsi108 GIGE network controller.
  24  */
  25
  26 #ifndef __TSI108_ETH_H
  27 #define __TSI108_ETH_H
  28
  29 #include <linux/types.h>
  30
  31 #define TSI_WRITE(offset, val) \
  32         out_be32((data->regs + (offset)), val)
  33
  34 #define TSI_READ(offset) \
  35         in_be32((data->regs + (offset)))
  36
  37 #define TSI_WRITE_PHY(offset, val) \
  38         out_be32((data->phyregs + (offset)), val)
  39
  40 #define TSI_READ_PHY(offset) \
  41         in_be32((data->phyregs + (offset)))
  42
  43 /*
  44  * TSI108 GIGE port registers
  45  */
  46
  47 #define TSI108_ETH_PORT_NUM             2
  48 #define TSI108_PBM_PORT                 2
  49 #define TSI108_SDRAM_PORT               4
  50
  51 #define TSI108_MAC_CFG1                 (0x000)
  52 #define TSI108_MAC_CFG1_SOFTRST         (1 << 31)
  53 #define TSI108_MAC_CFG1_LOOPBACK        (1 << 8)
  54 #define TSI108_MAC_CFG1_RXEN            (1 << 2)
  55 #define TSI108_MAC_CFG1_TXEN            (1 << 0)
  56
  57 #define TSI108_MAC_CFG2                 (0x004)
  58 #define TSI108_MAC_CFG2_DFLT_PREAMBLE   (7 << 12)
  59 #define TSI108_MAC_CFG2_IFACE_MASK      (3 << 8)
  60 #define TSI108_MAC_CFG2_NOGIG           (1 << 8)
  61 #define TSI108_MAC_CFG2_GIG             (2 << 8)
  62 #define TSI108_MAC_CFG2_PADCRC          (1 << 2)
  63 #define TSI108_MAC_CFG2_FULLDUPLEX      (1 << 0)
  64
  65 #define TSI108_MAC_MII_MGMT_CFG         (0x020)
  66 #define TSI108_MAC_MII_MGMT_CLK         (7 << 0)
  67 #define TSI108_MAC_MII_MGMT_RST         (1 << 31)
  68
  69 #define TSI108_MAC_MII_CMD              (0x024)
  70 #define TSI108_MAC_MII_CMD_READ         (1 << 0)
  71
  72 #define TSI108_MAC_MII_ADDR             (0x028)
  73 #define TSI108_MAC_MII_ADDR_REG         0
  74 #define TSI108_MAC_MII_ADDR_PHY         8
  75
  76 #define TSI108_MAC_MII_DATAOUT          (0x02c)
  77 #define TSI108_MAC_MII_DATAIN           (0x030)
  78
  79 #define TSI108_MAC_MII_IND              (0x034)
  80 #define TSI108_MAC_MII_IND_NOTVALID     (1 << 2)
  81 #define TSI108_MAC_MII_IND_SCANNING     (1 << 1)
  82 #define TSI108_MAC_MII_IND_BUSY         (1 << 0)
  83
  84 #define TSI108_MAC_IFCTRL               (0x038)
  85 #define TSI108_MAC_IFCTRL_PHYMODE       (1 << 24)
  86
  87 #define TSI108_MAC_ADDR1                (0x040)
  88 #define TSI108_MAC_ADDR2                (0x044)
  89
  90 #define TSI108_STAT_RXBYTES             (0x06c)
  91 #define TSI108_STAT_RXBYTES_CARRY       (1 << 24)
  92
  93 #define TSI108_STAT_RXPKTS              (0x070)
  94 #define TSI108_STAT_RXPKTS_CARRY        (1 << 18)
  95
  96 #define TSI108_STAT_RXFCS               (0x074)
  97 #define TSI108_STAT_RXFCS_CARRY         (1 << 12)
  98
  99 #define TSI108_STAT_RXMCAST             (0x078)
 100 #define TSI108_STAT_RXMCAST_CARRY       (1 << 18)
 101
 102 #define TSI108_STAT_RXALIGN             (0x08c)
 103 #define TSI108_STAT_RXALIGN_CARRY       (1 << 12)
 104
 105 #define TSI108_STAT_RXLENGTH            (0x090)
 106 #define TSI108_STAT_RXLENGTH_CARRY      (1 << 12)
 107
 108 #define TSI108_STAT_RXRUNT              (0x09c)
 109 #define TSI108_STAT_RXRUNT_CARRY        (1 << 12)
 110
 111 #define TSI108_STAT_RXJUMBO             (0x0a0)
 112 #define TSI108_STAT_RXJUMBO_CARRY       (1 << 12)
 113
 114 #define TSI108_STAT_RXFRAG              (0x0a4)
 115 #define TSI108_STAT_RXFRAG_CARRY        (1 << 12)
 116
 117 #define TSI108_STAT_RXJABBER            (0x0a8)
 118 #define TSI108_STAT_RXJABBER_CARRY      (1 << 12)
 119
 120 #define TSI108_STAT_RXDROP              (0x0ac)
 121 #define TSI108_STAT_RXDROP_CARRY        (1 << 12)
 122
 123 #define TSI108_STAT_TXBYTES             (0x0b0)
 124 #define TSI108_STAT_TXBYTES_CARRY       (1 << 24)
 125
 126 #define TSI108_STAT_TXPKTS              (0x0b4)
 127 #define TSI108_STAT_TXPKTS_CARRY        (1 << 18)
 128
 129 #define TSI108_STAT_TXEXDEF             (0x0c8)
 130 #define TSI108_STAT_TXEXDEF_CARRY       (1 << 12)
 131
 132 #define TSI108_STAT_TXEXCOL             (0x0d8)
 133 #define TSI108_STAT_TXEXCOL_CARRY       (1 << 12)
 134
 135 #define TSI108_STAT_TXTCOL              (0x0dc)
 136 #define TSI108_STAT_TXTCOL_CARRY        (1 << 13)
 137
 138 #define TSI108_STAT_TXPAUSEDROP         (0x0e4)
 139 #define TSI108_STAT_TXPAUSEDROP_CARRY   (1 << 12)
 140
 141 #define TSI108_STAT_CARRY1              (0x100)
 142 #define TSI108_STAT_CARRY1_RXBYTES      (1 << 16)
 143 #define TSI108_STAT_CARRY1_RXPKTS       (1 << 15)
 144 #define TSI108_STAT_CARRY1_RXFCS        (1 << 14)
 145 #define TSI108_STAT_CARRY1_RXMCAST      (1 << 13)
 146 #define TSI108_STAT_CARRY1_RXALIGN      (1 << 8)
 147 #define TSI108_STAT_CARRY1_RXLENGTH     (1 << 7)
 148 #define TSI108_STAT_CARRY1_RXRUNT       (1 << 4)
 149 #define TSI108_STAT_CARRY1_RXJUMBO      (1 << 3)
 150 #define TSI108_STAT_CARRY1_RXFRAG       (1 << 2)
 151 #define TSI108_STAT_CARRY1_RXJABBER     (1 << 1)
 152 #define TSI108_STAT_CARRY1_RXDROP       (1 << 0)
 153
 154 #define TSI108_STAT_CARRY2              (0x104)
 155 #define TSI108_STAT_CARRY2_TXBYTES      (1 << 13)
 156 #define TSI108_STAT_CARRY2_TXPKTS       (1 << 12)
 157 #define TSI108_STAT_CARRY2_TXEXDEF      (1 << 7)
 158 #define TSI108_STAT_CARRY2_TXEXCOL      (1 << 3)
 159 #define TSI108_STAT_CARRY2_TXTCOL       (1 << 2)
 160 #define TSI108_STAT_CARRY2_TXPAUSE      (1 << 0)
 161
 162 #define TSI108_STAT_CARRYMASK1          (0x108)
 163 #define TSI108_STAT_CARRYMASK2          (0x10c)
 164
 165 #define TSI108_EC_PORTCTRL              (0x200)
 166 #define TSI108_EC_PORTCTRL_STATRST      (1 << 31)
 167 #define TSI108_EC_PORTCTRL_STATEN       (1 << 28)
 168 #define TSI108_EC_PORTCTRL_NOGIG        (1 << 18)
 169 #define TSI108_EC_PORTCTRL_HALFDUPLEX   (1 << 16)
 170
 171 #define TSI108_EC_INTSTAT               (0x204)
 172 #define TSI108_EC_INTMASK               (0x208)
 173
 174 #define TSI108_INT_ANY                  (1 << 31)
 175 #define TSI108_INT_SFN                  (1 << 30)
 176 #define TSI108_INT_RXIDLE               (1 << 29)
 177 #define TSI108_INT_RXABORT              (1 << 28)
 178 #define TSI108_INT_RXERROR              (1 << 27)
 179 #define TSI108_INT_RXOVERRUN            (1 << 26)
 180 #define TSI108_INT_RXTHRESH             (1 << 25)
 181 #define TSI108_INT_RXWAIT               (1 << 24)
 182 #define TSI108_INT_RXQUEUE0             (1 << 16)
 183 #define TSI108_INT_STATCARRY            (1 << 15)
 184 #define TSI108_INT_TXIDLE               (1 << 13)
 185 #define TSI108_INT_TXABORT              (1 << 12)
 186 #define TSI108_INT_TXERROR              (1 << 11)
 187 #define TSI108_INT_TXUNDERRUN           (1 << 10)
 188 #define TSI108_INT_TXTHRESH             (1 <<  9)
 189 #define TSI108_INT_TXWAIT               (1 <<  8)
 190 #define TSI108_INT_TXQUEUE0             (1 <<  0)
 191
 192 #define TSI108_EC_TXCFG                 (0x220)
 193 #define TSI108_EC_TXCFG_RST             (1 << 31)
 194
 195 #define TSI108_EC_TXCTRL                (0x224)
 196 #define TSI108_EC_TXCTRL_IDLEINT        (1 << 31)
 197 #define TSI108_EC_TXCTRL_ABORT          (1 << 30)
 198 #define TSI108_EC_TXCTRL_GO             (1 << 15)
 199 #define TSI108_EC_TXCTRL_QUEUE0         (1 <<  0)
 200
 201 #define TSI108_EC_TXSTAT                (0x228)
 202 #define TSI108_EC_TXSTAT_ACTIVE         (1 << 15)
 203 #define TSI108_EC_TXSTAT_QUEUE0         (1 << 0)
 204
 205 #define TSI108_EC_TXESTAT               (0x22c)
 206 #define TSI108_EC_TXESTAT_Q0_ERR        (1 << 24)
 207 #define TSI108_EC_TXESTAT_Q0_DESCINT    (1 << 16)
 208 #define TSI108_EC_TXESTAT_Q0_EOF        (1 <<  8)
 209 #define TSI108_EC_TXESTAT_Q0_EOQ        (1 <<  0)
 210
 211 #define TSI108_EC_TXERR                 (0x278)
 212
 213 #define TSI108_EC_TXQ_CFG               (0x280)
 214 #define TSI108_EC_TXQ_CFG_DESC_INT      (1 << 20)
 215 #define TSI108_EC_TXQ_CFG_EOQ_OWN_INT   (1 << 19)
 216 #define TSI108_EC_TXQ_CFG_WSWP          (1 << 11)
 217 #define TSI108_EC_TXQ_CFG_BSWP          (1 << 10)
 218 #define TSI108_EC_TXQ_CFG_SFNPORT       0
 219
 220 #define TSI108_EC_TXQ_BUFCFG            (0x284)
 221 #define TSI108_EC_TXQ_BUFCFG_BURST8     (0 << 8)
 222 #define TSI108_EC_TXQ_BUFCFG_BURST32    (1 << 8)
 223 #define TSI108_EC_TXQ_BUFCFG_BURST128   (2 << 8)
 224 #define TSI108_EC_TXQ_BUFCFG_BURST256   (3 << 8)
 225 #define TSI108_EC_TXQ_BUFCFG_WSWP       (1 << 11)
 226 #define TSI108_EC_TXQ_BUFCFG_BSWP       (1 << 10)
 227 #define TSI108_EC_TXQ_BUFCFG_SFNPORT    0
 228
 229 #define TSI108_EC_TXQ_PTRLOW            (0x288)
 230
 231 #define TSI108_EC_TXQ_PTRHIGH           (0x28c)
 232 #define TSI108_EC_TXQ_PTRHIGH_VALID     (1 << 31)
 233
 234 #define TSI108_EC_TXTHRESH              (0x230)
 235 #define TSI108_EC_TXTHRESH_STARTFILL    0
 236 #define TSI108_EC_TXTHRESH_STOPFILL     16
 237
 238 #define TSI108_EC_RXCFG                 (0x320)
 239 #define TSI108_EC_RXCFG_RST             (1 << 31)
 240
 241 #define TSI108_EC_RXSTAT                (0x328)
 242 #define TSI108_EC_RXSTAT_ACTIVE         (1 << 15)
 243 #define TSI108_EC_RXSTAT_QUEUE0         (1 << 0)
 244
 245 #define TSI108_EC_RXESTAT               (0x32c)
 246 #define TSI108_EC_RXESTAT_Q0_ERR        (1 << 24)
 247 #define TSI108_EC_RXESTAT_Q0_DESCINT    (1 << 16)
 248 #define TSI108_EC_RXESTAT_Q0_EOF        (1 <<  8)
 249 #define TSI108_EC_RXESTAT_Q0_EOQ        (1 <<  0)
 250
 251 #define TSI108_EC_HASHADDR              (0x360)
 252 #define TSI108_EC_HASHADDR_AUTOINC      (1 << 31)
 253 #define TSI108_EC_HASHADDR_DO1STREAD    (1 << 30)
 254 #define TSI108_EC_HASHADDR_UNICAST      (0 <<  4)
 255 #define TSI108_EC_HASHADDR_MCAST        (1 <<  4)
 256
 257 #define TSI108_EC_HASHDATA              (0x364)
 258
 259 #define TSI108_EC_RXQ_PTRLOW            (0x388)
 260
 261 #define TSI108_EC_RXQ_PTRHIGH           (0x38c)
 262 #define TSI108_EC_RXQ_PTRHIGH_VALID     (1 << 31)
 263
 264 /* Station Enable -- accept packets destined for us */
 265 #define TSI108_EC_RXCFG_SE              (1 << 13)
 266 /* Unicast Frame Enable -- for packets not destined for us */
 267 #define TSI108_EC_RXCFG_UFE             (1 << 12)
 268 /* Multicast Frame Enable */
 269 #define TSI108_EC_RXCFG_MFE             (1 << 11)
 270 /* Broadcast Frame Enable */
 271 #define TSI108_EC_RXCFG_BFE             (1 << 10)
 272 #define TSI108_EC_RXCFG_UC_HASH         (1 <<  9)
 273 #define TSI108_EC_RXCFG_MC_HASH         (1 <<  8)
 274
 275 #define TSI108_EC_RXQ_CFG               (0x380)
 276 #define TSI108_EC_RXQ_CFG_DESC_INT      (1 << 20)
 277 #define TSI108_EC_RXQ_CFG_EOQ_OWN_INT   (1 << 19)
 278 #define TSI108_EC_RXQ_CFG_WSWP          (1 << 11)
 279 #define TSI108_EC_RXQ_CFG_BSWP          (1 << 10)
 280 #define TSI108_EC_RXQ_CFG_SFNPORT       0
 281
 282 #define TSI108_EC_RXQ_BUFCFG            (0x384)
 283 #define TSI108_EC_RXQ_BUFCFG_BURST8     (0 << 8)
 284 #define TSI108_EC_RXQ_BUFCFG_BURST32    (1 << 8)
 285 #define TSI108_EC_RXQ_BUFCFG_BURST128   (2 << 8)
 286 #define TSI108_EC_RXQ_BUFCFG_BURST256   (3 << 8)
 287 #define TSI108_EC_RXQ_BUFCFG_WSWP       (1 << 11)
 288 #define TSI108_EC_RXQ_BUFCFG_BSWP       (1 << 10)
 289 #define TSI108_EC_RXQ_BUFCFG_SFNPORT    0
 290
 291 #define TSI108_EC_RXCTRL                (0x324)
 292 #define TSI108_EC_RXCTRL_ABORT          (1 << 30)
 293 #define TSI108_EC_RXCTRL_GO             (1 << 15)
 294 #define TSI108_EC_RXCTRL_QUEUE0         (1 << 0)
 295
 296 #define TSI108_EC_RXERR                 (0x378)
 297
 298 #define TSI108_TX_EOF   (1 << 0)        /* End of frame; last fragment of packet */
 299 #define TSI108_TX_SOF   (1 << 1)        /* Start of frame; first frag. of packet */
 300 #define TSI108_TX_VLAN  (1 << 2)        /* Per-frame VLAN: enables VLAN override */
 301 #define TSI108_TX_HUGE  (1 << 3)        /* Huge frame enable */
 302 #define TSI108_TX_PAD   (1 << 4)        /* Pad the packet if too short */
 303 #define TSI108_TX_CRC   (1 << 5)        /* Generate CRC for this packet */
 304 #define TSI108_TX_INT   (1 << 14)       /* Generate an IRQ after frag. processed */
 305 #define TSI108_TX_RETRY (0xf << 16)     /* 4 bit field indicating num. of retries */
 306 #define TSI108_TX_COL   (1 << 20)       /* Set if a collision occurred */
 307 #define TSI108_TX_LCOL  (1 << 24)       /* Set if a late collision occurred */
 308 #define TSI108_TX_UNDER (1 << 25)       /* Set if a FIFO underrun occurred */
 309 #define TSI108_TX_RLIM  (1 << 26)       /* Set if the retry limit was reached */
 310 #define TSI108_TX_OK    (1 << 30)       /* Set if the frame TX was successful */
 311 #define TSI108_TX_OWN   (1 << 31)       /* Set if the device owns the descriptor */
 312
 313 /* Note: the descriptor layouts assume big-endian byte order. */
 314 typedef struct {
 315         u32 buf0;
 316         u32 buf1;               /* Base address of buffer */
 317         u32 next0;              /* Address of next descriptor, if any */
 318         u32 next1;
 319         u16 vlan;               /* VLAN, if override enabled for this packet */
 320         u16 len;                /* Length of buffer in bytes */
 321         u32 misc;               /* See TSI108_TX_* above */
 322         u32 reserved0;          /*reserved0 and reserved1 are added to make the desc */
 323         u32 reserved1;          /* 32-byte aligned */
 324 } __attribute__ ((aligned(32))) tx_desc;
 325
 326 #define TSI108_RX_EOF   (1 << 0)        /* End of frame; last fragment of packet */
 327 #define TSI108_RX_SOF   (1 << 1)        /* Start of frame; first frag. of packet */
 328 #define TSI108_RX_VLAN  (1 << 2)        /* Set on SOF if packet has a VLAN */
 329 #define TSI108_RX_FTYPE (1 << 3)        /* Length/Type field is type, not length */
 330 #define TSI108_RX_RUNT  (1 << 4)/* Packet is less than minimum size */
 331 #define TSI108_RX_HASH  (1 << 7)/* Hash table match */
 332 #define TSI108_RX_BAD   (1 << 8)        /* Bad frame */
 333 #define TSI108_RX_OVER  (1 << 9)        /* FIFO overrun occurred */
 334 #define TSI108_RX_TRUNC (1 << 11)       /* Packet truncated due to excess length */
 335 #define TSI108_RX_CRC   (1 << 12)       /* Packet had a CRC error */
 336 #define TSI108_RX_INT   (1 << 13)       /* Generate an IRQ after frag. processed */
 337 #define TSI108_RX_OWN   (1 << 15)       /* Set if the device owns the descriptor */
 338
 339 #define TSI108_RX_SKB_SIZE 1536         /* The RX skb length */
 340
 341 typedef struct {
 342         u32 buf0;               /* Base address of buffer */
 343         u32 buf1;               /* Base address of buffer */
 344         u32 next0;              /* Address of next descriptor, if any */
 345         u32 next1;              /* Address of next descriptor, if any */
 346         u16 vlan;               /* VLAN of received packet, first frag only */
 347         u16 len;                /* Length of received fragment in bytes */
 348         u16 blen;               /* Length of buffer in bytes */
 349         u16 misc;               /* See TSI108_RX_* above */
 350         u32 reserved0;          /* reserved0 and reserved1 are added to make the desc */
 351         u32 reserved1;          /* 32-byte aligned */
 352 } __attribute__ ((aligned(32))) rx_desc;
 353
 354 #endif                          /* __TSI108_ETH_H */