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Input: elantech - discard the first 2 positions on some firmwares
[deliverable/linux.git] / drivers / net / ethoc.c
1 /*
2 * linux/drivers/net/ethoc.c
3 *
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
12 */
13
14 #include <linux/etherdevice.h>
15 #include <linux/crc32.h>
16 #include <linux/io.h>
17 #include <linux/mii.h>
18 #include <linux/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/sched.h>
21 #include <linux/slab.h>
22 #include <net/ethoc.h>
23
24 static int buffer_size = 0x8000; /* 32 KBytes */
25 module_param(buffer_size, int, 0);
26 MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
27
28 /* register offsets */
29 #define MODER 0x00
30 #define INT_SOURCE 0x04
31 #define INT_MASK 0x08
32 #define IPGT 0x0c
33 #define IPGR1 0x10
34 #define IPGR2 0x14
35 #define PACKETLEN 0x18
36 #define COLLCONF 0x1c
37 #define TX_BD_NUM 0x20
38 #define CTRLMODER 0x24
39 #define MIIMODER 0x28
40 #define MIICOMMAND 0x2c
41 #define MIIADDRESS 0x30
42 #define MIITX_DATA 0x34
43 #define MIIRX_DATA 0x38
44 #define MIISTATUS 0x3c
45 #define MAC_ADDR0 0x40
46 #define MAC_ADDR1 0x44
47 #define ETH_HASH0 0x48
48 #define ETH_HASH1 0x4c
49 #define ETH_TXCTRL 0x50
50
51 /* mode register */
52 #define MODER_RXEN (1 << 0) /* receive enable */
53 #define MODER_TXEN (1 << 1) /* transmit enable */
54 #define MODER_NOPRE (1 << 2) /* no preamble */
55 #define MODER_BRO (1 << 3) /* broadcast address */
56 #define MODER_IAM (1 << 4) /* individual address mode */
57 #define MODER_PRO (1 << 5) /* promiscuous mode */
58 #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
59 #define MODER_LOOP (1 << 7) /* loopback */
60 #define MODER_NBO (1 << 8) /* no back-off */
61 #define MODER_EDE (1 << 9) /* excess defer enable */
62 #define MODER_FULLD (1 << 10) /* full duplex */
63 #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
64 #define MODER_DCRC (1 << 12) /* delayed CRC enable */
65 #define MODER_CRC (1 << 13) /* CRC enable */
66 #define MODER_HUGE (1 << 14) /* huge packets enable */
67 #define MODER_PAD (1 << 15) /* padding enabled */
68 #define MODER_RSM (1 << 16) /* receive small packets */
69
70 /* interrupt source and mask registers */
71 #define INT_MASK_TXF (1 << 0) /* transmit frame */
72 #define INT_MASK_TXE (1 << 1) /* transmit error */
73 #define INT_MASK_RXF (1 << 2) /* receive frame */
74 #define INT_MASK_RXE (1 << 3) /* receive error */
75 #define INT_MASK_BUSY (1 << 4)
76 #define INT_MASK_TXC (1 << 5) /* transmit control frame */
77 #define INT_MASK_RXC (1 << 6) /* receive control frame */
78
79 #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
80 #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
81
82 #define INT_MASK_ALL ( \
83 INT_MASK_TXF | INT_MASK_TXE | \
84 INT_MASK_RXF | INT_MASK_RXE | \
85 INT_MASK_TXC | INT_MASK_RXC | \
86 INT_MASK_BUSY \
87 )
88
89 /* packet length register */
90 #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
91 #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
92 #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
93 PACKETLEN_MAX(max))
94
95 /* transmit buffer number register */
96 #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
97
98 /* control module mode register */
99 #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
100 #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
101 #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
102
103 /* MII mode register */
104 #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
105 #define MIIMODER_NOPRE (1 << 8) /* no preamble */
106
107 /* MII command register */
108 #define MIICOMMAND_SCAN (1 << 0) /* scan status */
109 #define MIICOMMAND_READ (1 << 1) /* read status */
110 #define MIICOMMAND_WRITE (1 << 2) /* write control data */
111
112 /* MII address register */
113 #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
114 #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
115 #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
116 MIIADDRESS_RGAD(reg))
117
118 /* MII transmit data register */
119 #define MIITX_DATA_VAL(x) ((x) & 0xffff)
120
121 /* MII receive data register */
122 #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
123
124 /* MII status register */
125 #define MIISTATUS_LINKFAIL (1 << 0)
126 #define MIISTATUS_BUSY (1 << 1)
127 #define MIISTATUS_INVALID (1 << 2)
128
129 /* TX buffer descriptor */
130 #define TX_BD_CS (1 << 0) /* carrier sense lost */
131 #define TX_BD_DF (1 << 1) /* defer indication */
132 #define TX_BD_LC (1 << 2) /* late collision */
133 #define TX_BD_RL (1 << 3) /* retransmission limit */
134 #define TX_BD_RETRY_MASK (0x00f0)
135 #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
136 #define TX_BD_UR (1 << 8) /* transmitter underrun */
137 #define TX_BD_CRC (1 << 11) /* TX CRC enable */
138 #define TX_BD_PAD (1 << 12) /* pad enable for short packets */
139 #define TX_BD_WRAP (1 << 13)
140 #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
141 #define TX_BD_READY (1 << 15) /* TX buffer ready */
142 #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
143 #define TX_BD_LEN_MASK (0xffff << 16)
144
145 #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
146 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
147
148 /* RX buffer descriptor */
149 #define RX_BD_LC (1 << 0) /* late collision */
150 #define RX_BD_CRC (1 << 1) /* RX CRC error */
151 #define RX_BD_SF (1 << 2) /* short frame */
152 #define RX_BD_TL (1 << 3) /* too long */
153 #define RX_BD_DN (1 << 4) /* dribble nibble */
154 #define RX_BD_IS (1 << 5) /* invalid symbol */
155 #define RX_BD_OR (1 << 6) /* receiver overrun */
156 #define RX_BD_MISS (1 << 7)
157 #define RX_BD_CF (1 << 8) /* control frame */
158 #define RX_BD_WRAP (1 << 13)
159 #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
160 #define RX_BD_EMPTY (1 << 15)
161 #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
162
163 #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
164 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
165
166 #define ETHOC_BUFSIZ 1536
167 #define ETHOC_ZLEN 64
168 #define ETHOC_BD_BASE 0x400
169 #define ETHOC_TIMEOUT (HZ / 2)
170 #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
171
172 /**
173 * struct ethoc - driver-private device structure
174 * @iobase: pointer to I/O memory region
175 * @membase: pointer to buffer memory region
176 * @dma_alloc: dma allocated buffer size
177 * @io_region_size: I/O memory region size
178 * @num_tx: number of send buffers
179 * @cur_tx: last send buffer written
180 * @dty_tx: last buffer actually sent
181 * @num_rx: number of receive buffers
182 * @cur_rx: current receive buffer
183 * @netdev: pointer to network device structure
184 * @napi: NAPI structure
185 * @stats: network device statistics
186 * @msg_enable: device state flags
187 * @rx_lock: receive lock
188 * @lock: device lock
189 * @phy: attached PHY
190 * @mdio: MDIO bus for PHY access
191 * @phy_id: address of attached PHY
192 */
193 struct ethoc {
194 void __iomem *iobase;
195 void __iomem *membase;
196 int dma_alloc;
197 resource_size_t io_region_size;
198
199 unsigned int num_tx;
200 unsigned int cur_tx;
201 unsigned int dty_tx;
202
203 unsigned int num_rx;
204 unsigned int cur_rx;
205
206 struct net_device *netdev;
207 struct napi_struct napi;
208 struct net_device_stats stats;
209 u32 msg_enable;
210
211 spinlock_t rx_lock;
212 spinlock_t lock;
213
214 struct phy_device *phy;
215 struct mii_bus *mdio;
216 s8 phy_id;
217 };
218
219 /**
220 * struct ethoc_bd - buffer descriptor
221 * @stat: buffer statistics
222 * @addr: physical memory address
223 */
224 struct ethoc_bd {
225 u32 stat;
226 u32 addr;
227 };
228
229 static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
230 {
231 return ioread32(dev->iobase + offset);
232 }
233
234 static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
235 {
236 iowrite32(data, dev->iobase + offset);
237 }
238
239 static inline void ethoc_read_bd(struct ethoc *dev, int index,
240 struct ethoc_bd *bd)
241 {
242 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
243 bd->stat = ethoc_read(dev, offset + 0);
244 bd->addr = ethoc_read(dev, offset + 4);
245 }
246
247 static inline void ethoc_write_bd(struct ethoc *dev, int index,
248 const struct ethoc_bd *bd)
249 {
250 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
251 ethoc_write(dev, offset + 0, bd->stat);
252 ethoc_write(dev, offset + 4, bd->addr);
253 }
254
255 static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
256 {
257 u32 imask = ethoc_read(dev, INT_MASK);
258 imask |= mask;
259 ethoc_write(dev, INT_MASK, imask);
260 }
261
262 static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
263 {
264 u32 imask = ethoc_read(dev, INT_MASK);
265 imask &= ~mask;
266 ethoc_write(dev, INT_MASK, imask);
267 }
268
269 static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
270 {
271 ethoc_write(dev, INT_SOURCE, mask);
272 }
273
274 static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
275 {
276 u32 mode = ethoc_read(dev, MODER);
277 mode |= MODER_RXEN | MODER_TXEN;
278 ethoc_write(dev, MODER, mode);
279 }
280
281 static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
282 {
283 u32 mode = ethoc_read(dev, MODER);
284 mode &= ~(MODER_RXEN | MODER_TXEN);
285 ethoc_write(dev, MODER, mode);
286 }
287
288 static int ethoc_init_ring(struct ethoc *dev)
289 {
290 struct ethoc_bd bd;
291 int i;
292
293 dev->cur_tx = 0;
294 dev->dty_tx = 0;
295 dev->cur_rx = 0;
296
297 /* setup transmission buffers */
298 bd.addr = virt_to_phys(dev->membase);
299 bd.stat = TX_BD_IRQ | TX_BD_CRC;
300
301 for (i = 0; i < dev->num_tx; i++) {
302 if (i == dev->num_tx - 1)
303 bd.stat |= TX_BD_WRAP;
304
305 ethoc_write_bd(dev, i, &bd);
306 bd.addr += ETHOC_BUFSIZ;
307 }
308
309 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
310
311 for (i = 0; i < dev->num_rx; i++) {
312 if (i == dev->num_rx - 1)
313 bd.stat |= RX_BD_WRAP;
314
315 ethoc_write_bd(dev, dev->num_tx + i, &bd);
316 bd.addr += ETHOC_BUFSIZ;
317 }
318
319 return 0;
320 }
321
322 static int ethoc_reset(struct ethoc *dev)
323 {
324 u32 mode;
325
326 /* TODO: reset controller? */
327
328 ethoc_disable_rx_and_tx(dev);
329
330 /* TODO: setup registers */
331
332 /* enable FCS generation and automatic padding */
333 mode = ethoc_read(dev, MODER);
334 mode |= MODER_CRC | MODER_PAD;
335 ethoc_write(dev, MODER, mode);
336
337 /* set full-duplex mode */
338 mode = ethoc_read(dev, MODER);
339 mode |= MODER_FULLD;
340 ethoc_write(dev, MODER, mode);
341 ethoc_write(dev, IPGT, 0x15);
342
343 ethoc_ack_irq(dev, INT_MASK_ALL);
344 ethoc_enable_irq(dev, INT_MASK_ALL);
345 ethoc_enable_rx_and_tx(dev);
346 return 0;
347 }
348
349 static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
350 struct ethoc_bd *bd)
351 {
352 struct net_device *netdev = dev->netdev;
353 unsigned int ret = 0;
354
355 if (bd->stat & RX_BD_TL) {
356 dev_err(&netdev->dev, "RX: frame too long\n");
357 dev->stats.rx_length_errors++;
358 ret++;
359 }
360
361 if (bd->stat & RX_BD_SF) {
362 dev_err(&netdev->dev, "RX: frame too short\n");
363 dev->stats.rx_length_errors++;
364 ret++;
365 }
366
367 if (bd->stat & RX_BD_DN) {
368 dev_err(&netdev->dev, "RX: dribble nibble\n");
369 dev->stats.rx_frame_errors++;
370 }
371
372 if (bd->stat & RX_BD_CRC) {
373 dev_err(&netdev->dev, "RX: wrong CRC\n");
374 dev->stats.rx_crc_errors++;
375 ret++;
376 }
377
378 if (bd->stat & RX_BD_OR) {
379 dev_err(&netdev->dev, "RX: overrun\n");
380 dev->stats.rx_over_errors++;
381 ret++;
382 }
383
384 if (bd->stat & RX_BD_MISS)
385 dev->stats.rx_missed_errors++;
386
387 if (bd->stat & RX_BD_LC) {
388 dev_err(&netdev->dev, "RX: late collision\n");
389 dev->stats.collisions++;
390 ret++;
391 }
392
393 return ret;
394 }
395
396 static int ethoc_rx(struct net_device *dev, int limit)
397 {
398 struct ethoc *priv = netdev_priv(dev);
399 int count;
400
401 for (count = 0; count < limit; ++count) {
402 unsigned int entry;
403 struct ethoc_bd bd;
404
405 entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
406 ethoc_read_bd(priv, entry, &bd);
407 if (bd.stat & RX_BD_EMPTY)
408 break;
409
410 if (ethoc_update_rx_stats(priv, &bd) == 0) {
411 int size = bd.stat >> 16;
412 struct sk_buff *skb;
413
414 size -= 4; /* strip the CRC */
415 skb = netdev_alloc_skb_ip_align(dev, size);
416
417 if (likely(skb)) {
418 void *src = phys_to_virt(bd.addr);
419 memcpy_fromio(skb_put(skb, size), src, size);
420 skb->protocol = eth_type_trans(skb, dev);
421 priv->stats.rx_packets++;
422 priv->stats.rx_bytes += size;
423 netif_receive_skb(skb);
424 } else {
425 if (net_ratelimit())
426 dev_warn(&dev->dev, "low on memory - "
427 "packet dropped\n");
428
429 priv->stats.rx_dropped++;
430 break;
431 }
432 }
433
434 /* clear the buffer descriptor so it can be reused */
435 bd.stat &= ~RX_BD_STATS;
436 bd.stat |= RX_BD_EMPTY;
437 ethoc_write_bd(priv, entry, &bd);
438 priv->cur_rx++;
439 }
440
441 return count;
442 }
443
444 static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
445 {
446 struct net_device *netdev = dev->netdev;
447
448 if (bd->stat & TX_BD_LC) {
449 dev_err(&netdev->dev, "TX: late collision\n");
450 dev->stats.tx_window_errors++;
451 }
452
453 if (bd->stat & TX_BD_RL) {
454 dev_err(&netdev->dev, "TX: retransmit limit\n");
455 dev->stats.tx_aborted_errors++;
456 }
457
458 if (bd->stat & TX_BD_UR) {
459 dev_err(&netdev->dev, "TX: underrun\n");
460 dev->stats.tx_fifo_errors++;
461 }
462
463 if (bd->stat & TX_BD_CS) {
464 dev_err(&netdev->dev, "TX: carrier sense lost\n");
465 dev->stats.tx_carrier_errors++;
466 }
467
468 if (bd->stat & TX_BD_STATS)
469 dev->stats.tx_errors++;
470
471 dev->stats.collisions += (bd->stat >> 4) & 0xf;
472 dev->stats.tx_bytes += bd->stat >> 16;
473 dev->stats.tx_packets++;
474 return 0;
475 }
476
477 static void ethoc_tx(struct net_device *dev)
478 {
479 struct ethoc *priv = netdev_priv(dev);
480
481 spin_lock(&priv->lock);
482
483 while (priv->dty_tx != priv->cur_tx) {
484 unsigned int entry = priv->dty_tx % priv->num_tx;
485 struct ethoc_bd bd;
486
487 ethoc_read_bd(priv, entry, &bd);
488 if (bd.stat & TX_BD_READY)
489 break;
490
491 entry = (++priv->dty_tx) % priv->num_tx;
492 (void)ethoc_update_tx_stats(priv, &bd);
493 }
494
495 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
496 netif_wake_queue(dev);
497
498 ethoc_ack_irq(priv, INT_MASK_TX);
499 spin_unlock(&priv->lock);
500 }
501
502 static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
503 {
504 struct net_device *dev = (struct net_device *)dev_id;
505 struct ethoc *priv = netdev_priv(dev);
506 u32 pending;
507
508 ethoc_disable_irq(priv, INT_MASK_ALL);
509 pending = ethoc_read(priv, INT_SOURCE);
510 if (unlikely(pending == 0)) {
511 ethoc_enable_irq(priv, INT_MASK_ALL);
512 return IRQ_NONE;
513 }
514
515 ethoc_ack_irq(priv, pending);
516
517 if (pending & INT_MASK_BUSY) {
518 dev_err(&dev->dev, "packet dropped\n");
519 priv->stats.rx_dropped++;
520 }
521
522 if (pending & INT_MASK_RX) {
523 if (napi_schedule_prep(&priv->napi))
524 __napi_schedule(&priv->napi);
525 } else {
526 ethoc_enable_irq(priv, INT_MASK_RX);
527 }
528
529 if (pending & INT_MASK_TX)
530 ethoc_tx(dev);
531
532 ethoc_enable_irq(priv, INT_MASK_ALL & ~INT_MASK_RX);
533 return IRQ_HANDLED;
534 }
535
536 static int ethoc_get_mac_address(struct net_device *dev, void *addr)
537 {
538 struct ethoc *priv = netdev_priv(dev);
539 u8 *mac = (u8 *)addr;
540 u32 reg;
541
542 reg = ethoc_read(priv, MAC_ADDR0);
543 mac[2] = (reg >> 24) & 0xff;
544 mac[3] = (reg >> 16) & 0xff;
545 mac[4] = (reg >> 8) & 0xff;
546 mac[5] = (reg >> 0) & 0xff;
547
548 reg = ethoc_read(priv, MAC_ADDR1);
549 mac[0] = (reg >> 8) & 0xff;
550 mac[1] = (reg >> 0) & 0xff;
551
552 return 0;
553 }
554
555 static int ethoc_poll(struct napi_struct *napi, int budget)
556 {
557 struct ethoc *priv = container_of(napi, struct ethoc, napi);
558 int work_done = 0;
559
560 work_done = ethoc_rx(priv->netdev, budget);
561 if (work_done < budget) {
562 ethoc_enable_irq(priv, INT_MASK_RX);
563 napi_complete(napi);
564 }
565
566 return work_done;
567 }
568
569 static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
570 {
571 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
572 struct ethoc *priv = bus->priv;
573
574 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
575 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
576
577 while (time_before(jiffies, timeout)) {
578 u32 status = ethoc_read(priv, MIISTATUS);
579 if (!(status & MIISTATUS_BUSY)) {
580 u32 data = ethoc_read(priv, MIIRX_DATA);
581 /* reset MII command register */
582 ethoc_write(priv, MIICOMMAND, 0);
583 return data;
584 }
585
586 schedule();
587 }
588
589 return -EBUSY;
590 }
591
592 static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
593 {
594 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
595 struct ethoc *priv = bus->priv;
596
597 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
598 ethoc_write(priv, MIITX_DATA, val);
599 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
600
601 while (time_before(jiffies, timeout)) {
602 u32 stat = ethoc_read(priv, MIISTATUS);
603 if (!(stat & MIISTATUS_BUSY))
604 return 0;
605
606 schedule();
607 }
608
609 return -EBUSY;
610 }
611
612 static int ethoc_mdio_reset(struct mii_bus *bus)
613 {
614 return 0;
615 }
616
617 static void ethoc_mdio_poll(struct net_device *dev)
618 {
619 }
620
621 static int ethoc_mdio_probe(struct net_device *dev)
622 {
623 struct ethoc *priv = netdev_priv(dev);
624 struct phy_device *phy;
625 int i;
626
627 for (i = 0; i < PHY_MAX_ADDR; i++) {
628 phy = priv->mdio->phy_map[i];
629 if (phy) {
630 if (priv->phy_id != -1) {
631 /* attach to specified PHY */
632 if (priv->phy_id == phy->addr)
633 break;
634 } else {
635 /* autoselect PHY if none was specified */
636 if (phy->addr != 0)
637 break;
638 }
639 }
640 }
641
642 if (!phy) {
643 dev_err(&dev->dev, "no PHY found\n");
644 return -ENXIO;
645 }
646
647 phy = phy_connect(dev, dev_name(&phy->dev), ethoc_mdio_poll, 0,
648 PHY_INTERFACE_MODE_GMII);
649 if (IS_ERR(phy)) {
650 dev_err(&dev->dev, "could not attach to PHY\n");
651 return PTR_ERR(phy);
652 }
653
654 priv->phy = phy;
655 return 0;
656 }
657
658 static int ethoc_open(struct net_device *dev)
659 {
660 struct ethoc *priv = netdev_priv(dev);
661 unsigned int min_tx = 2;
662 unsigned int num_bd;
663 int ret;
664
665 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
666 dev->name, dev);
667 if (ret)
668 return ret;
669
670 /* calculate the number of TX/RX buffers, maximum 128 supported */
671 num_bd = min_t(unsigned int,
672 128, (dev->mem_end - dev->mem_start + 1) / ETHOC_BUFSIZ);
673 priv->num_tx = max(min_tx, num_bd / 4);
674 priv->num_rx = num_bd - priv->num_tx;
675 ethoc_write(priv, TX_BD_NUM, priv->num_tx);
676
677 ethoc_init_ring(priv);
678 ethoc_reset(priv);
679
680 if (netif_queue_stopped(dev)) {
681 dev_dbg(&dev->dev, " resuming queue\n");
682 netif_wake_queue(dev);
683 } else {
684 dev_dbg(&dev->dev, " starting queue\n");
685 netif_start_queue(dev);
686 }
687
688 phy_start(priv->phy);
689 napi_enable(&priv->napi);
690
691 if (netif_msg_ifup(priv)) {
692 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
693 dev->base_addr, dev->mem_start, dev->mem_end);
694 }
695
696 return 0;
697 }
698
699 static int ethoc_stop(struct net_device *dev)
700 {
701 struct ethoc *priv = netdev_priv(dev);
702
703 napi_disable(&priv->napi);
704
705 if (priv->phy)
706 phy_stop(priv->phy);
707
708 ethoc_disable_rx_and_tx(priv);
709 free_irq(dev->irq, dev);
710
711 if (!netif_queue_stopped(dev))
712 netif_stop_queue(dev);
713
714 return 0;
715 }
716
717 static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
718 {
719 struct ethoc *priv = netdev_priv(dev);
720 struct mii_ioctl_data *mdio = if_mii(ifr);
721 struct phy_device *phy = NULL;
722
723 if (!netif_running(dev))
724 return -EINVAL;
725
726 if (cmd != SIOCGMIIPHY) {
727 if (mdio->phy_id >= PHY_MAX_ADDR)
728 return -ERANGE;
729
730 phy = priv->mdio->phy_map[mdio->phy_id];
731 if (!phy)
732 return -ENODEV;
733 } else {
734 phy = priv->phy;
735 }
736
737 return phy_mii_ioctl(phy, mdio, cmd);
738 }
739
740 static int ethoc_config(struct net_device *dev, struct ifmap *map)
741 {
742 return -ENOSYS;
743 }
744
745 static int ethoc_set_mac_address(struct net_device *dev, void *addr)
746 {
747 struct ethoc *priv = netdev_priv(dev);
748 u8 *mac = (u8 *)addr;
749
750 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
751 (mac[4] << 8) | (mac[5] << 0));
752 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
753
754 return 0;
755 }
756
757 static void ethoc_set_multicast_list(struct net_device *dev)
758 {
759 struct ethoc *priv = netdev_priv(dev);
760 u32 mode = ethoc_read(priv, MODER);
761 struct netdev_hw_addr *ha;
762 u32 hash[2] = { 0, 0 };
763
764 /* set loopback mode if requested */
765 if (dev->flags & IFF_LOOPBACK)
766 mode |= MODER_LOOP;
767 else
768 mode &= ~MODER_LOOP;
769
770 /* receive broadcast frames if requested */
771 if (dev->flags & IFF_BROADCAST)
772 mode &= ~MODER_BRO;
773 else
774 mode |= MODER_BRO;
775
776 /* enable promiscuous mode if requested */
777 if (dev->flags & IFF_PROMISC)
778 mode |= MODER_PRO;
779 else
780 mode &= ~MODER_PRO;
781
782 ethoc_write(priv, MODER, mode);
783
784 /* receive multicast frames */
785 if (dev->flags & IFF_ALLMULTI) {
786 hash[0] = 0xffffffff;
787 hash[1] = 0xffffffff;
788 } else {
789 netdev_for_each_mc_addr(ha, dev) {
790 u32 crc = ether_crc(ETH_ALEN, ha->addr);
791 int bit = (crc >> 26) & 0x3f;
792 hash[bit >> 5] |= 1 << (bit & 0x1f);
793 }
794 }
795
796 ethoc_write(priv, ETH_HASH0, hash[0]);
797 ethoc_write(priv, ETH_HASH1, hash[1]);
798 }
799
800 static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
801 {
802 return -ENOSYS;
803 }
804
805 static void ethoc_tx_timeout(struct net_device *dev)
806 {
807 struct ethoc *priv = netdev_priv(dev);
808 u32 pending = ethoc_read(priv, INT_SOURCE);
809 if (likely(pending))
810 ethoc_interrupt(dev->irq, dev);
811 }
812
813 static struct net_device_stats *ethoc_stats(struct net_device *dev)
814 {
815 struct ethoc *priv = netdev_priv(dev);
816 return &priv->stats;
817 }
818
819 static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
820 {
821 struct ethoc *priv = netdev_priv(dev);
822 struct ethoc_bd bd;
823 unsigned int entry;
824 void *dest;
825
826 if (unlikely(skb->len > ETHOC_BUFSIZ)) {
827 priv->stats.tx_errors++;
828 goto out;
829 }
830
831 entry = priv->cur_tx % priv->num_tx;
832 spin_lock_irq(&priv->lock);
833 priv->cur_tx++;
834
835 ethoc_read_bd(priv, entry, &bd);
836 if (unlikely(skb->len < ETHOC_ZLEN))
837 bd.stat |= TX_BD_PAD;
838 else
839 bd.stat &= ~TX_BD_PAD;
840
841 dest = phys_to_virt(bd.addr);
842 memcpy_toio(dest, skb->data, skb->len);
843
844 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
845 bd.stat |= TX_BD_LEN(skb->len);
846 ethoc_write_bd(priv, entry, &bd);
847
848 bd.stat |= TX_BD_READY;
849 ethoc_write_bd(priv, entry, &bd);
850
851 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
852 dev_dbg(&dev->dev, "stopping queue\n");
853 netif_stop_queue(dev);
854 }
855
856 spin_unlock_irq(&priv->lock);
857 out:
858 dev_kfree_skb(skb);
859 return NETDEV_TX_OK;
860 }
861
862 static const struct net_device_ops ethoc_netdev_ops = {
863 .ndo_open = ethoc_open,
864 .ndo_stop = ethoc_stop,
865 .ndo_do_ioctl = ethoc_ioctl,
866 .ndo_set_config = ethoc_config,
867 .ndo_set_mac_address = ethoc_set_mac_address,
868 .ndo_set_multicast_list = ethoc_set_multicast_list,
869 .ndo_change_mtu = ethoc_change_mtu,
870 .ndo_tx_timeout = ethoc_tx_timeout,
871 .ndo_get_stats = ethoc_stats,
872 .ndo_start_xmit = ethoc_start_xmit,
873 };
874
875 /**
876 * ethoc_probe() - initialize OpenCores ethernet MAC
877 * pdev: platform device
878 */
879 static int ethoc_probe(struct platform_device *pdev)
880 {
881 struct net_device *netdev = NULL;
882 struct resource *res = NULL;
883 struct resource *mmio = NULL;
884 struct resource *mem = NULL;
885 struct ethoc *priv = NULL;
886 unsigned int phy;
887 int ret = 0;
888
889 /* allocate networking device */
890 netdev = alloc_etherdev(sizeof(struct ethoc));
891 if (!netdev) {
892 dev_err(&pdev->dev, "cannot allocate network device\n");
893 ret = -ENOMEM;
894 goto out;
895 }
896
897 SET_NETDEV_DEV(netdev, &pdev->dev);
898 platform_set_drvdata(pdev, netdev);
899
900 /* obtain I/O memory space */
901 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
902 if (!res) {
903 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
904 ret = -ENXIO;
905 goto free;
906 }
907
908 mmio = devm_request_mem_region(&pdev->dev, res->start,
909 resource_size(res), res->name);
910 if (!mmio) {
911 dev_err(&pdev->dev, "cannot request I/O memory space\n");
912 ret = -ENXIO;
913 goto free;
914 }
915
916 netdev->base_addr = mmio->start;
917
918 /* obtain buffer memory space */
919 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
920 if (res) {
921 mem = devm_request_mem_region(&pdev->dev, res->start,
922 resource_size(res), res->name);
923 if (!mem) {
924 dev_err(&pdev->dev, "cannot request memory space\n");
925 ret = -ENXIO;
926 goto free;
927 }
928
929 netdev->mem_start = mem->start;
930 netdev->mem_end = mem->end;
931 }
932
933
934 /* obtain device IRQ number */
935 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
936 if (!res) {
937 dev_err(&pdev->dev, "cannot obtain IRQ\n");
938 ret = -ENXIO;
939 goto free;
940 }
941
942 netdev->irq = res->start;
943
944 /* setup driver-private data */
945 priv = netdev_priv(netdev);
946 priv->netdev = netdev;
947 priv->dma_alloc = 0;
948 priv->io_region_size = mmio->end - mmio->start + 1;
949
950 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
951 resource_size(mmio));
952 if (!priv->iobase) {
953 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
954 ret = -ENXIO;
955 goto error;
956 }
957
958 if (netdev->mem_end) {
959 priv->membase = devm_ioremap_nocache(&pdev->dev,
960 netdev->mem_start, resource_size(mem));
961 if (!priv->membase) {
962 dev_err(&pdev->dev, "cannot remap memory space\n");
963 ret = -ENXIO;
964 goto error;
965 }
966 } else {
967 /* Allocate buffer memory */
968 priv->membase = dma_alloc_coherent(NULL,
969 buffer_size, (void *)&netdev->mem_start,
970 GFP_KERNEL);
971 if (!priv->membase) {
972 dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
973 buffer_size);
974 ret = -ENOMEM;
975 goto error;
976 }
977 netdev->mem_end = netdev->mem_start + buffer_size;
978 priv->dma_alloc = buffer_size;
979 }
980
981 /* Allow the platform setup code to pass in a MAC address. */
982 if (pdev->dev.platform_data) {
983 struct ethoc_platform_data *pdata =
984 (struct ethoc_platform_data *)pdev->dev.platform_data;
985 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
986 priv->phy_id = pdata->phy_id;
987 }
988
989 /* Check that the given MAC address is valid. If it isn't, read the
990 * current MAC from the controller. */
991 if (!is_valid_ether_addr(netdev->dev_addr))
992 ethoc_get_mac_address(netdev, netdev->dev_addr);
993
994 /* Check the MAC again for validity, if it still isn't choose and
995 * program a random one. */
996 if (!is_valid_ether_addr(netdev->dev_addr))
997 random_ether_addr(netdev->dev_addr);
998
999 ethoc_set_mac_address(netdev, netdev->dev_addr);
1000
1001 /* register MII bus */
1002 priv->mdio = mdiobus_alloc();
1003 if (!priv->mdio) {
1004 ret = -ENOMEM;
1005 goto free;
1006 }
1007
1008 priv->mdio->name = "ethoc-mdio";
1009 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1010 priv->mdio->name, pdev->id);
1011 priv->mdio->read = ethoc_mdio_read;
1012 priv->mdio->write = ethoc_mdio_write;
1013 priv->mdio->reset = ethoc_mdio_reset;
1014 priv->mdio->priv = priv;
1015
1016 priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1017 if (!priv->mdio->irq) {
1018 ret = -ENOMEM;
1019 goto free_mdio;
1020 }
1021
1022 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
1023 priv->mdio->irq[phy] = PHY_POLL;
1024
1025 ret = mdiobus_register(priv->mdio);
1026 if (ret) {
1027 dev_err(&netdev->dev, "failed to register MDIO bus\n");
1028 goto free_mdio;
1029 }
1030
1031 ret = ethoc_mdio_probe(netdev);
1032 if (ret) {
1033 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1034 goto error;
1035 }
1036
1037 ether_setup(netdev);
1038
1039 /* setup the net_device structure */
1040 netdev->netdev_ops = &ethoc_netdev_ops;
1041 netdev->watchdog_timeo = ETHOC_TIMEOUT;
1042 netdev->features |= 0;
1043
1044 /* setup NAPI */
1045 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1046
1047 spin_lock_init(&priv->rx_lock);
1048 spin_lock_init(&priv->lock);
1049
1050 ret = register_netdev(netdev);
1051 if (ret < 0) {
1052 dev_err(&netdev->dev, "failed to register interface\n");
1053 goto error2;
1054 }
1055
1056 goto out;
1057
1058 error2:
1059 netif_napi_del(&priv->napi);
1060 error:
1061 mdiobus_unregister(priv->mdio);
1062 free_mdio:
1063 kfree(priv->mdio->irq);
1064 mdiobus_free(priv->mdio);
1065 free:
1066 if (priv) {
1067 if (priv->dma_alloc)
1068 dma_free_coherent(NULL, priv->dma_alloc, priv->membase,
1069 netdev->mem_start);
1070 else if (priv->membase)
1071 devm_iounmap(&pdev->dev, priv->membase);
1072 if (priv->iobase)
1073 devm_iounmap(&pdev->dev, priv->iobase);
1074 }
1075 if (mem)
1076 devm_release_mem_region(&pdev->dev, mem->start,
1077 mem->end - mem->start + 1);
1078 if (mmio)
1079 devm_release_mem_region(&pdev->dev, mmio->start,
1080 mmio->end - mmio->start + 1);
1081 free_netdev(netdev);
1082 out:
1083 return ret;
1084 }
1085
1086 /**
1087 * ethoc_remove() - shutdown OpenCores ethernet MAC
1088 * @pdev: platform device
1089 */
1090 static int ethoc_remove(struct platform_device *pdev)
1091 {
1092 struct net_device *netdev = platform_get_drvdata(pdev);
1093 struct ethoc *priv = netdev_priv(netdev);
1094
1095 platform_set_drvdata(pdev, NULL);
1096
1097 if (netdev) {
1098 netif_napi_del(&priv->napi);
1099 phy_disconnect(priv->phy);
1100 priv->phy = NULL;
1101
1102 if (priv->mdio) {
1103 mdiobus_unregister(priv->mdio);
1104 kfree(priv->mdio->irq);
1105 mdiobus_free(priv->mdio);
1106 }
1107 if (priv->dma_alloc)
1108 dma_free_coherent(NULL, priv->dma_alloc, priv->membase,
1109 netdev->mem_start);
1110 else {
1111 devm_iounmap(&pdev->dev, priv->membase);
1112 devm_release_mem_region(&pdev->dev, netdev->mem_start,
1113 netdev->mem_end - netdev->mem_start + 1);
1114 }
1115 devm_iounmap(&pdev->dev, priv->iobase);
1116 devm_release_mem_region(&pdev->dev, netdev->base_addr,
1117 priv->io_region_size);
1118 unregister_netdev(netdev);
1119 free_netdev(netdev);
1120 }
1121
1122 return 0;
1123 }
1124
1125 #ifdef CONFIG_PM
1126 static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1127 {
1128 return -ENOSYS;
1129 }
1130
1131 static int ethoc_resume(struct platform_device *pdev)
1132 {
1133 return -ENOSYS;
1134 }
1135 #else
1136 # define ethoc_suspend NULL
1137 # define ethoc_resume NULL
1138 #endif
1139
1140 static struct platform_driver ethoc_driver = {
1141 .probe = ethoc_probe,
1142 .remove = ethoc_remove,
1143 .suspend = ethoc_suspend,
1144 .resume = ethoc_resume,
1145 .driver = {
1146 .name = "ethoc",
1147 },
1148 };
1149
1150 static int __init ethoc_init(void)
1151 {
1152 return platform_driver_register(&ethoc_driver);
1153 }
1154
1155 static void __exit ethoc_exit(void)
1156 {
1157 platform_driver_unregister(&ethoc_driver);
1158 }
1159
1160 module_init(ethoc_init);
1161 module_exit(ethoc_exit);
1162
1163 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1164 MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1165 MODULE_LICENSE("GPL v2");
1166
Linux kernel - Deliverables
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