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ethoc: fix buffer address mapping
[deliverable/linux.git] / drivers / net / ethoc.c
1 /*
2 * linux/drivers/net/ethoc.c
3 *
4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
5 * Copyright (C) 2008-2009 Avionic Design GmbH
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
12 */
13
14 #include <linux/etherdevice.h>
15 #include <linux/crc32.h>
16 #include <linux/io.h>
17 #include <linux/mii.h>
18 #include <linux/phy.h>
19 #include <linux/platform_device.h>
20 #include <net/ethoc.h>
21
22 /* register offsets */
23 #define MODER 0x00
24 #define INT_SOURCE 0x04
25 #define INT_MASK 0x08
26 #define IPGT 0x0c
27 #define IPGR1 0x10
28 #define IPGR2 0x14
29 #define PACKETLEN 0x18
30 #define COLLCONF 0x1c
31 #define TX_BD_NUM 0x20
32 #define CTRLMODER 0x24
33 #define MIIMODER 0x28
34 #define MIICOMMAND 0x2c
35 #define MIIADDRESS 0x30
36 #define MIITX_DATA 0x34
37 #define MIIRX_DATA 0x38
38 #define MIISTATUS 0x3c
39 #define MAC_ADDR0 0x40
40 #define MAC_ADDR1 0x44
41 #define ETH_HASH0 0x48
42 #define ETH_HASH1 0x4c
43 #define ETH_TXCTRL 0x50
44
45 /* mode register */
46 #define MODER_RXEN (1 << 0) /* receive enable */
47 #define MODER_TXEN (1 << 1) /* transmit enable */
48 #define MODER_NOPRE (1 << 2) /* no preamble */
49 #define MODER_BRO (1 << 3) /* broadcast address */
50 #define MODER_IAM (1 << 4) /* individual address mode */
51 #define MODER_PRO (1 << 5) /* promiscuous mode */
52 #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
53 #define MODER_LOOP (1 << 7) /* loopback */
54 #define MODER_NBO (1 << 8) /* no back-off */
55 #define MODER_EDE (1 << 9) /* excess defer enable */
56 #define MODER_FULLD (1 << 10) /* full duplex */
57 #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
58 #define MODER_DCRC (1 << 12) /* delayed CRC enable */
59 #define MODER_CRC (1 << 13) /* CRC enable */
60 #define MODER_HUGE (1 << 14) /* huge packets enable */
61 #define MODER_PAD (1 << 15) /* padding enabled */
62 #define MODER_RSM (1 << 16) /* receive small packets */
63
64 /* interrupt source and mask registers */
65 #define INT_MASK_TXF (1 << 0) /* transmit frame */
66 #define INT_MASK_TXE (1 << 1) /* transmit error */
67 #define INT_MASK_RXF (1 << 2) /* receive frame */
68 #define INT_MASK_RXE (1 << 3) /* receive error */
69 #define INT_MASK_BUSY (1 << 4)
70 #define INT_MASK_TXC (1 << 5) /* transmit control frame */
71 #define INT_MASK_RXC (1 << 6) /* receive control frame */
72
73 #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
74 #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
75
76 #define INT_MASK_ALL ( \
77 INT_MASK_TXF | INT_MASK_TXE | \
78 INT_MASK_RXF | INT_MASK_RXE | \
79 INT_MASK_TXC | INT_MASK_RXC | \
80 INT_MASK_BUSY \
81 )
82
83 /* packet length register */
84 #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
85 #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
86 #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
87 PACKETLEN_MAX(max))
88
89 /* transmit buffer number register */
90 #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
91
92 /* control module mode register */
93 #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
94 #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
95 #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
96
97 /* MII mode register */
98 #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
99 #define MIIMODER_NOPRE (1 << 8) /* no preamble */
100
101 /* MII command register */
102 #define MIICOMMAND_SCAN (1 << 0) /* scan status */
103 #define MIICOMMAND_READ (1 << 1) /* read status */
104 #define MIICOMMAND_WRITE (1 << 2) /* write control data */
105
106 /* MII address register */
107 #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
108 #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
109 #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
110 MIIADDRESS_RGAD(reg))
111
112 /* MII transmit data register */
113 #define MIITX_DATA_VAL(x) ((x) & 0xffff)
114
115 /* MII receive data register */
116 #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
117
118 /* MII status register */
119 #define MIISTATUS_LINKFAIL (1 << 0)
120 #define MIISTATUS_BUSY (1 << 1)
121 #define MIISTATUS_INVALID (1 << 2)
122
123 /* TX buffer descriptor */
124 #define TX_BD_CS (1 << 0) /* carrier sense lost */
125 #define TX_BD_DF (1 << 1) /* defer indication */
126 #define TX_BD_LC (1 << 2) /* late collision */
127 #define TX_BD_RL (1 << 3) /* retransmission limit */
128 #define TX_BD_RETRY_MASK (0x00f0)
129 #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
130 #define TX_BD_UR (1 << 8) /* transmitter underrun */
131 #define TX_BD_CRC (1 << 11) /* TX CRC enable */
132 #define TX_BD_PAD (1 << 12) /* pad enable for short packets */
133 #define TX_BD_WRAP (1 << 13)
134 #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
135 #define TX_BD_READY (1 << 15) /* TX buffer ready */
136 #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
137 #define TX_BD_LEN_MASK (0xffff << 16)
138
139 #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
140 TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
141
142 /* RX buffer descriptor */
143 #define RX_BD_LC (1 << 0) /* late collision */
144 #define RX_BD_CRC (1 << 1) /* RX CRC error */
145 #define RX_BD_SF (1 << 2) /* short frame */
146 #define RX_BD_TL (1 << 3) /* too long */
147 #define RX_BD_DN (1 << 4) /* dribble nibble */
148 #define RX_BD_IS (1 << 5) /* invalid symbol */
149 #define RX_BD_OR (1 << 6) /* receiver overrun */
150 #define RX_BD_MISS (1 << 7)
151 #define RX_BD_CF (1 << 8) /* control frame */
152 #define RX_BD_WRAP (1 << 13)
153 #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
154 #define RX_BD_EMPTY (1 << 15)
155 #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
156
157 #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
158 RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
159
160 #define ETHOC_BUFSIZ 1536
161 #define ETHOC_ZLEN 64
162 #define ETHOC_BD_BASE 0x400
163 #define ETHOC_TIMEOUT (HZ / 2)
164 #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
165
166 /**
167 * struct ethoc - driver-private device structure
168 * @iobase: pointer to I/O memory region
169 * @membase: pointer to buffer memory region
170 * @num_tx: number of send buffers
171 * @cur_tx: last send buffer written
172 * @dty_tx: last buffer actually sent
173 * @num_rx: number of receive buffers
174 * @cur_rx: current receive buffer
175 * @netdev: pointer to network device structure
176 * @napi: NAPI structure
177 * @stats: network device statistics
178 * @msg_enable: device state flags
179 * @rx_lock: receive lock
180 * @lock: device lock
181 * @phy: attached PHY
182 * @mdio: MDIO bus for PHY access
183 * @phy_id: address of attached PHY
184 */
185 struct ethoc {
186 void __iomem *iobase;
187 void __iomem *membase;
188
189 unsigned int num_tx;
190 unsigned int cur_tx;
191 unsigned int dty_tx;
192
193 unsigned int num_rx;
194 unsigned int cur_rx;
195
196 struct net_device *netdev;
197 struct napi_struct napi;
198 struct net_device_stats stats;
199 u32 msg_enable;
200
201 spinlock_t rx_lock;
202 spinlock_t lock;
203
204 struct phy_device *phy;
205 struct mii_bus *mdio;
206 s8 phy_id;
207 };
208
209 /**
210 * struct ethoc_bd - buffer descriptor
211 * @stat: buffer statistics
212 * @addr: physical memory address
213 */
214 struct ethoc_bd {
215 u32 stat;
216 u32 addr;
217 };
218
219 static u32 ethoc_read(struct ethoc *dev, loff_t offset)
220 {
221 return ioread32(dev->iobase + offset);
222 }
223
224 static void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
225 {
226 iowrite32(data, dev->iobase + offset);
227 }
228
229 static void ethoc_read_bd(struct ethoc *dev, int index, struct ethoc_bd *bd)
230 {
231 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
232 bd->stat = ethoc_read(dev, offset + 0);
233 bd->addr = ethoc_read(dev, offset + 4);
234 }
235
236 static void ethoc_write_bd(struct ethoc *dev, int index,
237 const struct ethoc_bd *bd)
238 {
239 loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
240 ethoc_write(dev, offset + 0, bd->stat);
241 ethoc_write(dev, offset + 4, bd->addr);
242 }
243
244 static void ethoc_enable_irq(struct ethoc *dev, u32 mask)
245 {
246 u32 imask = ethoc_read(dev, INT_MASK);
247 imask |= mask;
248 ethoc_write(dev, INT_MASK, imask);
249 }
250
251 static void ethoc_disable_irq(struct ethoc *dev, u32 mask)
252 {
253 u32 imask = ethoc_read(dev, INT_MASK);
254 imask &= ~mask;
255 ethoc_write(dev, INT_MASK, imask);
256 }
257
258 static void ethoc_ack_irq(struct ethoc *dev, u32 mask)
259 {
260 ethoc_write(dev, INT_SOURCE, mask);
261 }
262
263 static void ethoc_enable_rx_and_tx(struct ethoc *dev)
264 {
265 u32 mode = ethoc_read(dev, MODER);
266 mode |= MODER_RXEN | MODER_TXEN;
267 ethoc_write(dev, MODER, mode);
268 }
269
270 static void ethoc_disable_rx_and_tx(struct ethoc *dev)
271 {
272 u32 mode = ethoc_read(dev, MODER);
273 mode &= ~(MODER_RXEN | MODER_TXEN);
274 ethoc_write(dev, MODER, mode);
275 }
276
277 static int ethoc_init_ring(struct ethoc *dev)
278 {
279 struct ethoc_bd bd;
280 int i;
281
282 dev->cur_tx = 0;
283 dev->dty_tx = 0;
284 dev->cur_rx = 0;
285
286 /* setup transmission buffers */
287 bd.addr = virt_to_phys(dev->membase);
288 bd.stat = TX_BD_IRQ | TX_BD_CRC;
289
290 for (i = 0; i < dev->num_tx; i++) {
291 if (i == dev->num_tx - 1)
292 bd.stat |= TX_BD_WRAP;
293
294 ethoc_write_bd(dev, i, &bd);
295 bd.addr += ETHOC_BUFSIZ;
296 }
297
298 bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
299
300 for (i = 0; i < dev->num_rx; i++) {
301 if (i == dev->num_rx - 1)
302 bd.stat |= RX_BD_WRAP;
303
304 ethoc_write_bd(dev, dev->num_tx + i, &bd);
305 bd.addr += ETHOC_BUFSIZ;
306 }
307
308 return 0;
309 }
310
311 static int ethoc_reset(struct ethoc *dev)
312 {
313 u32 mode;
314
315 /* TODO: reset controller? */
316
317 ethoc_disable_rx_and_tx(dev);
318
319 /* TODO: setup registers */
320
321 /* enable FCS generation and automatic padding */
322 mode = ethoc_read(dev, MODER);
323 mode |= MODER_CRC | MODER_PAD;
324 ethoc_write(dev, MODER, mode);
325
326 /* set full-duplex mode */
327 mode = ethoc_read(dev, MODER);
328 mode |= MODER_FULLD;
329 ethoc_write(dev, MODER, mode);
330 ethoc_write(dev, IPGT, 0x15);
331
332 ethoc_ack_irq(dev, INT_MASK_ALL);
333 ethoc_enable_irq(dev, INT_MASK_ALL);
334 ethoc_enable_rx_and_tx(dev);
335 return 0;
336 }
337
338 static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
339 struct ethoc_bd *bd)
340 {
341 struct net_device *netdev = dev->netdev;
342 unsigned int ret = 0;
343
344 if (bd->stat & RX_BD_TL) {
345 dev_err(&netdev->dev, "RX: frame too long\n");
346 dev->stats.rx_length_errors++;
347 ret++;
348 }
349
350 if (bd->stat & RX_BD_SF) {
351 dev_err(&netdev->dev, "RX: frame too short\n");
352 dev->stats.rx_length_errors++;
353 ret++;
354 }
355
356 if (bd->stat & RX_BD_DN) {
357 dev_err(&netdev->dev, "RX: dribble nibble\n");
358 dev->stats.rx_frame_errors++;
359 }
360
361 if (bd->stat & RX_BD_CRC) {
362 dev_err(&netdev->dev, "RX: wrong CRC\n");
363 dev->stats.rx_crc_errors++;
364 ret++;
365 }
366
367 if (bd->stat & RX_BD_OR) {
368 dev_err(&netdev->dev, "RX: overrun\n");
369 dev->stats.rx_over_errors++;
370 ret++;
371 }
372
373 if (bd->stat & RX_BD_MISS)
374 dev->stats.rx_missed_errors++;
375
376 if (bd->stat & RX_BD_LC) {
377 dev_err(&netdev->dev, "RX: late collision\n");
378 dev->stats.collisions++;
379 ret++;
380 }
381
382 return ret;
383 }
384
385 static int ethoc_rx(struct net_device *dev, int limit)
386 {
387 struct ethoc *priv = netdev_priv(dev);
388 int count;
389
390 for (count = 0; count < limit; ++count) {
391 unsigned int entry;
392 struct ethoc_bd bd;
393
394 entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
395 ethoc_read_bd(priv, entry, &bd);
396 if (bd.stat & RX_BD_EMPTY)
397 break;
398
399 if (ethoc_update_rx_stats(priv, &bd) == 0) {
400 int size = bd.stat >> 16;
401 struct sk_buff *skb = netdev_alloc_skb(dev, size);
402 if (likely(skb)) {
403 void *src = phys_to_virt(bd.addr);
404 memcpy_fromio(skb_put(skb, size), src, size);
405 skb->protocol = eth_type_trans(skb, dev);
406 priv->stats.rx_packets++;
407 priv->stats.rx_bytes += size;
408 netif_receive_skb(skb);
409 } else {
410 if (net_ratelimit())
411 dev_warn(&dev->dev, "low on memory - "
412 "packet dropped\n");
413
414 priv->stats.rx_dropped++;
415 break;
416 }
417 }
418
419 /* clear the buffer descriptor so it can be reused */
420 bd.stat &= ~RX_BD_STATS;
421 bd.stat |= RX_BD_EMPTY;
422 ethoc_write_bd(priv, entry, &bd);
423 priv->cur_rx++;
424 }
425
426 return count;
427 }
428
429 static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
430 {
431 struct net_device *netdev = dev->netdev;
432
433 if (bd->stat & TX_BD_LC) {
434 dev_err(&netdev->dev, "TX: late collision\n");
435 dev->stats.tx_window_errors++;
436 }
437
438 if (bd->stat & TX_BD_RL) {
439 dev_err(&netdev->dev, "TX: retransmit limit\n");
440 dev->stats.tx_aborted_errors++;
441 }
442
443 if (bd->stat & TX_BD_UR) {
444 dev_err(&netdev->dev, "TX: underrun\n");
445 dev->stats.tx_fifo_errors++;
446 }
447
448 if (bd->stat & TX_BD_CS) {
449 dev_err(&netdev->dev, "TX: carrier sense lost\n");
450 dev->stats.tx_carrier_errors++;
451 }
452
453 if (bd->stat & TX_BD_STATS)
454 dev->stats.tx_errors++;
455
456 dev->stats.collisions += (bd->stat >> 4) & 0xf;
457 dev->stats.tx_bytes += bd->stat >> 16;
458 dev->stats.tx_packets++;
459 return 0;
460 }
461
462 static void ethoc_tx(struct net_device *dev)
463 {
464 struct ethoc *priv = netdev_priv(dev);
465
466 spin_lock(&priv->lock);
467
468 while (priv->dty_tx != priv->cur_tx) {
469 unsigned int entry = priv->dty_tx % priv->num_tx;
470 struct ethoc_bd bd;
471
472 ethoc_read_bd(priv, entry, &bd);
473 if (bd.stat & TX_BD_READY)
474 break;
475
476 entry = (++priv->dty_tx) % priv->num_tx;
477 (void)ethoc_update_tx_stats(priv, &bd);
478 }
479
480 if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
481 netif_wake_queue(dev);
482
483 ethoc_ack_irq(priv, INT_MASK_TX);
484 spin_unlock(&priv->lock);
485 }
486
487 static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
488 {
489 struct net_device *dev = (struct net_device *)dev_id;
490 struct ethoc *priv = netdev_priv(dev);
491 u32 pending;
492
493 ethoc_disable_irq(priv, INT_MASK_ALL);
494 pending = ethoc_read(priv, INT_SOURCE);
495 if (unlikely(pending == 0)) {
496 ethoc_enable_irq(priv, INT_MASK_ALL);
497 return IRQ_NONE;
498 }
499
500 ethoc_ack_irq(priv, INT_MASK_ALL);
501
502 if (pending & INT_MASK_BUSY) {
503 dev_err(&dev->dev, "packet dropped\n");
504 priv->stats.rx_dropped++;
505 }
506
507 if (pending & INT_MASK_RX) {
508 if (napi_schedule_prep(&priv->napi))
509 __napi_schedule(&priv->napi);
510 } else {
511 ethoc_enable_irq(priv, INT_MASK_RX);
512 }
513
514 if (pending & INT_MASK_TX)
515 ethoc_tx(dev);
516
517 ethoc_enable_irq(priv, INT_MASK_ALL & ~INT_MASK_RX);
518 return IRQ_HANDLED;
519 }
520
521 static int ethoc_get_mac_address(struct net_device *dev, void *addr)
522 {
523 struct ethoc *priv = netdev_priv(dev);
524 u8 *mac = (u8 *)addr;
525 u32 reg;
526
527 reg = ethoc_read(priv, MAC_ADDR0);
528 mac[2] = (reg >> 24) & 0xff;
529 mac[3] = (reg >> 16) & 0xff;
530 mac[4] = (reg >> 8) & 0xff;
531 mac[5] = (reg >> 0) & 0xff;
532
533 reg = ethoc_read(priv, MAC_ADDR1);
534 mac[0] = (reg >> 8) & 0xff;
535 mac[1] = (reg >> 0) & 0xff;
536
537 return 0;
538 }
539
540 static int ethoc_poll(struct napi_struct *napi, int budget)
541 {
542 struct ethoc *priv = container_of(napi, struct ethoc, napi);
543 int work_done = 0;
544
545 work_done = ethoc_rx(priv->netdev, budget);
546 if (work_done < budget) {
547 ethoc_enable_irq(priv, INT_MASK_RX);
548 napi_complete(napi);
549 }
550
551 return work_done;
552 }
553
554 static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
555 {
556 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
557 struct ethoc *priv = bus->priv;
558
559 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
560 ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
561
562 while (time_before(jiffies, timeout)) {
563 u32 status = ethoc_read(priv, MIISTATUS);
564 if (!(status & MIISTATUS_BUSY)) {
565 u32 data = ethoc_read(priv, MIIRX_DATA);
566 /* reset MII command register */
567 ethoc_write(priv, MIICOMMAND, 0);
568 return data;
569 }
570
571 schedule();
572 }
573
574 return -EBUSY;
575 }
576
577 static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
578 {
579 unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
580 struct ethoc *priv = bus->priv;
581
582 ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
583 ethoc_write(priv, MIITX_DATA, val);
584 ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
585
586 while (time_before(jiffies, timeout)) {
587 u32 stat = ethoc_read(priv, MIISTATUS);
588 if (!(stat & MIISTATUS_BUSY))
589 return 0;
590
591 schedule();
592 }
593
594 return -EBUSY;
595 }
596
597 static int ethoc_mdio_reset(struct mii_bus *bus)
598 {
599 return 0;
600 }
601
602 static void ethoc_mdio_poll(struct net_device *dev)
603 {
604 }
605
606 static int ethoc_mdio_probe(struct net_device *dev)
607 {
608 struct ethoc *priv = netdev_priv(dev);
609 struct phy_device *phy;
610 int i;
611
612 for (i = 0; i < PHY_MAX_ADDR; i++) {
613 phy = priv->mdio->phy_map[i];
614 if (phy) {
615 if (priv->phy_id != -1) {
616 /* attach to specified PHY */
617 if (priv->phy_id == phy->addr)
618 break;
619 } else {
620 /* autoselect PHY if none was specified */
621 if (phy->addr != 0)
622 break;
623 }
624 }
625 }
626
627 if (!phy) {
628 dev_err(&dev->dev, "no PHY found\n");
629 return -ENXIO;
630 }
631
632 phy = phy_connect(dev, dev_name(&phy->dev), &ethoc_mdio_poll, 0,
633 PHY_INTERFACE_MODE_GMII);
634 if (IS_ERR(phy)) {
635 dev_err(&dev->dev, "could not attach to PHY\n");
636 return PTR_ERR(phy);
637 }
638
639 priv->phy = phy;
640 return 0;
641 }
642
643 static int ethoc_open(struct net_device *dev)
644 {
645 struct ethoc *priv = netdev_priv(dev);
646 unsigned int min_tx = 2;
647 unsigned int num_bd;
648 int ret;
649
650 ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
651 dev->name, dev);
652 if (ret)
653 return ret;
654
655 /* calculate the number of TX/RX buffers */
656 num_bd = (dev->mem_end - dev->mem_start + 1) / ETHOC_BUFSIZ;
657 priv->num_tx = max(min_tx, num_bd / 4);
658 priv->num_rx = num_bd - priv->num_tx;
659 ethoc_write(priv, TX_BD_NUM, priv->num_tx);
660
661 ethoc_init_ring(priv);
662 ethoc_reset(priv);
663
664 if (netif_queue_stopped(dev)) {
665 dev_dbg(&dev->dev, " resuming queue\n");
666 netif_wake_queue(dev);
667 } else {
668 dev_dbg(&dev->dev, " starting queue\n");
669 netif_start_queue(dev);
670 }
671
672 phy_start(priv->phy);
673 napi_enable(&priv->napi);
674
675 if (netif_msg_ifup(priv)) {
676 dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
677 dev->base_addr, dev->mem_start, dev->mem_end);
678 }
679
680 return 0;
681 }
682
683 static int ethoc_stop(struct net_device *dev)
684 {
685 struct ethoc *priv = netdev_priv(dev);
686
687 napi_disable(&priv->napi);
688
689 if (priv->phy)
690 phy_stop(priv->phy);
691
692 ethoc_disable_rx_and_tx(priv);
693 free_irq(dev->irq, dev);
694
695 if (!netif_queue_stopped(dev))
696 netif_stop_queue(dev);
697
698 return 0;
699 }
700
701 static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
702 {
703 struct ethoc *priv = netdev_priv(dev);
704 struct mii_ioctl_data *mdio = if_mii(ifr);
705 struct phy_device *phy = NULL;
706
707 if (!netif_running(dev))
708 return -EINVAL;
709
710 if (cmd != SIOCGMIIPHY) {
711 if (mdio->phy_id >= PHY_MAX_ADDR)
712 return -ERANGE;
713
714 phy = priv->mdio->phy_map[mdio->phy_id];
715 if (!phy)
716 return -ENODEV;
717 } else {
718 phy = priv->phy;
719 }
720
721 return phy_mii_ioctl(phy, mdio, cmd);
722 }
723
724 static int ethoc_config(struct net_device *dev, struct ifmap *map)
725 {
726 return -ENOSYS;
727 }
728
729 static int ethoc_set_mac_address(struct net_device *dev, void *addr)
730 {
731 struct ethoc *priv = netdev_priv(dev);
732 u8 *mac = (u8 *)addr;
733
734 ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
735 (mac[4] << 8) | (mac[5] << 0));
736 ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
737
738 return 0;
739 }
740
741 static void ethoc_set_multicast_list(struct net_device *dev)
742 {
743 struct ethoc *priv = netdev_priv(dev);
744 u32 mode = ethoc_read(priv, MODER);
745 struct dev_mc_list *mc = NULL;
746 u32 hash[2] = { 0, 0 };
747
748 /* set loopback mode if requested */
749 if (dev->flags & IFF_LOOPBACK)
750 mode |= MODER_LOOP;
751 else
752 mode &= ~MODER_LOOP;
753
754 /* receive broadcast frames if requested */
755 if (dev->flags & IFF_BROADCAST)
756 mode &= ~MODER_BRO;
757 else
758 mode |= MODER_BRO;
759
760 /* enable promiscuous mode if requested */
761 if (dev->flags & IFF_PROMISC)
762 mode |= MODER_PRO;
763 else
764 mode &= ~MODER_PRO;
765
766 ethoc_write(priv, MODER, mode);
767
768 /* receive multicast frames */
769 if (dev->flags & IFF_ALLMULTI) {
770 hash[0] = 0xffffffff;
771 hash[1] = 0xffffffff;
772 } else {
773 for (mc = dev->mc_list; mc; mc = mc->next) {
774 u32 crc = ether_crc(mc->dmi_addrlen, mc->dmi_addr);
775 int bit = (crc >> 26) & 0x3f;
776 hash[bit >> 5] |= 1 << (bit & 0x1f);
777 }
778 }
779
780 ethoc_write(priv, ETH_HASH0, hash[0]);
781 ethoc_write(priv, ETH_HASH1, hash[1]);
782 }
783
784 static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
785 {
786 return -ENOSYS;
787 }
788
789 static void ethoc_tx_timeout(struct net_device *dev)
790 {
791 struct ethoc *priv = netdev_priv(dev);
792 u32 pending = ethoc_read(priv, INT_SOURCE);
793 if (likely(pending))
794 ethoc_interrupt(dev->irq, dev);
795 }
796
797 static struct net_device_stats *ethoc_stats(struct net_device *dev)
798 {
799 struct ethoc *priv = netdev_priv(dev);
800 return &priv->stats;
801 }
802
803 static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
804 {
805 struct ethoc *priv = netdev_priv(dev);
806 struct ethoc_bd bd;
807 unsigned int entry;
808 void *dest;
809
810 if (unlikely(skb->len > ETHOC_BUFSIZ)) {
811 priv->stats.tx_errors++;
812 goto out;
813 }
814
815 entry = priv->cur_tx % priv->num_tx;
816 spin_lock_irq(&priv->lock);
817 priv->cur_tx++;
818
819 ethoc_read_bd(priv, entry, &bd);
820 if (unlikely(skb->len < ETHOC_ZLEN))
821 bd.stat |= TX_BD_PAD;
822 else
823 bd.stat &= ~TX_BD_PAD;
824
825 dest = phys_to_virt(bd.addr);
826 memcpy_toio(dest, skb->data, skb->len);
827
828 bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
829 bd.stat |= TX_BD_LEN(skb->len);
830 ethoc_write_bd(priv, entry, &bd);
831
832 bd.stat |= TX_BD_READY;
833 ethoc_write_bd(priv, entry, &bd);
834
835 if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
836 dev_dbg(&dev->dev, "stopping queue\n");
837 netif_stop_queue(dev);
838 }
839
840 dev->trans_start = jiffies;
841 spin_unlock_irq(&priv->lock);
842 out:
843 dev_kfree_skb(skb);
844 return NETDEV_TX_OK;
845 }
846
847 static const struct net_device_ops ethoc_netdev_ops = {
848 .ndo_open = ethoc_open,
849 .ndo_stop = ethoc_stop,
850 .ndo_do_ioctl = ethoc_ioctl,
851 .ndo_set_config = ethoc_config,
852 .ndo_set_mac_address = ethoc_set_mac_address,
853 .ndo_set_multicast_list = ethoc_set_multicast_list,
854 .ndo_change_mtu = ethoc_change_mtu,
855 .ndo_tx_timeout = ethoc_tx_timeout,
856 .ndo_get_stats = ethoc_stats,
857 .ndo_start_xmit = ethoc_start_xmit,
858 };
859
860 /**
861 * ethoc_probe() - initialize OpenCores ethernet MAC
862 * pdev: platform device
863 */
864 static int ethoc_probe(struct platform_device *pdev)
865 {
866 struct net_device *netdev = NULL;
867 struct resource *res = NULL;
868 struct resource *mmio = NULL;
869 struct resource *mem = NULL;
870 struct ethoc *priv = NULL;
871 unsigned int phy;
872 int ret = 0;
873
874 /* allocate networking device */
875 netdev = alloc_etherdev(sizeof(struct ethoc));
876 if (!netdev) {
877 dev_err(&pdev->dev, "cannot allocate network device\n");
878 ret = -ENOMEM;
879 goto out;
880 }
881
882 SET_NETDEV_DEV(netdev, &pdev->dev);
883 platform_set_drvdata(pdev, netdev);
884
885 /* obtain I/O memory space */
886 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
887 if (!res) {
888 dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
889 ret = -ENXIO;
890 goto free;
891 }
892
893 mmio = devm_request_mem_region(&pdev->dev, res->start,
894 res->end - res->start + 1, res->name);
895 if (!mmio) {
896 dev_err(&pdev->dev, "cannot request I/O memory space\n");
897 ret = -ENXIO;
898 goto free;
899 }
900
901 netdev->base_addr = mmio->start;
902
903 /* obtain buffer memory space */
904 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
905 if (!res) {
906 dev_err(&pdev->dev, "cannot obtain memory space\n");
907 ret = -ENXIO;
908 goto free;
909 }
910
911 mem = devm_request_mem_region(&pdev->dev, res->start,
912 res->end - res->start + 1, res->name);
913 if (!mem) {
914 dev_err(&pdev->dev, "cannot request memory space\n");
915 ret = -ENXIO;
916 goto free;
917 }
918
919 netdev->mem_start = mem->start;
920 netdev->mem_end = mem->end;
921
922 /* obtain device IRQ number */
923 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
924 if (!res) {
925 dev_err(&pdev->dev, "cannot obtain IRQ\n");
926 ret = -ENXIO;
927 goto free;
928 }
929
930 netdev->irq = res->start;
931
932 /* setup driver-private data */
933 priv = netdev_priv(netdev);
934 priv->netdev = netdev;
935
936 priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
937 mmio->end - mmio->start + 1);
938 if (!priv->iobase) {
939 dev_err(&pdev->dev, "cannot remap I/O memory space\n");
940 ret = -ENXIO;
941 goto error;
942 }
943
944 priv->membase = devm_ioremap_nocache(&pdev->dev, netdev->mem_start,
945 mem->end - mem->start + 1);
946 if (!priv->membase) {
947 dev_err(&pdev->dev, "cannot remap memory space\n");
948 ret = -ENXIO;
949 goto error;
950 }
951
952 /* Allow the platform setup code to pass in a MAC address. */
953 if (pdev->dev.platform_data) {
954 struct ethoc_platform_data *pdata =
955 (struct ethoc_platform_data *)pdev->dev.platform_data;
956 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
957 priv->phy_id = pdata->phy_id;
958 }
959
960 /* Check that the given MAC address is valid. If it isn't, read the
961 * current MAC from the controller. */
962 if (!is_valid_ether_addr(netdev->dev_addr))
963 ethoc_get_mac_address(netdev, netdev->dev_addr);
964
965 /* Check the MAC again for validity, if it still isn't choose and
966 * program a random one. */
967 if (!is_valid_ether_addr(netdev->dev_addr))
968 random_ether_addr(netdev->dev_addr);
969
970 ethoc_set_mac_address(netdev, netdev->dev_addr);
971
972 /* register MII bus */
973 priv->mdio = mdiobus_alloc();
974 if (!priv->mdio) {
975 ret = -ENOMEM;
976 goto free;
977 }
978
979 priv->mdio->name = "ethoc-mdio";
980 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
981 priv->mdio->name, pdev->id);
982 priv->mdio->read = ethoc_mdio_read;
983 priv->mdio->write = ethoc_mdio_write;
984 priv->mdio->reset = ethoc_mdio_reset;
985 priv->mdio->priv = priv;
986
987 priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
988 if (!priv->mdio->irq) {
989 ret = -ENOMEM;
990 goto free_mdio;
991 }
992
993 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
994 priv->mdio->irq[phy] = PHY_POLL;
995
996 ret = mdiobus_register(priv->mdio);
997 if (ret) {
998 dev_err(&netdev->dev, "failed to register MDIO bus\n");
999 goto free_mdio;
1000 }
1001
1002 ret = ethoc_mdio_probe(netdev);
1003 if (ret) {
1004 dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1005 goto error;
1006 }
1007
1008 ether_setup(netdev);
1009
1010 /* setup the net_device structure */
1011 netdev->netdev_ops = &ethoc_netdev_ops;
1012 netdev->watchdog_timeo = ETHOC_TIMEOUT;
1013 netdev->features |= 0;
1014
1015 /* setup NAPI */
1016 memset(&priv->napi, 0, sizeof(priv->napi));
1017 netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1018
1019 spin_lock_init(&priv->rx_lock);
1020 spin_lock_init(&priv->lock);
1021
1022 ret = register_netdev(netdev);
1023 if (ret < 0) {
1024 dev_err(&netdev->dev, "failed to register interface\n");
1025 goto error;
1026 }
1027
1028 goto out;
1029
1030 error:
1031 mdiobus_unregister(priv->mdio);
1032 free_mdio:
1033 kfree(priv->mdio->irq);
1034 mdiobus_free(priv->mdio);
1035 free:
1036 free_netdev(netdev);
1037 out:
1038 return ret;
1039 }
1040
1041 /**
1042 * ethoc_remove() - shutdown OpenCores ethernet MAC
1043 * @pdev: platform device
1044 */
1045 static int ethoc_remove(struct platform_device *pdev)
1046 {
1047 struct net_device *netdev = platform_get_drvdata(pdev);
1048 struct ethoc *priv = netdev_priv(netdev);
1049
1050 platform_set_drvdata(pdev, NULL);
1051
1052 if (netdev) {
1053 phy_disconnect(priv->phy);
1054 priv->phy = NULL;
1055
1056 if (priv->mdio) {
1057 mdiobus_unregister(priv->mdio);
1058 kfree(priv->mdio->irq);
1059 mdiobus_free(priv->mdio);
1060 }
1061
1062 unregister_netdev(netdev);
1063 free_netdev(netdev);
1064 }
1065
1066 return 0;
1067 }
1068
1069 #ifdef CONFIG_PM
1070 static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1071 {
1072 return -ENOSYS;
1073 }
1074
1075 static int ethoc_resume(struct platform_device *pdev)
1076 {
1077 return -ENOSYS;
1078 }
1079 #else
1080 # define ethoc_suspend NULL
1081 # define ethoc_resume NULL
1082 #endif
1083
1084 static struct platform_driver ethoc_driver = {
1085 .probe = ethoc_probe,
1086 .remove = ethoc_remove,
1087 .suspend = ethoc_suspend,
1088 .resume = ethoc_resume,
1089 .driver = {
1090 .name = "ethoc",
1091 },
1092 };
1093
1094 static int __init ethoc_init(void)
1095 {
1096 return platform_driver_register(&ethoc_driver);
1097 }
1098
1099 static void __exit ethoc_exit(void)
1100 {
1101 platform_driver_unregister(&ethoc_driver);
1102 }
1103
1104 module_init(ethoc_init);
1105 module_exit(ethoc_exit);
1106
1107 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1108 MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1109 MODULE_LICENSE("GPL v2");
1110
Linux kernel - Deliverables
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