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[NET]: Nuke SET_MODULE_OWNER macro.
[deliverable/linux.git] / drivers / net / fealnx.c
1 /*
2 Written 1998-2000 by Donald Becker.
3
4 This software may be used and distributed according to the terms of
5 the GNU General Public License (GPL), incorporated herein by reference.
6 Drivers based on or derived from this code fall under the GPL and must
7 retain the authorship, copyright and license notice. This file is not
8 a complete program and may only be used when the entire operating
9 system is licensed under the GPL.
10
11 The author may be reached as becker@scyld.com, or C/O
12 Scyld Computing Corporation
13 410 Severn Ave., Suite 210
14 Annapolis MD 21403
15
16 Support information and updates available at
17 http://www.scyld.com/network/pci-skeleton.html
18
19 Linux kernel updates:
20
21 Version 2.51, Nov 17, 2001 (jgarzik):
22 - Add ethtool support
23 - Replace some MII-related magic numbers with constants
24
25 */
26
27 #define DRV_NAME "fealnx"
28 #define DRV_VERSION "2.52"
29 #define DRV_RELDATE "Sep-11-2006"
30
31 static int debug; /* 1-> print debug message */
32 static int max_interrupt_work = 20;
33
34 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
35 static int multicast_filter_limit = 32;
36
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. */
38 /* Setting to > 1518 effectively disables this feature. */
39 static int rx_copybreak;
40
41 /* Used to pass the media type, etc. */
42 /* Both 'options[]' and 'full_duplex[]' should exist for driver */
43 /* interoperability. */
44 /* The media type is usually passed in 'options[]'. */
45 #define MAX_UNITS 8 /* More are supported, limit only on options */
46 static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
47 static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
48
49 /* Operational parameters that are set at compile time. */
50 /* Keep the ring sizes a power of two for compile efficiency. */
51 /* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */
52 /* Making the Tx ring too large decreases the effectiveness of channel */
53 /* bonding and packet priority. */
54 /* There are no ill effects from too-large receive rings. */
55 // 88-12-9 modify,
56 // #define TX_RING_SIZE 16
57 // #define RX_RING_SIZE 32
58 #define TX_RING_SIZE 6
59 #define RX_RING_SIZE 12
60 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc)
61 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc)
62
63 /* Operational parameters that usually are not changed. */
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (2*HZ)
66
67 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
68
69
70 /* Include files, designed to support most kernel versions 2.0.0 and later. */
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/string.h>
74 #include <linux/timer.h>
75 #include <linux/errno.h>
76 #include <linux/ioport.h>
77 #include <linux/slab.h>
78 #include <linux/interrupt.h>
79 #include <linux/pci.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/init.h>
84 #include <linux/mii.h>
85 #include <linux/ethtool.h>
86 #include <linux/crc32.h>
87 #include <linux/delay.h>
88 #include <linux/bitops.h>
89
90 #include <asm/processor.h> /* Processor type for cache alignment. */
91 #include <asm/io.h>
92 #include <asm/uaccess.h>
93
94 /* These identify the driver base version and may not be removed. */
95 static char version[] =
96 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
97
98
99 /* This driver was written to use PCI memory space, however some x86 systems
100 work only with I/O space accesses. */
101 #ifndef __alpha__
102 #define USE_IO_OPS
103 #endif
104
105 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
106 /* This is only in the support-all-kernels source code. */
107
108 #define RUN_AT(x) (jiffies + (x))
109
110 MODULE_AUTHOR("Myson or whoever");
111 MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver");
112 MODULE_LICENSE("GPL");
113 module_param(max_interrupt_work, int, 0);
114 //MODULE_PARM(min_pci_latency, "i");
115 module_param(debug, int, 0);
116 module_param(rx_copybreak, int, 0);
117 module_param(multicast_filter_limit, int, 0);
118 module_param_array(options, int, NULL, 0);
119 module_param_array(full_duplex, int, NULL, 0);
120 MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt");
121 MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)");
122 MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames");
123 MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses");
124 MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
125 MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
126
127 enum {
128 MIN_REGION_SIZE = 136,
129 };
130
131 /* A chip capabilities table, matching the entries in pci_tbl[] above. */
132 enum chip_capability_flags {
133 HAS_MII_XCVR,
134 HAS_CHIP_XCVR,
135 };
136
137 /* 89/6/13 add, */
138 /* for different PHY */
139 enum phy_type_flags {
140 MysonPHY = 1,
141 AhdocPHY = 2,
142 SeeqPHY = 3,
143 MarvellPHY = 4,
144 Myson981 = 5,
145 LevelOnePHY = 6,
146 OtherPHY = 10,
147 };
148
149 struct chip_info {
150 char *chip_name;
151 int flags;
152 };
153
154 static const struct chip_info skel_netdrv_tbl[] __devinitdata = {
155 { "100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
156 { "100/10M Ethernet PCI Adapter", HAS_CHIP_XCVR },
157 { "1000/100/10M Ethernet PCI Adapter", HAS_MII_XCVR },
158 };
159
160 /* Offsets to the Command and Status Registers. */
161 enum fealnx_offsets {
162 PAR0 = 0x0, /* physical address 0-3 */
163 PAR1 = 0x04, /* physical address 4-5 */
164 MAR0 = 0x08, /* multicast address 0-3 */
165 MAR1 = 0x0C, /* multicast address 4-7 */
166 FAR0 = 0x10, /* flow-control address 0-3 */
167 FAR1 = 0x14, /* flow-control address 4-5 */
168 TCRRCR = 0x18, /* receive & transmit configuration */
169 BCR = 0x1C, /* bus command */
170 TXPDR = 0x20, /* transmit polling demand */
171 RXPDR = 0x24, /* receive polling demand */
172 RXCWP = 0x28, /* receive current word pointer */
173 TXLBA = 0x2C, /* transmit list base address */
174 RXLBA = 0x30, /* receive list base address */
175 ISR = 0x34, /* interrupt status */
176 IMR = 0x38, /* interrupt mask */
177 FTH = 0x3C, /* flow control high/low threshold */
178 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */
179 TALLY = 0x44, /* tally counters for crc and mpa */
180 TSR = 0x48, /* tally counter for transmit status */
181 BMCRSR = 0x4c, /* basic mode control and status */
182 PHYIDENTIFIER = 0x50, /* phy identifier */
183 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link
184 partner ability */
185 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */
186 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */
187 };
188
189 /* Bits in the interrupt status/enable registers. */
190 /* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
191 enum intr_status_bits {
192 RFCON = 0x00020000, /* receive flow control xon packet */
193 RFCOFF = 0x00010000, /* receive flow control xoff packet */
194 LSCStatus = 0x00008000, /* link status change */
195 ANCStatus = 0x00004000, /* autonegotiation completed */
196 FBE = 0x00002000, /* fatal bus error */
197 FBEMask = 0x00001800, /* mask bit12-11 */
198 ParityErr = 0x00000000, /* parity error */
199 TargetErr = 0x00001000, /* target abort */
200 MasterErr = 0x00000800, /* master error */
201 TUNF = 0x00000400, /* transmit underflow */
202 ROVF = 0x00000200, /* receive overflow */
203 ETI = 0x00000100, /* transmit early int */
204 ERI = 0x00000080, /* receive early int */
205 CNTOVF = 0x00000040, /* counter overflow */
206 RBU = 0x00000020, /* receive buffer unavailable */
207 TBU = 0x00000010, /* transmit buffer unavilable */
208 TI = 0x00000008, /* transmit interrupt */
209 RI = 0x00000004, /* receive interrupt */
210 RxErr = 0x00000002, /* receive error */
211 };
212
213 /* Bits in the NetworkConfig register, W for writing, R for reading */
214 /* FIXME: some names are invented by me. Marked with (name?) */
215 /* If you have docs and know bit names, please fix 'em */
216 enum rx_mode_bits {
217 CR_W_ENH = 0x02000000, /* enhanced mode (name?) */
218 CR_W_FD = 0x00100000, /* full duplex */
219 CR_W_PS10 = 0x00080000, /* 10 mbit */
220 CR_W_TXEN = 0x00040000, /* tx enable (name?) */
221 CR_W_PS1000 = 0x00010000, /* 1000 mbit */
222 /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */
223 CR_W_RXMODEMASK = 0x000000e0,
224 CR_W_PROM = 0x00000080, /* promiscuous mode */
225 CR_W_AB = 0x00000040, /* accept broadcast */
226 CR_W_AM = 0x00000020, /* accept mutlicast */
227 CR_W_ARP = 0x00000008, /* receive runt pkt */
228 CR_W_ALP = 0x00000004, /* receive long pkt */
229 CR_W_SEP = 0x00000002, /* receive error pkt */
230 CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */
231
232 CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */
233 CR_R_FD = 0x00100000, /* full duplex detected */
234 CR_R_PS10 = 0x00080000, /* 10 mbit detected */
235 CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */
236 };
237
238 /* The Tulip Rx and Tx buffer descriptors. */
239 struct fealnx_desc {
240 s32 status;
241 s32 control;
242 u32 buffer;
243 u32 next_desc;
244 struct fealnx_desc *next_desc_logical;
245 struct sk_buff *skbuff;
246 u32 reserved1;
247 u32 reserved2;
248 };
249
250 /* Bits in network_desc.status */
251 enum rx_desc_status_bits {
252 RXOWN = 0x80000000, /* own bit */
253 FLNGMASK = 0x0fff0000, /* frame length */
254 FLNGShift = 16,
255 MARSTATUS = 0x00004000, /* multicast address received */
256 BARSTATUS = 0x00002000, /* broadcast address received */
257 PHYSTATUS = 0x00001000, /* physical address received */
258 RXFSD = 0x00000800, /* first descriptor */
259 RXLSD = 0x00000400, /* last descriptor */
260 ErrorSummary = 0x80, /* error summary */
261 RUNT = 0x40, /* runt packet received */
262 LONG = 0x20, /* long packet received */
263 FAE = 0x10, /* frame align error */
264 CRC = 0x08, /* crc error */
265 RXER = 0x04, /* receive error */
266 };
267
268 enum rx_desc_control_bits {
269 RXIC = 0x00800000, /* interrupt control */
270 RBSShift = 0,
271 };
272
273 enum tx_desc_status_bits {
274 TXOWN = 0x80000000, /* own bit */
275 JABTO = 0x00004000, /* jabber timeout */
276 CSL = 0x00002000, /* carrier sense lost */
277 LC = 0x00001000, /* late collision */
278 EC = 0x00000800, /* excessive collision */
279 UDF = 0x00000400, /* fifo underflow */
280 DFR = 0x00000200, /* deferred */
281 HF = 0x00000100, /* heartbeat fail */
282 NCRMask = 0x000000ff, /* collision retry count */
283 NCRShift = 0,
284 };
285
286 enum tx_desc_control_bits {
287 TXIC = 0x80000000, /* interrupt control */
288 ETIControl = 0x40000000, /* early transmit interrupt */
289 TXLD = 0x20000000, /* last descriptor */
290 TXFD = 0x10000000, /* first descriptor */
291 CRCEnable = 0x08000000, /* crc control */
292 PADEnable = 0x04000000, /* padding control */
293 RetryTxLC = 0x02000000, /* retry late collision */
294 PKTSMask = 0x3ff800, /* packet size bit21-11 */
295 PKTSShift = 11,
296 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */
297 TBSShift = 0,
298 };
299
300 /* BootROM/EEPROM/MII Management Register */
301 #define MASK_MIIR_MII_READ 0x00000000
302 #define MASK_MIIR_MII_WRITE 0x00000008
303 #define MASK_MIIR_MII_MDO 0x00000004
304 #define MASK_MIIR_MII_MDI 0x00000002
305 #define MASK_MIIR_MII_MDC 0x00000001
306
307 /* ST+OP+PHYAD+REGAD+TA */
308 #define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
309 #define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
310
311 /* ------------------------------------------------------------------------- */
312 /* Constants for Myson PHY */
313 /* ------------------------------------------------------------------------- */
314 #define MysonPHYID 0xd0000302
315 /* 89-7-27 add, (begin) */
316 #define MysonPHYID0 0x0302
317 #define StatusRegister 18
318 #define SPEED100 0x0400 // bit10
319 #define FULLMODE 0x0800 // bit11
320 /* 89-7-27 add, (end) */
321
322 /* ------------------------------------------------------------------------- */
323 /* Constants for Seeq 80225 PHY */
324 /* ------------------------------------------------------------------------- */
325 #define SeeqPHYID0 0x0016
326
327 #define MIIRegister18 18
328 #define SPD_DET_100 0x80
329 #define DPLX_DET_FULL 0x40
330
331 /* ------------------------------------------------------------------------- */
332 /* Constants for Ahdoc 101 PHY */
333 /* ------------------------------------------------------------------------- */
334 #define AhdocPHYID0 0x0022
335
336 #define DiagnosticReg 18
337 #define DPLX_FULL 0x0800
338 #define Speed_100 0x0400
339
340 /* 89/6/13 add, */
341 /* -------------------------------------------------------------------------- */
342 /* Constants */
343 /* -------------------------------------------------------------------------- */
344 #define MarvellPHYID0 0x0141
345 #define LevelOnePHYID0 0x0013
346
347 #define MII1000BaseTControlReg 9
348 #define MII1000BaseTStatusReg 10
349 #define SpecificReg 17
350
351 /* for 1000BaseT Control Register */
352 #define PHYAbletoPerform1000FullDuplex 0x0200
353 #define PHYAbletoPerform1000HalfDuplex 0x0100
354 #define PHY1000AbilityMask 0x300
355
356 // for phy specific status register, marvell phy.
357 #define SpeedMask 0x0c000
358 #define Speed_1000M 0x08000
359 #define Speed_100M 0x4000
360 #define Speed_10M 0
361 #define Full_Duplex 0x2000
362
363 // 89/12/29 add, for phy specific status register, levelone phy, (begin)
364 #define LXT1000_100M 0x08000
365 #define LXT1000_1000M 0x0c000
366 #define LXT1000_Full 0x200
367 // 89/12/29 add, for phy specific status register, levelone phy, (end)
368
369 /* for 3-in-1 case, BMCRSR register */
370 #define LinkIsUp2 0x00040000
371
372 /* for PHY */
373 #define LinkIsUp 0x0004
374
375
376 struct netdev_private {
377 /* Descriptor rings first for alignment. */
378 struct fealnx_desc *rx_ring;
379 struct fealnx_desc *tx_ring;
380
381 dma_addr_t rx_ring_dma;
382 dma_addr_t tx_ring_dma;
383
384 spinlock_t lock;
385
386 struct net_device_stats stats;
387
388 /* Media monitoring timer. */
389 struct timer_list timer;
390
391 /* Reset timer */
392 struct timer_list reset_timer;
393 int reset_timer_armed;
394 unsigned long crvalue_sv;
395 unsigned long imrvalue_sv;
396
397 /* Frequently used values: keep some adjacent for cache effect. */
398 int flags;
399 struct pci_dev *pci_dev;
400 unsigned long crvalue;
401 unsigned long bcrvalue;
402 unsigned long imrvalue;
403 struct fealnx_desc *cur_rx;
404 struct fealnx_desc *lack_rxbuf;
405 int really_rx_count;
406 struct fealnx_desc *cur_tx;
407 struct fealnx_desc *cur_tx_copy;
408 int really_tx_count;
409 int free_tx_count;
410 unsigned int rx_buf_sz; /* Based on MTU+slack. */
411
412 /* These values are keep track of the transceiver/media in use. */
413 unsigned int linkok;
414 unsigned int line_speed;
415 unsigned int duplexmode;
416 unsigned int default_port:4; /* Last dev->if_port value. */
417 unsigned int PHYType;
418
419 /* MII transceiver section. */
420 int mii_cnt; /* MII device addresses. */
421 unsigned char phys[2]; /* MII device addresses. */
422 struct mii_if_info mii;
423 void __iomem *mem;
424 };
425
426
427 static int mdio_read(struct net_device *dev, int phy_id, int location);
428 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
429 static int netdev_open(struct net_device *dev);
430 static void getlinktype(struct net_device *dev);
431 static void getlinkstatus(struct net_device *dev);
432 static void netdev_timer(unsigned long data);
433 static void reset_timer(unsigned long data);
434 static void tx_timeout(struct net_device *dev);
435 static void init_ring(struct net_device *dev);
436 static int start_tx(struct sk_buff *skb, struct net_device *dev);
437 static irqreturn_t intr_handler(int irq, void *dev_instance);
438 static int netdev_rx(struct net_device *dev);
439 static void set_rx_mode(struct net_device *dev);
440 static void __set_rx_mode(struct net_device *dev);
441 static struct net_device_stats *get_stats(struct net_device *dev);
442 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
443 static const struct ethtool_ops netdev_ethtool_ops;
444 static int netdev_close(struct net_device *dev);
445 static void reset_rx_descriptors(struct net_device *dev);
446 static void reset_tx_descriptors(struct net_device *dev);
447
448 static void stop_nic_rx(void __iomem *ioaddr, long crvalue)
449 {
450 int delay = 0x1000;
451 iowrite32(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
452 while (--delay) {
453 if ( (ioread32(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
454 break;
455 }
456 }
457
458
459 static void stop_nic_rxtx(void __iomem *ioaddr, long crvalue)
460 {
461 int delay = 0x1000;
462 iowrite32(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
463 while (--delay) {
464 if ( (ioread32(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
465 == (CR_R_RXSTOP+CR_R_TXSTOP) )
466 break;
467 }
468 }
469
470
471 static int __devinit fealnx_init_one(struct pci_dev *pdev,
472 const struct pci_device_id *ent)
473 {
474 struct netdev_private *np;
475 int i, option, err, irq;
476 static int card_idx = -1;
477 char boardname[12];
478 void __iomem *ioaddr;
479 unsigned long len;
480 unsigned int chip_id = ent->driver_data;
481 struct net_device *dev;
482 void *ring_space;
483 dma_addr_t ring_dma;
484 #ifdef USE_IO_OPS
485 int bar = 0;
486 #else
487 int bar = 1;
488 #endif
489
490 /* when built into the kernel, we only print version if device is found */
491 #ifndef MODULE
492 static int printed_version;
493 if (!printed_version++)
494 printk(version);
495 #endif
496
497 card_idx++;
498 sprintf(boardname, "fealnx%d", card_idx);
499
500 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
501
502 i = pci_enable_device(pdev);
503 if (i) return i;
504 pci_set_master(pdev);
505
506 len = pci_resource_len(pdev, bar);
507 if (len < MIN_REGION_SIZE) {
508 dev_err(&pdev->dev,
509 "region size %ld too small, aborting\n", len);
510 return -ENODEV;
511 }
512
513 i = pci_request_regions(pdev, boardname);
514 if (i)
515 return i;
516
517 irq = pdev->irq;
518
519 ioaddr = pci_iomap(pdev, bar, len);
520 if (!ioaddr) {
521 err = -ENOMEM;
522 goto err_out_res;
523 }
524
525 dev = alloc_etherdev(sizeof(struct netdev_private));
526 if (!dev) {
527 err = -ENOMEM;
528 goto err_out_unmap;
529 }
530 SET_NETDEV_DEV(dev, &pdev->dev);
531
532 /* read ethernet id */
533 for (i = 0; i < 6; ++i)
534 dev->dev_addr[i] = ioread8(ioaddr + PAR0 + i);
535
536 /* Reset the chip to erase previous misconfiguration. */
537 iowrite32(0x00000001, ioaddr + BCR);
538
539 dev->base_addr = (unsigned long)ioaddr;
540 dev->irq = irq;
541
542 /* Make certain the descriptor lists are aligned. */
543 np = netdev_priv(dev);
544 np->mem = ioaddr;
545 spin_lock_init(&np->lock);
546 np->pci_dev = pdev;
547 np->flags = skel_netdrv_tbl[chip_id].flags;
548 pci_set_drvdata(pdev, dev);
549 np->mii.dev = dev;
550 np->mii.mdio_read = mdio_read;
551 np->mii.mdio_write = mdio_write;
552 np->mii.phy_id_mask = 0x1f;
553 np->mii.reg_num_mask = 0x1f;
554
555 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
556 if (!ring_space) {
557 err = -ENOMEM;
558 goto err_out_free_dev;
559 }
560 np->rx_ring = (struct fealnx_desc *)ring_space;
561 np->rx_ring_dma = ring_dma;
562
563 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
564 if (!ring_space) {
565 err = -ENOMEM;
566 goto err_out_free_rx;
567 }
568 np->tx_ring = (struct fealnx_desc *)ring_space;
569 np->tx_ring_dma = ring_dma;
570
571 /* find the connected MII xcvrs */
572 if (np->flags == HAS_MII_XCVR) {
573 int phy, phy_idx = 0;
574
575 for (phy = 1; phy < 32 && phy_idx < 4; phy++) {
576 int mii_status = mdio_read(dev, phy, 1);
577
578 if (mii_status != 0xffff && mii_status != 0x0000) {
579 np->phys[phy_idx++] = phy;
580 dev_info(&pdev->dev,
581 "MII PHY found at address %d, status "
582 "0x%4.4x.\n", phy, mii_status);
583 /* get phy type */
584 {
585 unsigned int data;
586
587 data = mdio_read(dev, np->phys[0], 2);
588 if (data == SeeqPHYID0)
589 np->PHYType = SeeqPHY;
590 else if (data == AhdocPHYID0)
591 np->PHYType = AhdocPHY;
592 else if (data == MarvellPHYID0)
593 np->PHYType = MarvellPHY;
594 else if (data == MysonPHYID0)
595 np->PHYType = Myson981;
596 else if (data == LevelOnePHYID0)
597 np->PHYType = LevelOnePHY;
598 else
599 np->PHYType = OtherPHY;
600 }
601 }
602 }
603
604 np->mii_cnt = phy_idx;
605 if (phy_idx == 0)
606 dev_warn(&pdev->dev,
607 "MII PHY not found -- this device may "
608 "not operate correctly.\n");
609 } else {
610 np->phys[0] = 32;
611 /* 89/6/23 add, (begin) */
612 /* get phy type */
613 if (ioread32(ioaddr + PHYIDENTIFIER) == MysonPHYID)
614 np->PHYType = MysonPHY;
615 else
616 np->PHYType = OtherPHY;
617 }
618 np->mii.phy_id = np->phys[0];
619
620 if (dev->mem_start)
621 option = dev->mem_start;
622
623 /* The lower four bits are the media type. */
624 if (option > 0) {
625 if (option & 0x200)
626 np->mii.full_duplex = 1;
627 np->default_port = option & 15;
628 }
629
630 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
631 np->mii.full_duplex = full_duplex[card_idx];
632
633 if (np->mii.full_duplex) {
634 dev_info(&pdev->dev, "Media type forced to Full Duplex.\n");
635 /* 89/6/13 add, (begin) */
636 // if (np->PHYType==MarvellPHY)
637 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
638 unsigned int data;
639
640 data = mdio_read(dev, np->phys[0], 9);
641 data = (data & 0xfcff) | 0x0200;
642 mdio_write(dev, np->phys[0], 9, data);
643 }
644 /* 89/6/13 add, (end) */
645 if (np->flags == HAS_MII_XCVR)
646 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
647 else
648 iowrite32(ADVERTISE_FULL, ioaddr + ANARANLPAR);
649 np->mii.force_media = 1;
650 }
651
652 /* The chip-specific entries in the device structure. */
653 dev->open = &netdev_open;
654 dev->hard_start_xmit = &start_tx;
655 dev->stop = &netdev_close;
656 dev->get_stats = &get_stats;
657 dev->set_multicast_list = &set_rx_mode;
658 dev->do_ioctl = &mii_ioctl;
659 dev->ethtool_ops = &netdev_ethtool_ops;
660 dev->tx_timeout = &tx_timeout;
661 dev->watchdog_timeo = TX_TIMEOUT;
662
663 err = register_netdev(dev);
664 if (err)
665 goto err_out_free_tx;
666
667 printk(KERN_INFO "%s: %s at %p, ",
668 dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr);
669 for (i = 0; i < 5; i++)
670 printk("%2.2x:", dev->dev_addr[i]);
671 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
672
673 return 0;
674
675 err_out_free_tx:
676 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
677 err_out_free_rx:
678 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
679 err_out_free_dev:
680 free_netdev(dev);
681 err_out_unmap:
682 pci_iounmap(pdev, ioaddr);
683 err_out_res:
684 pci_release_regions(pdev);
685 return err;
686 }
687
688
689 static void __devexit fealnx_remove_one(struct pci_dev *pdev)
690 {
691 struct net_device *dev = pci_get_drvdata(pdev);
692
693 if (dev) {
694 struct netdev_private *np = netdev_priv(dev);
695
696 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
697 np->tx_ring_dma);
698 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
699 np->rx_ring_dma);
700 unregister_netdev(dev);
701 pci_iounmap(pdev, np->mem);
702 free_netdev(dev);
703 pci_release_regions(pdev);
704 pci_set_drvdata(pdev, NULL);
705 } else
706 printk(KERN_ERR "fealnx: remove for unknown device\n");
707 }
708
709
710 static ulong m80x_send_cmd_to_phy(void __iomem *miiport, int opcode, int phyad, int regad)
711 {
712 ulong miir;
713 int i;
714 unsigned int mask, data;
715
716 /* enable MII output */
717 miir = (ulong) ioread32(miiport);
718 miir &= 0xfffffff0;
719
720 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
721
722 /* send 32 1's preamble */
723 for (i = 0; i < 32; i++) {
724 /* low MDC; MDO is already high (miir) */
725 miir &= ~MASK_MIIR_MII_MDC;
726 iowrite32(miir, miiport);
727
728 /* high MDC */
729 miir |= MASK_MIIR_MII_MDC;
730 iowrite32(miir, miiport);
731 }
732
733 /* calculate ST+OP+PHYAD+REGAD+TA */
734 data = opcode | (phyad << 7) | (regad << 2);
735
736 /* sent out */
737 mask = 0x8000;
738 while (mask) {
739 /* low MDC, prepare MDO */
740 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
741 if (mask & data)
742 miir |= MASK_MIIR_MII_MDO;
743
744 iowrite32(miir, miiport);
745 /* high MDC */
746 miir |= MASK_MIIR_MII_MDC;
747 iowrite32(miir, miiport);
748 udelay(30);
749
750 /* next */
751 mask >>= 1;
752 if (mask == 0x2 && opcode == OP_READ)
753 miir &= ~MASK_MIIR_MII_WRITE;
754 }
755 return miir;
756 }
757
758
759 static int mdio_read(struct net_device *dev, int phyad, int regad)
760 {
761 struct netdev_private *np = netdev_priv(dev);
762 void __iomem *miiport = np->mem + MANAGEMENT;
763 ulong miir;
764 unsigned int mask, data;
765
766 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad);
767
768 /* read data */
769 mask = 0x8000;
770 data = 0;
771 while (mask) {
772 /* low MDC */
773 miir &= ~MASK_MIIR_MII_MDC;
774 iowrite32(miir, miiport);
775
776 /* read MDI */
777 miir = ioread32(miiport);
778 if (miir & MASK_MIIR_MII_MDI)
779 data |= mask;
780
781 /* high MDC, and wait */
782 miir |= MASK_MIIR_MII_MDC;
783 iowrite32(miir, miiport);
784 udelay(30);
785
786 /* next */
787 mask >>= 1;
788 }
789
790 /* low MDC */
791 miir &= ~MASK_MIIR_MII_MDC;
792 iowrite32(miir, miiport);
793
794 return data & 0xffff;
795 }
796
797
798 static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
799 {
800 struct netdev_private *np = netdev_priv(dev);
801 void __iomem *miiport = np->mem + MANAGEMENT;
802 ulong miir;
803 unsigned int mask;
804
805 miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad);
806
807 /* write data */
808 mask = 0x8000;
809 while (mask) {
810 /* low MDC, prepare MDO */
811 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
812 if (mask & data)
813 miir |= MASK_MIIR_MII_MDO;
814 iowrite32(miir, miiport);
815
816 /* high MDC */
817 miir |= MASK_MIIR_MII_MDC;
818 iowrite32(miir, miiport);
819
820 /* next */
821 mask >>= 1;
822 }
823
824 /* low MDC */
825 miir &= ~MASK_MIIR_MII_MDC;
826 iowrite32(miir, miiport);
827 }
828
829
830 static int netdev_open(struct net_device *dev)
831 {
832 struct netdev_private *np = netdev_priv(dev);
833 void __iomem *ioaddr = np->mem;
834 int i;
835
836 iowrite32(0x00000001, ioaddr + BCR); /* Reset */
837
838 if (request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev))
839 return -EAGAIN;
840
841 for (i = 0; i < 3; i++)
842 iowrite16(((unsigned short*)dev->dev_addr)[i],
843 ioaddr + PAR0 + i*2);
844
845 init_ring(dev);
846
847 iowrite32(np->rx_ring_dma, ioaddr + RXLBA);
848 iowrite32(np->tx_ring_dma, ioaddr + TXLBA);
849
850 /* Initialize other registers. */
851 /* Configure the PCI bus bursts and FIFO thresholds.
852 486: Set 8 longword burst.
853 586: no burst limit.
854 Burst length 5:3
855 0 0 0 1
856 0 0 1 4
857 0 1 0 8
858 0 1 1 16
859 1 0 0 32
860 1 0 1 64
861 1 1 0 128
862 1 1 1 256
863 Wait the specified 50 PCI cycles after a reset by initializing
864 Tx and Rx queues and the address filter list.
865 FIXME (Ueimor): optimistic for alpha + posted writes ? */
866 #if defined(__powerpc__) || defined(__sparc__)
867 // 89/9/1 modify,
868 // np->bcrvalue=0x04 | 0x0x38; /* big-endian, 256 burst length */
869 np->bcrvalue = 0x04 | 0x10; /* big-endian, tx 8 burst length */
870 np->crvalue = 0xe00; /* rx 128 burst length */
871 #elif defined(__alpha__) || defined(__x86_64__)
872 // 89/9/1 modify,
873 // np->bcrvalue=0x38; /* little-endian, 256 burst length */
874 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
875 np->crvalue = 0xe00; /* rx 128 burst length */
876 #elif defined(__i386__)
877 #if defined(MODULE)
878 // 89/9/1 modify,
879 // np->bcrvalue=0x38; /* little-endian, 256 burst length */
880 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
881 np->crvalue = 0xe00; /* rx 128 burst length */
882 #else
883 /* When not a module we can work around broken '486 PCI boards. */
884 #define x86 boot_cpu_data.x86
885 // 89/9/1 modify,
886 // np->bcrvalue=(x86 <= 4 ? 0x10 : 0x38);
887 np->bcrvalue = 0x10;
888 np->crvalue = (x86 <= 4 ? 0xa00 : 0xe00);
889 if (x86 <= 4)
890 printk(KERN_INFO "%s: This is a 386/486 PCI system, setting burst "
891 "length to %x.\n", dev->name, (x86 <= 4 ? 0x10 : 0x38));
892 #endif
893 #else
894 // 89/9/1 modify,
895 // np->bcrvalue=0x38;
896 np->bcrvalue = 0x10;
897 np->crvalue = 0xe00; /* rx 128 burst length */
898 #warning Processor architecture undefined!
899 #endif
900 // 89/12/29 add,
901 // 90/1/16 modify,
902 // np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
903 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
904 if (np->pci_dev->device == 0x891) {
905 np->bcrvalue |= 0x200; /* set PROG bit */
906 np->crvalue |= CR_W_ENH; /* set enhanced bit */
907 np->imrvalue |= ETI;
908 }
909 iowrite32(np->bcrvalue, ioaddr + BCR);
910
911 if (dev->if_port == 0)
912 dev->if_port = np->default_port;
913
914 iowrite32(0, ioaddr + RXPDR);
915 // 89/9/1 modify,
916 // np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
917 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
918 np->mii.full_duplex = np->mii.force_media;
919 getlinkstatus(dev);
920 if (np->linkok)
921 getlinktype(dev);
922 __set_rx_mode(dev);
923
924 netif_start_queue(dev);
925
926 /* Clear and Enable interrupts by setting the interrupt mask. */
927 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
928 iowrite32(np->imrvalue, ioaddr + IMR);
929
930 if (debug)
931 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
932
933 /* Set the timer to check for link beat. */
934 init_timer(&np->timer);
935 np->timer.expires = RUN_AT(3 * HZ);
936 np->timer.data = (unsigned long) dev;
937 np->timer.function = &netdev_timer;
938
939 /* timer handler */
940 add_timer(&np->timer);
941
942 init_timer(&np->reset_timer);
943 np->reset_timer.data = (unsigned long) dev;
944 np->reset_timer.function = &reset_timer;
945 np->reset_timer_armed = 0;
946
947 return 0;
948 }
949
950
951 static void getlinkstatus(struct net_device *dev)
952 /* function: Routine will read MII Status Register to get link status. */
953 /* input : dev... pointer to the adapter block. */
954 /* output : none. */
955 {
956 struct netdev_private *np = netdev_priv(dev);
957 unsigned int i, DelayTime = 0x1000;
958
959 np->linkok = 0;
960
961 if (np->PHYType == MysonPHY) {
962 for (i = 0; i < DelayTime; ++i) {
963 if (ioread32(np->mem + BMCRSR) & LinkIsUp2) {
964 np->linkok = 1;
965 return;
966 }
967 udelay(100);
968 }
969 } else {
970 for (i = 0; i < DelayTime; ++i) {
971 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
972 np->linkok = 1;
973 return;
974 }
975 udelay(100);
976 }
977 }
978 }
979
980
981 static void getlinktype(struct net_device *dev)
982 {
983 struct netdev_private *np = netdev_priv(dev);
984
985 if (np->PHYType == MysonPHY) { /* 3-in-1 case */
986 if (ioread32(np->mem + TCRRCR) & CR_R_FD)
987 np->duplexmode = 2; /* full duplex */
988 else
989 np->duplexmode = 1; /* half duplex */
990 if (ioread32(np->mem + TCRRCR) & CR_R_PS10)
991 np->line_speed = 1; /* 10M */
992 else
993 np->line_speed = 2; /* 100M */
994 } else {
995 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */
996 unsigned int data;
997
998 data = mdio_read(dev, np->phys[0], MIIRegister18);
999 if (data & SPD_DET_100)
1000 np->line_speed = 2; /* 100M */
1001 else
1002 np->line_speed = 1; /* 10M */
1003 if (data & DPLX_DET_FULL)
1004 np->duplexmode = 2; /* full duplex mode */
1005 else
1006 np->duplexmode = 1; /* half duplex mode */
1007 } else if (np->PHYType == AhdocPHY) {
1008 unsigned int data;
1009
1010 data = mdio_read(dev, np->phys[0], DiagnosticReg);
1011 if (data & Speed_100)
1012 np->line_speed = 2; /* 100M */
1013 else
1014 np->line_speed = 1; /* 10M */
1015 if (data & DPLX_FULL)
1016 np->duplexmode = 2; /* full duplex mode */
1017 else
1018 np->duplexmode = 1; /* half duplex mode */
1019 }
1020 /* 89/6/13 add, (begin) */
1021 else if (np->PHYType == MarvellPHY) {
1022 unsigned int data;
1023
1024 data = mdio_read(dev, np->phys[0], SpecificReg);
1025 if (data & Full_Duplex)
1026 np->duplexmode = 2; /* full duplex mode */
1027 else
1028 np->duplexmode = 1; /* half duplex mode */
1029 data &= SpeedMask;
1030 if (data == Speed_1000M)
1031 np->line_speed = 3; /* 1000M */
1032 else if (data == Speed_100M)
1033 np->line_speed = 2; /* 100M */
1034 else
1035 np->line_speed = 1; /* 10M */
1036 }
1037 /* 89/6/13 add, (end) */
1038 /* 89/7/27 add, (begin) */
1039 else if (np->PHYType == Myson981) {
1040 unsigned int data;
1041
1042 data = mdio_read(dev, np->phys[0], StatusRegister);
1043
1044 if (data & SPEED100)
1045 np->line_speed = 2;
1046 else
1047 np->line_speed = 1;
1048
1049 if (data & FULLMODE)
1050 np->duplexmode = 2;
1051 else
1052 np->duplexmode = 1;
1053 }
1054 /* 89/7/27 add, (end) */
1055 /* 89/12/29 add */
1056 else if (np->PHYType == LevelOnePHY) {
1057 unsigned int data;
1058
1059 data = mdio_read(dev, np->phys[0], SpecificReg);
1060 if (data & LXT1000_Full)
1061 np->duplexmode = 2; /* full duplex mode */
1062 else
1063 np->duplexmode = 1; /* half duplex mode */
1064 data &= SpeedMask;
1065 if (data == LXT1000_1000M)
1066 np->line_speed = 3; /* 1000M */
1067 else if (data == LXT1000_100M)
1068 np->line_speed = 2; /* 100M */
1069 else
1070 np->line_speed = 1; /* 10M */
1071 }
1072 np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000);
1073 if (np->line_speed == 1)
1074 np->crvalue |= CR_W_PS10;
1075 else if (np->line_speed == 3)
1076 np->crvalue |= CR_W_PS1000;
1077 if (np->duplexmode == 2)
1078 np->crvalue |= CR_W_FD;
1079 }
1080 }
1081
1082
1083 /* Take lock before calling this */
1084 static void allocate_rx_buffers(struct net_device *dev)
1085 {
1086 struct netdev_private *np = netdev_priv(dev);
1087
1088 /* allocate skb for rx buffers */
1089 while (np->really_rx_count != RX_RING_SIZE) {
1090 struct sk_buff *skb;
1091
1092 skb = dev_alloc_skb(np->rx_buf_sz);
1093 if (skb == NULL)
1094 break; /* Better luck next round. */
1095
1096 while (np->lack_rxbuf->skbuff)
1097 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1098
1099 skb->dev = dev; /* Mark as being used by this device. */
1100 np->lack_rxbuf->skbuff = skb;
1101 np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->data,
1102 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1103 np->lack_rxbuf->status = RXOWN;
1104 ++np->really_rx_count;
1105 }
1106 }
1107
1108
1109 static void netdev_timer(unsigned long data)
1110 {
1111 struct net_device *dev = (struct net_device *) data;
1112 struct netdev_private *np = netdev_priv(dev);
1113 void __iomem *ioaddr = np->mem;
1114 int old_crvalue = np->crvalue;
1115 unsigned int old_linkok = np->linkok;
1116 unsigned long flags;
1117
1118 if (debug)
1119 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
1120 "config %8.8x.\n", dev->name, ioread32(ioaddr + ISR),
1121 ioread32(ioaddr + TCRRCR));
1122
1123 spin_lock_irqsave(&np->lock, flags);
1124
1125 if (np->flags == HAS_MII_XCVR) {
1126 getlinkstatus(dev);
1127 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */
1128 getlinktype(dev);
1129 if (np->crvalue != old_crvalue) {
1130 stop_nic_rxtx(ioaddr, np->crvalue);
1131 iowrite32(np->crvalue, ioaddr + TCRRCR);
1132 }
1133 }
1134 }
1135
1136 allocate_rx_buffers(dev);
1137
1138 spin_unlock_irqrestore(&np->lock, flags);
1139
1140 np->timer.expires = RUN_AT(10 * HZ);
1141 add_timer(&np->timer);
1142 }
1143
1144
1145 /* Take lock before calling */
1146 /* Reset chip and disable rx, tx and interrupts */
1147 static void reset_and_disable_rxtx(struct net_device *dev)
1148 {
1149 struct netdev_private *np = netdev_priv(dev);
1150 void __iomem *ioaddr = np->mem;
1151 int delay=51;
1152
1153 /* Reset the chip's Tx and Rx processes. */
1154 stop_nic_rxtx(ioaddr, 0);
1155
1156 /* Disable interrupts by clearing the interrupt mask. */
1157 iowrite32(0, ioaddr + IMR);
1158
1159 /* Reset the chip to erase previous misconfiguration. */
1160 iowrite32(0x00000001, ioaddr + BCR);
1161
1162 /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
1163 We surely wait too long (address+data phase). Who cares? */
1164 while (--delay) {
1165 ioread32(ioaddr + BCR);
1166 rmb();
1167 }
1168 }
1169
1170
1171 /* Take lock before calling */
1172 /* Restore chip after reset */
1173 static void enable_rxtx(struct net_device *dev)
1174 {
1175 struct netdev_private *np = netdev_priv(dev);
1176 void __iomem *ioaddr = np->mem;
1177
1178 reset_rx_descriptors(dev);
1179
1180 iowrite32(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
1181 ioaddr + TXLBA);
1182 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1183 ioaddr + RXLBA);
1184
1185 iowrite32(np->bcrvalue, ioaddr + BCR);
1186
1187 iowrite32(0, ioaddr + RXPDR);
1188 __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
1189
1190 /* Clear and Enable interrupts by setting the interrupt mask. */
1191 iowrite32(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
1192 iowrite32(np->imrvalue, ioaddr + IMR);
1193
1194 iowrite32(0, ioaddr + TXPDR);
1195 }
1196
1197
1198 static void reset_timer(unsigned long data)
1199 {
1200 struct net_device *dev = (struct net_device *) data;
1201 struct netdev_private *np = netdev_priv(dev);
1202 unsigned long flags;
1203
1204 printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name);
1205
1206 spin_lock_irqsave(&np->lock, flags);
1207 np->crvalue = np->crvalue_sv;
1208 np->imrvalue = np->imrvalue_sv;
1209
1210 reset_and_disable_rxtx(dev);
1211 /* works for me without this:
1212 reset_tx_descriptors(dev); */
1213 enable_rxtx(dev);
1214 netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */
1215
1216 np->reset_timer_armed = 0;
1217
1218 spin_unlock_irqrestore(&np->lock, flags);
1219 }
1220
1221
1222 static void tx_timeout(struct net_device *dev)
1223 {
1224 struct netdev_private *np = netdev_priv(dev);
1225 void __iomem *ioaddr = np->mem;
1226 unsigned long flags;
1227 int i;
1228
1229 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
1230 " resetting...\n", dev->name, ioread32(ioaddr + ISR));
1231
1232 {
1233 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
1234 for (i = 0; i < RX_RING_SIZE; i++)
1235 printk(" %8.8x", (unsigned int) np->rx_ring[i].status);
1236 printk("\n" KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1237 for (i = 0; i < TX_RING_SIZE; i++)
1238 printk(" %4.4x", np->tx_ring[i].status);
1239 printk("\n");
1240 }
1241
1242 spin_lock_irqsave(&np->lock, flags);
1243
1244 reset_and_disable_rxtx(dev);
1245 reset_tx_descriptors(dev);
1246 enable_rxtx(dev);
1247
1248 spin_unlock_irqrestore(&np->lock, flags);
1249
1250 dev->trans_start = jiffies;
1251 np->stats.tx_errors++;
1252 netif_wake_queue(dev); /* or .._start_.. ?? */
1253 }
1254
1255
1256 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1257 static void init_ring(struct net_device *dev)
1258 {
1259 struct netdev_private *np = netdev_priv(dev);
1260 int i;
1261
1262 /* initialize rx variables */
1263 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1264 np->cur_rx = &np->rx_ring[0];
1265 np->lack_rxbuf = np->rx_ring;
1266 np->really_rx_count = 0;
1267
1268 /* initial rx descriptors. */
1269 for (i = 0; i < RX_RING_SIZE; i++) {
1270 np->rx_ring[i].status = 0;
1271 np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1272 np->rx_ring[i].next_desc = np->rx_ring_dma +
1273 (i + 1)*sizeof(struct fealnx_desc);
1274 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1275 np->rx_ring[i].skbuff = NULL;
1276 }
1277
1278 /* for the last rx descriptor */
1279 np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1280 np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1281
1282 /* allocate skb for rx buffers */
1283 for (i = 0; i < RX_RING_SIZE; i++) {
1284 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1285
1286 if (skb == NULL) {
1287 np->lack_rxbuf = &np->rx_ring[i];
1288 break;
1289 }
1290
1291 ++np->really_rx_count;
1292 np->rx_ring[i].skbuff = skb;
1293 skb->dev = dev; /* Mark as being used by this device. */
1294 np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->data,
1295 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1296 np->rx_ring[i].status = RXOWN;
1297 np->rx_ring[i].control |= RXIC;
1298 }
1299
1300 /* initialize tx variables */
1301 np->cur_tx = &np->tx_ring[0];
1302 np->cur_tx_copy = &np->tx_ring[0];
1303 np->really_tx_count = 0;
1304 np->free_tx_count = TX_RING_SIZE;
1305
1306 for (i = 0; i < TX_RING_SIZE; i++) {
1307 np->tx_ring[i].status = 0;
1308 /* do we need np->tx_ring[i].control = XXX; ?? */
1309 np->tx_ring[i].next_desc = np->tx_ring_dma +
1310 (i + 1)*sizeof(struct fealnx_desc);
1311 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1312 np->tx_ring[i].skbuff = NULL;
1313 }
1314
1315 /* for the last tx descriptor */
1316 np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1317 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1318 }
1319
1320
1321 static int start_tx(struct sk_buff *skb, struct net_device *dev)
1322 {
1323 struct netdev_private *np = netdev_priv(dev);
1324 unsigned long flags;
1325
1326 spin_lock_irqsave(&np->lock, flags);
1327
1328 np->cur_tx_copy->skbuff = skb;
1329
1330 #define one_buffer
1331 #define BPT 1022
1332 #if defined(one_buffer)
1333 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1334 skb->len, PCI_DMA_TODEVICE);
1335 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1336 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1337 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1338 // 89/12/29 add,
1339 if (np->pci_dev->device == 0x891)
1340 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1341 np->cur_tx_copy->status = TXOWN;
1342 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1343 --np->free_tx_count;
1344 #elif defined(two_buffer)
1345 if (skb->len > BPT) {
1346 struct fealnx_desc *next;
1347
1348 /* for the first descriptor */
1349 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1350 BPT, PCI_DMA_TODEVICE);
1351 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1352 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1353 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */
1354
1355 /* for the last descriptor */
1356 next = np->cur_tx_copy->next_desc_logical;
1357 next->skbuff = skb;
1358 next->control = TXIC | TXLD | CRCEnable | PADEnable;
1359 next->control |= (skb->len << PKTSShift); /* pkt size */
1360 next->control |= ((skb->len - BPT) << TBSShift); /* buf size */
1361 // 89/12/29 add,
1362 if (np->pci_dev->device == 0x891)
1363 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1364 next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT,
1365 skb->len - BPT, PCI_DMA_TODEVICE);
1366
1367 next->status = TXOWN;
1368 np->cur_tx_copy->status = TXOWN;
1369
1370 np->cur_tx_copy = next->next_desc_logical;
1371 np->free_tx_count -= 2;
1372 } else {
1373 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1374 skb->len, PCI_DMA_TODEVICE);
1375 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1376 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1377 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1378 // 89/12/29 add,
1379 if (np->pci_dev->device == 0x891)
1380 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1381 np->cur_tx_copy->status = TXOWN;
1382 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1383 --np->free_tx_count;
1384 }
1385 #endif
1386
1387 if (np->free_tx_count < 2)
1388 netif_stop_queue(dev);
1389 ++np->really_tx_count;
1390 iowrite32(0, np->mem + TXPDR);
1391 dev->trans_start = jiffies;
1392
1393 spin_unlock_irqrestore(&np->lock, flags);
1394 return 0;
1395 }
1396
1397
1398 /* Take lock before calling */
1399 /* Chip probably hosed tx ring. Clean up. */
1400 static void reset_tx_descriptors(struct net_device *dev)
1401 {
1402 struct netdev_private *np = netdev_priv(dev);
1403 struct fealnx_desc *cur;
1404 int i;
1405
1406 /* initialize tx variables */
1407 np->cur_tx = &np->tx_ring[0];
1408 np->cur_tx_copy = &np->tx_ring[0];
1409 np->really_tx_count = 0;
1410 np->free_tx_count = TX_RING_SIZE;
1411
1412 for (i = 0; i < TX_RING_SIZE; i++) {
1413 cur = &np->tx_ring[i];
1414 if (cur->skbuff) {
1415 pci_unmap_single(np->pci_dev, cur->buffer,
1416 cur->skbuff->len, PCI_DMA_TODEVICE);
1417 dev_kfree_skb_any(cur->skbuff);
1418 cur->skbuff = NULL;
1419 }
1420 cur->status = 0;
1421 cur->control = 0; /* needed? */
1422 /* probably not needed. We do it for purely paranoid reasons */
1423 cur->next_desc = np->tx_ring_dma +
1424 (i + 1)*sizeof(struct fealnx_desc);
1425 cur->next_desc_logical = &np->tx_ring[i + 1];
1426 }
1427 /* for the last tx descriptor */
1428 np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma;
1429 np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0];
1430 }
1431
1432
1433 /* Take lock and stop rx before calling this */
1434 static void reset_rx_descriptors(struct net_device *dev)
1435 {
1436 struct netdev_private *np = netdev_priv(dev);
1437 struct fealnx_desc *cur = np->cur_rx;
1438 int i;
1439
1440 allocate_rx_buffers(dev);
1441
1442 for (i = 0; i < RX_RING_SIZE; i++) {
1443 if (cur->skbuff)
1444 cur->status = RXOWN;
1445 cur = cur->next_desc_logical;
1446 }
1447
1448 iowrite32(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1449 np->mem + RXLBA);
1450 }
1451
1452
1453 /* The interrupt handler does all of the Rx thread work and cleans up
1454 after the Tx thread. */
1455 static irqreturn_t intr_handler(int irq, void *dev_instance)
1456 {
1457 struct net_device *dev = (struct net_device *) dev_instance;
1458 struct netdev_private *np = netdev_priv(dev);
1459 void __iomem *ioaddr = np->mem;
1460 long boguscnt = max_interrupt_work;
1461 unsigned int num_tx = 0;
1462 int handled = 0;
1463
1464 spin_lock(&np->lock);
1465
1466 iowrite32(0, ioaddr + IMR);
1467
1468 do {
1469 u32 intr_status = ioread32(ioaddr + ISR);
1470
1471 /* Acknowledge all of the current interrupt sources ASAP. */
1472 iowrite32(intr_status, ioaddr + ISR);
1473
1474 if (debug)
1475 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
1476 intr_status);
1477
1478 if (!(intr_status & np->imrvalue))
1479 break;
1480
1481 handled = 1;
1482
1483 // 90/1/16 delete,
1484 //
1485 // if (intr_status & FBE)
1486 // { /* fatal error */
1487 // stop_nic_tx(ioaddr, 0);
1488 // stop_nic_rx(ioaddr, 0);
1489 // break;
1490 // };
1491
1492 if (intr_status & TUNF)
1493 iowrite32(0, ioaddr + TXPDR);
1494
1495 if (intr_status & CNTOVF) {
1496 /* missed pkts */
1497 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1498
1499 /* crc error */
1500 np->stats.rx_crc_errors +=
1501 (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1502 }
1503
1504 if (intr_status & (RI | RBU)) {
1505 if (intr_status & RI)
1506 netdev_rx(dev);
1507 else {
1508 stop_nic_rx(ioaddr, np->crvalue);
1509 reset_rx_descriptors(dev);
1510 iowrite32(np->crvalue, ioaddr + TCRRCR);
1511 }
1512 }
1513
1514 while (np->really_tx_count) {
1515 long tx_status = np->cur_tx->status;
1516 long tx_control = np->cur_tx->control;
1517
1518 if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */
1519 struct fealnx_desc *next;
1520
1521 next = np->cur_tx->next_desc_logical;
1522 tx_status = next->status;
1523 tx_control = next->control;
1524 }
1525
1526 if (tx_status & TXOWN)
1527 break;
1528
1529 if (!(np->crvalue & CR_W_ENH)) {
1530 if (tx_status & (CSL | LC | EC | UDF | HF)) {
1531 np->stats.tx_errors++;
1532 if (tx_status & EC)
1533 np->stats.tx_aborted_errors++;
1534 if (tx_status & CSL)
1535 np->stats.tx_carrier_errors++;
1536 if (tx_status & LC)
1537 np->stats.tx_window_errors++;
1538 if (tx_status & UDF)
1539 np->stats.tx_fifo_errors++;
1540 if ((tx_status & HF) && np->mii.full_duplex == 0)
1541 np->stats.tx_heartbeat_errors++;
1542
1543 } else {
1544 np->stats.tx_bytes +=
1545 ((tx_control & PKTSMask) >> PKTSShift);
1546
1547 np->stats.collisions +=
1548 ((tx_status & NCRMask) >> NCRShift);
1549 np->stats.tx_packets++;
1550 }
1551 } else {
1552 np->stats.tx_bytes +=
1553 ((tx_control & PKTSMask) >> PKTSShift);
1554 np->stats.tx_packets++;
1555 }
1556
1557 /* Free the original skb. */
1558 pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1559 np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1560 dev_kfree_skb_irq(np->cur_tx->skbuff);
1561 np->cur_tx->skbuff = NULL;
1562 --np->really_tx_count;
1563 if (np->cur_tx->control & TXLD) {
1564 np->cur_tx = np->cur_tx->next_desc_logical;
1565 ++np->free_tx_count;
1566 } else {
1567 np->cur_tx = np->cur_tx->next_desc_logical;
1568 np->cur_tx = np->cur_tx->next_desc_logical;
1569 np->free_tx_count += 2;
1570 }
1571 num_tx++;
1572 } /* end of for loop */
1573
1574 if (num_tx && np->free_tx_count >= 2)
1575 netif_wake_queue(dev);
1576
1577 /* read transmit status for enhanced mode only */
1578 if (np->crvalue & CR_W_ENH) {
1579 long data;
1580
1581 data = ioread32(ioaddr + TSR);
1582 np->stats.tx_errors += (data & 0xff000000) >> 24;
1583 np->stats.tx_aborted_errors += (data & 0xff000000) >> 24;
1584 np->stats.tx_window_errors += (data & 0x00ff0000) >> 16;
1585 np->stats.collisions += (data & 0x0000ffff);
1586 }
1587
1588 if (--boguscnt < 0) {
1589 printk(KERN_WARNING "%s: Too much work at interrupt, "
1590 "status=0x%4.4x.\n", dev->name, intr_status);
1591 if (!np->reset_timer_armed) {
1592 np->reset_timer_armed = 1;
1593 np->reset_timer.expires = RUN_AT(HZ/2);
1594 add_timer(&np->reset_timer);
1595 stop_nic_rxtx(ioaddr, 0);
1596 netif_stop_queue(dev);
1597 /* or netif_tx_disable(dev); ?? */
1598 /* Prevent other paths from enabling tx,rx,intrs */
1599 np->crvalue_sv = np->crvalue;
1600 np->imrvalue_sv = np->imrvalue;
1601 np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */
1602 np->imrvalue = 0;
1603 }
1604
1605 break;
1606 }
1607 } while (1);
1608
1609 /* read the tally counters */
1610 /* missed pkts */
1611 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1612
1613 /* crc error */
1614 np->stats.rx_crc_errors += (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1615
1616 if (debug)
1617 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1618 dev->name, ioread32(ioaddr + ISR));
1619
1620 iowrite32(np->imrvalue, ioaddr + IMR);
1621
1622 spin_unlock(&np->lock);
1623
1624 return IRQ_RETVAL(handled);
1625 }
1626
1627
1628 /* This routine is logically part of the interrupt handler, but separated
1629 for clarity and better register allocation. */
1630 static int netdev_rx(struct net_device *dev)
1631 {
1632 struct netdev_private *np = netdev_priv(dev);
1633 void __iomem *ioaddr = np->mem;
1634
1635 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1636 while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
1637 s32 rx_status = np->cur_rx->status;
1638
1639 if (np->really_rx_count == 0)
1640 break;
1641
1642 if (debug)
1643 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status);
1644
1645 if ((!((rx_status & RXFSD) && (rx_status & RXLSD)))
1646 || (rx_status & ErrorSummary)) {
1647 if (rx_status & ErrorSummary) { /* there was a fatal error */
1648 if (debug)
1649 printk(KERN_DEBUG
1650 "%s: Receive error, Rx status %8.8x.\n",
1651 dev->name, rx_status);
1652
1653 np->stats.rx_errors++; /* end of a packet. */
1654 if (rx_status & (LONG | RUNT))
1655 np->stats.rx_length_errors++;
1656 if (rx_status & RXER)
1657 np->stats.rx_frame_errors++;
1658 if (rx_status & CRC)
1659 np->stats.rx_crc_errors++;
1660 } else {
1661 int need_to_reset = 0;
1662 int desno = 0;
1663
1664 if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */
1665 struct fealnx_desc *cur;
1666
1667 /* check this packet is received completely? */
1668 cur = np->cur_rx;
1669 while (desno <= np->really_rx_count) {
1670 ++desno;
1671 if ((!(cur->status & RXOWN))
1672 && (cur->status & RXLSD))
1673 break;
1674 /* goto next rx descriptor */
1675 cur = cur->next_desc_logical;
1676 }
1677 if (desno > np->really_rx_count)
1678 need_to_reset = 1;
1679 } else /* RXLSD did not find, something error */
1680 need_to_reset = 1;
1681
1682 if (need_to_reset == 0) {
1683 int i;
1684
1685 np->stats.rx_length_errors++;
1686
1687 /* free all rx descriptors related this long pkt */
1688 for (i = 0; i < desno; ++i) {
1689 if (!np->cur_rx->skbuff) {
1690 printk(KERN_DEBUG
1691 "%s: I'm scared\n", dev->name);
1692 break;
1693 }
1694 np->cur_rx->status = RXOWN;
1695 np->cur_rx = np->cur_rx->next_desc_logical;
1696 }
1697 continue;
1698 } else { /* rx error, need to reset this chip */
1699 stop_nic_rx(ioaddr, np->crvalue);
1700 reset_rx_descriptors(dev);
1701 iowrite32(np->crvalue, ioaddr + TCRRCR);
1702 }
1703 break; /* exit the while loop */
1704 }
1705 } else { /* this received pkt is ok */
1706
1707 struct sk_buff *skb;
1708 /* Omit the four octet CRC from the length. */
1709 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4;
1710
1711 #ifndef final_version
1712 if (debug)
1713 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1714 " status %x.\n", pkt_len, rx_status);
1715 #endif
1716
1717 /* Check if the packet is long enough to accept without copying
1718 to a minimally-sized skbuff. */
1719 if (pkt_len < rx_copybreak &&
1720 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1721 skb_reserve(skb, 2); /* 16 byte align the IP header */
1722 pci_dma_sync_single_for_cpu(np->pci_dev,
1723 np->cur_rx->buffer,
1724 np->rx_buf_sz,
1725 PCI_DMA_FROMDEVICE);
1726 /* Call copy + cksum if available. */
1727
1728 #if ! defined(__alpha__)
1729 skb_copy_to_linear_data(skb,
1730 np->cur_rx->skbuff->data, pkt_len);
1731 skb_put(skb, pkt_len);
1732 #else
1733 memcpy(skb_put(skb, pkt_len),
1734 np->cur_rx->skbuff->data, pkt_len);
1735 #endif
1736 pci_dma_sync_single_for_device(np->pci_dev,
1737 np->cur_rx->buffer,
1738 np->rx_buf_sz,
1739 PCI_DMA_FROMDEVICE);
1740 } else {
1741 pci_unmap_single(np->pci_dev,
1742 np->cur_rx->buffer,
1743 np->rx_buf_sz,
1744 PCI_DMA_FROMDEVICE);
1745 skb_put(skb = np->cur_rx->skbuff, pkt_len);
1746 np->cur_rx->skbuff = NULL;
1747 --np->really_rx_count;
1748 }
1749 skb->protocol = eth_type_trans(skb, dev);
1750 netif_rx(skb);
1751 dev->last_rx = jiffies;
1752 np->stats.rx_packets++;
1753 np->stats.rx_bytes += pkt_len;
1754 }
1755
1756 np->cur_rx = np->cur_rx->next_desc_logical;
1757 } /* end of while loop */
1758
1759 /* allocate skb for rx buffers */
1760 allocate_rx_buffers(dev);
1761
1762 return 0;
1763 }
1764
1765
1766 static struct net_device_stats *get_stats(struct net_device *dev)
1767 {
1768 struct netdev_private *np = netdev_priv(dev);
1769 void __iomem *ioaddr = np->mem;
1770
1771 /* The chip only need report frame silently dropped. */
1772 if (netif_running(dev)) {
1773 np->stats.rx_missed_errors += ioread32(ioaddr + TALLY) & 0x7fff;
1774 np->stats.rx_crc_errors += (ioread32(ioaddr + TALLY) & 0x7fff0000) >> 16;
1775 }
1776
1777 return &np->stats;
1778 }
1779
1780
1781 /* for dev->set_multicast_list */
1782 static void set_rx_mode(struct net_device *dev)
1783 {
1784 spinlock_t *lp = &((struct netdev_private *)netdev_priv(dev))->lock;
1785 unsigned long flags;
1786 spin_lock_irqsave(lp, flags);
1787 __set_rx_mode(dev);
1788 spin_unlock_irqrestore(lp, flags);
1789 }
1790
1791
1792 /* Take lock before calling */
1793 static void __set_rx_mode(struct net_device *dev)
1794 {
1795 struct netdev_private *np = netdev_priv(dev);
1796 void __iomem *ioaddr = np->mem;
1797 u32 mc_filter[2]; /* Multicast hash filter */
1798 u32 rx_mode;
1799
1800 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1801 memset(mc_filter, 0xff, sizeof(mc_filter));
1802 rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM;
1803 } else if ((dev->mc_count > multicast_filter_limit)
1804 || (dev->flags & IFF_ALLMULTI)) {
1805 /* Too many to match, or accept all multicasts. */
1806 memset(mc_filter, 0xff, sizeof(mc_filter));
1807 rx_mode = CR_W_AB | CR_W_AM;
1808 } else {
1809 struct dev_mc_list *mclist;
1810 int i;
1811
1812 memset(mc_filter, 0, sizeof(mc_filter));
1813 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1814 i++, mclist = mclist->next) {
1815 unsigned int bit;
1816 bit = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26) ^ 0x3F;
1817 mc_filter[bit >> 5] |= (1 << bit);
1818 }
1819 rx_mode = CR_W_AB | CR_W_AM;
1820 }
1821
1822 stop_nic_rxtx(ioaddr, np->crvalue);
1823
1824 iowrite32(mc_filter[0], ioaddr + MAR0);
1825 iowrite32(mc_filter[1], ioaddr + MAR1);
1826 np->crvalue &= ~CR_W_RXMODEMASK;
1827 np->crvalue |= rx_mode;
1828 iowrite32(np->crvalue, ioaddr + TCRRCR);
1829 }
1830
1831 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1832 {
1833 struct netdev_private *np = netdev_priv(dev);
1834
1835 strcpy(info->driver, DRV_NAME);
1836 strcpy(info->version, DRV_VERSION);
1837 strcpy(info->bus_info, pci_name(np->pci_dev));
1838 }
1839
1840 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1841 {
1842 struct netdev_private *np = netdev_priv(dev);
1843 int rc;
1844
1845 spin_lock_irq(&np->lock);
1846 rc = mii_ethtool_gset(&np->mii, cmd);
1847 spin_unlock_irq(&np->lock);
1848
1849 return rc;
1850 }
1851
1852 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1853 {
1854 struct netdev_private *np = netdev_priv(dev);
1855 int rc;
1856
1857 spin_lock_irq(&np->lock);
1858 rc = mii_ethtool_sset(&np->mii, cmd);
1859 spin_unlock_irq(&np->lock);
1860
1861 return rc;
1862 }
1863
1864 static int netdev_nway_reset(struct net_device *dev)
1865 {
1866 struct netdev_private *np = netdev_priv(dev);
1867 return mii_nway_restart(&np->mii);
1868 }
1869
1870 static u32 netdev_get_link(struct net_device *dev)
1871 {
1872 struct netdev_private *np = netdev_priv(dev);
1873 return mii_link_ok(&np->mii);
1874 }
1875
1876 static u32 netdev_get_msglevel(struct net_device *dev)
1877 {
1878 return debug;
1879 }
1880
1881 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1882 {
1883 debug = value;
1884 }
1885
1886 static const struct ethtool_ops netdev_ethtool_ops = {
1887 .get_drvinfo = netdev_get_drvinfo,
1888 .get_settings = netdev_get_settings,
1889 .set_settings = netdev_set_settings,
1890 .nway_reset = netdev_nway_reset,
1891 .get_link = netdev_get_link,
1892 .get_msglevel = netdev_get_msglevel,
1893 .set_msglevel = netdev_set_msglevel,
1894 .get_sg = ethtool_op_get_sg,
1895 .get_tx_csum = ethtool_op_get_tx_csum,
1896 };
1897
1898 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1899 {
1900 struct netdev_private *np = netdev_priv(dev);
1901 int rc;
1902
1903 if (!netif_running(dev))
1904 return -EINVAL;
1905
1906 spin_lock_irq(&np->lock);
1907 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
1908 spin_unlock_irq(&np->lock);
1909
1910 return rc;
1911 }
1912
1913
1914 static int netdev_close(struct net_device *dev)
1915 {
1916 struct netdev_private *np = netdev_priv(dev);
1917 void __iomem *ioaddr = np->mem;
1918 int i;
1919
1920 netif_stop_queue(dev);
1921
1922 /* Disable interrupts by clearing the interrupt mask. */
1923 iowrite32(0x0000, ioaddr + IMR);
1924
1925 /* Stop the chip's Tx and Rx processes. */
1926 stop_nic_rxtx(ioaddr, 0);
1927
1928 del_timer_sync(&np->timer);
1929 del_timer_sync(&np->reset_timer);
1930
1931 free_irq(dev->irq, dev);
1932
1933 /* Free all the skbuffs in the Rx queue. */
1934 for (i = 0; i < RX_RING_SIZE; i++) {
1935 struct sk_buff *skb = np->rx_ring[i].skbuff;
1936
1937 np->rx_ring[i].status = 0;
1938 if (skb) {
1939 pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1940 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1941 dev_kfree_skb(skb);
1942 np->rx_ring[i].skbuff = NULL;
1943 }
1944 }
1945
1946 for (i = 0; i < TX_RING_SIZE; i++) {
1947 struct sk_buff *skb = np->tx_ring[i].skbuff;
1948
1949 if (skb) {
1950 pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1951 skb->len, PCI_DMA_TODEVICE);
1952 dev_kfree_skb(skb);
1953 np->tx_ring[i].skbuff = NULL;
1954 }
1955 }
1956
1957 return 0;
1958 }
1959
1960 static struct pci_device_id fealnx_pci_tbl[] = {
1961 {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1962 {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1963 {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1964 {} /* terminate list */
1965 };
1966 MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl);
1967
1968
1969 static struct pci_driver fealnx_driver = {
1970 .name = "fealnx",
1971 .id_table = fealnx_pci_tbl,
1972 .probe = fealnx_init_one,
1973 .remove = __devexit_p(fealnx_remove_one),
1974 };
1975
1976 static int __init fealnx_init(void)
1977 {
1978 /* when a module, this is printed whether or not devices are found in probe */
1979 #ifdef MODULE
1980 printk(version);
1981 #endif
1982
1983 return pci_register_driver(&fealnx_driver);
1984 }
1985
1986 static void __exit fealnx_exit(void)
1987 {
1988 pci_unregister_driver(&fealnx_driver);
1989 }
1990
1991 module_init(fealnx_init);
1992 module_exit(fealnx_exit);
Linux kernel - Deliverables
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