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ipsec: update MAX_AH_AUTH_LEN to support sha512
[deliverable/linux.git] / drivers / net / fec.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010 Freescale Semiconductor, Inc.
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
41 #include <linux/io.h>
42 #include <linux/irq.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/phy.h>
46 #include <linux/fec.h>
47
48 #include <asm/cacheflush.h>
49
50 #ifndef CONFIG_ARM
51 #include <asm/coldfire.h>
52 #include <asm/mcfsim.h>
53 #endif
54
55 #include "fec.h"
56
57 #if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
58 #define FEC_ALIGNMENT 0xf
59 #else
60 #define FEC_ALIGNMENT 0x3
61 #endif
62
63 #define DRIVER_NAME "fec"
64
65 /* Controller is ENET-MAC */
66 #define FEC_QUIRK_ENET_MAC (1 << 0)
67 /* Controller needs driver to swap frame */
68 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
69
70 static struct platform_device_id fec_devtype[] = {
71 {
72 .name = DRIVER_NAME,
73 .driver_data = 0,
74 }, {
75 .name = "imx28-fec",
76 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
77 }
78 };
79
80 static unsigned char macaddr[ETH_ALEN];
81 module_param_array(macaddr, byte, NULL, 0);
82 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
83
84 #if defined(CONFIG_M5272)
85 /*
86 * Some hardware gets it MAC address out of local flash memory.
87 * if this is non-zero then assume it is the address to get MAC from.
88 */
89 #if defined(CONFIG_NETtel)
90 #define FEC_FLASHMAC 0xf0006006
91 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
92 #define FEC_FLASHMAC 0xf0006000
93 #elif defined(CONFIG_CANCam)
94 #define FEC_FLASHMAC 0xf0020000
95 #elif defined (CONFIG_M5272C3)
96 #define FEC_FLASHMAC (0xffe04000 + 4)
97 #elif defined(CONFIG_MOD5272)
98 #define FEC_FLASHMAC 0xffc0406b
99 #else
100 #define FEC_FLASHMAC 0
101 #endif
102 #endif /* CONFIG_M5272 */
103
104 /* The number of Tx and Rx buffers. These are allocated from the page
105 * pool. The code may assume these are power of two, so it it best
106 * to keep them that size.
107 * We don't need to allocate pages for the transmitter. We just use
108 * the skbuffer directly.
109 */
110 #define FEC_ENET_RX_PAGES 8
111 #define FEC_ENET_RX_FRSIZE 2048
112 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
113 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
114 #define FEC_ENET_TX_FRSIZE 2048
115 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
116 #define TX_RING_SIZE 16 /* Must be power of two */
117 #define TX_RING_MOD_MASK 15 /* for this to work */
118
119 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
120 #error "FEC: descriptor ring size constants too large"
121 #endif
122
123 /* Interrupt events/masks. */
124 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
125 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
126 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
127 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
128 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
129 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
130 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
131 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
132 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
133 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
134
135 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
136
137 /* The FEC stores dest/src/type, data, and checksum for receive packets.
138 */
139 #define PKT_MAXBUF_SIZE 1518
140 #define PKT_MINBUF_SIZE 64
141 #define PKT_MAXBLR_SIZE 1520
142
143
144 /*
145 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
146 * size bits. Other FEC hardware does not, so we need to take that into
147 * account when setting it.
148 */
149 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
150 defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
151 defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
152 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
153 #else
154 #define OPT_FRAME_SIZE 0
155 #endif
156
157 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
158 * tx_bd_base always point to the base of the buffer descriptors. The
159 * cur_rx and cur_tx point to the currently available buffer.
160 * The dirty_tx tracks the current buffer that is being sent by the
161 * controller. The cur_tx and dirty_tx are equal under both completely
162 * empty and completely full conditions. The empty/ready indicator in
163 * the buffer descriptor determines the actual condition.
164 */
165 struct fec_enet_private {
166 /* Hardware registers of the FEC device */
167 void __iomem *hwp;
168
169 struct net_device *netdev;
170
171 struct clk *clk;
172
173 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
174 unsigned char *tx_bounce[TX_RING_SIZE];
175 struct sk_buff* tx_skbuff[TX_RING_SIZE];
176 struct sk_buff* rx_skbuff[RX_RING_SIZE];
177 ushort skb_cur;
178 ushort skb_dirty;
179
180 /* CPM dual port RAM relative addresses */
181 dma_addr_t bd_dma;
182 /* Address of Rx and Tx buffers */
183 struct bufdesc *rx_bd_base;
184 struct bufdesc *tx_bd_base;
185 /* The next free ring entry */
186 struct bufdesc *cur_rx, *cur_tx;
187 /* The ring entries to be free()ed */
188 struct bufdesc *dirty_tx;
189
190 uint tx_full;
191 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
192 spinlock_t hw_lock;
193
194 struct platform_device *pdev;
195
196 int opened;
197
198 /* Phylib and MDIO interface */
199 struct mii_bus *mii_bus;
200 struct phy_device *phy_dev;
201 int mii_timeout;
202 uint phy_speed;
203 phy_interface_t phy_interface;
204 int link;
205 int full_duplex;
206 struct completion mdio_done;
207 };
208
209 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
210 static void fec_enet_tx(struct net_device *dev);
211 static void fec_enet_rx(struct net_device *dev);
212 static int fec_enet_close(struct net_device *dev);
213 static void fec_restart(struct net_device *dev, int duplex);
214 static void fec_stop(struct net_device *dev);
215
216 /* FEC MII MMFR bits definition */
217 #define FEC_MMFR_ST (1 << 30)
218 #define FEC_MMFR_OP_READ (2 << 28)
219 #define FEC_MMFR_OP_WRITE (1 << 28)
220 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
221 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
222 #define FEC_MMFR_TA (2 << 16)
223 #define FEC_MMFR_DATA(v) (v & 0xffff)
224
225 #define FEC_MII_TIMEOUT 1000 /* us */
226
227 /* Transmitter timeout */
228 #define TX_TIMEOUT (2 * HZ)
229
230 static void *swap_buffer(void *bufaddr, int len)
231 {
232 int i;
233 unsigned int *buf = bufaddr;
234
235 for (i = 0; i < (len + 3) / 4; i++, buf++)
236 *buf = cpu_to_be32(*buf);
237
238 return bufaddr;
239 }
240
241 static netdev_tx_t
242 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
243 {
244 struct fec_enet_private *fep = netdev_priv(dev);
245 const struct platform_device_id *id_entry =
246 platform_get_device_id(fep->pdev);
247 struct bufdesc *bdp;
248 void *bufaddr;
249 unsigned short status;
250 unsigned long flags;
251
252 if (!fep->link) {
253 /* Link is down or autonegotiation is in progress. */
254 return NETDEV_TX_BUSY;
255 }
256
257 spin_lock_irqsave(&fep->hw_lock, flags);
258 /* Fill in a Tx ring entry */
259 bdp = fep->cur_tx;
260
261 status = bdp->cbd_sc;
262
263 if (status & BD_ENET_TX_READY) {
264 /* Ooops. All transmit buffers are full. Bail out.
265 * This should not happen, since dev->tbusy should be set.
266 */
267 printk("%s: tx queue full!.\n", dev->name);
268 spin_unlock_irqrestore(&fep->hw_lock, flags);
269 return NETDEV_TX_BUSY;
270 }
271
272 /* Clear all of the status flags */
273 status &= ~BD_ENET_TX_STATS;
274
275 /* Set buffer length and buffer pointer */
276 bufaddr = skb->data;
277 bdp->cbd_datlen = skb->len;
278
279 /*
280 * On some FEC implementations data must be aligned on
281 * 4-byte boundaries. Use bounce buffers to copy data
282 * and get it aligned. Ugh.
283 */
284 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
285 unsigned int index;
286 index = bdp - fep->tx_bd_base;
287 memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len);
288 bufaddr = fep->tx_bounce[index];
289 }
290
291 /*
292 * Some design made an incorrect assumption on endian mode of
293 * the system that it's running on. As the result, driver has to
294 * swap every frame going to and coming from the controller.
295 */
296 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
297 swap_buffer(bufaddr, skb->len);
298
299 /* Save skb pointer */
300 fep->tx_skbuff[fep->skb_cur] = skb;
301
302 dev->stats.tx_bytes += skb->len;
303 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
304
305 /* Push the data cache so the CPM does not get stale memory
306 * data.
307 */
308 bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr,
309 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
310
311 /* Send it on its way. Tell FEC it's ready, interrupt when done,
312 * it's the last BD of the frame, and to put the CRC on the end.
313 */
314 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
315 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
316 bdp->cbd_sc = status;
317
318 /* Trigger transmission start */
319 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
320
321 /* If this was the last BD in the ring, start at the beginning again. */
322 if (status & BD_ENET_TX_WRAP)
323 bdp = fep->tx_bd_base;
324 else
325 bdp++;
326
327 if (bdp == fep->dirty_tx) {
328 fep->tx_full = 1;
329 netif_stop_queue(dev);
330 }
331
332 fep->cur_tx = bdp;
333
334 spin_unlock_irqrestore(&fep->hw_lock, flags);
335
336 return NETDEV_TX_OK;
337 }
338
339 static void
340 fec_timeout(struct net_device *dev)
341 {
342 struct fec_enet_private *fep = netdev_priv(dev);
343
344 dev->stats.tx_errors++;
345
346 fec_restart(dev, fep->full_duplex);
347 netif_wake_queue(dev);
348 }
349
350 static irqreturn_t
351 fec_enet_interrupt(int irq, void * dev_id)
352 {
353 struct net_device *dev = dev_id;
354 struct fec_enet_private *fep = netdev_priv(dev);
355 uint int_events;
356 irqreturn_t ret = IRQ_NONE;
357
358 do {
359 int_events = readl(fep->hwp + FEC_IEVENT);
360 writel(int_events, fep->hwp + FEC_IEVENT);
361
362 if (int_events & FEC_ENET_RXF) {
363 ret = IRQ_HANDLED;
364 fec_enet_rx(dev);
365 }
366
367 /* Transmit OK, or non-fatal error. Update the buffer
368 * descriptors. FEC handles all errors, we just discover
369 * them as part of the transmit process.
370 */
371 if (int_events & FEC_ENET_TXF) {
372 ret = IRQ_HANDLED;
373 fec_enet_tx(dev);
374 }
375
376 if (int_events & FEC_ENET_MII) {
377 ret = IRQ_HANDLED;
378 complete(&fep->mdio_done);
379 }
380 } while (int_events);
381
382 return ret;
383 }
384
385
386 static void
387 fec_enet_tx(struct net_device *dev)
388 {
389 struct fec_enet_private *fep;
390 struct bufdesc *bdp;
391 unsigned short status;
392 struct sk_buff *skb;
393
394 fep = netdev_priv(dev);
395 spin_lock(&fep->hw_lock);
396 bdp = fep->dirty_tx;
397
398 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
399 if (bdp == fep->cur_tx && fep->tx_full == 0)
400 break;
401
402 dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
403 bdp->cbd_bufaddr = 0;
404
405 skb = fep->tx_skbuff[fep->skb_dirty];
406 /* Check for errors. */
407 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
408 BD_ENET_TX_RL | BD_ENET_TX_UN |
409 BD_ENET_TX_CSL)) {
410 dev->stats.tx_errors++;
411 if (status & BD_ENET_TX_HB) /* No heartbeat */
412 dev->stats.tx_heartbeat_errors++;
413 if (status & BD_ENET_TX_LC) /* Late collision */
414 dev->stats.tx_window_errors++;
415 if (status & BD_ENET_TX_RL) /* Retrans limit */
416 dev->stats.tx_aborted_errors++;
417 if (status & BD_ENET_TX_UN) /* Underrun */
418 dev->stats.tx_fifo_errors++;
419 if (status & BD_ENET_TX_CSL) /* Carrier lost */
420 dev->stats.tx_carrier_errors++;
421 } else {
422 dev->stats.tx_packets++;
423 }
424
425 if (status & BD_ENET_TX_READY)
426 printk("HEY! Enet xmit interrupt and TX_READY.\n");
427
428 /* Deferred means some collisions occurred during transmit,
429 * but we eventually sent the packet OK.
430 */
431 if (status & BD_ENET_TX_DEF)
432 dev->stats.collisions++;
433
434 /* Free the sk buffer associated with this last transmit */
435 dev_kfree_skb_any(skb);
436 fep->tx_skbuff[fep->skb_dirty] = NULL;
437 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
438
439 /* Update pointer to next buffer descriptor to be transmitted */
440 if (status & BD_ENET_TX_WRAP)
441 bdp = fep->tx_bd_base;
442 else
443 bdp++;
444
445 /* Since we have freed up a buffer, the ring is no longer full
446 */
447 if (fep->tx_full) {
448 fep->tx_full = 0;
449 if (netif_queue_stopped(dev))
450 netif_wake_queue(dev);
451 }
452 }
453 fep->dirty_tx = bdp;
454 spin_unlock(&fep->hw_lock);
455 }
456
457
458 /* During a receive, the cur_rx points to the current incoming buffer.
459 * When we update through the ring, if the next incoming buffer has
460 * not been given to the system, we just set the empty indicator,
461 * effectively tossing the packet.
462 */
463 static void
464 fec_enet_rx(struct net_device *dev)
465 {
466 struct fec_enet_private *fep = netdev_priv(dev);
467 const struct platform_device_id *id_entry =
468 platform_get_device_id(fep->pdev);
469 struct bufdesc *bdp;
470 unsigned short status;
471 struct sk_buff *skb;
472 ushort pkt_len;
473 __u8 *data;
474
475 #ifdef CONFIG_M532x
476 flush_cache_all();
477 #endif
478
479 spin_lock(&fep->hw_lock);
480
481 /* First, grab all of the stats for the incoming packet.
482 * These get messed up if we get called due to a busy condition.
483 */
484 bdp = fep->cur_rx;
485
486 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
487
488 /* Since we have allocated space to hold a complete frame,
489 * the last indicator should be set.
490 */
491 if ((status & BD_ENET_RX_LAST) == 0)
492 printk("FEC ENET: rcv is not +last\n");
493
494 if (!fep->opened)
495 goto rx_processing_done;
496
497 /* Check for errors. */
498 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
499 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
500 dev->stats.rx_errors++;
501 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
502 /* Frame too long or too short. */
503 dev->stats.rx_length_errors++;
504 }
505 if (status & BD_ENET_RX_NO) /* Frame alignment */
506 dev->stats.rx_frame_errors++;
507 if (status & BD_ENET_RX_CR) /* CRC Error */
508 dev->stats.rx_crc_errors++;
509 if (status & BD_ENET_RX_OV) /* FIFO overrun */
510 dev->stats.rx_fifo_errors++;
511 }
512
513 /* Report late collisions as a frame error.
514 * On this error, the BD is closed, but we don't know what we
515 * have in the buffer. So, just drop this frame on the floor.
516 */
517 if (status & BD_ENET_RX_CL) {
518 dev->stats.rx_errors++;
519 dev->stats.rx_frame_errors++;
520 goto rx_processing_done;
521 }
522
523 /* Process the incoming frame. */
524 dev->stats.rx_packets++;
525 pkt_len = bdp->cbd_datlen;
526 dev->stats.rx_bytes += pkt_len;
527 data = (__u8*)__va(bdp->cbd_bufaddr);
528
529 dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
530 DMA_FROM_DEVICE);
531
532 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
533 swap_buffer(data, pkt_len);
534
535 /* This does 16 byte alignment, exactly what we need.
536 * The packet length includes FCS, but we don't want to
537 * include that when passing upstream as it messes up
538 * bridging applications.
539 */
540 skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
541
542 if (unlikely(!skb)) {
543 printk("%s: Memory squeeze, dropping packet.\n",
544 dev->name);
545 dev->stats.rx_dropped++;
546 } else {
547 skb_reserve(skb, NET_IP_ALIGN);
548 skb_put(skb, pkt_len - 4); /* Make room */
549 skb_copy_to_linear_data(skb, data, pkt_len - 4);
550 skb->protocol = eth_type_trans(skb, dev);
551 netif_rx(skb);
552 }
553
554 bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen,
555 DMA_FROM_DEVICE);
556 rx_processing_done:
557 /* Clear the status flags for this buffer */
558 status &= ~BD_ENET_RX_STATS;
559
560 /* Mark the buffer empty */
561 status |= BD_ENET_RX_EMPTY;
562 bdp->cbd_sc = status;
563
564 /* Update BD pointer to next entry */
565 if (status & BD_ENET_RX_WRAP)
566 bdp = fep->rx_bd_base;
567 else
568 bdp++;
569 /* Doing this here will keep the FEC running while we process
570 * incoming frames. On a heavily loaded network, we should be
571 * able to keep up at the expense of system resources.
572 */
573 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
574 }
575 fep->cur_rx = bdp;
576
577 spin_unlock(&fep->hw_lock);
578 }
579
580 /* ------------------------------------------------------------------------- */
581 static void __inline__ fec_get_mac(struct net_device *dev)
582 {
583 struct fec_enet_private *fep = netdev_priv(dev);
584 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
585 unsigned char *iap, tmpaddr[ETH_ALEN];
586
587 /*
588 * try to get mac address in following order:
589 *
590 * 1) module parameter via kernel command line in form
591 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
592 */
593 iap = macaddr;
594
595 /*
596 * 2) from flash or fuse (via platform data)
597 */
598 if (!is_valid_ether_addr(iap)) {
599 #ifdef CONFIG_M5272
600 if (FEC_FLASHMAC)
601 iap = (unsigned char *)FEC_FLASHMAC;
602 #else
603 if (pdata)
604 memcpy(iap, pdata->mac, ETH_ALEN);
605 #endif
606 }
607
608 /*
609 * 3) FEC mac registers set by bootloader
610 */
611 if (!is_valid_ether_addr(iap)) {
612 *((unsigned long *) &tmpaddr[0]) =
613 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
614 *((unsigned short *) &tmpaddr[4]) =
615 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
616 iap = &tmpaddr[0];
617 }
618
619 memcpy(dev->dev_addr, iap, ETH_ALEN);
620
621 /* Adjust MAC if using macaddr */
622 if (iap == macaddr)
623 dev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id;
624 }
625
626 /* ------------------------------------------------------------------------- */
627
628 /*
629 * Phy section
630 */
631 static void fec_enet_adjust_link(struct net_device *dev)
632 {
633 struct fec_enet_private *fep = netdev_priv(dev);
634 struct phy_device *phy_dev = fep->phy_dev;
635 unsigned long flags;
636
637 int status_change = 0;
638
639 spin_lock_irqsave(&fep->hw_lock, flags);
640
641 /* Prevent a state halted on mii error */
642 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
643 phy_dev->state = PHY_RESUMING;
644 goto spin_unlock;
645 }
646
647 /* Duplex link change */
648 if (phy_dev->link) {
649 if (fep->full_duplex != phy_dev->duplex) {
650 fec_restart(dev, phy_dev->duplex);
651 status_change = 1;
652 }
653 }
654
655 /* Link on or off change */
656 if (phy_dev->link != fep->link) {
657 fep->link = phy_dev->link;
658 if (phy_dev->link)
659 fec_restart(dev, phy_dev->duplex);
660 else
661 fec_stop(dev);
662 status_change = 1;
663 }
664
665 spin_unlock:
666 spin_unlock_irqrestore(&fep->hw_lock, flags);
667
668 if (status_change)
669 phy_print_status(phy_dev);
670 }
671
672 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
673 {
674 struct fec_enet_private *fep = bus->priv;
675 unsigned long time_left;
676
677 fep->mii_timeout = 0;
678 init_completion(&fep->mdio_done);
679
680 /* start a read op */
681 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
682 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
683 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
684
685 /* wait for end of transfer */
686 time_left = wait_for_completion_timeout(&fep->mdio_done,
687 usecs_to_jiffies(FEC_MII_TIMEOUT));
688 if (time_left == 0) {
689 fep->mii_timeout = 1;
690 printk(KERN_ERR "FEC: MDIO read timeout\n");
691 return -ETIMEDOUT;
692 }
693
694 /* return value */
695 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
696 }
697
698 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
699 u16 value)
700 {
701 struct fec_enet_private *fep = bus->priv;
702 unsigned long time_left;
703
704 fep->mii_timeout = 0;
705 init_completion(&fep->mdio_done);
706
707 /* start a write op */
708 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
709 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
710 FEC_MMFR_TA | FEC_MMFR_DATA(value),
711 fep->hwp + FEC_MII_DATA);
712
713 /* wait for end of transfer */
714 time_left = wait_for_completion_timeout(&fep->mdio_done,
715 usecs_to_jiffies(FEC_MII_TIMEOUT));
716 if (time_left == 0) {
717 fep->mii_timeout = 1;
718 printk(KERN_ERR "FEC: MDIO write timeout\n");
719 return -ETIMEDOUT;
720 }
721
722 return 0;
723 }
724
725 static int fec_enet_mdio_reset(struct mii_bus *bus)
726 {
727 return 0;
728 }
729
730 static int fec_enet_mii_probe(struct net_device *dev)
731 {
732 struct fec_enet_private *fep = netdev_priv(dev);
733 struct phy_device *phy_dev = NULL;
734 char mdio_bus_id[MII_BUS_ID_SIZE];
735 char phy_name[MII_BUS_ID_SIZE + 3];
736 int phy_id;
737 int dev_id = fep->pdev->id;
738
739 fep->phy_dev = NULL;
740
741 /* check for attached phy */
742 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
743 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
744 continue;
745 if (fep->mii_bus->phy_map[phy_id] == NULL)
746 continue;
747 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
748 continue;
749 if (dev_id--)
750 continue;
751 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
752 break;
753 }
754
755 if (phy_id >= PHY_MAX_ADDR) {
756 printk(KERN_INFO "%s: no PHY, assuming direct connection "
757 "to switch\n", dev->name);
758 strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE);
759 phy_id = 0;
760 }
761
762 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
763 phy_dev = phy_connect(dev, phy_name, &fec_enet_adjust_link, 0,
764 PHY_INTERFACE_MODE_MII);
765 if (IS_ERR(phy_dev)) {
766 printk(KERN_ERR "%s: could not attach to PHY\n", dev->name);
767 return PTR_ERR(phy_dev);
768 }
769
770 /* mask with MAC supported features */
771 phy_dev->supported &= PHY_BASIC_FEATURES;
772 phy_dev->advertising = phy_dev->supported;
773
774 fep->phy_dev = phy_dev;
775 fep->link = 0;
776 fep->full_duplex = 0;
777
778 printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] "
779 "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name,
780 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
781 fep->phy_dev->irq);
782
783 return 0;
784 }
785
786 static int fec_enet_mii_init(struct platform_device *pdev)
787 {
788 static struct mii_bus *fec0_mii_bus;
789 struct net_device *dev = platform_get_drvdata(pdev);
790 struct fec_enet_private *fep = netdev_priv(dev);
791 const struct platform_device_id *id_entry =
792 platform_get_device_id(fep->pdev);
793 int err = -ENXIO, i;
794
795 /*
796 * The dual fec interfaces are not equivalent with enet-mac.
797 * Here are the differences:
798 *
799 * - fec0 supports MII & RMII modes while fec1 only supports RMII
800 * - fec0 acts as the 1588 time master while fec1 is slave
801 * - external phys can only be configured by fec0
802 *
803 * That is to say fec1 can not work independently. It only works
804 * when fec0 is working. The reason behind this design is that the
805 * second interface is added primarily for Switch mode.
806 *
807 * Because of the last point above, both phys are attached on fec0
808 * mdio interface in board design, and need to be configured by
809 * fec0 mii_bus.
810 */
811 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) {
812 /* fec1 uses fec0 mii_bus */
813 fep->mii_bus = fec0_mii_bus;
814 return 0;
815 }
816
817 fep->mii_timeout = 0;
818
819 /*
820 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
821 */
822 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
823 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
824
825 fep->mii_bus = mdiobus_alloc();
826 if (fep->mii_bus == NULL) {
827 err = -ENOMEM;
828 goto err_out;
829 }
830
831 fep->mii_bus->name = "fec_enet_mii_bus";
832 fep->mii_bus->read = fec_enet_mdio_read;
833 fep->mii_bus->write = fec_enet_mdio_write;
834 fep->mii_bus->reset = fec_enet_mdio_reset;
835 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id + 1);
836 fep->mii_bus->priv = fep;
837 fep->mii_bus->parent = &pdev->dev;
838
839 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
840 if (!fep->mii_bus->irq) {
841 err = -ENOMEM;
842 goto err_out_free_mdiobus;
843 }
844
845 for (i = 0; i < PHY_MAX_ADDR; i++)
846 fep->mii_bus->irq[i] = PHY_POLL;
847
848 platform_set_drvdata(dev, fep->mii_bus);
849
850 if (mdiobus_register(fep->mii_bus))
851 goto err_out_free_mdio_irq;
852
853 /* save fec0 mii_bus */
854 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
855 fec0_mii_bus = fep->mii_bus;
856
857 return 0;
858
859 err_out_free_mdio_irq:
860 kfree(fep->mii_bus->irq);
861 err_out_free_mdiobus:
862 mdiobus_free(fep->mii_bus);
863 err_out:
864 return err;
865 }
866
867 static void fec_enet_mii_remove(struct fec_enet_private *fep)
868 {
869 if (fep->phy_dev)
870 phy_disconnect(fep->phy_dev);
871 mdiobus_unregister(fep->mii_bus);
872 kfree(fep->mii_bus->irq);
873 mdiobus_free(fep->mii_bus);
874 }
875
876 static int fec_enet_get_settings(struct net_device *dev,
877 struct ethtool_cmd *cmd)
878 {
879 struct fec_enet_private *fep = netdev_priv(dev);
880 struct phy_device *phydev = fep->phy_dev;
881
882 if (!phydev)
883 return -ENODEV;
884
885 return phy_ethtool_gset(phydev, cmd);
886 }
887
888 static int fec_enet_set_settings(struct net_device *dev,
889 struct ethtool_cmd *cmd)
890 {
891 struct fec_enet_private *fep = netdev_priv(dev);
892 struct phy_device *phydev = fep->phy_dev;
893
894 if (!phydev)
895 return -ENODEV;
896
897 return phy_ethtool_sset(phydev, cmd);
898 }
899
900 static void fec_enet_get_drvinfo(struct net_device *dev,
901 struct ethtool_drvinfo *info)
902 {
903 struct fec_enet_private *fep = netdev_priv(dev);
904
905 strcpy(info->driver, fep->pdev->dev.driver->name);
906 strcpy(info->version, "Revision: 1.0");
907 strcpy(info->bus_info, dev_name(&dev->dev));
908 }
909
910 static struct ethtool_ops fec_enet_ethtool_ops = {
911 .get_settings = fec_enet_get_settings,
912 .set_settings = fec_enet_set_settings,
913 .get_drvinfo = fec_enet_get_drvinfo,
914 .get_link = ethtool_op_get_link,
915 };
916
917 static int fec_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
918 {
919 struct fec_enet_private *fep = netdev_priv(dev);
920 struct phy_device *phydev = fep->phy_dev;
921
922 if (!netif_running(dev))
923 return -EINVAL;
924
925 if (!phydev)
926 return -ENODEV;
927
928 return phy_mii_ioctl(phydev, rq, cmd);
929 }
930
931 static void fec_enet_free_buffers(struct net_device *dev)
932 {
933 struct fec_enet_private *fep = netdev_priv(dev);
934 int i;
935 struct sk_buff *skb;
936 struct bufdesc *bdp;
937
938 bdp = fep->rx_bd_base;
939 for (i = 0; i < RX_RING_SIZE; i++) {
940 skb = fep->rx_skbuff[i];
941
942 if (bdp->cbd_bufaddr)
943 dma_unmap_single(&dev->dev, bdp->cbd_bufaddr,
944 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
945 if (skb)
946 dev_kfree_skb(skb);
947 bdp++;
948 }
949
950 bdp = fep->tx_bd_base;
951 for (i = 0; i < TX_RING_SIZE; i++)
952 kfree(fep->tx_bounce[i]);
953 }
954
955 static int fec_enet_alloc_buffers(struct net_device *dev)
956 {
957 struct fec_enet_private *fep = netdev_priv(dev);
958 int i;
959 struct sk_buff *skb;
960 struct bufdesc *bdp;
961
962 bdp = fep->rx_bd_base;
963 for (i = 0; i < RX_RING_SIZE; i++) {
964 skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE);
965 if (!skb) {
966 fec_enet_free_buffers(dev);
967 return -ENOMEM;
968 }
969 fep->rx_skbuff[i] = skb;
970
971 bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data,
972 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
973 bdp->cbd_sc = BD_ENET_RX_EMPTY;
974 bdp++;
975 }
976
977 /* Set the last buffer to wrap. */
978 bdp--;
979 bdp->cbd_sc |= BD_SC_WRAP;
980
981 bdp = fep->tx_bd_base;
982 for (i = 0; i < TX_RING_SIZE; i++) {
983 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
984
985 bdp->cbd_sc = 0;
986 bdp->cbd_bufaddr = 0;
987 bdp++;
988 }
989
990 /* Set the last buffer to wrap. */
991 bdp--;
992 bdp->cbd_sc |= BD_SC_WRAP;
993
994 return 0;
995 }
996
997 static int
998 fec_enet_open(struct net_device *dev)
999 {
1000 struct fec_enet_private *fep = netdev_priv(dev);
1001 int ret;
1002
1003 /* I should reset the ring buffers here, but I don't yet know
1004 * a simple way to do that.
1005 */
1006
1007 ret = fec_enet_alloc_buffers(dev);
1008 if (ret)
1009 return ret;
1010
1011 /* Probe and connect to PHY when open the interface */
1012 ret = fec_enet_mii_probe(dev);
1013 if (ret) {
1014 fec_enet_free_buffers(dev);
1015 return ret;
1016 }
1017 phy_start(fep->phy_dev);
1018 netif_start_queue(dev);
1019 fep->opened = 1;
1020 return 0;
1021 }
1022
1023 static int
1024 fec_enet_close(struct net_device *dev)
1025 {
1026 struct fec_enet_private *fep = netdev_priv(dev);
1027
1028 /* Don't know what to do yet. */
1029 fep->opened = 0;
1030 netif_stop_queue(dev);
1031 fec_stop(dev);
1032
1033 if (fep->phy_dev)
1034 phy_disconnect(fep->phy_dev);
1035
1036 fec_enet_free_buffers(dev);
1037
1038 return 0;
1039 }
1040
1041 /* Set or clear the multicast filter for this adaptor.
1042 * Skeleton taken from sunlance driver.
1043 * The CPM Ethernet implementation allows Multicast as well as individual
1044 * MAC address filtering. Some of the drivers check to make sure it is
1045 * a group multicast address, and discard those that are not. I guess I
1046 * will do the same for now, but just remove the test if you want
1047 * individual filtering as well (do the upper net layers want or support
1048 * this kind of feature?).
1049 */
1050
1051 #define HASH_BITS 6 /* #bits in hash */
1052 #define CRC32_POLY 0xEDB88320
1053
1054 static void set_multicast_list(struct net_device *dev)
1055 {
1056 struct fec_enet_private *fep = netdev_priv(dev);
1057 struct netdev_hw_addr *ha;
1058 unsigned int i, bit, data, crc, tmp;
1059 unsigned char hash;
1060
1061 if (dev->flags & IFF_PROMISC) {
1062 tmp = readl(fep->hwp + FEC_R_CNTRL);
1063 tmp |= 0x8;
1064 writel(tmp, fep->hwp + FEC_R_CNTRL);
1065 return;
1066 }
1067
1068 tmp = readl(fep->hwp + FEC_R_CNTRL);
1069 tmp &= ~0x8;
1070 writel(tmp, fep->hwp + FEC_R_CNTRL);
1071
1072 if (dev->flags & IFF_ALLMULTI) {
1073 /* Catch all multicast addresses, so set the
1074 * filter to all 1's
1075 */
1076 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1077 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1078
1079 return;
1080 }
1081
1082 /* Clear filter and add the addresses in hash register
1083 */
1084 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1085 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1086
1087 netdev_for_each_mc_addr(ha, dev) {
1088 /* Only support group multicast for now */
1089 if (!(ha->addr[0] & 1))
1090 continue;
1091
1092 /* calculate crc32 value of mac address */
1093 crc = 0xffffffff;
1094
1095 for (i = 0; i < dev->addr_len; i++) {
1096 data = ha->addr[i];
1097 for (bit = 0; bit < 8; bit++, data >>= 1) {
1098 crc = (crc >> 1) ^
1099 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1100 }
1101 }
1102
1103 /* only upper 6 bits (HASH_BITS) are used
1104 * which point to specific bit in he hash registers
1105 */
1106 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1107
1108 if (hash > 31) {
1109 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1110 tmp |= 1 << (hash - 32);
1111 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1112 } else {
1113 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1114 tmp |= 1 << hash;
1115 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1116 }
1117 }
1118 }
1119
1120 /* Set a MAC change in hardware. */
1121 static int
1122 fec_set_mac_address(struct net_device *dev, void *p)
1123 {
1124 struct fec_enet_private *fep = netdev_priv(dev);
1125 struct sockaddr *addr = p;
1126
1127 if (!is_valid_ether_addr(addr->sa_data))
1128 return -EADDRNOTAVAIL;
1129
1130 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1131
1132 writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
1133 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
1134 fep->hwp + FEC_ADDR_LOW);
1135 writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24),
1136 fep->hwp + FEC_ADDR_HIGH);
1137 return 0;
1138 }
1139
1140 static const struct net_device_ops fec_netdev_ops = {
1141 .ndo_open = fec_enet_open,
1142 .ndo_stop = fec_enet_close,
1143 .ndo_start_xmit = fec_enet_start_xmit,
1144 .ndo_set_multicast_list = set_multicast_list,
1145 .ndo_change_mtu = eth_change_mtu,
1146 .ndo_validate_addr = eth_validate_addr,
1147 .ndo_tx_timeout = fec_timeout,
1148 .ndo_set_mac_address = fec_set_mac_address,
1149 .ndo_do_ioctl = fec_enet_ioctl,
1150 };
1151
1152 /*
1153 * XXX: We need to clean up on failure exits here.
1154 *
1155 */
1156 static int fec_enet_init(struct net_device *dev)
1157 {
1158 struct fec_enet_private *fep = netdev_priv(dev);
1159 struct bufdesc *cbd_base;
1160 struct bufdesc *bdp;
1161 int i;
1162
1163 /* Allocate memory for buffer descriptors. */
1164 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1165 GFP_KERNEL);
1166 if (!cbd_base) {
1167 printk("FEC: allocate descriptor memory failed?\n");
1168 return -ENOMEM;
1169 }
1170
1171 spin_lock_init(&fep->hw_lock);
1172
1173 fep->hwp = (void __iomem *)dev->base_addr;
1174 fep->netdev = dev;
1175
1176 /* Get the Ethernet address */
1177 fec_get_mac(dev);
1178
1179 /* Set receive and transmit descriptor base. */
1180 fep->rx_bd_base = cbd_base;
1181 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1182
1183 /* The FEC Ethernet specific entries in the device structure */
1184 dev->watchdog_timeo = TX_TIMEOUT;
1185 dev->netdev_ops = &fec_netdev_ops;
1186 dev->ethtool_ops = &fec_enet_ethtool_ops;
1187
1188 /* Initialize the receive buffer descriptors. */
1189 bdp = fep->rx_bd_base;
1190 for (i = 0; i < RX_RING_SIZE; i++) {
1191
1192 /* Initialize the BD for every fragment in the page. */
1193 bdp->cbd_sc = 0;
1194 bdp++;
1195 }
1196
1197 /* Set the last buffer to wrap */
1198 bdp--;
1199 bdp->cbd_sc |= BD_SC_WRAP;
1200
1201 /* ...and the same for transmit */
1202 bdp = fep->tx_bd_base;
1203 for (i = 0; i < TX_RING_SIZE; i++) {
1204
1205 /* Initialize the BD for every fragment in the page. */
1206 bdp->cbd_sc = 0;
1207 bdp->cbd_bufaddr = 0;
1208 bdp++;
1209 }
1210
1211 /* Set the last buffer to wrap */
1212 bdp--;
1213 bdp->cbd_sc |= BD_SC_WRAP;
1214
1215 fec_restart(dev, 0);
1216
1217 return 0;
1218 }
1219
1220 /* This function is called to start or restart the FEC during a link
1221 * change. This only happens when switching between half and full
1222 * duplex.
1223 */
1224 static void
1225 fec_restart(struct net_device *dev, int duplex)
1226 {
1227 struct fec_enet_private *fep = netdev_priv(dev);
1228 const struct platform_device_id *id_entry =
1229 platform_get_device_id(fep->pdev);
1230 int i;
1231 u32 val, temp_mac[2];
1232
1233 /* Whack a reset. We should wait for this. */
1234 writel(1, fep->hwp + FEC_ECNTRL);
1235 udelay(10);
1236
1237 /*
1238 * enet-mac reset will reset mac address registers too,
1239 * so need to reconfigure it.
1240 */
1241 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1242 memcpy(&temp_mac, dev->dev_addr, ETH_ALEN);
1243 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
1244 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
1245 }
1246
1247 /* Clear any outstanding interrupt. */
1248 writel(0xffc00000, fep->hwp + FEC_IEVENT);
1249
1250 /* Reset all multicast. */
1251 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1252 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1253 #ifndef CONFIG_M5272
1254 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1255 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1256 #endif
1257
1258 /* Set maximum receive buffer size. */
1259 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
1260
1261 /* Set receive and transmit descriptor base. */
1262 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
1263 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
1264 fep->hwp + FEC_X_DES_START);
1265
1266 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1267 fep->cur_rx = fep->rx_bd_base;
1268
1269 /* Reset SKB transmit buffers. */
1270 fep->skb_cur = fep->skb_dirty = 0;
1271 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
1272 if (fep->tx_skbuff[i]) {
1273 dev_kfree_skb_any(fep->tx_skbuff[i]);
1274 fep->tx_skbuff[i] = NULL;
1275 }
1276 }
1277
1278 /* Enable MII mode */
1279 if (duplex) {
1280 /* MII enable / FD enable */
1281 writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
1282 writel(0x04, fep->hwp + FEC_X_CNTRL);
1283 } else {
1284 /* MII enable / No Rcv on Xmit */
1285 writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
1286 writel(0x0, fep->hwp + FEC_X_CNTRL);
1287 }
1288 fep->full_duplex = duplex;
1289
1290 /* Set MII speed */
1291 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1292
1293 /*
1294 * The phy interface and speed need to get configured
1295 * differently on enet-mac.
1296 */
1297 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1298 val = readl(fep->hwp + FEC_R_CNTRL);
1299
1300 /* MII or RMII */
1301 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1302 val |= (1 << 8);
1303 else
1304 val &= ~(1 << 8);
1305
1306 /* 10M or 100M */
1307 if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
1308 val &= ~(1 << 9);
1309 else
1310 val |= (1 << 9);
1311
1312 writel(val, fep->hwp + FEC_R_CNTRL);
1313 } else {
1314 #ifdef FEC_MIIGSK_ENR
1315 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
1316 /* disable the gasket and wait */
1317 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1318 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1319 udelay(1);
1320
1321 /*
1322 * configure the gasket:
1323 * RMII, 50 MHz, no loopback, no echo
1324 */
1325 writel(1, fep->hwp + FEC_MIIGSK_CFGR);
1326
1327 /* re-enable the gasket */
1328 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1329 }
1330 #endif
1331 }
1332
1333 /* And last, enable the transmit and receive processing */
1334 writel(2, fep->hwp + FEC_ECNTRL);
1335 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1336
1337 /* Enable interrupts we wish to service */
1338 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1339 }
1340
1341 static void
1342 fec_stop(struct net_device *dev)
1343 {
1344 struct fec_enet_private *fep = netdev_priv(dev);
1345
1346 /* We cannot expect a graceful transmit stop without link !!! */
1347 if (fep->link) {
1348 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1349 udelay(10);
1350 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1351 printk("fec_stop : Graceful transmit stop did not complete !\n");
1352 }
1353
1354 /* Whack a reset. We should wait for this. */
1355 writel(1, fep->hwp + FEC_ECNTRL);
1356 udelay(10);
1357 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1358 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1359 }
1360
1361 static int __devinit
1362 fec_probe(struct platform_device *pdev)
1363 {
1364 struct fec_enet_private *fep;
1365 struct fec_platform_data *pdata;
1366 struct net_device *ndev;
1367 int i, irq, ret = 0;
1368 struct resource *r;
1369
1370 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1371 if (!r)
1372 return -ENXIO;
1373
1374 r = request_mem_region(r->start, resource_size(r), pdev->name);
1375 if (!r)
1376 return -EBUSY;
1377
1378 /* Init network device */
1379 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1380 if (!ndev)
1381 return -ENOMEM;
1382
1383 SET_NETDEV_DEV(ndev, &pdev->dev);
1384
1385 /* setup board info structure */
1386 fep = netdev_priv(ndev);
1387 memset(fep, 0, sizeof(*fep));
1388
1389 ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r));
1390 fep->pdev = pdev;
1391
1392 if (!ndev->base_addr) {
1393 ret = -ENOMEM;
1394 goto failed_ioremap;
1395 }
1396
1397 platform_set_drvdata(pdev, ndev);
1398
1399 pdata = pdev->dev.platform_data;
1400 if (pdata)
1401 fep->phy_interface = pdata->phy;
1402
1403 /* This device has up to three irqs on some platforms */
1404 for (i = 0; i < 3; i++) {
1405 irq = platform_get_irq(pdev, i);
1406 if (i && irq < 0)
1407 break;
1408 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1409 if (ret) {
1410 while (i >= 0) {
1411 irq = platform_get_irq(pdev, i);
1412 free_irq(irq, ndev);
1413 i--;
1414 }
1415 goto failed_irq;
1416 }
1417 }
1418
1419 fep->clk = clk_get(&pdev->dev, "fec_clk");
1420 if (IS_ERR(fep->clk)) {
1421 ret = PTR_ERR(fep->clk);
1422 goto failed_clk;
1423 }
1424 clk_enable(fep->clk);
1425
1426 ret = fec_enet_init(ndev);
1427 if (ret)
1428 goto failed_init;
1429
1430 ret = fec_enet_mii_init(pdev);
1431 if (ret)
1432 goto failed_mii_init;
1433
1434 /* Carrier starts down, phylib will bring it up */
1435 netif_carrier_off(ndev);
1436
1437 ret = register_netdev(ndev);
1438 if (ret)
1439 goto failed_register;
1440
1441 return 0;
1442
1443 failed_register:
1444 fec_enet_mii_remove(fep);
1445 failed_mii_init:
1446 failed_init:
1447 clk_disable(fep->clk);
1448 clk_put(fep->clk);
1449 failed_clk:
1450 for (i = 0; i < 3; i++) {
1451 irq = platform_get_irq(pdev, i);
1452 if (irq > 0)
1453 free_irq(irq, ndev);
1454 }
1455 failed_irq:
1456 iounmap((void __iomem *)ndev->base_addr);
1457 failed_ioremap:
1458 free_netdev(ndev);
1459
1460 return ret;
1461 }
1462
1463 static int __devexit
1464 fec_drv_remove(struct platform_device *pdev)
1465 {
1466 struct net_device *ndev = platform_get_drvdata(pdev);
1467 struct fec_enet_private *fep = netdev_priv(ndev);
1468
1469 platform_set_drvdata(pdev, NULL);
1470
1471 fec_stop(ndev);
1472 fec_enet_mii_remove(fep);
1473 clk_disable(fep->clk);
1474 clk_put(fep->clk);
1475 iounmap((void __iomem *)ndev->base_addr);
1476 unregister_netdev(ndev);
1477 free_netdev(ndev);
1478 return 0;
1479 }
1480
1481 #ifdef CONFIG_PM
1482 static int
1483 fec_suspend(struct device *dev)
1484 {
1485 struct net_device *ndev = dev_get_drvdata(dev);
1486 struct fec_enet_private *fep;
1487
1488 if (ndev) {
1489 fep = netdev_priv(ndev);
1490 if (netif_running(ndev)) {
1491 fec_stop(ndev);
1492 netif_device_detach(ndev);
1493 }
1494 clk_disable(fep->clk);
1495 }
1496 return 0;
1497 }
1498
1499 static int
1500 fec_resume(struct device *dev)
1501 {
1502 struct net_device *ndev = dev_get_drvdata(dev);
1503 struct fec_enet_private *fep;
1504
1505 if (ndev) {
1506 fep = netdev_priv(ndev);
1507 clk_enable(fep->clk);
1508 if (netif_running(ndev)) {
1509 fec_restart(ndev, fep->full_duplex);
1510 netif_device_attach(ndev);
1511 }
1512 }
1513 return 0;
1514 }
1515
1516 static const struct dev_pm_ops fec_pm_ops = {
1517 .suspend = fec_suspend,
1518 .resume = fec_resume,
1519 .freeze = fec_suspend,
1520 .thaw = fec_resume,
1521 .poweroff = fec_suspend,
1522 .restore = fec_resume,
1523 };
1524 #endif
1525
1526 static struct platform_driver fec_driver = {
1527 .driver = {
1528 .name = DRIVER_NAME,
1529 .owner = THIS_MODULE,
1530 #ifdef CONFIG_PM
1531 .pm = &fec_pm_ops,
1532 #endif
1533 },
1534 .id_table = fec_devtype,
1535 .probe = fec_probe,
1536 .remove = __devexit_p(fec_drv_remove),
1537 };
1538
1539 static int __init
1540 fec_enet_module_init(void)
1541 {
1542 printk(KERN_INFO "FEC Ethernet Driver\n");
1543
1544 return platform_driver_register(&fec_driver);
1545 }
1546
1547 static void __exit
1548 fec_enet_cleanup(void)
1549 {
1550 platform_driver_unregister(&fec_driver);
1551 }
1552
1553 module_exit(fec_enet_cleanup);
1554 module_init(fec_enet_module_init);
1555
1556 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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