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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[deliverable/linux.git] / drivers / net / fec.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/workqueue.h>
38 #include <linux/bitops.h>
39 #include <linux/io.h>
40 #include <linux/irq.h>
41 #include <linux/clk.h>
42 #include <linux/platform_device.h>
43 #include <linux/phy.h>
44 #include <linux/fec.h>
45
46 #include <asm/cacheflush.h>
47
48 #ifndef CONFIG_ARCH_MXC
49 #include <asm/coldfire.h>
50 #include <asm/mcfsim.h>
51 #endif
52
53 #include "fec.h"
54
55 #ifdef CONFIG_ARCH_MXC
56 #include <mach/hardware.h>
57 #define FEC_ALIGNMENT 0xf
58 #else
59 #define FEC_ALIGNMENT 0x3
60 #endif
61
62 /*
63 * Define the fixed address of the FEC hardware.
64 */
65 #if defined(CONFIG_M5272)
66
67 static unsigned char fec_mac_default[] = {
68 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
69 };
70
71 /*
72 * Some hardware gets it MAC address out of local flash memory.
73 * if this is non-zero then assume it is the address to get MAC from.
74 */
75 #if defined(CONFIG_NETtel)
76 #define FEC_FLASHMAC 0xf0006006
77 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
78 #define FEC_FLASHMAC 0xf0006000
79 #elif defined(CONFIG_CANCam)
80 #define FEC_FLASHMAC 0xf0020000
81 #elif defined (CONFIG_M5272C3)
82 #define FEC_FLASHMAC (0xffe04000 + 4)
83 #elif defined(CONFIG_MOD5272)
84 #define FEC_FLASHMAC 0xffc0406b
85 #else
86 #define FEC_FLASHMAC 0
87 #endif
88 #endif /* CONFIG_M5272 */
89
90 /* The number of Tx and Rx buffers. These are allocated from the page
91 * pool. The code may assume these are power of two, so it it best
92 * to keep them that size.
93 * We don't need to allocate pages for the transmitter. We just use
94 * the skbuffer directly.
95 */
96 #define FEC_ENET_RX_PAGES 8
97 #define FEC_ENET_RX_FRSIZE 2048
98 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
99 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
100 #define FEC_ENET_TX_FRSIZE 2048
101 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
102 #define TX_RING_SIZE 16 /* Must be power of two */
103 #define TX_RING_MOD_MASK 15 /* for this to work */
104
105 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
106 #error "FEC: descriptor ring size constants too large"
107 #endif
108
109 /* Interrupt events/masks. */
110 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
111 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
112 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
113 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
114 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
115 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
116 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
117 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
118 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
119 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
120
121 /* The FEC stores dest/src/type, data, and checksum for receive packets.
122 */
123 #define PKT_MAXBUF_SIZE 1518
124 #define PKT_MINBUF_SIZE 64
125 #define PKT_MAXBLR_SIZE 1520
126
127
128 /*
129 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
130 * size bits. Other FEC hardware does not, so we need to take that into
131 * account when setting it.
132 */
133 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
134 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
135 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
136 #else
137 #define OPT_FRAME_SIZE 0
138 #endif
139
140 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
141 * tx_bd_base always point to the base of the buffer descriptors. The
142 * cur_rx and cur_tx point to the currently available buffer.
143 * The dirty_tx tracks the current buffer that is being sent by the
144 * controller. The cur_tx and dirty_tx are equal under both completely
145 * empty and completely full conditions. The empty/ready indicator in
146 * the buffer descriptor determines the actual condition.
147 */
148 struct fec_enet_private {
149 /* Hardware registers of the FEC device */
150 void __iomem *hwp;
151
152 struct net_device *netdev;
153
154 struct clk *clk;
155
156 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
157 unsigned char *tx_bounce[TX_RING_SIZE];
158 struct sk_buff* tx_skbuff[TX_RING_SIZE];
159 struct sk_buff* rx_skbuff[RX_RING_SIZE];
160 ushort skb_cur;
161 ushort skb_dirty;
162
163 /* CPM dual port RAM relative addresses */
164 dma_addr_t bd_dma;
165 /* Address of Rx and Tx buffers */
166 struct bufdesc *rx_bd_base;
167 struct bufdesc *tx_bd_base;
168 /* The next free ring entry */
169 struct bufdesc *cur_rx, *cur_tx;
170 /* The ring entries to be free()ed */
171 struct bufdesc *dirty_tx;
172
173 uint tx_full;
174 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
175 spinlock_t hw_lock;
176
177 struct platform_device *pdev;
178
179 int opened;
180
181 /* Phylib and MDIO interface */
182 struct mii_bus *mii_bus;
183 struct phy_device *phy_dev;
184 int mii_timeout;
185 uint phy_speed;
186 phy_interface_t phy_interface;
187 int index;
188 int link;
189 int full_duplex;
190 struct completion mdio_done;
191 };
192
193 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
194 static void fec_enet_tx(struct net_device *dev);
195 static void fec_enet_rx(struct net_device *dev);
196 static int fec_enet_close(struct net_device *dev);
197 static void fec_restart(struct net_device *dev, int duplex);
198 static void fec_stop(struct net_device *dev);
199
200 /* FEC MII MMFR bits definition */
201 #define FEC_MMFR_ST (1 << 30)
202 #define FEC_MMFR_OP_READ (2 << 28)
203 #define FEC_MMFR_OP_WRITE (1 << 28)
204 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
205 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
206 #define FEC_MMFR_TA (2 << 16)
207 #define FEC_MMFR_DATA(v) (v & 0xffff)
208
209 #define FEC_MII_TIMEOUT 1000 /* us */
210
211 /* Transmitter timeout */
212 #define TX_TIMEOUT (2 * HZ)
213
214 static netdev_tx_t
215 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
216 {
217 struct fec_enet_private *fep = netdev_priv(dev);
218 struct bufdesc *bdp;
219 void *bufaddr;
220 unsigned short status;
221 unsigned long flags;
222
223 if (!fep->link) {
224 /* Link is down or autonegotiation is in progress. */
225 return NETDEV_TX_BUSY;
226 }
227
228 spin_lock_irqsave(&fep->hw_lock, flags);
229 /* Fill in a Tx ring entry */
230 bdp = fep->cur_tx;
231
232 status = bdp->cbd_sc;
233
234 if (status & BD_ENET_TX_READY) {
235 /* Ooops. All transmit buffers are full. Bail out.
236 * This should not happen, since dev->tbusy should be set.
237 */
238 printk("%s: tx queue full!.\n", dev->name);
239 spin_unlock_irqrestore(&fep->hw_lock, flags);
240 return NETDEV_TX_BUSY;
241 }
242
243 /* Clear all of the status flags */
244 status &= ~BD_ENET_TX_STATS;
245
246 /* Set buffer length and buffer pointer */
247 bufaddr = skb->data;
248 bdp->cbd_datlen = skb->len;
249
250 /*
251 * On some FEC implementations data must be aligned on
252 * 4-byte boundaries. Use bounce buffers to copy data
253 * and get it aligned. Ugh.
254 */
255 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
256 unsigned int index;
257 index = bdp - fep->tx_bd_base;
258 memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len);
259 bufaddr = fep->tx_bounce[index];
260 }
261
262 /* Save skb pointer */
263 fep->tx_skbuff[fep->skb_cur] = skb;
264
265 dev->stats.tx_bytes += skb->len;
266 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
267
268 /* Push the data cache so the CPM does not get stale memory
269 * data.
270 */
271 bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr,
272 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
273
274 /* Send it on its way. Tell FEC it's ready, interrupt when done,
275 * it's the last BD of the frame, and to put the CRC on the end.
276 */
277 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
278 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
279 bdp->cbd_sc = status;
280
281 /* Trigger transmission start */
282 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
283
284 /* If this was the last BD in the ring, start at the beginning again. */
285 if (status & BD_ENET_TX_WRAP)
286 bdp = fep->tx_bd_base;
287 else
288 bdp++;
289
290 if (bdp == fep->dirty_tx) {
291 fep->tx_full = 1;
292 netif_stop_queue(dev);
293 }
294
295 fep->cur_tx = bdp;
296
297 spin_unlock_irqrestore(&fep->hw_lock, flags);
298
299 return NETDEV_TX_OK;
300 }
301
302 static void
303 fec_timeout(struct net_device *dev)
304 {
305 struct fec_enet_private *fep = netdev_priv(dev);
306
307 dev->stats.tx_errors++;
308
309 fec_restart(dev, fep->full_duplex);
310 netif_wake_queue(dev);
311 }
312
313 static irqreturn_t
314 fec_enet_interrupt(int irq, void * dev_id)
315 {
316 struct net_device *dev = dev_id;
317 struct fec_enet_private *fep = netdev_priv(dev);
318 uint int_events;
319 irqreturn_t ret = IRQ_NONE;
320
321 do {
322 int_events = readl(fep->hwp + FEC_IEVENT);
323 writel(int_events, fep->hwp + FEC_IEVENT);
324
325 if (int_events & FEC_ENET_RXF) {
326 ret = IRQ_HANDLED;
327 fec_enet_rx(dev);
328 }
329
330 /* Transmit OK, or non-fatal error. Update the buffer
331 * descriptors. FEC handles all errors, we just discover
332 * them as part of the transmit process.
333 */
334 if (int_events & FEC_ENET_TXF) {
335 ret = IRQ_HANDLED;
336 fec_enet_tx(dev);
337 }
338
339 if (int_events & FEC_ENET_MII) {
340 ret = IRQ_HANDLED;
341 complete(&fep->mdio_done);
342 }
343 } while (int_events);
344
345 return ret;
346 }
347
348
349 static void
350 fec_enet_tx(struct net_device *dev)
351 {
352 struct fec_enet_private *fep;
353 struct bufdesc *bdp;
354 unsigned short status;
355 struct sk_buff *skb;
356
357 fep = netdev_priv(dev);
358 spin_lock(&fep->hw_lock);
359 bdp = fep->dirty_tx;
360
361 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
362 if (bdp == fep->cur_tx && fep->tx_full == 0)
363 break;
364
365 dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
366 bdp->cbd_bufaddr = 0;
367
368 skb = fep->tx_skbuff[fep->skb_dirty];
369 /* Check for errors. */
370 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
371 BD_ENET_TX_RL | BD_ENET_TX_UN |
372 BD_ENET_TX_CSL)) {
373 dev->stats.tx_errors++;
374 if (status & BD_ENET_TX_HB) /* No heartbeat */
375 dev->stats.tx_heartbeat_errors++;
376 if (status & BD_ENET_TX_LC) /* Late collision */
377 dev->stats.tx_window_errors++;
378 if (status & BD_ENET_TX_RL) /* Retrans limit */
379 dev->stats.tx_aborted_errors++;
380 if (status & BD_ENET_TX_UN) /* Underrun */
381 dev->stats.tx_fifo_errors++;
382 if (status & BD_ENET_TX_CSL) /* Carrier lost */
383 dev->stats.tx_carrier_errors++;
384 } else {
385 dev->stats.tx_packets++;
386 }
387
388 if (status & BD_ENET_TX_READY)
389 printk("HEY! Enet xmit interrupt and TX_READY.\n");
390
391 /* Deferred means some collisions occurred during transmit,
392 * but we eventually sent the packet OK.
393 */
394 if (status & BD_ENET_TX_DEF)
395 dev->stats.collisions++;
396
397 /* Free the sk buffer associated with this last transmit */
398 dev_kfree_skb_any(skb);
399 fep->tx_skbuff[fep->skb_dirty] = NULL;
400 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
401
402 /* Update pointer to next buffer descriptor to be transmitted */
403 if (status & BD_ENET_TX_WRAP)
404 bdp = fep->tx_bd_base;
405 else
406 bdp++;
407
408 /* Since we have freed up a buffer, the ring is no longer full
409 */
410 if (fep->tx_full) {
411 fep->tx_full = 0;
412 if (netif_queue_stopped(dev))
413 netif_wake_queue(dev);
414 }
415 }
416 fep->dirty_tx = bdp;
417 spin_unlock(&fep->hw_lock);
418 }
419
420
421 /* During a receive, the cur_rx points to the current incoming buffer.
422 * When we update through the ring, if the next incoming buffer has
423 * not been given to the system, we just set the empty indicator,
424 * effectively tossing the packet.
425 */
426 static void
427 fec_enet_rx(struct net_device *dev)
428 {
429 struct fec_enet_private *fep = netdev_priv(dev);
430 struct bufdesc *bdp;
431 unsigned short status;
432 struct sk_buff *skb;
433 ushort pkt_len;
434 __u8 *data;
435
436 #ifdef CONFIG_M532x
437 flush_cache_all();
438 #endif
439
440 spin_lock(&fep->hw_lock);
441
442 /* First, grab all of the stats for the incoming packet.
443 * These get messed up if we get called due to a busy condition.
444 */
445 bdp = fep->cur_rx;
446
447 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
448
449 /* Since we have allocated space to hold a complete frame,
450 * the last indicator should be set.
451 */
452 if ((status & BD_ENET_RX_LAST) == 0)
453 printk("FEC ENET: rcv is not +last\n");
454
455 if (!fep->opened)
456 goto rx_processing_done;
457
458 /* Check for errors. */
459 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
460 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
461 dev->stats.rx_errors++;
462 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
463 /* Frame too long or too short. */
464 dev->stats.rx_length_errors++;
465 }
466 if (status & BD_ENET_RX_NO) /* Frame alignment */
467 dev->stats.rx_frame_errors++;
468 if (status & BD_ENET_RX_CR) /* CRC Error */
469 dev->stats.rx_crc_errors++;
470 if (status & BD_ENET_RX_OV) /* FIFO overrun */
471 dev->stats.rx_fifo_errors++;
472 }
473
474 /* Report late collisions as a frame error.
475 * On this error, the BD is closed, but we don't know what we
476 * have in the buffer. So, just drop this frame on the floor.
477 */
478 if (status & BD_ENET_RX_CL) {
479 dev->stats.rx_errors++;
480 dev->stats.rx_frame_errors++;
481 goto rx_processing_done;
482 }
483
484 /* Process the incoming frame. */
485 dev->stats.rx_packets++;
486 pkt_len = bdp->cbd_datlen;
487 dev->stats.rx_bytes += pkt_len;
488 data = (__u8*)__va(bdp->cbd_bufaddr);
489
490 dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
491 DMA_FROM_DEVICE);
492
493 /* This does 16 byte alignment, exactly what we need.
494 * The packet length includes FCS, but we don't want to
495 * include that when passing upstream as it messes up
496 * bridging applications.
497 */
498 skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
499
500 if (unlikely(!skb)) {
501 printk("%s: Memory squeeze, dropping packet.\n",
502 dev->name);
503 dev->stats.rx_dropped++;
504 } else {
505 skb_reserve(skb, NET_IP_ALIGN);
506 skb_put(skb, pkt_len - 4); /* Make room */
507 skb_copy_to_linear_data(skb, data, pkt_len - 4);
508 skb->protocol = eth_type_trans(skb, dev);
509 netif_rx(skb);
510 }
511
512 bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen,
513 DMA_FROM_DEVICE);
514 rx_processing_done:
515 /* Clear the status flags for this buffer */
516 status &= ~BD_ENET_RX_STATS;
517
518 /* Mark the buffer empty */
519 status |= BD_ENET_RX_EMPTY;
520 bdp->cbd_sc = status;
521
522 /* Update BD pointer to next entry */
523 if (status & BD_ENET_RX_WRAP)
524 bdp = fep->rx_bd_base;
525 else
526 bdp++;
527 /* Doing this here will keep the FEC running while we process
528 * incoming frames. On a heavily loaded network, we should be
529 * able to keep up at the expense of system resources.
530 */
531 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
532 }
533 fep->cur_rx = bdp;
534
535 spin_unlock(&fep->hw_lock);
536 }
537
538 /* ------------------------------------------------------------------------- */
539 #ifdef CONFIG_M5272
540 static void __inline__ fec_get_mac(struct net_device *dev)
541 {
542 struct fec_enet_private *fep = netdev_priv(dev);
543 unsigned char *iap, tmpaddr[ETH_ALEN];
544
545 if (FEC_FLASHMAC) {
546 /*
547 * Get MAC address from FLASH.
548 * If it is all 1's or 0's, use the default.
549 */
550 iap = (unsigned char *)FEC_FLASHMAC;
551 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
552 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
553 iap = fec_mac_default;
554 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
555 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
556 iap = fec_mac_default;
557 } else {
558 *((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW);
559 *((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
560 iap = &tmpaddr[0];
561 }
562
563 memcpy(dev->dev_addr, iap, ETH_ALEN);
564
565 /* Adjust MAC if using default MAC address */
566 if (iap == fec_mac_default)
567 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
568 }
569 #endif
570
571 /* ------------------------------------------------------------------------- */
572
573 /*
574 * Phy section
575 */
576 static void fec_enet_adjust_link(struct net_device *dev)
577 {
578 struct fec_enet_private *fep = netdev_priv(dev);
579 struct phy_device *phy_dev = fep->phy_dev;
580 unsigned long flags;
581
582 int status_change = 0;
583
584 spin_lock_irqsave(&fep->hw_lock, flags);
585
586 /* Prevent a state halted on mii error */
587 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
588 phy_dev->state = PHY_RESUMING;
589 goto spin_unlock;
590 }
591
592 /* Duplex link change */
593 if (phy_dev->link) {
594 if (fep->full_duplex != phy_dev->duplex) {
595 fec_restart(dev, phy_dev->duplex);
596 status_change = 1;
597 }
598 }
599
600 /* Link on or off change */
601 if (phy_dev->link != fep->link) {
602 fep->link = phy_dev->link;
603 if (phy_dev->link)
604 fec_restart(dev, phy_dev->duplex);
605 else
606 fec_stop(dev);
607 status_change = 1;
608 }
609
610 spin_unlock:
611 spin_unlock_irqrestore(&fep->hw_lock, flags);
612
613 if (status_change)
614 phy_print_status(phy_dev);
615 }
616
617 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
618 {
619 struct fec_enet_private *fep = bus->priv;
620 unsigned long time_left;
621
622 fep->mii_timeout = 0;
623 init_completion(&fep->mdio_done);
624
625 /* start a read op */
626 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
627 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
628 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
629
630 /* wait for end of transfer */
631 time_left = wait_for_completion_timeout(&fep->mdio_done,
632 usecs_to_jiffies(FEC_MII_TIMEOUT));
633 if (time_left == 0) {
634 fep->mii_timeout = 1;
635 printk(KERN_ERR "FEC: MDIO read timeout\n");
636 return -ETIMEDOUT;
637 }
638
639 /* return value */
640 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
641 }
642
643 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
644 u16 value)
645 {
646 struct fec_enet_private *fep = bus->priv;
647 unsigned long time_left;
648
649 fep->mii_timeout = 0;
650 init_completion(&fep->mdio_done);
651
652 /* start a read op */
653 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
654 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
655 FEC_MMFR_TA | FEC_MMFR_DATA(value),
656 fep->hwp + FEC_MII_DATA);
657
658 /* wait for end of transfer */
659 time_left = wait_for_completion_timeout(&fep->mdio_done,
660 usecs_to_jiffies(FEC_MII_TIMEOUT));
661 if (time_left == 0) {
662 fep->mii_timeout = 1;
663 printk(KERN_ERR "FEC: MDIO write timeout\n");
664 return -ETIMEDOUT;
665 }
666
667 return 0;
668 }
669
670 static int fec_enet_mdio_reset(struct mii_bus *bus)
671 {
672 return 0;
673 }
674
675 static int fec_enet_mii_probe(struct net_device *dev)
676 {
677 struct fec_enet_private *fep = netdev_priv(dev);
678 struct phy_device *phy_dev = NULL;
679 int ret;
680
681 fep->phy_dev = NULL;
682
683 /* find the first phy */
684 phy_dev = phy_find_first(fep->mii_bus);
685 if (!phy_dev) {
686 printk(KERN_ERR "%s: no PHY found\n", dev->name);
687 return -ENODEV;
688 }
689
690 /* attach the mac to the phy */
691 ret = phy_connect_direct(dev, phy_dev,
692 &fec_enet_adjust_link, 0,
693 PHY_INTERFACE_MODE_MII);
694 if (ret) {
695 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
696 return ret;
697 }
698
699 /* mask with MAC supported features */
700 phy_dev->supported &= PHY_BASIC_FEATURES;
701 phy_dev->advertising = phy_dev->supported;
702
703 fep->phy_dev = phy_dev;
704 fep->link = 0;
705 fep->full_duplex = 0;
706
707 printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] "
708 "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name,
709 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
710 fep->phy_dev->irq);
711
712 return 0;
713 }
714
715 static int fec_enet_mii_init(struct platform_device *pdev)
716 {
717 struct net_device *dev = platform_get_drvdata(pdev);
718 struct fec_enet_private *fep = netdev_priv(dev);
719 int err = -ENXIO, i;
720
721 fep->mii_timeout = 0;
722
723 /*
724 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
725 */
726 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
727 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
728
729 fep->mii_bus = mdiobus_alloc();
730 if (fep->mii_bus == NULL) {
731 err = -ENOMEM;
732 goto err_out;
733 }
734
735 fep->mii_bus->name = "fec_enet_mii_bus";
736 fep->mii_bus->read = fec_enet_mdio_read;
737 fep->mii_bus->write = fec_enet_mdio_write;
738 fep->mii_bus->reset = fec_enet_mdio_reset;
739 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
740 fep->mii_bus->priv = fep;
741 fep->mii_bus->parent = &pdev->dev;
742
743 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
744 if (!fep->mii_bus->irq) {
745 err = -ENOMEM;
746 goto err_out_free_mdiobus;
747 }
748
749 for (i = 0; i < PHY_MAX_ADDR; i++)
750 fep->mii_bus->irq[i] = PHY_POLL;
751
752 platform_set_drvdata(dev, fep->mii_bus);
753
754 if (mdiobus_register(fep->mii_bus))
755 goto err_out_free_mdio_irq;
756
757 return 0;
758
759 err_out_free_mdio_irq:
760 kfree(fep->mii_bus->irq);
761 err_out_free_mdiobus:
762 mdiobus_free(fep->mii_bus);
763 err_out:
764 return err;
765 }
766
767 static void fec_enet_mii_remove(struct fec_enet_private *fep)
768 {
769 if (fep->phy_dev)
770 phy_disconnect(fep->phy_dev);
771 mdiobus_unregister(fep->mii_bus);
772 kfree(fep->mii_bus->irq);
773 mdiobus_free(fep->mii_bus);
774 }
775
776 static int fec_enet_get_settings(struct net_device *dev,
777 struct ethtool_cmd *cmd)
778 {
779 struct fec_enet_private *fep = netdev_priv(dev);
780 struct phy_device *phydev = fep->phy_dev;
781
782 if (!phydev)
783 return -ENODEV;
784
785 return phy_ethtool_gset(phydev, cmd);
786 }
787
788 static int fec_enet_set_settings(struct net_device *dev,
789 struct ethtool_cmd *cmd)
790 {
791 struct fec_enet_private *fep = netdev_priv(dev);
792 struct phy_device *phydev = fep->phy_dev;
793
794 if (!phydev)
795 return -ENODEV;
796
797 return phy_ethtool_sset(phydev, cmd);
798 }
799
800 static void fec_enet_get_drvinfo(struct net_device *dev,
801 struct ethtool_drvinfo *info)
802 {
803 struct fec_enet_private *fep = netdev_priv(dev);
804
805 strcpy(info->driver, fep->pdev->dev.driver->name);
806 strcpy(info->version, "Revision: 1.0");
807 strcpy(info->bus_info, dev_name(&dev->dev));
808 }
809
810 static struct ethtool_ops fec_enet_ethtool_ops = {
811 .get_settings = fec_enet_get_settings,
812 .set_settings = fec_enet_set_settings,
813 .get_drvinfo = fec_enet_get_drvinfo,
814 .get_link = ethtool_op_get_link,
815 };
816
817 static int fec_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
818 {
819 struct fec_enet_private *fep = netdev_priv(dev);
820 struct phy_device *phydev = fep->phy_dev;
821
822 if (!netif_running(dev))
823 return -EINVAL;
824
825 if (!phydev)
826 return -ENODEV;
827
828 return phy_mii_ioctl(phydev, rq, cmd);
829 }
830
831 static void fec_enet_free_buffers(struct net_device *dev)
832 {
833 struct fec_enet_private *fep = netdev_priv(dev);
834 int i;
835 struct sk_buff *skb;
836 struct bufdesc *bdp;
837
838 bdp = fep->rx_bd_base;
839 for (i = 0; i < RX_RING_SIZE; i++) {
840 skb = fep->rx_skbuff[i];
841
842 if (bdp->cbd_bufaddr)
843 dma_unmap_single(&dev->dev, bdp->cbd_bufaddr,
844 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
845 if (skb)
846 dev_kfree_skb(skb);
847 bdp++;
848 }
849
850 bdp = fep->tx_bd_base;
851 for (i = 0; i < TX_RING_SIZE; i++)
852 kfree(fep->tx_bounce[i]);
853 }
854
855 static int fec_enet_alloc_buffers(struct net_device *dev)
856 {
857 struct fec_enet_private *fep = netdev_priv(dev);
858 int i;
859 struct sk_buff *skb;
860 struct bufdesc *bdp;
861
862 bdp = fep->rx_bd_base;
863 for (i = 0; i < RX_RING_SIZE; i++) {
864 skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE);
865 if (!skb) {
866 fec_enet_free_buffers(dev);
867 return -ENOMEM;
868 }
869 fep->rx_skbuff[i] = skb;
870
871 bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data,
872 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
873 bdp->cbd_sc = BD_ENET_RX_EMPTY;
874 bdp++;
875 }
876
877 /* Set the last buffer to wrap. */
878 bdp--;
879 bdp->cbd_sc |= BD_SC_WRAP;
880
881 bdp = fep->tx_bd_base;
882 for (i = 0; i < TX_RING_SIZE; i++) {
883 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
884
885 bdp->cbd_sc = 0;
886 bdp->cbd_bufaddr = 0;
887 bdp++;
888 }
889
890 /* Set the last buffer to wrap. */
891 bdp--;
892 bdp->cbd_sc |= BD_SC_WRAP;
893
894 return 0;
895 }
896
897 static int
898 fec_enet_open(struct net_device *dev)
899 {
900 struct fec_enet_private *fep = netdev_priv(dev);
901 int ret;
902
903 /* I should reset the ring buffers here, but I don't yet know
904 * a simple way to do that.
905 */
906
907 ret = fec_enet_alloc_buffers(dev);
908 if (ret)
909 return ret;
910
911 /* Probe and connect to PHY when open the interface */
912 ret = fec_enet_mii_probe(dev);
913 if (ret) {
914 fec_enet_free_buffers(dev);
915 return ret;
916 }
917 phy_start(fep->phy_dev);
918 netif_start_queue(dev);
919 fep->opened = 1;
920 return 0;
921 }
922
923 static int
924 fec_enet_close(struct net_device *dev)
925 {
926 struct fec_enet_private *fep = netdev_priv(dev);
927
928 /* Don't know what to do yet. */
929 fep->opened = 0;
930 netif_stop_queue(dev);
931 fec_stop(dev);
932
933 if (fep->phy_dev)
934 phy_disconnect(fep->phy_dev);
935
936 fec_enet_free_buffers(dev);
937
938 return 0;
939 }
940
941 /* Set or clear the multicast filter for this adaptor.
942 * Skeleton taken from sunlance driver.
943 * The CPM Ethernet implementation allows Multicast as well as individual
944 * MAC address filtering. Some of the drivers check to make sure it is
945 * a group multicast address, and discard those that are not. I guess I
946 * will do the same for now, but just remove the test if you want
947 * individual filtering as well (do the upper net layers want or support
948 * this kind of feature?).
949 */
950
951 #define HASH_BITS 6 /* #bits in hash */
952 #define CRC32_POLY 0xEDB88320
953
954 static void set_multicast_list(struct net_device *dev)
955 {
956 struct fec_enet_private *fep = netdev_priv(dev);
957 struct netdev_hw_addr *ha;
958 unsigned int i, bit, data, crc, tmp;
959 unsigned char hash;
960
961 if (dev->flags & IFF_PROMISC) {
962 tmp = readl(fep->hwp + FEC_R_CNTRL);
963 tmp |= 0x8;
964 writel(tmp, fep->hwp + FEC_R_CNTRL);
965 return;
966 }
967
968 tmp = readl(fep->hwp + FEC_R_CNTRL);
969 tmp &= ~0x8;
970 writel(tmp, fep->hwp + FEC_R_CNTRL);
971
972 if (dev->flags & IFF_ALLMULTI) {
973 /* Catch all multicast addresses, so set the
974 * filter to all 1's
975 */
976 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
977 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
978
979 return;
980 }
981
982 /* Clear filter and add the addresses in hash register
983 */
984 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
985 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
986
987 netdev_for_each_mc_addr(ha, dev) {
988 /* Only support group multicast for now */
989 if (!(ha->addr[0] & 1))
990 continue;
991
992 /* calculate crc32 value of mac address */
993 crc = 0xffffffff;
994
995 for (i = 0; i < dev->addr_len; i++) {
996 data = ha->addr[i];
997 for (bit = 0; bit < 8; bit++, data >>= 1) {
998 crc = (crc >> 1) ^
999 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1000 }
1001 }
1002
1003 /* only upper 6 bits (HASH_BITS) are used
1004 * which point to specific bit in he hash registers
1005 */
1006 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1007
1008 if (hash > 31) {
1009 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1010 tmp |= 1 << (hash - 32);
1011 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1012 } else {
1013 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1014 tmp |= 1 << hash;
1015 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1016 }
1017 }
1018 }
1019
1020 /* Set a MAC change in hardware. */
1021 static int
1022 fec_set_mac_address(struct net_device *dev, void *p)
1023 {
1024 struct fec_enet_private *fep = netdev_priv(dev);
1025 struct sockaddr *addr = p;
1026
1027 if (!is_valid_ether_addr(addr->sa_data))
1028 return -EADDRNOTAVAIL;
1029
1030 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1031
1032 writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
1033 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24),
1034 fep->hwp + FEC_ADDR_LOW);
1035 writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24),
1036 fep->hwp + FEC_ADDR_HIGH);
1037 return 0;
1038 }
1039
1040 static const struct net_device_ops fec_netdev_ops = {
1041 .ndo_open = fec_enet_open,
1042 .ndo_stop = fec_enet_close,
1043 .ndo_start_xmit = fec_enet_start_xmit,
1044 .ndo_set_multicast_list = set_multicast_list,
1045 .ndo_change_mtu = eth_change_mtu,
1046 .ndo_validate_addr = eth_validate_addr,
1047 .ndo_tx_timeout = fec_timeout,
1048 .ndo_set_mac_address = fec_set_mac_address,
1049 .ndo_do_ioctl = fec_enet_ioctl,
1050 };
1051
1052 /*
1053 * XXX: We need to clean up on failure exits here.
1054 *
1055 * index is only used in legacy code
1056 */
1057 static int fec_enet_init(struct net_device *dev, int index)
1058 {
1059 struct fec_enet_private *fep = netdev_priv(dev);
1060 struct bufdesc *cbd_base;
1061 struct bufdesc *bdp;
1062 int i;
1063
1064 /* Allocate memory for buffer descriptors. */
1065 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1066 GFP_KERNEL);
1067 if (!cbd_base) {
1068 printk("FEC: allocate descriptor memory failed?\n");
1069 return -ENOMEM;
1070 }
1071
1072 spin_lock_init(&fep->hw_lock);
1073
1074 fep->index = index;
1075 fep->hwp = (void __iomem *)dev->base_addr;
1076 fep->netdev = dev;
1077
1078 /* Set the Ethernet address */
1079 #ifdef CONFIG_M5272
1080 fec_get_mac(dev);
1081 #else
1082 {
1083 unsigned long l;
1084 l = readl(fep->hwp + FEC_ADDR_LOW);
1085 dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24);
1086 dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16);
1087 dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8);
1088 dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0);
1089 l = readl(fep->hwp + FEC_ADDR_HIGH);
1090 dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24);
1091 dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16);
1092 }
1093 #endif
1094
1095 /* Set receive and transmit descriptor base. */
1096 fep->rx_bd_base = cbd_base;
1097 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1098
1099 /* The FEC Ethernet specific entries in the device structure */
1100 dev->watchdog_timeo = TX_TIMEOUT;
1101 dev->netdev_ops = &fec_netdev_ops;
1102 dev->ethtool_ops = &fec_enet_ethtool_ops;
1103
1104 /* Initialize the receive buffer descriptors. */
1105 bdp = fep->rx_bd_base;
1106 for (i = 0; i < RX_RING_SIZE; i++) {
1107
1108 /* Initialize the BD for every fragment in the page. */
1109 bdp->cbd_sc = 0;
1110 bdp++;
1111 }
1112
1113 /* Set the last buffer to wrap */
1114 bdp--;
1115 bdp->cbd_sc |= BD_SC_WRAP;
1116
1117 /* ...and the same for transmit */
1118 bdp = fep->tx_bd_base;
1119 for (i = 0; i < TX_RING_SIZE; i++) {
1120
1121 /* Initialize the BD for every fragment in the page. */
1122 bdp->cbd_sc = 0;
1123 bdp->cbd_bufaddr = 0;
1124 bdp++;
1125 }
1126
1127 /* Set the last buffer to wrap */
1128 bdp--;
1129 bdp->cbd_sc |= BD_SC_WRAP;
1130
1131 fec_restart(dev, 0);
1132
1133 return 0;
1134 }
1135
1136 /* This function is called to start or restart the FEC during a link
1137 * change. This only happens when switching between half and full
1138 * duplex.
1139 */
1140 static void
1141 fec_restart(struct net_device *dev, int duplex)
1142 {
1143 struct fec_enet_private *fep = netdev_priv(dev);
1144 int i;
1145
1146 /* Whack a reset. We should wait for this. */
1147 writel(1, fep->hwp + FEC_ECNTRL);
1148 udelay(10);
1149
1150 /* Clear any outstanding interrupt. */
1151 writel(0xffc00000, fep->hwp + FEC_IEVENT);
1152
1153 /* Reset all multicast. */
1154 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1155 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1156 #ifndef CONFIG_M5272
1157 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1158 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1159 #endif
1160
1161 /* Set maximum receive buffer size. */
1162 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
1163
1164 /* Set receive and transmit descriptor base. */
1165 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
1166 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
1167 fep->hwp + FEC_X_DES_START);
1168
1169 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
1170 fep->cur_rx = fep->rx_bd_base;
1171
1172 /* Reset SKB transmit buffers. */
1173 fep->skb_cur = fep->skb_dirty = 0;
1174 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
1175 if (fep->tx_skbuff[i]) {
1176 dev_kfree_skb_any(fep->tx_skbuff[i]);
1177 fep->tx_skbuff[i] = NULL;
1178 }
1179 }
1180
1181 /* Enable MII mode */
1182 if (duplex) {
1183 /* MII enable / FD enable */
1184 writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
1185 writel(0x04, fep->hwp + FEC_X_CNTRL);
1186 } else {
1187 /* MII enable / No Rcv on Xmit */
1188 writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
1189 writel(0x0, fep->hwp + FEC_X_CNTRL);
1190 }
1191 fep->full_duplex = duplex;
1192
1193 /* Set MII speed */
1194 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1195
1196 #ifdef FEC_MIIGSK_ENR
1197 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
1198 /* disable the gasket and wait */
1199 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1200 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1201 udelay(1);
1202
1203 /* configure the gasket: RMII, 50 MHz, no loopback, no echo */
1204 writel(1, fep->hwp + FEC_MIIGSK_CFGR);
1205
1206 /* re-enable the gasket */
1207 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1208 }
1209 #endif
1210
1211 /* And last, enable the transmit and receive processing */
1212 writel(2, fep->hwp + FEC_ECNTRL);
1213 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1214
1215 /* Enable interrupts we wish to service */
1216 writel(FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII,
1217 fep->hwp + FEC_IMASK);
1218 }
1219
1220 static void
1221 fec_stop(struct net_device *dev)
1222 {
1223 struct fec_enet_private *fep = netdev_priv(dev);
1224
1225 /* We cannot expect a graceful transmit stop without link !!! */
1226 if (fep->link) {
1227 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1228 udelay(10);
1229 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1230 printk("fec_stop : Graceful transmit stop did not complete !\n");
1231 }
1232
1233 /* Whack a reset. We should wait for this. */
1234 writel(1, fep->hwp + FEC_ECNTRL);
1235 udelay(10);
1236
1237 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1238 }
1239
1240 static int __devinit
1241 fec_probe(struct platform_device *pdev)
1242 {
1243 struct fec_enet_private *fep;
1244 struct fec_platform_data *pdata;
1245 struct net_device *ndev;
1246 int i, irq, ret = 0;
1247 struct resource *r;
1248
1249 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1250 if (!r)
1251 return -ENXIO;
1252
1253 r = request_mem_region(r->start, resource_size(r), pdev->name);
1254 if (!r)
1255 return -EBUSY;
1256
1257 /* Init network device */
1258 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1259 if (!ndev)
1260 return -ENOMEM;
1261
1262 SET_NETDEV_DEV(ndev, &pdev->dev);
1263
1264 /* setup board info structure */
1265 fep = netdev_priv(ndev);
1266 memset(fep, 0, sizeof(*fep));
1267
1268 ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r));
1269 fep->pdev = pdev;
1270
1271 if (!ndev->base_addr) {
1272 ret = -ENOMEM;
1273 goto failed_ioremap;
1274 }
1275
1276 platform_set_drvdata(pdev, ndev);
1277
1278 pdata = pdev->dev.platform_data;
1279 if (pdata)
1280 fep->phy_interface = pdata->phy;
1281
1282 /* This device has up to three irqs on some platforms */
1283 for (i = 0; i < 3; i++) {
1284 irq = platform_get_irq(pdev, i);
1285 if (i && irq < 0)
1286 break;
1287 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1288 if (ret) {
1289 while (i >= 0) {
1290 irq = platform_get_irq(pdev, i);
1291 free_irq(irq, ndev);
1292 i--;
1293 }
1294 goto failed_irq;
1295 }
1296 }
1297
1298 fep->clk = clk_get(&pdev->dev, "fec_clk");
1299 if (IS_ERR(fep->clk)) {
1300 ret = PTR_ERR(fep->clk);
1301 goto failed_clk;
1302 }
1303 clk_enable(fep->clk);
1304
1305 ret = fec_enet_init(ndev, 0);
1306 if (ret)
1307 goto failed_init;
1308
1309 ret = fec_enet_mii_init(pdev);
1310 if (ret)
1311 goto failed_mii_init;
1312
1313 ret = register_netdev(ndev);
1314 if (ret)
1315 goto failed_register;
1316
1317 return 0;
1318
1319 failed_register:
1320 fec_enet_mii_remove(fep);
1321 failed_mii_init:
1322 failed_init:
1323 clk_disable(fep->clk);
1324 clk_put(fep->clk);
1325 failed_clk:
1326 for (i = 0; i < 3; i++) {
1327 irq = platform_get_irq(pdev, i);
1328 if (irq > 0)
1329 free_irq(irq, ndev);
1330 }
1331 failed_irq:
1332 iounmap((void __iomem *)ndev->base_addr);
1333 failed_ioremap:
1334 free_netdev(ndev);
1335
1336 return ret;
1337 }
1338
1339 static int __devexit
1340 fec_drv_remove(struct platform_device *pdev)
1341 {
1342 struct net_device *ndev = platform_get_drvdata(pdev);
1343 struct fec_enet_private *fep = netdev_priv(ndev);
1344
1345 platform_set_drvdata(pdev, NULL);
1346
1347 fec_stop(ndev);
1348 fec_enet_mii_remove(fep);
1349 clk_disable(fep->clk);
1350 clk_put(fep->clk);
1351 iounmap((void __iomem *)ndev->base_addr);
1352 unregister_netdev(ndev);
1353 free_netdev(ndev);
1354 return 0;
1355 }
1356
1357 #ifdef CONFIG_PM
1358 static int
1359 fec_suspend(struct device *dev)
1360 {
1361 struct net_device *ndev = dev_get_drvdata(dev);
1362 struct fec_enet_private *fep;
1363
1364 if (ndev) {
1365 fep = netdev_priv(ndev);
1366 if (netif_running(ndev))
1367 fec_enet_close(ndev);
1368 clk_disable(fep->clk);
1369 }
1370 return 0;
1371 }
1372
1373 static int
1374 fec_resume(struct device *dev)
1375 {
1376 struct net_device *ndev = dev_get_drvdata(dev);
1377 struct fec_enet_private *fep;
1378
1379 if (ndev) {
1380 fep = netdev_priv(ndev);
1381 clk_enable(fep->clk);
1382 if (netif_running(ndev))
1383 fec_enet_open(ndev);
1384 }
1385 return 0;
1386 }
1387
1388 static const struct dev_pm_ops fec_pm_ops = {
1389 .suspend = fec_suspend,
1390 .resume = fec_resume,
1391 .freeze = fec_suspend,
1392 .thaw = fec_resume,
1393 .poweroff = fec_suspend,
1394 .restore = fec_resume,
1395 };
1396 #endif
1397
1398 static struct platform_driver fec_driver = {
1399 .driver = {
1400 .name = "fec",
1401 .owner = THIS_MODULE,
1402 #ifdef CONFIG_PM
1403 .pm = &fec_pm_ops,
1404 #endif
1405 },
1406 .probe = fec_probe,
1407 .remove = __devexit_p(fec_drv_remove),
1408 };
1409
1410 static int __init
1411 fec_enet_module_init(void)
1412 {
1413 printk(KERN_INFO "FEC Ethernet Driver\n");
1414
1415 return platform_driver_register(&fec_driver);
1416 }
1417
1418 static void __exit
1419 fec_enet_cleanup(void)
1420 {
1421 platform_driver_unregister(&fec_driver);
1422 }
1423
1424 module_exit(fec_enet_cleanup);
1425 module_init(fec_enet_module_init);
1426
1427 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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