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[deliverable/linux.git] / drivers / net / fec.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/workqueue.h>
38 #include <linux/bitops.h>
39 #include <linux/io.h>
40 #include <linux/irq.h>
41
42 #include <asm/cacheflush.h>
43 #include <asm/coldfire.h>
44 #include <asm/mcfsim.h>
45
46 #include "fec.h"
47
48 #if defined(CONFIG_FEC2)
49 #define FEC_MAX_PORTS 2
50 #else
51 #define FEC_MAX_PORTS 1
52 #endif
53
54 #if defined(CONFIG_M5272)
55 #define HAVE_mii_link_interrupt
56 #endif
57
58 /*
59 * Define the fixed address of the FEC hardware.
60 */
61 static unsigned int fec_hw[] = {
62 #if defined(CONFIG_M5272)
63 (MCF_MBAR + 0x840),
64 #elif defined(CONFIG_M527x)
65 (MCF_MBAR + 0x1000),
66 (MCF_MBAR + 0x1800),
67 #elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
68 (MCF_MBAR + 0x1000),
69 #elif defined(CONFIG_M520x)
70 (MCF_MBAR+0x30000),
71 #elif defined(CONFIG_M532x)
72 (MCF_MBAR+0xfc030000),
73 #endif
74 };
75
76 static unsigned char fec_mac_default[] = {
77 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
78 };
79
80 /*
81 * Some hardware gets it MAC address out of local flash memory.
82 * if this is non-zero then assume it is the address to get MAC from.
83 */
84 #if defined(CONFIG_NETtel)
85 #define FEC_FLASHMAC 0xf0006006
86 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
87 #define FEC_FLASHMAC 0xf0006000
88 #elif defined(CONFIG_CANCam)
89 #define FEC_FLASHMAC 0xf0020000
90 #elif defined (CONFIG_M5272C3)
91 #define FEC_FLASHMAC (0xffe04000 + 4)
92 #elif defined(CONFIG_MOD5272)
93 #define FEC_FLASHMAC 0xffc0406b
94 #else
95 #define FEC_FLASHMAC 0
96 #endif
97
98 /* Forward declarations of some structures to support different PHYs
99 */
100
101 typedef struct {
102 uint mii_data;
103 void (*funct)(uint mii_reg, struct net_device *dev);
104 } phy_cmd_t;
105
106 typedef struct {
107 uint id;
108 char *name;
109
110 const phy_cmd_t *config;
111 const phy_cmd_t *startup;
112 const phy_cmd_t *ack_int;
113 const phy_cmd_t *shutdown;
114 } phy_info_t;
115
116 /* The number of Tx and Rx buffers. These are allocated from the page
117 * pool. The code may assume these are power of two, so it it best
118 * to keep them that size.
119 * We don't need to allocate pages for the transmitter. We just use
120 * the skbuffer directly.
121 */
122 #define FEC_ENET_RX_PAGES 8
123 #define FEC_ENET_RX_FRSIZE 2048
124 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
125 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
126 #define FEC_ENET_TX_FRSIZE 2048
127 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
128 #define TX_RING_SIZE 16 /* Must be power of two */
129 #define TX_RING_MOD_MASK 15 /* for this to work */
130
131 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
132 #error "FEC: descriptor ring size constants too large"
133 #endif
134
135 /* Interrupt events/masks.
136 */
137 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
138 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
139 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
140 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
141 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
142 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
143 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
144 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
145 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
146 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
147
148 /* The FEC stores dest/src/type, data, and checksum for receive packets.
149 */
150 #define PKT_MAXBUF_SIZE 1518
151 #define PKT_MINBUF_SIZE 64
152 #define PKT_MAXBLR_SIZE 1520
153
154
155 /*
156 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
157 * size bits. Other FEC hardware does not, so we need to take that into
158 * account when setting it.
159 */
160 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
161 defined(CONFIG_M520x) || defined(CONFIG_M532x)
162 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
163 #else
164 #define OPT_FRAME_SIZE 0
165 #endif
166
167 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
168 * tx_bd_base always point to the base of the buffer descriptors. The
169 * cur_rx and cur_tx point to the currently available buffer.
170 * The dirty_tx tracks the current buffer that is being sent by the
171 * controller. The cur_tx and dirty_tx are equal under both completely
172 * empty and completely full conditions. The empty/ready indicator in
173 * the buffer descriptor determines the actual condition.
174 */
175 struct fec_enet_private {
176 /* Hardware registers of the FEC device */
177 volatile fec_t *hwp;
178
179 struct net_device *netdev;
180
181 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
182 unsigned char *tx_bounce[TX_RING_SIZE];
183 struct sk_buff* tx_skbuff[TX_RING_SIZE];
184 ushort skb_cur;
185 ushort skb_dirty;
186
187 /* CPM dual port RAM relative addresses.
188 */
189 dma_addr_t bd_dma;
190 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
191 cbd_t *tx_bd_base;
192 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
193 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
194 uint tx_full;
195 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
196 spinlock_t hw_lock;
197 /* hold while accessing the mii_list_t() elements */
198 spinlock_t mii_lock;
199
200 uint phy_id;
201 uint phy_id_done;
202 uint phy_status;
203 uint phy_speed;
204 phy_info_t const *phy;
205 struct work_struct phy_task;
206
207 uint sequence_done;
208 uint mii_phy_task_queued;
209
210 uint phy_addr;
211
212 int index;
213 int opened;
214 int link;
215 int old_link;
216 int full_duplex;
217 };
218
219 static int fec_enet_open(struct net_device *dev);
220 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
221 static void fec_enet_mii(struct net_device *dev);
222 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
223 static void fec_enet_tx(struct net_device *dev);
224 static void fec_enet_rx(struct net_device *dev);
225 static int fec_enet_close(struct net_device *dev);
226 static void set_multicast_list(struct net_device *dev);
227 static void fec_restart(struct net_device *dev, int duplex);
228 static void fec_stop(struct net_device *dev);
229 static void fec_set_mac_address(struct net_device *dev);
230
231
232 /* MII processing. We keep this as simple as possible. Requests are
233 * placed on the list (if there is room). When the request is finished
234 * by the MII, an optional function may be called.
235 */
236 typedef struct mii_list {
237 uint mii_regval;
238 void (*mii_func)(uint val, struct net_device *dev);
239 struct mii_list *mii_next;
240 } mii_list_t;
241
242 #define NMII 20
243 static mii_list_t mii_cmds[NMII];
244 static mii_list_t *mii_free;
245 static mii_list_t *mii_head;
246 static mii_list_t *mii_tail;
247
248 static int mii_queue(struct net_device *dev, int request,
249 void (*func)(uint, struct net_device *));
250
251 /* Make MII read/write commands for the FEC.
252 */
253 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
254 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
255 (VAL & 0xffff))
256 #define mk_mii_end 0
257
258 /* Transmitter timeout.
259 */
260 #define TX_TIMEOUT (2*HZ)
261
262 /* Register definitions for the PHY.
263 */
264
265 #define MII_REG_CR 0 /* Control Register */
266 #define MII_REG_SR 1 /* Status Register */
267 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
268 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
269 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
270 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
271 #define MII_REG_ANER 6 /* A-N Expansion Register */
272 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
273 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
274
275 /* values for phy_status */
276
277 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
278 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
279 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
280 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
281 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
282 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
283 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
284
285 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
286 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
287 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
288 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
289 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
290 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
291 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
292 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
293
294
295 static int
296 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
297 {
298 struct fec_enet_private *fep;
299 volatile fec_t *fecp;
300 volatile cbd_t *bdp;
301 unsigned short status;
302 unsigned long flags;
303
304 fep = netdev_priv(dev);
305 fecp = (volatile fec_t*)dev->base_addr;
306
307 if (!fep->link) {
308 /* Link is down or autonegotiation is in progress. */
309 return 1;
310 }
311
312 spin_lock_irqsave(&fep->hw_lock, flags);
313 /* Fill in a Tx ring entry */
314 bdp = fep->cur_tx;
315
316 status = bdp->cbd_sc;
317 #ifndef final_version
318 if (status & BD_ENET_TX_READY) {
319 /* Ooops. All transmit buffers are full. Bail out.
320 * This should not happen, since dev->tbusy should be set.
321 */
322 printk("%s: tx queue full!.\n", dev->name);
323 spin_unlock_irqrestore(&fep->hw_lock, flags);
324 return 1;
325 }
326 #endif
327
328 /* Clear all of the status flags.
329 */
330 status &= ~BD_ENET_TX_STATS;
331
332 /* Set buffer length and buffer pointer.
333 */
334 bdp->cbd_bufaddr = __pa(skb->data);
335 bdp->cbd_datlen = skb->len;
336
337 /*
338 * On some FEC implementations data must be aligned on
339 * 4-byte boundaries. Use bounce buffers to copy data
340 * and get it aligned. Ugh.
341 */
342 if (bdp->cbd_bufaddr & 0x3) {
343 unsigned int index;
344 index = bdp - fep->tx_bd_base;
345 memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len);
346 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
347 }
348
349 /* Save skb pointer.
350 */
351 fep->tx_skbuff[fep->skb_cur] = skb;
352
353 dev->stats.tx_bytes += skb->len;
354 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
355
356 /* Push the data cache so the CPM does not get stale memory
357 * data.
358 */
359 dma_sync_single(NULL, bdp->cbd_bufaddr,
360 bdp->cbd_datlen, DMA_TO_DEVICE);
361
362 /* Send it on its way. Tell FEC it's ready, interrupt when done,
363 * it's the last BD of the frame, and to put the CRC on the end.
364 */
365
366 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
367 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
368 bdp->cbd_sc = status;
369
370 dev->trans_start = jiffies;
371
372 /* Trigger transmission start */
373 fecp->fec_x_des_active = 0;
374
375 /* If this was the last BD in the ring, start at the beginning again.
376 */
377 if (status & BD_ENET_TX_WRAP) {
378 bdp = fep->tx_bd_base;
379 } else {
380 bdp++;
381 }
382
383 if (bdp == fep->dirty_tx) {
384 fep->tx_full = 1;
385 netif_stop_queue(dev);
386 }
387
388 fep->cur_tx = (cbd_t *)bdp;
389
390 spin_unlock_irqrestore(&fep->hw_lock, flags);
391
392 return 0;
393 }
394
395 static void
396 fec_timeout(struct net_device *dev)
397 {
398 struct fec_enet_private *fep = netdev_priv(dev);
399
400 printk("%s: transmit timed out.\n", dev->name);
401 dev->stats.tx_errors++;
402 #ifndef final_version
403 {
404 int i;
405 cbd_t *bdp;
406
407 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
408 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
409 (unsigned long)fep->dirty_tx,
410 (unsigned long)fep->cur_rx);
411
412 bdp = fep->tx_bd_base;
413 printk(" tx: %u buffers\n", TX_RING_SIZE);
414 for (i = 0 ; i < TX_RING_SIZE; i++) {
415 printk(" %08x: %04x %04x %08x\n",
416 (uint) bdp,
417 bdp->cbd_sc,
418 bdp->cbd_datlen,
419 (int) bdp->cbd_bufaddr);
420 bdp++;
421 }
422
423 bdp = fep->rx_bd_base;
424 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
425 for (i = 0 ; i < RX_RING_SIZE; i++) {
426 printk(" %08x: %04x %04x %08x\n",
427 (uint) bdp,
428 bdp->cbd_sc,
429 bdp->cbd_datlen,
430 (int) bdp->cbd_bufaddr);
431 bdp++;
432 }
433 }
434 #endif
435 fec_restart(dev, fep->full_duplex);
436 netif_wake_queue(dev);
437 }
438
439 /* The interrupt handler.
440 * This is called from the MPC core interrupt.
441 */
442 static irqreturn_t
443 fec_enet_interrupt(int irq, void * dev_id)
444 {
445 struct net_device *dev = dev_id;
446 volatile fec_t *fecp;
447 uint int_events;
448 irqreturn_t ret = IRQ_NONE;
449
450 fecp = (volatile fec_t*)dev->base_addr;
451
452 /* Get the interrupt events that caused us to be here.
453 */
454 do {
455 int_events = fecp->fec_ievent;
456 fecp->fec_ievent = int_events;
457
458 /* Handle receive event in its own function.
459 */
460 if (int_events & FEC_ENET_RXF) {
461 ret = IRQ_HANDLED;
462 fec_enet_rx(dev);
463 }
464
465 /* Transmit OK, or non-fatal error. Update the buffer
466 descriptors. FEC handles all errors, we just discover
467 them as part of the transmit process.
468 */
469 if (int_events & FEC_ENET_TXF) {
470 ret = IRQ_HANDLED;
471 fec_enet_tx(dev);
472 }
473
474 if (int_events & FEC_ENET_MII) {
475 ret = IRQ_HANDLED;
476 fec_enet_mii(dev);
477 }
478
479 } while (int_events);
480
481 return ret;
482 }
483
484
485 static void
486 fec_enet_tx(struct net_device *dev)
487 {
488 struct fec_enet_private *fep;
489 volatile cbd_t *bdp;
490 unsigned short status;
491 struct sk_buff *skb;
492
493 fep = netdev_priv(dev);
494 spin_lock_irq(&fep->hw_lock);
495 bdp = fep->dirty_tx;
496
497 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
498 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
499
500 skb = fep->tx_skbuff[fep->skb_dirty];
501 /* Check for errors. */
502 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
503 BD_ENET_TX_RL | BD_ENET_TX_UN |
504 BD_ENET_TX_CSL)) {
505 dev->stats.tx_errors++;
506 if (status & BD_ENET_TX_HB) /* No heartbeat */
507 dev->stats.tx_heartbeat_errors++;
508 if (status & BD_ENET_TX_LC) /* Late collision */
509 dev->stats.tx_window_errors++;
510 if (status & BD_ENET_TX_RL) /* Retrans limit */
511 dev->stats.tx_aborted_errors++;
512 if (status & BD_ENET_TX_UN) /* Underrun */
513 dev->stats.tx_fifo_errors++;
514 if (status & BD_ENET_TX_CSL) /* Carrier lost */
515 dev->stats.tx_carrier_errors++;
516 } else {
517 dev->stats.tx_packets++;
518 }
519
520 #ifndef final_version
521 if (status & BD_ENET_TX_READY)
522 printk("HEY! Enet xmit interrupt and TX_READY.\n");
523 #endif
524 /* Deferred means some collisions occurred during transmit,
525 * but we eventually sent the packet OK.
526 */
527 if (status & BD_ENET_TX_DEF)
528 dev->stats.collisions++;
529
530 /* Free the sk buffer associated with this last transmit.
531 */
532 dev_kfree_skb_any(skb);
533 fep->tx_skbuff[fep->skb_dirty] = NULL;
534 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
535
536 /* Update pointer to next buffer descriptor to be transmitted.
537 */
538 if (status & BD_ENET_TX_WRAP)
539 bdp = fep->tx_bd_base;
540 else
541 bdp++;
542
543 /* Since we have freed up a buffer, the ring is no longer
544 * full.
545 */
546 if (fep->tx_full) {
547 fep->tx_full = 0;
548 if (netif_queue_stopped(dev))
549 netif_wake_queue(dev);
550 }
551 }
552 fep->dirty_tx = (cbd_t *)bdp;
553 spin_unlock_irq(&fep->hw_lock);
554 }
555
556
557 /* During a receive, the cur_rx points to the current incoming buffer.
558 * When we update through the ring, if the next incoming buffer has
559 * not been given to the system, we just set the empty indicator,
560 * effectively tossing the packet.
561 */
562 static void
563 fec_enet_rx(struct net_device *dev)
564 {
565 struct fec_enet_private *fep;
566 volatile fec_t *fecp;
567 volatile cbd_t *bdp;
568 unsigned short status;
569 struct sk_buff *skb;
570 ushort pkt_len;
571 __u8 *data;
572
573 #ifdef CONFIG_M532x
574 flush_cache_all();
575 #endif
576
577 fep = netdev_priv(dev);
578 fecp = (volatile fec_t*)dev->base_addr;
579
580 spin_lock_irq(&fep->hw_lock);
581
582 /* First, grab all of the stats for the incoming packet.
583 * These get messed up if we get called due to a busy condition.
584 */
585 bdp = fep->cur_rx;
586
587 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
588
589 #ifndef final_version
590 /* Since we have allocated space to hold a complete frame,
591 * the last indicator should be set.
592 */
593 if ((status & BD_ENET_RX_LAST) == 0)
594 printk("FEC ENET: rcv is not +last\n");
595 #endif
596
597 if (!fep->opened)
598 goto rx_processing_done;
599
600 /* Check for errors. */
601 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
602 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
603 dev->stats.rx_errors++;
604 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
605 /* Frame too long or too short. */
606 dev->stats.rx_length_errors++;
607 }
608 if (status & BD_ENET_RX_NO) /* Frame alignment */
609 dev->stats.rx_frame_errors++;
610 if (status & BD_ENET_RX_CR) /* CRC Error */
611 dev->stats.rx_crc_errors++;
612 if (status & BD_ENET_RX_OV) /* FIFO overrun */
613 dev->stats.rx_fifo_errors++;
614 }
615
616 /* Report late collisions as a frame error.
617 * On this error, the BD is closed, but we don't know what we
618 * have in the buffer. So, just drop this frame on the floor.
619 */
620 if (status & BD_ENET_RX_CL) {
621 dev->stats.rx_errors++;
622 dev->stats.rx_frame_errors++;
623 goto rx_processing_done;
624 }
625
626 /* Process the incoming frame.
627 */
628 dev->stats.rx_packets++;
629 pkt_len = bdp->cbd_datlen;
630 dev->stats.rx_bytes += pkt_len;
631 data = (__u8*)__va(bdp->cbd_bufaddr);
632
633 dma_sync_single(NULL, (unsigned long)__pa(data),
634 pkt_len - 4, DMA_FROM_DEVICE);
635
636 /* This does 16 byte alignment, exactly what we need.
637 * The packet length includes FCS, but we don't want to
638 * include that when passing upstream as it messes up
639 * bridging applications.
640 */
641 skb = dev_alloc_skb(pkt_len-4);
642
643 if (skb == NULL) {
644 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
645 dev->stats.rx_dropped++;
646 } else {
647 skb_put(skb,pkt_len-4); /* Make room */
648 skb_copy_to_linear_data(skb, data, pkt_len-4);
649 skb->protocol=eth_type_trans(skb,dev);
650 netif_rx(skb);
651 }
652 rx_processing_done:
653
654 /* Clear the status flags for this buffer.
655 */
656 status &= ~BD_ENET_RX_STATS;
657
658 /* Mark the buffer empty.
659 */
660 status |= BD_ENET_RX_EMPTY;
661 bdp->cbd_sc = status;
662
663 /* Update BD pointer to next entry.
664 */
665 if (status & BD_ENET_RX_WRAP)
666 bdp = fep->rx_bd_base;
667 else
668 bdp++;
669
670 #if 1
671 /* Doing this here will keep the FEC running while we process
672 * incoming frames. On a heavily loaded network, we should be
673 * able to keep up at the expense of system resources.
674 */
675 fecp->fec_r_des_active = 0;
676 #endif
677 } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
678 fep->cur_rx = (cbd_t *)bdp;
679
680 #if 0
681 /* Doing this here will allow us to process all frames in the
682 * ring before the FEC is allowed to put more there. On a heavily
683 * loaded network, some frames may be lost. Unfortunately, this
684 * increases the interrupt overhead since we can potentially work
685 * our way back to the interrupt return only to come right back
686 * here.
687 */
688 fecp->fec_r_des_active = 0;
689 #endif
690
691 spin_unlock_irq(&fep->hw_lock);
692 }
693
694
695 /* called from interrupt context */
696 static void
697 fec_enet_mii(struct net_device *dev)
698 {
699 struct fec_enet_private *fep;
700 volatile fec_t *ep;
701 mii_list_t *mip;
702 uint mii_reg;
703
704 fep = netdev_priv(dev);
705 spin_lock_irq(&fep->mii_lock);
706
707 ep = fep->hwp;
708 mii_reg = ep->fec_mii_data;
709
710 if ((mip = mii_head) == NULL) {
711 printk("MII and no head!\n");
712 goto unlock;
713 }
714
715 if (mip->mii_func != NULL)
716 (*(mip->mii_func))(mii_reg, dev);
717
718 mii_head = mip->mii_next;
719 mip->mii_next = mii_free;
720 mii_free = mip;
721
722 if ((mip = mii_head) != NULL)
723 ep->fec_mii_data = mip->mii_regval;
724
725 unlock:
726 spin_unlock_irq(&fep->mii_lock);
727 }
728
729 static int
730 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
731 {
732 struct fec_enet_private *fep;
733 unsigned long flags;
734 mii_list_t *mip;
735 int retval;
736
737 /* Add PHY address to register command.
738 */
739 fep = netdev_priv(dev);
740 spin_lock_irqsave(&fep->mii_lock, flags);
741
742 regval |= fep->phy_addr << 23;
743 retval = 0;
744
745 if ((mip = mii_free) != NULL) {
746 mii_free = mip->mii_next;
747 mip->mii_regval = regval;
748 mip->mii_func = func;
749 mip->mii_next = NULL;
750 if (mii_head) {
751 mii_tail->mii_next = mip;
752 mii_tail = mip;
753 } else {
754 mii_head = mii_tail = mip;
755 fep->hwp->fec_mii_data = regval;
756 }
757 } else {
758 retval = 1;
759 }
760
761 spin_unlock_irqrestore(&fep->mii_lock, flags);
762 return retval;
763 }
764
765 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
766 {
767 if(!c)
768 return;
769
770 for (; c->mii_data != mk_mii_end; c++)
771 mii_queue(dev, c->mii_data, c->funct);
772 }
773
774 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
775 {
776 struct fec_enet_private *fep = netdev_priv(dev);
777 volatile uint *s = &(fep->phy_status);
778 uint status;
779
780 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
781
782 if (mii_reg & 0x0004)
783 status |= PHY_STAT_LINK;
784 if (mii_reg & 0x0010)
785 status |= PHY_STAT_FAULT;
786 if (mii_reg & 0x0020)
787 status |= PHY_STAT_ANC;
788 *s = status;
789 }
790
791 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
792 {
793 struct fec_enet_private *fep = netdev_priv(dev);
794 volatile uint *s = &(fep->phy_status);
795 uint status;
796
797 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
798
799 if (mii_reg & 0x1000)
800 status |= PHY_CONF_ANE;
801 if (mii_reg & 0x4000)
802 status |= PHY_CONF_LOOP;
803 *s = status;
804 }
805
806 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
807 {
808 struct fec_enet_private *fep = netdev_priv(dev);
809 volatile uint *s = &(fep->phy_status);
810 uint status;
811
812 status = *s & ~(PHY_CONF_SPMASK);
813
814 if (mii_reg & 0x0020)
815 status |= PHY_CONF_10HDX;
816 if (mii_reg & 0x0040)
817 status |= PHY_CONF_10FDX;
818 if (mii_reg & 0x0080)
819 status |= PHY_CONF_100HDX;
820 if (mii_reg & 0x00100)
821 status |= PHY_CONF_100FDX;
822 *s = status;
823 }
824
825 /* ------------------------------------------------------------------------- */
826 /* The Level one LXT970 is used by many boards */
827
828 #define MII_LXT970_MIRROR 16 /* Mirror register */
829 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
830 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
831 #define MII_LXT970_CONFIG 19 /* Configuration Register */
832 #define MII_LXT970_CSR 20 /* Chip Status Register */
833
834 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
835 {
836 struct fec_enet_private *fep = netdev_priv(dev);
837 volatile uint *s = &(fep->phy_status);
838 uint status;
839
840 status = *s & ~(PHY_STAT_SPMASK);
841 if (mii_reg & 0x0800) {
842 if (mii_reg & 0x1000)
843 status |= PHY_STAT_100FDX;
844 else
845 status |= PHY_STAT_100HDX;
846 } else {
847 if (mii_reg & 0x1000)
848 status |= PHY_STAT_10FDX;
849 else
850 status |= PHY_STAT_10HDX;
851 }
852 *s = status;
853 }
854
855 static phy_cmd_t const phy_cmd_lxt970_config[] = {
856 { mk_mii_read(MII_REG_CR), mii_parse_cr },
857 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
858 { mk_mii_end, }
859 };
860 static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
861 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
862 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
863 { mk_mii_end, }
864 };
865 static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
866 /* read SR and ISR to acknowledge */
867 { mk_mii_read(MII_REG_SR), mii_parse_sr },
868 { mk_mii_read(MII_LXT970_ISR), NULL },
869
870 /* find out the current status */
871 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
872 { mk_mii_end, }
873 };
874 static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
875 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
876 { mk_mii_end, }
877 };
878 static phy_info_t const phy_info_lxt970 = {
879 .id = 0x07810000,
880 .name = "LXT970",
881 .config = phy_cmd_lxt970_config,
882 .startup = phy_cmd_lxt970_startup,
883 .ack_int = phy_cmd_lxt970_ack_int,
884 .shutdown = phy_cmd_lxt970_shutdown
885 };
886
887 /* ------------------------------------------------------------------------- */
888 /* The Level one LXT971 is used on some of my custom boards */
889
890 /* register definitions for the 971 */
891
892 #define MII_LXT971_PCR 16 /* Port Control Register */
893 #define MII_LXT971_SR2 17 /* Status Register 2 */
894 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
895 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
896 #define MII_LXT971_LCR 20 /* LED Control Register */
897 #define MII_LXT971_TCR 30 /* Transmit Control Register */
898
899 /*
900 * I had some nice ideas of running the MDIO faster...
901 * The 971 should support 8MHz and I tried it, but things acted really
902 * weird, so 2.5 MHz ought to be enough for anyone...
903 */
904
905 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
906 {
907 struct fec_enet_private *fep = netdev_priv(dev);
908 volatile uint *s = &(fep->phy_status);
909 uint status;
910
911 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
912
913 if (mii_reg & 0x0400) {
914 fep->link = 1;
915 status |= PHY_STAT_LINK;
916 } else {
917 fep->link = 0;
918 }
919 if (mii_reg & 0x0080)
920 status |= PHY_STAT_ANC;
921 if (mii_reg & 0x4000) {
922 if (mii_reg & 0x0200)
923 status |= PHY_STAT_100FDX;
924 else
925 status |= PHY_STAT_100HDX;
926 } else {
927 if (mii_reg & 0x0200)
928 status |= PHY_STAT_10FDX;
929 else
930 status |= PHY_STAT_10HDX;
931 }
932 if (mii_reg & 0x0008)
933 status |= PHY_STAT_FAULT;
934
935 *s = status;
936 }
937
938 static phy_cmd_t const phy_cmd_lxt971_config[] = {
939 /* limit to 10MBit because my prototype board
940 * doesn't work with 100. */
941 { mk_mii_read(MII_REG_CR), mii_parse_cr },
942 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
943 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
944 { mk_mii_end, }
945 };
946 static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
947 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
948 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
949 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
950 /* Somehow does the 971 tell me that the link is down
951 * the first read after power-up.
952 * read here to get a valid value in ack_int */
953 { mk_mii_read(MII_REG_SR), mii_parse_sr },
954 { mk_mii_end, }
955 };
956 static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
957 /* acknowledge the int before reading status ! */
958 { mk_mii_read(MII_LXT971_ISR), NULL },
959 /* find out the current status */
960 { mk_mii_read(MII_REG_SR), mii_parse_sr },
961 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
962 { mk_mii_end, }
963 };
964 static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
965 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
966 { mk_mii_end, }
967 };
968 static phy_info_t const phy_info_lxt971 = {
969 .id = 0x0001378e,
970 .name = "LXT971",
971 .config = phy_cmd_lxt971_config,
972 .startup = phy_cmd_lxt971_startup,
973 .ack_int = phy_cmd_lxt971_ack_int,
974 .shutdown = phy_cmd_lxt971_shutdown
975 };
976
977 /* ------------------------------------------------------------------------- */
978 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
979
980 /* register definitions */
981
982 #define MII_QS6612_MCR 17 /* Mode Control Register */
983 #define MII_QS6612_FTR 27 /* Factory Test Register */
984 #define MII_QS6612_MCO 28 /* Misc. Control Register */
985 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
986 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
987 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
988
989 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
990 {
991 struct fec_enet_private *fep = netdev_priv(dev);
992 volatile uint *s = &(fep->phy_status);
993 uint status;
994
995 status = *s & ~(PHY_STAT_SPMASK);
996
997 switch((mii_reg >> 2) & 7) {
998 case 1: status |= PHY_STAT_10HDX; break;
999 case 2: status |= PHY_STAT_100HDX; break;
1000 case 5: status |= PHY_STAT_10FDX; break;
1001 case 6: status |= PHY_STAT_100FDX; break;
1002 }
1003
1004 *s = status;
1005 }
1006
1007 static phy_cmd_t const phy_cmd_qs6612_config[] = {
1008 /* The PHY powers up isolated on the RPX,
1009 * so send a command to allow operation.
1010 */
1011 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1012
1013 /* parse cr and anar to get some info */
1014 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1015 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1016 { mk_mii_end, }
1017 };
1018 static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
1019 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1020 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1021 { mk_mii_end, }
1022 };
1023 static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
1024 /* we need to read ISR, SR and ANER to acknowledge */
1025 { mk_mii_read(MII_QS6612_ISR), NULL },
1026 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1027 { mk_mii_read(MII_REG_ANER), NULL },
1028
1029 /* read pcr to get info */
1030 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1031 { mk_mii_end, }
1032 };
1033 static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
1034 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1035 { mk_mii_end, }
1036 };
1037 static phy_info_t const phy_info_qs6612 = {
1038 .id = 0x00181440,
1039 .name = "QS6612",
1040 .config = phy_cmd_qs6612_config,
1041 .startup = phy_cmd_qs6612_startup,
1042 .ack_int = phy_cmd_qs6612_ack_int,
1043 .shutdown = phy_cmd_qs6612_shutdown
1044 };
1045
1046 /* ------------------------------------------------------------------------- */
1047 /* AMD AM79C874 phy */
1048
1049 /* register definitions for the 874 */
1050
1051 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1052 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1053 #define MII_AM79C874_DR 18 /* Diagnostic Register */
1054 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1055 #define MII_AM79C874_MCR 21 /* ModeControl Register */
1056 #define MII_AM79C874_DC 23 /* Disconnect Counter */
1057 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
1058
1059 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1060 {
1061 struct fec_enet_private *fep = netdev_priv(dev);
1062 volatile uint *s = &(fep->phy_status);
1063 uint status;
1064
1065 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
1066
1067 if (mii_reg & 0x0080)
1068 status |= PHY_STAT_ANC;
1069 if (mii_reg & 0x0400)
1070 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
1071 else
1072 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1073
1074 *s = status;
1075 }
1076
1077 static phy_cmd_t const phy_cmd_am79c874_config[] = {
1078 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1079 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1080 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1081 { mk_mii_end, }
1082 };
1083 static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
1084 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1085 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1086 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1087 { mk_mii_end, }
1088 };
1089 static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
1090 /* find out the current status */
1091 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1092 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1093 /* we only need to read ISR to acknowledge */
1094 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1095 { mk_mii_end, }
1096 };
1097 static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
1098 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1099 { mk_mii_end, }
1100 };
1101 static phy_info_t const phy_info_am79c874 = {
1102 .id = 0x00022561,
1103 .name = "AM79C874",
1104 .config = phy_cmd_am79c874_config,
1105 .startup = phy_cmd_am79c874_startup,
1106 .ack_int = phy_cmd_am79c874_ack_int,
1107 .shutdown = phy_cmd_am79c874_shutdown
1108 };
1109
1110
1111 /* ------------------------------------------------------------------------- */
1112 /* Kendin KS8721BL phy */
1113
1114 /* register definitions for the 8721 */
1115
1116 #define MII_KS8721BL_RXERCR 21
1117 #define MII_KS8721BL_ICSR 27
1118 #define MII_KS8721BL_PHYCR 31
1119
1120 static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1121 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1122 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1123 { mk_mii_end, }
1124 };
1125 static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1126 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1127 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1128 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1129 { mk_mii_end, }
1130 };
1131 static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1132 /* find out the current status */
1133 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1134 /* we only need to read ISR to acknowledge */
1135 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1136 { mk_mii_end, }
1137 };
1138 static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
1139 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1140 { mk_mii_end, }
1141 };
1142 static phy_info_t const phy_info_ks8721bl = {
1143 .id = 0x00022161,
1144 .name = "KS8721BL",
1145 .config = phy_cmd_ks8721bl_config,
1146 .startup = phy_cmd_ks8721bl_startup,
1147 .ack_int = phy_cmd_ks8721bl_ack_int,
1148 .shutdown = phy_cmd_ks8721bl_shutdown
1149 };
1150
1151 /* ------------------------------------------------------------------------- */
1152 /* register definitions for the DP83848 */
1153
1154 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1155
1156 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1157 {
1158 struct fec_enet_private *fep = netdev_priv(dev);
1159 volatile uint *s = &(fep->phy_status);
1160
1161 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1162
1163 /* Link up */
1164 if (mii_reg & 0x0001) {
1165 fep->link = 1;
1166 *s |= PHY_STAT_LINK;
1167 } else
1168 fep->link = 0;
1169 /* Status of link */
1170 if (mii_reg & 0x0010) /* Autonegotioation complete */
1171 *s |= PHY_STAT_ANC;
1172 if (mii_reg & 0x0002) { /* 10MBps? */
1173 if (mii_reg & 0x0004) /* Full Duplex? */
1174 *s |= PHY_STAT_10FDX;
1175 else
1176 *s |= PHY_STAT_10HDX;
1177 } else { /* 100 Mbps? */
1178 if (mii_reg & 0x0004) /* Full Duplex? */
1179 *s |= PHY_STAT_100FDX;
1180 else
1181 *s |= PHY_STAT_100HDX;
1182 }
1183 if (mii_reg & 0x0008)
1184 *s |= PHY_STAT_FAULT;
1185 }
1186
1187 static phy_info_t phy_info_dp83848= {
1188 0x020005c9,
1189 "DP83848",
1190
1191 (const phy_cmd_t []) { /* config */
1192 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1193 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1194 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1195 { mk_mii_end, }
1196 },
1197 (const phy_cmd_t []) { /* startup - enable interrupts */
1198 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1199 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1200 { mk_mii_end, }
1201 },
1202 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1203 { mk_mii_end, }
1204 },
1205 (const phy_cmd_t []) { /* shutdown */
1206 { mk_mii_end, }
1207 },
1208 };
1209
1210 /* ------------------------------------------------------------------------- */
1211
1212 static phy_info_t const * const phy_info[] = {
1213 &phy_info_lxt970,
1214 &phy_info_lxt971,
1215 &phy_info_qs6612,
1216 &phy_info_am79c874,
1217 &phy_info_ks8721bl,
1218 &phy_info_dp83848,
1219 NULL
1220 };
1221
1222 /* ------------------------------------------------------------------------- */
1223 #ifdef HAVE_mii_link_interrupt
1224 static irqreturn_t
1225 mii_link_interrupt(int irq, void * dev_id);
1226 #endif
1227
1228 #if defined(CONFIG_M5272)
1229 /*
1230 * Code specific to Coldfire 5272 setup.
1231 */
1232 static void __inline__ fec_request_intrs(struct net_device *dev)
1233 {
1234 volatile unsigned long *icrp;
1235 static const struct idesc {
1236 char *name;
1237 unsigned short irq;
1238 irq_handler_t handler;
1239 } *idp, id[] = {
1240 { "fec(RX)", 86, fec_enet_interrupt },
1241 { "fec(TX)", 87, fec_enet_interrupt },
1242 { "fec(OTHER)", 88, fec_enet_interrupt },
1243 { "fec(MII)", 66, mii_link_interrupt },
1244 { NULL },
1245 };
1246
1247 /* Setup interrupt handlers. */
1248 for (idp = id; idp->name; idp++) {
1249 if (request_irq(idp->irq, idp->handler, IRQF_DISABLED, idp->name, dev) != 0)
1250 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1251 }
1252
1253 /* Unmask interrupt at ColdFire 5272 SIM */
1254 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1255 *icrp = 0x00000ddd;
1256 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1257 *icrp = 0x0d000000;
1258 }
1259
1260 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1261 {
1262 volatile fec_t *fecp;
1263
1264 fecp = fep->hwp;
1265 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1266 fecp->fec_x_cntrl = 0x00;
1267
1268 /*
1269 * Set MII speed to 2.5 MHz
1270 * See 5272 manual section 11.5.8: MSCR
1271 */
1272 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1273 fecp->fec_mii_speed = fep->phy_speed;
1274
1275 fec_restart(dev, 0);
1276 }
1277
1278 static void __inline__ fec_get_mac(struct net_device *dev)
1279 {
1280 struct fec_enet_private *fep = netdev_priv(dev);
1281 volatile fec_t *fecp;
1282 unsigned char *iap, tmpaddr[ETH_ALEN];
1283
1284 fecp = fep->hwp;
1285
1286 if (FEC_FLASHMAC) {
1287 /*
1288 * Get MAC address from FLASH.
1289 * If it is all 1's or 0's, use the default.
1290 */
1291 iap = (unsigned char *)FEC_FLASHMAC;
1292 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1293 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1294 iap = fec_mac_default;
1295 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1296 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1297 iap = fec_mac_default;
1298 } else {
1299 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1300 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1301 iap = &tmpaddr[0];
1302 }
1303
1304 memcpy(dev->dev_addr, iap, ETH_ALEN);
1305
1306 /* Adjust MAC if using default MAC address */
1307 if (iap == fec_mac_default)
1308 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1309 }
1310
1311 static void __inline__ fec_disable_phy_intr(void)
1312 {
1313 volatile unsigned long *icrp;
1314 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1315 *icrp = 0x08000000;
1316 }
1317
1318 static void __inline__ fec_phy_ack_intr(void)
1319 {
1320 volatile unsigned long *icrp;
1321 /* Acknowledge the interrupt */
1322 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1323 *icrp = 0x0d000000;
1324 }
1325
1326 /* ------------------------------------------------------------------------- */
1327
1328 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
1329
1330 /*
1331 * Code specific to Coldfire 5230/5231/5232/5234/5235,
1332 * the 5270/5271/5274/5275 and 5280/5282 setups.
1333 */
1334 static void __inline__ fec_request_intrs(struct net_device *dev)
1335 {
1336 struct fec_enet_private *fep;
1337 int b;
1338 static const struct idesc {
1339 char *name;
1340 unsigned short irq;
1341 } *idp, id[] = {
1342 { "fec(TXF)", 23 },
1343 { "fec(RXF)", 27 },
1344 { "fec(MII)", 29 },
1345 { NULL },
1346 };
1347
1348 fep = netdev_priv(dev);
1349 b = (fep->index) ? 128 : 64;
1350
1351 /* Setup interrupt handlers. */
1352 for (idp = id; idp->name; idp++) {
1353 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name, dev) != 0)
1354 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1355 }
1356
1357 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1358 {
1359 volatile unsigned char *icrp;
1360 volatile unsigned long *imrp;
1361 int i, ilip;
1362
1363 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1364 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1365 MCFINTC_ICR0);
1366 for (i = 23, ilip = 0x28; (i < 36); i++)
1367 icrp[i] = ilip--;
1368
1369 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1370 MCFINTC_IMRH);
1371 *imrp &= ~0x0000000f;
1372 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1373 MCFINTC_IMRL);
1374 *imrp &= ~0xff800001;
1375 }
1376
1377 #if defined(CONFIG_M528x)
1378 /* Set up gpio outputs for MII lines */
1379 {
1380 volatile u16 *gpio_paspar;
1381 volatile u8 *gpio_pehlpar;
1382
1383 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1384 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
1385 *gpio_paspar |= 0x0f00;
1386 *gpio_pehlpar = 0xc0;
1387 }
1388 #endif
1389
1390 #if defined(CONFIG_M527x)
1391 /* Set up gpio outputs for MII lines */
1392 {
1393 volatile u8 *gpio_par_fec;
1394 volatile u16 *gpio_par_feci2c;
1395
1396 gpio_par_feci2c = (volatile u16 *)(MCF_IPSBAR + 0x100082);
1397 /* Set up gpio outputs for FEC0 MII lines */
1398 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100078);
1399
1400 *gpio_par_feci2c |= 0x0f00;
1401 *gpio_par_fec |= 0xc0;
1402
1403 #if defined(CONFIG_FEC2)
1404 /* Set up gpio outputs for FEC1 MII lines */
1405 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100079);
1406
1407 *gpio_par_feci2c |= 0x00a0;
1408 *gpio_par_fec |= 0xc0;
1409 #endif /* CONFIG_FEC2 */
1410 }
1411 #endif /* CONFIG_M527x */
1412 }
1413
1414 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1415 {
1416 volatile fec_t *fecp;
1417
1418 fecp = fep->hwp;
1419 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1420 fecp->fec_x_cntrl = 0x00;
1421
1422 /*
1423 * Set MII speed to 2.5 MHz
1424 * See 5282 manual section 17.5.4.7: MSCR
1425 */
1426 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1427 fecp->fec_mii_speed = fep->phy_speed;
1428
1429 fec_restart(dev, 0);
1430 }
1431
1432 static void __inline__ fec_get_mac(struct net_device *dev)
1433 {
1434 struct fec_enet_private *fep = netdev_priv(dev);
1435 volatile fec_t *fecp;
1436 unsigned char *iap, tmpaddr[ETH_ALEN];
1437
1438 fecp = fep->hwp;
1439
1440 if (FEC_FLASHMAC) {
1441 /*
1442 * Get MAC address from FLASH.
1443 * If it is all 1's or 0's, use the default.
1444 */
1445 iap = FEC_FLASHMAC;
1446 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1447 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1448 iap = fec_mac_default;
1449 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1450 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1451 iap = fec_mac_default;
1452 } else {
1453 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1454 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1455 iap = &tmpaddr[0];
1456 }
1457
1458 memcpy(dev->dev_addr, iap, ETH_ALEN);
1459
1460 /* Adjust MAC if using default MAC address */
1461 if (iap == fec_mac_default)
1462 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1463 }
1464
1465 static void __inline__ fec_disable_phy_intr(void)
1466 {
1467 }
1468
1469 static void __inline__ fec_phy_ack_intr(void)
1470 {
1471 }
1472
1473 /* ------------------------------------------------------------------------- */
1474
1475 #elif defined(CONFIG_M520x)
1476
1477 /*
1478 * Code specific to Coldfire 520x
1479 */
1480 static void __inline__ fec_request_intrs(struct net_device *dev)
1481 {
1482 struct fec_enet_private *fep;
1483 int b;
1484 static const struct idesc {
1485 char *name;
1486 unsigned short irq;
1487 } *idp, id[] = {
1488 { "fec(TXF)", 23 },
1489 { "fec(RXF)", 27 },
1490 { "fec(MII)", 29 },
1491 { NULL },
1492 };
1493
1494 fep = netdev_priv(dev);
1495 b = 64 + 13;
1496
1497 /* Setup interrupt handlers. */
1498 for (idp = id; idp->name; idp++) {
1499 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
1500 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1501 }
1502
1503 /* Unmask interrupts at ColdFire interrupt controller */
1504 {
1505 volatile unsigned char *icrp;
1506 volatile unsigned long *imrp;
1507
1508 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
1509 MCFINTC_ICR0);
1510 for (b = 36; (b < 49); b++)
1511 icrp[b] = 0x04;
1512 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
1513 MCFINTC_IMRH);
1514 *imrp &= ~0x0001FFF0;
1515 }
1516 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
1517 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
1518 }
1519
1520 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1521 {
1522 volatile fec_t *fecp;
1523
1524 fecp = fep->hwp;
1525 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1526 fecp->fec_x_cntrl = 0x00;
1527
1528 /*
1529 * Set MII speed to 2.5 MHz
1530 * See 5282 manual section 17.5.4.7: MSCR
1531 */
1532 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1533 fecp->fec_mii_speed = fep->phy_speed;
1534
1535 fec_restart(dev, 0);
1536 }
1537
1538 static void __inline__ fec_get_mac(struct net_device *dev)
1539 {
1540 struct fec_enet_private *fep = netdev_priv(dev);
1541 volatile fec_t *fecp;
1542 unsigned char *iap, tmpaddr[ETH_ALEN];
1543
1544 fecp = fep->hwp;
1545
1546 if (FEC_FLASHMAC) {
1547 /*
1548 * Get MAC address from FLASH.
1549 * If it is all 1's or 0's, use the default.
1550 */
1551 iap = FEC_FLASHMAC;
1552 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1553 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1554 iap = fec_mac_default;
1555 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1556 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1557 iap = fec_mac_default;
1558 } else {
1559 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1560 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1561 iap = &tmpaddr[0];
1562 }
1563
1564 memcpy(dev->dev_addr, iap, ETH_ALEN);
1565
1566 /* Adjust MAC if using default MAC address */
1567 if (iap == fec_mac_default)
1568 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1569 }
1570
1571 static void __inline__ fec_disable_phy_intr(void)
1572 {
1573 }
1574
1575 static void __inline__ fec_phy_ack_intr(void)
1576 {
1577 }
1578
1579 /* ------------------------------------------------------------------------- */
1580
1581 #elif defined(CONFIG_M532x)
1582 /*
1583 * Code specific for M532x
1584 */
1585 static void __inline__ fec_request_intrs(struct net_device *dev)
1586 {
1587 struct fec_enet_private *fep;
1588 int b;
1589 static const struct idesc {
1590 char *name;
1591 unsigned short irq;
1592 } *idp, id[] = {
1593 { "fec(TXF)", 36 },
1594 { "fec(RXF)", 40 },
1595 { "fec(MII)", 42 },
1596 { NULL },
1597 };
1598
1599 fep = netdev_priv(dev);
1600 b = (fep->index) ? 128 : 64;
1601
1602 /* Setup interrupt handlers. */
1603 for (idp = id; idp->name; idp++) {
1604 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
1605 printk("FEC: Could not allocate %s IRQ(%d)!\n",
1606 idp->name, b+idp->irq);
1607 }
1608
1609 /* Unmask interrupts */
1610 MCF_INTC0_ICR36 = 0x2;
1611 MCF_INTC0_ICR37 = 0x2;
1612 MCF_INTC0_ICR38 = 0x2;
1613 MCF_INTC0_ICR39 = 0x2;
1614 MCF_INTC0_ICR40 = 0x2;
1615 MCF_INTC0_ICR41 = 0x2;
1616 MCF_INTC0_ICR42 = 0x2;
1617 MCF_INTC0_ICR43 = 0x2;
1618 MCF_INTC0_ICR44 = 0x2;
1619 MCF_INTC0_ICR45 = 0x2;
1620 MCF_INTC0_ICR46 = 0x2;
1621 MCF_INTC0_ICR47 = 0x2;
1622 MCF_INTC0_ICR48 = 0x2;
1623
1624 MCF_INTC0_IMRH &= ~(
1625 MCF_INTC_IMRH_INT_MASK36 |
1626 MCF_INTC_IMRH_INT_MASK37 |
1627 MCF_INTC_IMRH_INT_MASK38 |
1628 MCF_INTC_IMRH_INT_MASK39 |
1629 MCF_INTC_IMRH_INT_MASK40 |
1630 MCF_INTC_IMRH_INT_MASK41 |
1631 MCF_INTC_IMRH_INT_MASK42 |
1632 MCF_INTC_IMRH_INT_MASK43 |
1633 MCF_INTC_IMRH_INT_MASK44 |
1634 MCF_INTC_IMRH_INT_MASK45 |
1635 MCF_INTC_IMRH_INT_MASK46 |
1636 MCF_INTC_IMRH_INT_MASK47 |
1637 MCF_INTC_IMRH_INT_MASK48 );
1638
1639 /* Set up gpio outputs for MII lines */
1640 MCF_GPIO_PAR_FECI2C |= (0 |
1641 MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
1642 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
1643 MCF_GPIO_PAR_FEC = (0 |
1644 MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
1645 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
1646 }
1647
1648 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1649 {
1650 volatile fec_t *fecp;
1651
1652 fecp = fep->hwp;
1653 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1654 fecp->fec_x_cntrl = 0x00;
1655
1656 /*
1657 * Set MII speed to 2.5 MHz
1658 */
1659 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1660 fecp->fec_mii_speed = fep->phy_speed;
1661
1662 fec_restart(dev, 0);
1663 }
1664
1665 static void __inline__ fec_get_mac(struct net_device *dev)
1666 {
1667 struct fec_enet_private *fep = netdev_priv(dev);
1668 volatile fec_t *fecp;
1669 unsigned char *iap, tmpaddr[ETH_ALEN];
1670
1671 fecp = fep->hwp;
1672
1673 if (FEC_FLASHMAC) {
1674 /*
1675 * Get MAC address from FLASH.
1676 * If it is all 1's or 0's, use the default.
1677 */
1678 iap = FEC_FLASHMAC;
1679 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1680 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1681 iap = fec_mac_default;
1682 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1683 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1684 iap = fec_mac_default;
1685 } else {
1686 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1687 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1688 iap = &tmpaddr[0];
1689 }
1690
1691 memcpy(dev->dev_addr, iap, ETH_ALEN);
1692
1693 /* Adjust MAC if using default MAC address */
1694 if (iap == fec_mac_default)
1695 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1696 }
1697
1698 static void __inline__ fec_disable_phy_intr(void)
1699 {
1700 }
1701
1702 static void __inline__ fec_phy_ack_intr(void)
1703 {
1704 }
1705
1706 #endif
1707
1708 /* ------------------------------------------------------------------------- */
1709
1710 static void mii_display_status(struct net_device *dev)
1711 {
1712 struct fec_enet_private *fep = netdev_priv(dev);
1713 volatile uint *s = &(fep->phy_status);
1714
1715 if (!fep->link && !fep->old_link) {
1716 /* Link is still down - don't print anything */
1717 return;
1718 }
1719
1720 printk("%s: status: ", dev->name);
1721
1722 if (!fep->link) {
1723 printk("link down");
1724 } else {
1725 printk("link up");
1726
1727 switch(*s & PHY_STAT_SPMASK) {
1728 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1729 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1730 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1731 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1732 default:
1733 printk(", Unknown speed/duplex");
1734 }
1735
1736 if (*s & PHY_STAT_ANC)
1737 printk(", auto-negotiation complete");
1738 }
1739
1740 if (*s & PHY_STAT_FAULT)
1741 printk(", remote fault");
1742
1743 printk(".\n");
1744 }
1745
1746 static void mii_display_config(struct work_struct *work)
1747 {
1748 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1749 struct net_device *dev = fep->netdev;
1750 uint status = fep->phy_status;
1751
1752 /*
1753 ** When we get here, phy_task is already removed from
1754 ** the workqueue. It is thus safe to allow to reuse it.
1755 */
1756 fep->mii_phy_task_queued = 0;
1757 printk("%s: config: auto-negotiation ", dev->name);
1758
1759 if (status & PHY_CONF_ANE)
1760 printk("on");
1761 else
1762 printk("off");
1763
1764 if (status & PHY_CONF_100FDX)
1765 printk(", 100FDX");
1766 if (status & PHY_CONF_100HDX)
1767 printk(", 100HDX");
1768 if (status & PHY_CONF_10FDX)
1769 printk(", 10FDX");
1770 if (status & PHY_CONF_10HDX)
1771 printk(", 10HDX");
1772 if (!(status & PHY_CONF_SPMASK))
1773 printk(", No speed/duplex selected?");
1774
1775 if (status & PHY_CONF_LOOP)
1776 printk(", loopback enabled");
1777
1778 printk(".\n");
1779
1780 fep->sequence_done = 1;
1781 }
1782
1783 static void mii_relink(struct work_struct *work)
1784 {
1785 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1786 struct net_device *dev = fep->netdev;
1787 int duplex;
1788
1789 /*
1790 ** When we get here, phy_task is already removed from
1791 ** the workqueue. It is thus safe to allow to reuse it.
1792 */
1793 fep->mii_phy_task_queued = 0;
1794 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1795 mii_display_status(dev);
1796 fep->old_link = fep->link;
1797
1798 if (fep->link) {
1799 duplex = 0;
1800 if (fep->phy_status
1801 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1802 duplex = 1;
1803 fec_restart(dev, duplex);
1804 } else
1805 fec_stop(dev);
1806
1807 #if 0
1808 enable_irq(fep->mii_irq);
1809 #endif
1810
1811 }
1812
1813 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
1814 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1815 {
1816 struct fec_enet_private *fep = netdev_priv(dev);
1817
1818 /*
1819 ** We cannot queue phy_task twice in the workqueue. It
1820 ** would cause an endless loop in the workqueue.
1821 ** Fortunately, if the last mii_relink entry has not yet been
1822 ** executed now, it will do the job for the current interrupt,
1823 ** which is just what we want.
1824 */
1825 if (fep->mii_phy_task_queued)
1826 return;
1827
1828 fep->mii_phy_task_queued = 1;
1829 INIT_WORK(&fep->phy_task, mii_relink);
1830 schedule_work(&fep->phy_task);
1831 }
1832
1833 /* mii_queue_config is called in interrupt context from fec_enet_mii */
1834 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1835 {
1836 struct fec_enet_private *fep = netdev_priv(dev);
1837
1838 if (fep->mii_phy_task_queued)
1839 return;
1840
1841 fep->mii_phy_task_queued = 1;
1842 INIT_WORK(&fep->phy_task, mii_display_config);
1843 schedule_work(&fep->phy_task);
1844 }
1845
1846 phy_cmd_t const phy_cmd_relink[] = {
1847 { mk_mii_read(MII_REG_CR), mii_queue_relink },
1848 { mk_mii_end, }
1849 };
1850 phy_cmd_t const phy_cmd_config[] = {
1851 { mk_mii_read(MII_REG_CR), mii_queue_config },
1852 { mk_mii_end, }
1853 };
1854
1855 /* Read remainder of PHY ID.
1856 */
1857 static void
1858 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1859 {
1860 struct fec_enet_private *fep;
1861 int i;
1862
1863 fep = netdev_priv(dev);
1864 fep->phy_id |= (mii_reg & 0xffff);
1865 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
1866
1867 for(i = 0; phy_info[i]; i++) {
1868 if(phy_info[i]->id == (fep->phy_id >> 4))
1869 break;
1870 }
1871
1872 if (phy_info[i])
1873 printk(" -- %s\n", phy_info[i]->name);
1874 else
1875 printk(" -- unknown PHY!\n");
1876
1877 fep->phy = phy_info[i];
1878 fep->phy_id_done = 1;
1879 }
1880
1881 /* Scan all of the MII PHY addresses looking for someone to respond
1882 * with a valid ID. This usually happens quickly.
1883 */
1884 static void
1885 mii_discover_phy(uint mii_reg, struct net_device *dev)
1886 {
1887 struct fec_enet_private *fep;
1888 volatile fec_t *fecp;
1889 uint phytype;
1890
1891 fep = netdev_priv(dev);
1892 fecp = fep->hwp;
1893
1894 if (fep->phy_addr < 32) {
1895 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
1896
1897 /* Got first part of ID, now get remainder.
1898 */
1899 fep->phy_id = phytype << 16;
1900 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
1901 mii_discover_phy3);
1902 } else {
1903 fep->phy_addr++;
1904 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1905 mii_discover_phy);
1906 }
1907 } else {
1908 printk("FEC: No PHY device found.\n");
1909 /* Disable external MII interface */
1910 fecp->fec_mii_speed = fep->phy_speed = 0;
1911 fec_disable_phy_intr();
1912 }
1913 }
1914
1915 /* This interrupt occurs when the PHY detects a link change.
1916 */
1917 #ifdef HAVE_mii_link_interrupt
1918 static irqreturn_t
1919 mii_link_interrupt(int irq, void * dev_id)
1920 {
1921 struct net_device *dev = dev_id;
1922 struct fec_enet_private *fep = netdev_priv(dev);
1923
1924 fec_phy_ack_intr();
1925
1926 #if 0
1927 disable_irq(fep->mii_irq); /* disable now, enable later */
1928 #endif
1929
1930 mii_do_cmd(dev, fep->phy->ack_int);
1931 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1932
1933 return IRQ_HANDLED;
1934 }
1935 #endif
1936
1937 static int
1938 fec_enet_open(struct net_device *dev)
1939 {
1940 struct fec_enet_private *fep = netdev_priv(dev);
1941
1942 /* I should reset the ring buffers here, but I don't yet know
1943 * a simple way to do that.
1944 */
1945 fec_set_mac_address(dev);
1946
1947 fep->sequence_done = 0;
1948 fep->link = 0;
1949
1950 if (fep->phy) {
1951 mii_do_cmd(dev, fep->phy->ack_int);
1952 mii_do_cmd(dev, fep->phy->config);
1953 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1954
1955 /* Poll until the PHY tells us its configuration
1956 * (not link state).
1957 * Request is initiated by mii_do_cmd above, but answer
1958 * comes by interrupt.
1959 * This should take about 25 usec per register at 2.5 MHz,
1960 * and we read approximately 5 registers.
1961 */
1962 while(!fep->sequence_done)
1963 schedule();
1964
1965 mii_do_cmd(dev, fep->phy->startup);
1966
1967 /* Set the initial link state to true. A lot of hardware
1968 * based on this device does not implement a PHY interrupt,
1969 * so we are never notified of link change.
1970 */
1971 fep->link = 1;
1972 } else {
1973 fep->link = 1; /* lets just try it and see */
1974 /* no phy, go full duplex, it's most likely a hub chip */
1975 fec_restart(dev, 1);
1976 }
1977
1978 netif_start_queue(dev);
1979 fep->opened = 1;
1980 return 0; /* Success */
1981 }
1982
1983 static int
1984 fec_enet_close(struct net_device *dev)
1985 {
1986 struct fec_enet_private *fep = netdev_priv(dev);
1987
1988 /* Don't know what to do yet.
1989 */
1990 fep->opened = 0;
1991 netif_stop_queue(dev);
1992 fec_stop(dev);
1993
1994 return 0;
1995 }
1996
1997 /* Set or clear the multicast filter for this adaptor.
1998 * Skeleton taken from sunlance driver.
1999 * The CPM Ethernet implementation allows Multicast as well as individual
2000 * MAC address filtering. Some of the drivers check to make sure it is
2001 * a group multicast address, and discard those that are not. I guess I
2002 * will do the same for now, but just remove the test if you want
2003 * individual filtering as well (do the upper net layers want or support
2004 * this kind of feature?).
2005 */
2006
2007 #define HASH_BITS 6 /* #bits in hash */
2008 #define CRC32_POLY 0xEDB88320
2009
2010 static void set_multicast_list(struct net_device *dev)
2011 {
2012 struct fec_enet_private *fep;
2013 volatile fec_t *ep;
2014 struct dev_mc_list *dmi;
2015 unsigned int i, j, bit, data, crc;
2016 unsigned char hash;
2017
2018 fep = netdev_priv(dev);
2019 ep = fep->hwp;
2020
2021 if (dev->flags&IFF_PROMISC) {
2022 ep->fec_r_cntrl |= 0x0008;
2023 } else {
2024
2025 ep->fec_r_cntrl &= ~0x0008;
2026
2027 if (dev->flags & IFF_ALLMULTI) {
2028 /* Catch all multicast addresses, so set the
2029 * filter to all 1's.
2030 */
2031 ep->fec_grp_hash_table_high = 0xffffffff;
2032 ep->fec_grp_hash_table_low = 0xffffffff;
2033 } else {
2034 /* Clear filter and add the addresses in hash register.
2035 */
2036 ep->fec_grp_hash_table_high = 0;
2037 ep->fec_grp_hash_table_low = 0;
2038
2039 dmi = dev->mc_list;
2040
2041 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
2042 {
2043 /* Only support group multicast for now.
2044 */
2045 if (!(dmi->dmi_addr[0] & 1))
2046 continue;
2047
2048 /* calculate crc32 value of mac address
2049 */
2050 crc = 0xffffffff;
2051
2052 for (i = 0; i < dmi->dmi_addrlen; i++)
2053 {
2054 data = dmi->dmi_addr[i];
2055 for (bit = 0; bit < 8; bit++, data >>= 1)
2056 {
2057 crc = (crc >> 1) ^
2058 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2059 }
2060 }
2061
2062 /* only upper 6 bits (HASH_BITS) are used
2063 which point to specific bit in he hash registers
2064 */
2065 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2066
2067 if (hash > 31)
2068 ep->fec_grp_hash_table_high |= 1 << (hash - 32);
2069 else
2070 ep->fec_grp_hash_table_low |= 1 << hash;
2071 }
2072 }
2073 }
2074 }
2075
2076 /* Set a MAC change in hardware.
2077 */
2078 static void
2079 fec_set_mac_address(struct net_device *dev)
2080 {
2081 volatile fec_t *fecp;
2082
2083 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
2084
2085 /* Set station address. */
2086 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
2087 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
2088 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
2089 (dev->dev_addr[4] << 24);
2090
2091 }
2092
2093 /* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
2094 */
2095 /*
2096 * XXX: We need to clean up on failure exits here.
2097 */
2098 int __init fec_enet_init(struct net_device *dev)
2099 {
2100 struct fec_enet_private *fep = netdev_priv(dev);
2101 unsigned long mem_addr;
2102 volatile cbd_t *bdp;
2103 cbd_t *cbd_base;
2104 volatile fec_t *fecp;
2105 int i, j;
2106 static int index = 0;
2107
2108 /* Only allow us to be probed once. */
2109 if (index >= FEC_MAX_PORTS)
2110 return -ENXIO;
2111
2112 /* Allocate memory for buffer descriptors.
2113 */
2114 mem_addr = (unsigned long)dma_alloc_coherent(NULL, PAGE_SIZE,
2115 &fep->bd_dma, GFP_KERNEL);
2116 if (mem_addr == 0) {
2117 printk("FEC: allocate descriptor memory failed?\n");
2118 return -ENOMEM;
2119 }
2120
2121 spin_lock_init(&fep->hw_lock);
2122 spin_lock_init(&fep->mii_lock);
2123
2124 /* Create an Ethernet device instance.
2125 */
2126 fecp = (volatile fec_t *) fec_hw[index];
2127
2128 fep->index = index;
2129 fep->hwp = fecp;
2130 fep->netdev = dev;
2131
2132 /* Whack a reset. We should wait for this.
2133 */
2134 fecp->fec_ecntrl = 1;
2135 udelay(10);
2136
2137 /* Set the Ethernet address. If using multiple Enets on the 8xx,
2138 * this needs some work to get unique addresses.
2139 *
2140 * This is our default MAC address unless the user changes
2141 * it via eth_mac_addr (our dev->set_mac_addr handler).
2142 */
2143 fec_get_mac(dev);
2144
2145 cbd_base = (cbd_t *)mem_addr;
2146 /* XXX: missing check for allocation failure */
2147
2148 /* Set receive and transmit descriptor base.
2149 */
2150 fep->rx_bd_base = cbd_base;
2151 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
2152
2153 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2154 fep->cur_rx = fep->rx_bd_base;
2155
2156 fep->skb_cur = fep->skb_dirty = 0;
2157
2158 /* Initialize the receive buffer descriptors.
2159 */
2160 bdp = fep->rx_bd_base;
2161 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
2162
2163 /* Allocate a page.
2164 */
2165 mem_addr = __get_free_page(GFP_KERNEL);
2166 /* XXX: missing check for allocation failure */
2167
2168 /* Initialize the BD for every fragment in the page.
2169 */
2170 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2171 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2172 bdp->cbd_bufaddr = __pa(mem_addr);
2173 mem_addr += FEC_ENET_RX_FRSIZE;
2174 bdp++;
2175 }
2176 }
2177
2178 /* Set the last buffer to wrap.
2179 */
2180 bdp--;
2181 bdp->cbd_sc |= BD_SC_WRAP;
2182
2183 /* ...and the same for transmmit.
2184 */
2185 bdp = fep->tx_bd_base;
2186 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2187 if (j >= FEC_ENET_TX_FRPPG) {
2188 mem_addr = __get_free_page(GFP_KERNEL);
2189 j = 1;
2190 } else {
2191 mem_addr += FEC_ENET_TX_FRSIZE;
2192 j++;
2193 }
2194 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2195
2196 /* Initialize the BD for every fragment in the page.
2197 */
2198 bdp->cbd_sc = 0;
2199 bdp->cbd_bufaddr = 0;
2200 bdp++;
2201 }
2202
2203 /* Set the last buffer to wrap.
2204 */
2205 bdp--;
2206 bdp->cbd_sc |= BD_SC_WRAP;
2207
2208 /* Set receive and transmit descriptor base.
2209 */
2210 fecp->fec_r_des_start = fep->bd_dma;
2211 fecp->fec_x_des_start = (unsigned long)fep->bd_dma + sizeof(cbd_t)
2212 * RX_RING_SIZE;
2213
2214 /* Install our interrupt handlers. This varies depending on
2215 * the architecture.
2216 */
2217 fec_request_intrs(dev);
2218
2219 fecp->fec_grp_hash_table_high = 0;
2220 fecp->fec_grp_hash_table_low = 0;
2221 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2222 fecp->fec_ecntrl = 2;
2223 fecp->fec_r_des_active = 0;
2224 #ifndef CONFIG_M5272
2225 fecp->fec_hash_table_high = 0;
2226 fecp->fec_hash_table_low = 0;
2227 #endif
2228
2229 dev->base_addr = (unsigned long)fecp;
2230
2231 /* The FEC Ethernet specific entries in the device structure. */
2232 dev->open = fec_enet_open;
2233 dev->hard_start_xmit = fec_enet_start_xmit;
2234 dev->tx_timeout = fec_timeout;
2235 dev->watchdog_timeo = TX_TIMEOUT;
2236 dev->stop = fec_enet_close;
2237 dev->set_multicast_list = set_multicast_list;
2238
2239 for (i=0; i<NMII-1; i++)
2240 mii_cmds[i].mii_next = &mii_cmds[i+1];
2241 mii_free = mii_cmds;
2242
2243 /* setup MII interface */
2244 fec_set_mii(dev, fep);
2245
2246 /* Clear and enable interrupts */
2247 fecp->fec_ievent = 0xffc00000;
2248 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII);
2249
2250 /* Queue up command to detect the PHY and initialize the
2251 * remainder of the interface.
2252 */
2253 fep->phy_id_done = 0;
2254 fep->phy_addr = 0;
2255 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2256
2257 index++;
2258 return 0;
2259 }
2260
2261 /* This function is called to start or restart the FEC during a link
2262 * change. This only happens when switching between half and full
2263 * duplex.
2264 */
2265 static void
2266 fec_restart(struct net_device *dev, int duplex)
2267 {
2268 struct fec_enet_private *fep;
2269 volatile cbd_t *bdp;
2270 volatile fec_t *fecp;
2271 int i;
2272
2273 fep = netdev_priv(dev);
2274 fecp = fep->hwp;
2275
2276 /* Whack a reset. We should wait for this.
2277 */
2278 fecp->fec_ecntrl = 1;
2279 udelay(10);
2280
2281 /* Clear any outstanding interrupt.
2282 */
2283 fecp->fec_ievent = 0xffc00000;
2284
2285 /* Set station address.
2286 */
2287 fec_set_mac_address(dev);
2288
2289 /* Reset all multicast.
2290 */
2291 fecp->fec_grp_hash_table_high = 0;
2292 fecp->fec_grp_hash_table_low = 0;
2293
2294 /* Set maximum receive buffer size.
2295 */
2296 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2297
2298 /* Set receive and transmit descriptor base.
2299 */
2300 fecp->fec_r_des_start = fep->bd_dma;
2301 fecp->fec_x_des_start = (unsigned long)fep->bd_dma + sizeof(cbd_t)
2302 * RX_RING_SIZE;
2303
2304 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2305 fep->cur_rx = fep->rx_bd_base;
2306
2307 /* Reset SKB transmit buffers.
2308 */
2309 fep->skb_cur = fep->skb_dirty = 0;
2310 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2311 if (fep->tx_skbuff[i] != NULL) {
2312 dev_kfree_skb_any(fep->tx_skbuff[i]);
2313 fep->tx_skbuff[i] = NULL;
2314 }
2315 }
2316
2317 /* Initialize the receive buffer descriptors.
2318 */
2319 bdp = fep->rx_bd_base;
2320 for (i=0; i<RX_RING_SIZE; i++) {
2321
2322 /* Initialize the BD for every fragment in the page.
2323 */
2324 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2325 bdp++;
2326 }
2327
2328 /* Set the last buffer to wrap.
2329 */
2330 bdp--;
2331 bdp->cbd_sc |= BD_SC_WRAP;
2332
2333 /* ...and the same for transmmit.
2334 */
2335 bdp = fep->tx_bd_base;
2336 for (i=0; i<TX_RING_SIZE; i++) {
2337
2338 /* Initialize the BD for every fragment in the page.
2339 */
2340 bdp->cbd_sc = 0;
2341 bdp->cbd_bufaddr = 0;
2342 bdp++;
2343 }
2344
2345 /* Set the last buffer to wrap.
2346 */
2347 bdp--;
2348 bdp->cbd_sc |= BD_SC_WRAP;
2349
2350 /* Enable MII mode.
2351 */
2352 if (duplex) {
2353 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2354 fecp->fec_x_cntrl = 0x04; /* FD enable */
2355 } else {
2356 /* MII enable|No Rcv on Xmit */
2357 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2358 fecp->fec_x_cntrl = 0x00;
2359 }
2360 fep->full_duplex = duplex;
2361
2362 /* Set MII speed.
2363 */
2364 fecp->fec_mii_speed = fep->phy_speed;
2365
2366 /* And last, enable the transmit and receive processing.
2367 */
2368 fecp->fec_ecntrl = 2;
2369 fecp->fec_r_des_active = 0;
2370
2371 /* Enable interrupts we wish to service.
2372 */
2373 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII);
2374 }
2375
2376 static void
2377 fec_stop(struct net_device *dev)
2378 {
2379 volatile fec_t *fecp;
2380 struct fec_enet_private *fep;
2381
2382 fep = netdev_priv(dev);
2383 fecp = fep->hwp;
2384
2385 /*
2386 ** We cannot expect a graceful transmit stop without link !!!
2387 */
2388 if (fep->link)
2389 {
2390 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
2391 udelay(10);
2392 if (!(fecp->fec_ievent & FEC_ENET_GRA))
2393 printk("fec_stop : Graceful transmit stop did not complete !\n");
2394 }
2395
2396 /* Whack a reset. We should wait for this.
2397 */
2398 fecp->fec_ecntrl = 1;
2399 udelay(10);
2400
2401 /* Clear outstanding MII command interrupts.
2402 */
2403 fecp->fec_ievent = FEC_ENET_MII;
2404
2405 fecp->fec_imask = FEC_ENET_MII;
2406 fecp->fec_mii_speed = fep->phy_speed;
2407 }
2408
2409 static int __init fec_enet_module_init(void)
2410 {
2411 struct net_device *dev;
2412 int i, err;
2413
2414 printk("FEC ENET Version 0.2\n");
2415
2416 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2417 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2418 if (!dev)
2419 return -ENOMEM;
2420 err = fec_enet_init(dev);
2421 if (err) {
2422 free_netdev(dev);
2423 continue;
2424 }
2425 if (register_netdev(dev) != 0) {
2426 /* XXX: missing cleanup here */
2427 free_netdev(dev);
2428 return -EIO;
2429 }
2430
2431 printk("%s: ethernet %pM\n", dev->name, dev->dev_addr);
2432 }
2433 return 0;
2434 }
2435
2436 module_init(fec_enet_module_init);
2437
2438 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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