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fec: Fix KS8721BL_ICSR phy register offset
[deliverable/linux.git] / drivers / net / fec.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/workqueue.h>
38 #include <linux/bitops.h>
39 #include <linux/io.h>
40 #include <linux/irq.h>
41
42 #include <asm/cacheflush.h>
43 #include <asm/coldfire.h>
44 #include <asm/mcfsim.h>
45
46 #include "fec.h"
47
48 #if defined(CONFIG_FEC2)
49 #define FEC_MAX_PORTS 2
50 #else
51 #define FEC_MAX_PORTS 1
52 #endif
53
54 #if defined(CONFIG_M5272)
55 #define HAVE_mii_link_interrupt
56 #endif
57
58 /*
59 * Define the fixed address of the FEC hardware.
60 */
61 static unsigned int fec_hw[] = {
62 #if defined(CONFIG_M5272)
63 (MCF_MBAR + 0x840),
64 #elif defined(CONFIG_M527x)
65 (MCF_MBAR + 0x1000),
66 (MCF_MBAR + 0x1800),
67 #elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
68 (MCF_MBAR + 0x1000),
69 #elif defined(CONFIG_M520x)
70 (MCF_MBAR+0x30000),
71 #elif defined(CONFIG_M532x)
72 (MCF_MBAR+0xfc030000),
73 #endif
74 };
75
76 static unsigned char fec_mac_default[] = {
77 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
78 };
79
80 /*
81 * Some hardware gets it MAC address out of local flash memory.
82 * if this is non-zero then assume it is the address to get MAC from.
83 */
84 #if defined(CONFIG_NETtel)
85 #define FEC_FLASHMAC 0xf0006006
86 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
87 #define FEC_FLASHMAC 0xf0006000
88 #elif defined(CONFIG_CANCam)
89 #define FEC_FLASHMAC 0xf0020000
90 #elif defined (CONFIG_M5272C3)
91 #define FEC_FLASHMAC (0xffe04000 + 4)
92 #elif defined(CONFIG_MOD5272)
93 #define FEC_FLASHMAC 0xffc0406b
94 #else
95 #define FEC_FLASHMAC 0
96 #endif
97
98 /* Forward declarations of some structures to support different PHYs
99 */
100
101 typedef struct {
102 uint mii_data;
103 void (*funct)(uint mii_reg, struct net_device *dev);
104 } phy_cmd_t;
105
106 typedef struct {
107 uint id;
108 char *name;
109
110 const phy_cmd_t *config;
111 const phy_cmd_t *startup;
112 const phy_cmd_t *ack_int;
113 const phy_cmd_t *shutdown;
114 } phy_info_t;
115
116 /* The number of Tx and Rx buffers. These are allocated from the page
117 * pool. The code may assume these are power of two, so it it best
118 * to keep them that size.
119 * We don't need to allocate pages for the transmitter. We just use
120 * the skbuffer directly.
121 */
122 #define FEC_ENET_RX_PAGES 8
123 #define FEC_ENET_RX_FRSIZE 2048
124 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
125 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
126 #define FEC_ENET_TX_FRSIZE 2048
127 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
128 #define TX_RING_SIZE 16 /* Must be power of two */
129 #define TX_RING_MOD_MASK 15 /* for this to work */
130
131 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
132 #error "FEC: descriptor ring size constants too large"
133 #endif
134
135 /* Interrupt events/masks.
136 */
137 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
138 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
139 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
140 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
141 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
142 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
143 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
144 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
145 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
146 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
147
148 /* The FEC stores dest/src/type, data, and checksum for receive packets.
149 */
150 #define PKT_MAXBUF_SIZE 1518
151 #define PKT_MINBUF_SIZE 64
152 #define PKT_MAXBLR_SIZE 1520
153
154
155 /*
156 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
157 * size bits. Other FEC hardware does not, so we need to take that into
158 * account when setting it.
159 */
160 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
161 defined(CONFIG_M520x) || defined(CONFIG_M532x)
162 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
163 #else
164 #define OPT_FRAME_SIZE 0
165 #endif
166
167 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
168 * tx_bd_base always point to the base of the buffer descriptors. The
169 * cur_rx and cur_tx point to the currently available buffer.
170 * The dirty_tx tracks the current buffer that is being sent by the
171 * controller. The cur_tx and dirty_tx are equal under both completely
172 * empty and completely full conditions. The empty/ready indicator in
173 * the buffer descriptor determines the actual condition.
174 */
175 struct fec_enet_private {
176 /* Hardware registers of the FEC device */
177 volatile fec_t *hwp;
178
179 struct net_device *netdev;
180
181 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
182 unsigned char *tx_bounce[TX_RING_SIZE];
183 struct sk_buff* tx_skbuff[TX_RING_SIZE];
184 ushort skb_cur;
185 ushort skb_dirty;
186
187 /* CPM dual port RAM relative addresses.
188 */
189 dma_addr_t bd_dma;
190 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
191 cbd_t *tx_bd_base;
192 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
193 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
194 uint tx_full;
195 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
196 spinlock_t hw_lock;
197 /* hold while accessing the mii_list_t() elements */
198 spinlock_t mii_lock;
199
200 uint phy_id;
201 uint phy_id_done;
202 uint phy_status;
203 uint phy_speed;
204 phy_info_t const *phy;
205 struct work_struct phy_task;
206
207 uint sequence_done;
208 uint mii_phy_task_queued;
209
210 uint phy_addr;
211
212 int index;
213 int opened;
214 int link;
215 int old_link;
216 int full_duplex;
217 };
218
219 static int fec_enet_open(struct net_device *dev);
220 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
221 static void fec_enet_mii(struct net_device *dev);
222 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
223 static void fec_enet_tx(struct net_device *dev);
224 static void fec_enet_rx(struct net_device *dev);
225 static int fec_enet_close(struct net_device *dev);
226 static void set_multicast_list(struct net_device *dev);
227 static void fec_restart(struct net_device *dev, int duplex);
228 static void fec_stop(struct net_device *dev);
229 static void fec_set_mac_address(struct net_device *dev);
230
231
232 /* MII processing. We keep this as simple as possible. Requests are
233 * placed on the list (if there is room). When the request is finished
234 * by the MII, an optional function may be called.
235 */
236 typedef struct mii_list {
237 uint mii_regval;
238 void (*mii_func)(uint val, struct net_device *dev);
239 struct mii_list *mii_next;
240 } mii_list_t;
241
242 #define NMII 20
243 static mii_list_t mii_cmds[NMII];
244 static mii_list_t *mii_free;
245 static mii_list_t *mii_head;
246 static mii_list_t *mii_tail;
247
248 static int mii_queue(struct net_device *dev, int request,
249 void (*func)(uint, struct net_device *));
250
251 /* Make MII read/write commands for the FEC.
252 */
253 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
254 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
255 (VAL & 0xffff))
256 #define mk_mii_end 0
257
258 /* Transmitter timeout.
259 */
260 #define TX_TIMEOUT (2*HZ)
261
262 /* Register definitions for the PHY.
263 */
264
265 #define MII_REG_CR 0 /* Control Register */
266 #define MII_REG_SR 1 /* Status Register */
267 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
268 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
269 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
270 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
271 #define MII_REG_ANER 6 /* A-N Expansion Register */
272 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
273 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
274
275 /* values for phy_status */
276
277 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
278 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
279 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
280 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
281 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
282 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
283 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
284
285 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
286 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
287 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
288 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
289 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
290 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
291 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
292 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
293
294
295 static int
296 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
297 {
298 struct fec_enet_private *fep;
299 volatile fec_t *fecp;
300 volatile cbd_t *bdp;
301 unsigned short status;
302 unsigned long flags;
303
304 fep = netdev_priv(dev);
305 fecp = (volatile fec_t*)dev->base_addr;
306
307 if (!fep->link) {
308 /* Link is down or autonegotiation is in progress. */
309 return 1;
310 }
311
312 spin_lock_irqsave(&fep->hw_lock, flags);
313 /* Fill in a Tx ring entry */
314 bdp = fep->cur_tx;
315
316 status = bdp->cbd_sc;
317 #ifndef final_version
318 if (status & BD_ENET_TX_READY) {
319 /* Ooops. All transmit buffers are full. Bail out.
320 * This should not happen, since dev->tbusy should be set.
321 */
322 printk("%s: tx queue full!.\n", dev->name);
323 spin_unlock_irqrestore(&fep->hw_lock, flags);
324 return 1;
325 }
326 #endif
327
328 /* Clear all of the status flags.
329 */
330 status &= ~BD_ENET_TX_STATS;
331
332 /* Set buffer length and buffer pointer.
333 */
334 bdp->cbd_bufaddr = __pa(skb->data);
335 bdp->cbd_datlen = skb->len;
336
337 /*
338 * On some FEC implementations data must be aligned on
339 * 4-byte boundaries. Use bounce buffers to copy data
340 * and get it aligned. Ugh.
341 */
342 if (bdp->cbd_bufaddr & 0x3) {
343 unsigned int index;
344 index = bdp - fep->tx_bd_base;
345 memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len);
346 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
347 }
348
349 /* Save skb pointer.
350 */
351 fep->tx_skbuff[fep->skb_cur] = skb;
352
353 dev->stats.tx_bytes += skb->len;
354 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
355
356 /* Push the data cache so the CPM does not get stale memory
357 * data.
358 */
359 flush_dcache_range((unsigned long)skb->data,
360 (unsigned long)skb->data + skb->len);
361
362 /* Send it on its way. Tell FEC it's ready, interrupt when done,
363 * it's the last BD of the frame, and to put the CRC on the end.
364 */
365
366 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
367 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
368 bdp->cbd_sc = status;
369
370 dev->trans_start = jiffies;
371
372 /* Trigger transmission start */
373 fecp->fec_x_des_active = 0;
374
375 /* If this was the last BD in the ring, start at the beginning again.
376 */
377 if (status & BD_ENET_TX_WRAP) {
378 bdp = fep->tx_bd_base;
379 } else {
380 bdp++;
381 }
382
383 if (bdp == fep->dirty_tx) {
384 fep->tx_full = 1;
385 netif_stop_queue(dev);
386 }
387
388 fep->cur_tx = (cbd_t *)bdp;
389
390 spin_unlock_irqrestore(&fep->hw_lock, flags);
391
392 return 0;
393 }
394
395 static void
396 fec_timeout(struct net_device *dev)
397 {
398 struct fec_enet_private *fep = netdev_priv(dev);
399
400 printk("%s: transmit timed out.\n", dev->name);
401 dev->stats.tx_errors++;
402 #ifndef final_version
403 {
404 int i;
405 cbd_t *bdp;
406
407 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
408 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
409 (unsigned long)fep->dirty_tx,
410 (unsigned long)fep->cur_rx);
411
412 bdp = fep->tx_bd_base;
413 printk(" tx: %u buffers\n", TX_RING_SIZE);
414 for (i = 0 ; i < TX_RING_SIZE; i++) {
415 printk(" %08x: %04x %04x %08x\n",
416 (uint) bdp,
417 bdp->cbd_sc,
418 bdp->cbd_datlen,
419 (int) bdp->cbd_bufaddr);
420 bdp++;
421 }
422
423 bdp = fep->rx_bd_base;
424 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
425 for (i = 0 ; i < RX_RING_SIZE; i++) {
426 printk(" %08x: %04x %04x %08x\n",
427 (uint) bdp,
428 bdp->cbd_sc,
429 bdp->cbd_datlen,
430 (int) bdp->cbd_bufaddr);
431 bdp++;
432 }
433 }
434 #endif
435 fec_restart(dev, fep->full_duplex);
436 netif_wake_queue(dev);
437 }
438
439 /* The interrupt handler.
440 * This is called from the MPC core interrupt.
441 */
442 static irqreturn_t
443 fec_enet_interrupt(int irq, void * dev_id)
444 {
445 struct net_device *dev = dev_id;
446 volatile fec_t *fecp;
447 uint int_events;
448 irqreturn_t ret = IRQ_NONE;
449
450 fecp = (volatile fec_t*)dev->base_addr;
451
452 /* Get the interrupt events that caused us to be here.
453 */
454 do {
455 int_events = fecp->fec_ievent;
456 fecp->fec_ievent = int_events;
457
458 /* Handle receive event in its own function.
459 */
460 if (int_events & FEC_ENET_RXF) {
461 ret = IRQ_HANDLED;
462 fec_enet_rx(dev);
463 }
464
465 /* Transmit OK, or non-fatal error. Update the buffer
466 descriptors. FEC handles all errors, we just discover
467 them as part of the transmit process.
468 */
469 if (int_events & FEC_ENET_TXF) {
470 ret = IRQ_HANDLED;
471 fec_enet_tx(dev);
472 }
473
474 if (int_events & FEC_ENET_MII) {
475 ret = IRQ_HANDLED;
476 fec_enet_mii(dev);
477 }
478
479 } while (int_events);
480
481 return ret;
482 }
483
484
485 static void
486 fec_enet_tx(struct net_device *dev)
487 {
488 struct fec_enet_private *fep;
489 volatile cbd_t *bdp;
490 unsigned short status;
491 struct sk_buff *skb;
492
493 fep = netdev_priv(dev);
494 spin_lock_irq(&fep->hw_lock);
495 bdp = fep->dirty_tx;
496
497 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
498 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
499
500 skb = fep->tx_skbuff[fep->skb_dirty];
501 /* Check for errors. */
502 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
503 BD_ENET_TX_RL | BD_ENET_TX_UN |
504 BD_ENET_TX_CSL)) {
505 dev->stats.tx_errors++;
506 if (status & BD_ENET_TX_HB) /* No heartbeat */
507 dev->stats.tx_heartbeat_errors++;
508 if (status & BD_ENET_TX_LC) /* Late collision */
509 dev->stats.tx_window_errors++;
510 if (status & BD_ENET_TX_RL) /* Retrans limit */
511 dev->stats.tx_aborted_errors++;
512 if (status & BD_ENET_TX_UN) /* Underrun */
513 dev->stats.tx_fifo_errors++;
514 if (status & BD_ENET_TX_CSL) /* Carrier lost */
515 dev->stats.tx_carrier_errors++;
516 } else {
517 dev->stats.tx_packets++;
518 }
519
520 #ifndef final_version
521 if (status & BD_ENET_TX_READY)
522 printk("HEY! Enet xmit interrupt and TX_READY.\n");
523 #endif
524 /* Deferred means some collisions occurred during transmit,
525 * but we eventually sent the packet OK.
526 */
527 if (status & BD_ENET_TX_DEF)
528 dev->stats.collisions++;
529
530 /* Free the sk buffer associated with this last transmit.
531 */
532 dev_kfree_skb_any(skb);
533 fep->tx_skbuff[fep->skb_dirty] = NULL;
534 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
535
536 /* Update pointer to next buffer descriptor to be transmitted.
537 */
538 if (status & BD_ENET_TX_WRAP)
539 bdp = fep->tx_bd_base;
540 else
541 bdp++;
542
543 /* Since we have freed up a buffer, the ring is no longer
544 * full.
545 */
546 if (fep->tx_full) {
547 fep->tx_full = 0;
548 if (netif_queue_stopped(dev))
549 netif_wake_queue(dev);
550 }
551 }
552 fep->dirty_tx = (cbd_t *)bdp;
553 spin_unlock_irq(&fep->hw_lock);
554 }
555
556
557 /* During a receive, the cur_rx points to the current incoming buffer.
558 * When we update through the ring, if the next incoming buffer has
559 * not been given to the system, we just set the empty indicator,
560 * effectively tossing the packet.
561 */
562 static void
563 fec_enet_rx(struct net_device *dev)
564 {
565 struct fec_enet_private *fep;
566 volatile fec_t *fecp;
567 volatile cbd_t *bdp;
568 unsigned short status;
569 struct sk_buff *skb;
570 ushort pkt_len;
571 __u8 *data;
572
573 #ifdef CONFIG_M532x
574 flush_cache_all();
575 #endif
576
577 fep = netdev_priv(dev);
578 fecp = (volatile fec_t*)dev->base_addr;
579
580 spin_lock_irq(&fep->hw_lock);
581
582 /* First, grab all of the stats for the incoming packet.
583 * These get messed up if we get called due to a busy condition.
584 */
585 bdp = fep->cur_rx;
586
587 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
588
589 #ifndef final_version
590 /* Since we have allocated space to hold a complete frame,
591 * the last indicator should be set.
592 */
593 if ((status & BD_ENET_RX_LAST) == 0)
594 printk("FEC ENET: rcv is not +last\n");
595 #endif
596
597 if (!fep->opened)
598 goto rx_processing_done;
599
600 /* Check for errors. */
601 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
602 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
603 dev->stats.rx_errors++;
604 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
605 /* Frame too long or too short. */
606 dev->stats.rx_length_errors++;
607 }
608 if (status & BD_ENET_RX_NO) /* Frame alignment */
609 dev->stats.rx_frame_errors++;
610 if (status & BD_ENET_RX_CR) /* CRC Error */
611 dev->stats.rx_crc_errors++;
612 if (status & BD_ENET_RX_OV) /* FIFO overrun */
613 dev->stats.rx_fifo_errors++;
614 }
615
616 /* Report late collisions as a frame error.
617 * On this error, the BD is closed, but we don't know what we
618 * have in the buffer. So, just drop this frame on the floor.
619 */
620 if (status & BD_ENET_RX_CL) {
621 dev->stats.rx_errors++;
622 dev->stats.rx_frame_errors++;
623 goto rx_processing_done;
624 }
625
626 /* Process the incoming frame.
627 */
628 dev->stats.rx_packets++;
629 pkt_len = bdp->cbd_datlen;
630 dev->stats.rx_bytes += pkt_len;
631 data = (__u8*)__va(bdp->cbd_bufaddr);
632
633 /* This does 16 byte alignment, exactly what we need.
634 * The packet length includes FCS, but we don't want to
635 * include that when passing upstream as it messes up
636 * bridging applications.
637 */
638 skb = dev_alloc_skb(pkt_len-4);
639
640 if (skb == NULL) {
641 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
642 dev->stats.rx_dropped++;
643 } else {
644 skb_put(skb,pkt_len-4); /* Make room */
645 skb_copy_to_linear_data(skb, data, pkt_len-4);
646 skb->protocol=eth_type_trans(skb,dev);
647 netif_rx(skb);
648 }
649 rx_processing_done:
650
651 /* Clear the status flags for this buffer.
652 */
653 status &= ~BD_ENET_RX_STATS;
654
655 /* Mark the buffer empty.
656 */
657 status |= BD_ENET_RX_EMPTY;
658 bdp->cbd_sc = status;
659
660 /* Update BD pointer to next entry.
661 */
662 if (status & BD_ENET_RX_WRAP)
663 bdp = fep->rx_bd_base;
664 else
665 bdp++;
666
667 #if 1
668 /* Doing this here will keep the FEC running while we process
669 * incoming frames. On a heavily loaded network, we should be
670 * able to keep up at the expense of system resources.
671 */
672 fecp->fec_r_des_active = 0;
673 #endif
674 } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
675 fep->cur_rx = (cbd_t *)bdp;
676
677 #if 0
678 /* Doing this here will allow us to process all frames in the
679 * ring before the FEC is allowed to put more there. On a heavily
680 * loaded network, some frames may be lost. Unfortunately, this
681 * increases the interrupt overhead since we can potentially work
682 * our way back to the interrupt return only to come right back
683 * here.
684 */
685 fecp->fec_r_des_active = 0;
686 #endif
687
688 spin_unlock_irq(&fep->hw_lock);
689 }
690
691
692 /* called from interrupt context */
693 static void
694 fec_enet_mii(struct net_device *dev)
695 {
696 struct fec_enet_private *fep;
697 volatile fec_t *ep;
698 mii_list_t *mip;
699 uint mii_reg;
700
701 fep = netdev_priv(dev);
702 spin_lock_irq(&fep->mii_lock);
703
704 ep = fep->hwp;
705 mii_reg = ep->fec_mii_data;
706
707 if ((mip = mii_head) == NULL) {
708 printk("MII and no head!\n");
709 goto unlock;
710 }
711
712 if (mip->mii_func != NULL)
713 (*(mip->mii_func))(mii_reg, dev);
714
715 mii_head = mip->mii_next;
716 mip->mii_next = mii_free;
717 mii_free = mip;
718
719 if ((mip = mii_head) != NULL)
720 ep->fec_mii_data = mip->mii_regval;
721
722 unlock:
723 spin_unlock_irq(&fep->mii_lock);
724 }
725
726 static int
727 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
728 {
729 struct fec_enet_private *fep;
730 unsigned long flags;
731 mii_list_t *mip;
732 int retval;
733
734 /* Add PHY address to register command.
735 */
736 fep = netdev_priv(dev);
737 spin_lock_irqsave(&fep->mii_lock, flags);
738
739 regval |= fep->phy_addr << 23;
740 retval = 0;
741
742 if ((mip = mii_free) != NULL) {
743 mii_free = mip->mii_next;
744 mip->mii_regval = regval;
745 mip->mii_func = func;
746 mip->mii_next = NULL;
747 if (mii_head) {
748 mii_tail->mii_next = mip;
749 mii_tail = mip;
750 } else {
751 mii_head = mii_tail = mip;
752 fep->hwp->fec_mii_data = regval;
753 }
754 } else {
755 retval = 1;
756 }
757
758 spin_unlock_irqrestore(&fep->mii_lock, flags);
759 return retval;
760 }
761
762 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
763 {
764 if(!c)
765 return;
766
767 for (; c->mii_data != mk_mii_end; c++)
768 mii_queue(dev, c->mii_data, c->funct);
769 }
770
771 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
772 {
773 struct fec_enet_private *fep = netdev_priv(dev);
774 volatile uint *s = &(fep->phy_status);
775 uint status;
776
777 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
778
779 if (mii_reg & 0x0004)
780 status |= PHY_STAT_LINK;
781 if (mii_reg & 0x0010)
782 status |= PHY_STAT_FAULT;
783 if (mii_reg & 0x0020)
784 status |= PHY_STAT_ANC;
785 *s = status;
786 }
787
788 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
789 {
790 struct fec_enet_private *fep = netdev_priv(dev);
791 volatile uint *s = &(fep->phy_status);
792 uint status;
793
794 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
795
796 if (mii_reg & 0x1000)
797 status |= PHY_CONF_ANE;
798 if (mii_reg & 0x4000)
799 status |= PHY_CONF_LOOP;
800 *s = status;
801 }
802
803 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
804 {
805 struct fec_enet_private *fep = netdev_priv(dev);
806 volatile uint *s = &(fep->phy_status);
807 uint status;
808
809 status = *s & ~(PHY_CONF_SPMASK);
810
811 if (mii_reg & 0x0020)
812 status |= PHY_CONF_10HDX;
813 if (mii_reg & 0x0040)
814 status |= PHY_CONF_10FDX;
815 if (mii_reg & 0x0080)
816 status |= PHY_CONF_100HDX;
817 if (mii_reg & 0x00100)
818 status |= PHY_CONF_100FDX;
819 *s = status;
820 }
821
822 /* ------------------------------------------------------------------------- */
823 /* The Level one LXT970 is used by many boards */
824
825 #define MII_LXT970_MIRROR 16 /* Mirror register */
826 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
827 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
828 #define MII_LXT970_CONFIG 19 /* Configuration Register */
829 #define MII_LXT970_CSR 20 /* Chip Status Register */
830
831 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
832 {
833 struct fec_enet_private *fep = netdev_priv(dev);
834 volatile uint *s = &(fep->phy_status);
835 uint status;
836
837 status = *s & ~(PHY_STAT_SPMASK);
838 if (mii_reg & 0x0800) {
839 if (mii_reg & 0x1000)
840 status |= PHY_STAT_100FDX;
841 else
842 status |= PHY_STAT_100HDX;
843 } else {
844 if (mii_reg & 0x1000)
845 status |= PHY_STAT_10FDX;
846 else
847 status |= PHY_STAT_10HDX;
848 }
849 *s = status;
850 }
851
852 static phy_cmd_t const phy_cmd_lxt970_config[] = {
853 { mk_mii_read(MII_REG_CR), mii_parse_cr },
854 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
855 { mk_mii_end, }
856 };
857 static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
858 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
859 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
860 { mk_mii_end, }
861 };
862 static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
863 /* read SR and ISR to acknowledge */
864 { mk_mii_read(MII_REG_SR), mii_parse_sr },
865 { mk_mii_read(MII_LXT970_ISR), NULL },
866
867 /* find out the current status */
868 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
869 { mk_mii_end, }
870 };
871 static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
872 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
873 { mk_mii_end, }
874 };
875 static phy_info_t const phy_info_lxt970 = {
876 .id = 0x07810000,
877 .name = "LXT970",
878 .config = phy_cmd_lxt970_config,
879 .startup = phy_cmd_lxt970_startup,
880 .ack_int = phy_cmd_lxt970_ack_int,
881 .shutdown = phy_cmd_lxt970_shutdown
882 };
883
884 /* ------------------------------------------------------------------------- */
885 /* The Level one LXT971 is used on some of my custom boards */
886
887 /* register definitions for the 971 */
888
889 #define MII_LXT971_PCR 16 /* Port Control Register */
890 #define MII_LXT971_SR2 17 /* Status Register 2 */
891 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
892 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
893 #define MII_LXT971_LCR 20 /* LED Control Register */
894 #define MII_LXT971_TCR 30 /* Transmit Control Register */
895
896 /*
897 * I had some nice ideas of running the MDIO faster...
898 * The 971 should support 8MHz and I tried it, but things acted really
899 * weird, so 2.5 MHz ought to be enough for anyone...
900 */
901
902 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
903 {
904 struct fec_enet_private *fep = netdev_priv(dev);
905 volatile uint *s = &(fep->phy_status);
906 uint status;
907
908 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
909
910 if (mii_reg & 0x0400) {
911 fep->link = 1;
912 status |= PHY_STAT_LINK;
913 } else {
914 fep->link = 0;
915 }
916 if (mii_reg & 0x0080)
917 status |= PHY_STAT_ANC;
918 if (mii_reg & 0x4000) {
919 if (mii_reg & 0x0200)
920 status |= PHY_STAT_100FDX;
921 else
922 status |= PHY_STAT_100HDX;
923 } else {
924 if (mii_reg & 0x0200)
925 status |= PHY_STAT_10FDX;
926 else
927 status |= PHY_STAT_10HDX;
928 }
929 if (mii_reg & 0x0008)
930 status |= PHY_STAT_FAULT;
931
932 *s = status;
933 }
934
935 static phy_cmd_t const phy_cmd_lxt971_config[] = {
936 /* limit to 10MBit because my prototype board
937 * doesn't work with 100. */
938 { mk_mii_read(MII_REG_CR), mii_parse_cr },
939 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
940 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
941 { mk_mii_end, }
942 };
943 static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
944 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
945 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
946 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
947 /* Somehow does the 971 tell me that the link is down
948 * the first read after power-up.
949 * read here to get a valid value in ack_int */
950 { mk_mii_read(MII_REG_SR), mii_parse_sr },
951 { mk_mii_end, }
952 };
953 static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
954 /* acknowledge the int before reading status ! */
955 { mk_mii_read(MII_LXT971_ISR), NULL },
956 /* find out the current status */
957 { mk_mii_read(MII_REG_SR), mii_parse_sr },
958 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
959 { mk_mii_end, }
960 };
961 static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
962 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
963 { mk_mii_end, }
964 };
965 static phy_info_t const phy_info_lxt971 = {
966 .id = 0x0001378e,
967 .name = "LXT971",
968 .config = phy_cmd_lxt971_config,
969 .startup = phy_cmd_lxt971_startup,
970 .ack_int = phy_cmd_lxt971_ack_int,
971 .shutdown = phy_cmd_lxt971_shutdown
972 };
973
974 /* ------------------------------------------------------------------------- */
975 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
976
977 /* register definitions */
978
979 #define MII_QS6612_MCR 17 /* Mode Control Register */
980 #define MII_QS6612_FTR 27 /* Factory Test Register */
981 #define MII_QS6612_MCO 28 /* Misc. Control Register */
982 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
983 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
984 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
985
986 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
987 {
988 struct fec_enet_private *fep = netdev_priv(dev);
989 volatile uint *s = &(fep->phy_status);
990 uint status;
991
992 status = *s & ~(PHY_STAT_SPMASK);
993
994 switch((mii_reg >> 2) & 7) {
995 case 1: status |= PHY_STAT_10HDX; break;
996 case 2: status |= PHY_STAT_100HDX; break;
997 case 5: status |= PHY_STAT_10FDX; break;
998 case 6: status |= PHY_STAT_100FDX; break;
999 }
1000
1001 *s = status;
1002 }
1003
1004 static phy_cmd_t const phy_cmd_qs6612_config[] = {
1005 /* The PHY powers up isolated on the RPX,
1006 * so send a command to allow operation.
1007 */
1008 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1009
1010 /* parse cr and anar to get some info */
1011 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1012 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1013 { mk_mii_end, }
1014 };
1015 static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
1016 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1017 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1018 { mk_mii_end, }
1019 };
1020 static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
1021 /* we need to read ISR, SR and ANER to acknowledge */
1022 { mk_mii_read(MII_QS6612_ISR), NULL },
1023 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1024 { mk_mii_read(MII_REG_ANER), NULL },
1025
1026 /* read pcr to get info */
1027 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1028 { mk_mii_end, }
1029 };
1030 static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
1031 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1032 { mk_mii_end, }
1033 };
1034 static phy_info_t const phy_info_qs6612 = {
1035 .id = 0x00181440,
1036 .name = "QS6612",
1037 .config = phy_cmd_qs6612_config,
1038 .startup = phy_cmd_qs6612_startup,
1039 .ack_int = phy_cmd_qs6612_ack_int,
1040 .shutdown = phy_cmd_qs6612_shutdown
1041 };
1042
1043 /* ------------------------------------------------------------------------- */
1044 /* AMD AM79C874 phy */
1045
1046 /* register definitions for the 874 */
1047
1048 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1049 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1050 #define MII_AM79C874_DR 18 /* Diagnostic Register */
1051 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1052 #define MII_AM79C874_MCR 21 /* ModeControl Register */
1053 #define MII_AM79C874_DC 23 /* Disconnect Counter */
1054 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
1055
1056 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1057 {
1058 struct fec_enet_private *fep = netdev_priv(dev);
1059 volatile uint *s = &(fep->phy_status);
1060 uint status;
1061
1062 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
1063
1064 if (mii_reg & 0x0080)
1065 status |= PHY_STAT_ANC;
1066 if (mii_reg & 0x0400)
1067 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
1068 else
1069 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1070
1071 *s = status;
1072 }
1073
1074 static phy_cmd_t const phy_cmd_am79c874_config[] = {
1075 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1076 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1077 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1078 { mk_mii_end, }
1079 };
1080 static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
1081 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1082 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1083 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1084 { mk_mii_end, }
1085 };
1086 static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
1087 /* find out the current status */
1088 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1089 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1090 /* we only need to read ISR to acknowledge */
1091 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1092 { mk_mii_end, }
1093 };
1094 static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
1095 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1096 { mk_mii_end, }
1097 };
1098 static phy_info_t const phy_info_am79c874 = {
1099 .id = 0x00022561,
1100 .name = "AM79C874",
1101 .config = phy_cmd_am79c874_config,
1102 .startup = phy_cmd_am79c874_startup,
1103 .ack_int = phy_cmd_am79c874_ack_int,
1104 .shutdown = phy_cmd_am79c874_shutdown
1105 };
1106
1107
1108 /* ------------------------------------------------------------------------- */
1109 /* Kendin KS8721BL phy */
1110
1111 /* register definitions for the 8721 */
1112
1113 #define MII_KS8721BL_RXERCR 21
1114 #define MII_KS8721BL_ICSR 27
1115 #define MII_KS8721BL_PHYCR 31
1116
1117 static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1118 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1119 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1120 { mk_mii_end, }
1121 };
1122 static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1123 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1124 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1125 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1126 { mk_mii_end, }
1127 };
1128 static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1129 /* find out the current status */
1130 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1131 /* we only need to read ISR to acknowledge */
1132 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1133 { mk_mii_end, }
1134 };
1135 static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
1136 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1137 { mk_mii_end, }
1138 };
1139 static phy_info_t const phy_info_ks8721bl = {
1140 .id = 0x00022161,
1141 .name = "KS8721BL",
1142 .config = phy_cmd_ks8721bl_config,
1143 .startup = phy_cmd_ks8721bl_startup,
1144 .ack_int = phy_cmd_ks8721bl_ack_int,
1145 .shutdown = phy_cmd_ks8721bl_shutdown
1146 };
1147
1148 /* ------------------------------------------------------------------------- */
1149 /* register definitions for the DP83848 */
1150
1151 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1152
1153 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1154 {
1155 struct fec_enet_private *fep = netdev_priv(dev);
1156 volatile uint *s = &(fep->phy_status);
1157
1158 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1159
1160 /* Link up */
1161 if (mii_reg & 0x0001) {
1162 fep->link = 1;
1163 *s |= PHY_STAT_LINK;
1164 } else
1165 fep->link = 0;
1166 /* Status of link */
1167 if (mii_reg & 0x0010) /* Autonegotioation complete */
1168 *s |= PHY_STAT_ANC;
1169 if (mii_reg & 0x0002) { /* 10MBps? */
1170 if (mii_reg & 0x0004) /* Full Duplex? */
1171 *s |= PHY_STAT_10FDX;
1172 else
1173 *s |= PHY_STAT_10HDX;
1174 } else { /* 100 Mbps? */
1175 if (mii_reg & 0x0004) /* Full Duplex? */
1176 *s |= PHY_STAT_100FDX;
1177 else
1178 *s |= PHY_STAT_100HDX;
1179 }
1180 if (mii_reg & 0x0008)
1181 *s |= PHY_STAT_FAULT;
1182 }
1183
1184 static phy_info_t phy_info_dp83848= {
1185 0x020005c9,
1186 "DP83848",
1187
1188 (const phy_cmd_t []) { /* config */
1189 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1190 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1191 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1192 { mk_mii_end, }
1193 },
1194 (const phy_cmd_t []) { /* startup - enable interrupts */
1195 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1196 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1197 { mk_mii_end, }
1198 },
1199 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1200 { mk_mii_end, }
1201 },
1202 (const phy_cmd_t []) { /* shutdown */
1203 { mk_mii_end, }
1204 },
1205 };
1206
1207 /* ------------------------------------------------------------------------- */
1208
1209 static phy_info_t const * const phy_info[] = {
1210 &phy_info_lxt970,
1211 &phy_info_lxt971,
1212 &phy_info_qs6612,
1213 &phy_info_am79c874,
1214 &phy_info_ks8721bl,
1215 &phy_info_dp83848,
1216 NULL
1217 };
1218
1219 /* ------------------------------------------------------------------------- */
1220 #ifdef HAVE_mii_link_interrupt
1221 static irqreturn_t
1222 mii_link_interrupt(int irq, void * dev_id);
1223 #endif
1224
1225 #if defined(CONFIG_M5272)
1226 /*
1227 * Code specific to Coldfire 5272 setup.
1228 */
1229 static void __inline__ fec_request_intrs(struct net_device *dev)
1230 {
1231 volatile unsigned long *icrp;
1232 static const struct idesc {
1233 char *name;
1234 unsigned short irq;
1235 irq_handler_t handler;
1236 } *idp, id[] = {
1237 { "fec(RX)", 86, fec_enet_interrupt },
1238 { "fec(TX)", 87, fec_enet_interrupt },
1239 { "fec(OTHER)", 88, fec_enet_interrupt },
1240 { "fec(MII)", 66, mii_link_interrupt },
1241 { NULL },
1242 };
1243
1244 /* Setup interrupt handlers. */
1245 for (idp = id; idp->name; idp++) {
1246 if (request_irq(idp->irq, idp->handler, IRQF_DISABLED, idp->name, dev) != 0)
1247 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1248 }
1249
1250 /* Unmask interrupt at ColdFire 5272 SIM */
1251 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1252 *icrp = 0x00000ddd;
1253 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1254 *icrp = 0x0d000000;
1255 }
1256
1257 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1258 {
1259 volatile fec_t *fecp;
1260
1261 fecp = fep->hwp;
1262 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1263 fecp->fec_x_cntrl = 0x00;
1264
1265 /*
1266 * Set MII speed to 2.5 MHz
1267 * See 5272 manual section 11.5.8: MSCR
1268 */
1269 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1270 fecp->fec_mii_speed = fep->phy_speed;
1271
1272 fec_restart(dev, 0);
1273 }
1274
1275 static void __inline__ fec_get_mac(struct net_device *dev)
1276 {
1277 struct fec_enet_private *fep = netdev_priv(dev);
1278 volatile fec_t *fecp;
1279 unsigned char *iap, tmpaddr[ETH_ALEN];
1280
1281 fecp = fep->hwp;
1282
1283 if (FEC_FLASHMAC) {
1284 /*
1285 * Get MAC address from FLASH.
1286 * If it is all 1's or 0's, use the default.
1287 */
1288 iap = (unsigned char *)FEC_FLASHMAC;
1289 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1290 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1291 iap = fec_mac_default;
1292 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1293 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1294 iap = fec_mac_default;
1295 } else {
1296 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1297 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1298 iap = &tmpaddr[0];
1299 }
1300
1301 memcpy(dev->dev_addr, iap, ETH_ALEN);
1302
1303 /* Adjust MAC if using default MAC address */
1304 if (iap == fec_mac_default)
1305 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1306 }
1307
1308 static void __inline__ fec_disable_phy_intr(void)
1309 {
1310 volatile unsigned long *icrp;
1311 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1312 *icrp = 0x08000000;
1313 }
1314
1315 static void __inline__ fec_phy_ack_intr(void)
1316 {
1317 volatile unsigned long *icrp;
1318 /* Acknowledge the interrupt */
1319 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1320 *icrp = 0x0d000000;
1321 }
1322
1323 /* ------------------------------------------------------------------------- */
1324
1325 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
1326
1327 /*
1328 * Code specific to Coldfire 5230/5231/5232/5234/5235,
1329 * the 5270/5271/5274/5275 and 5280/5282 setups.
1330 */
1331 static void __inline__ fec_request_intrs(struct net_device *dev)
1332 {
1333 struct fec_enet_private *fep;
1334 int b;
1335 static const struct idesc {
1336 char *name;
1337 unsigned short irq;
1338 } *idp, id[] = {
1339 { "fec(TXF)", 23 },
1340 { "fec(RXF)", 27 },
1341 { "fec(MII)", 29 },
1342 { NULL },
1343 };
1344
1345 fep = netdev_priv(dev);
1346 b = (fep->index) ? 128 : 64;
1347
1348 /* Setup interrupt handlers. */
1349 for (idp = id; idp->name; idp++) {
1350 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name, dev) != 0)
1351 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1352 }
1353
1354 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1355 {
1356 volatile unsigned char *icrp;
1357 volatile unsigned long *imrp;
1358 int i, ilip;
1359
1360 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1361 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1362 MCFINTC_ICR0);
1363 for (i = 23, ilip = 0x28; (i < 36); i++)
1364 icrp[i] = ilip--;
1365
1366 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1367 MCFINTC_IMRH);
1368 *imrp &= ~0x0000000f;
1369 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1370 MCFINTC_IMRL);
1371 *imrp &= ~0xff800001;
1372 }
1373
1374 #if defined(CONFIG_M528x)
1375 /* Set up gpio outputs for MII lines */
1376 {
1377 volatile u16 *gpio_paspar;
1378 volatile u8 *gpio_pehlpar;
1379
1380 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1381 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
1382 *gpio_paspar |= 0x0f00;
1383 *gpio_pehlpar = 0xc0;
1384 }
1385 #endif
1386
1387 #if defined(CONFIG_M527x)
1388 /* Set up gpio outputs for MII lines */
1389 {
1390 volatile u8 *gpio_par_fec;
1391 volatile u16 *gpio_par_feci2c;
1392
1393 gpio_par_feci2c = (volatile u16 *)(MCF_IPSBAR + 0x100082);
1394 /* Set up gpio outputs for FEC0 MII lines */
1395 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100078);
1396
1397 *gpio_par_feci2c |= 0x0f00;
1398 *gpio_par_fec |= 0xc0;
1399
1400 #if defined(CONFIG_FEC2)
1401 /* Set up gpio outputs for FEC1 MII lines */
1402 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100079);
1403
1404 *gpio_par_feci2c |= 0x00a0;
1405 *gpio_par_fec |= 0xc0;
1406 #endif /* CONFIG_FEC2 */
1407 }
1408 #endif /* CONFIG_M527x */
1409 }
1410
1411 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1412 {
1413 volatile fec_t *fecp;
1414
1415 fecp = fep->hwp;
1416 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1417 fecp->fec_x_cntrl = 0x00;
1418
1419 /*
1420 * Set MII speed to 2.5 MHz
1421 * See 5282 manual section 17.5.4.7: MSCR
1422 */
1423 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1424 fecp->fec_mii_speed = fep->phy_speed;
1425
1426 fec_restart(dev, 0);
1427 }
1428
1429 static void __inline__ fec_get_mac(struct net_device *dev)
1430 {
1431 struct fec_enet_private *fep = netdev_priv(dev);
1432 volatile fec_t *fecp;
1433 unsigned char *iap, tmpaddr[ETH_ALEN];
1434
1435 fecp = fep->hwp;
1436
1437 if (FEC_FLASHMAC) {
1438 /*
1439 * Get MAC address from FLASH.
1440 * If it is all 1's or 0's, use the default.
1441 */
1442 iap = FEC_FLASHMAC;
1443 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1444 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1445 iap = fec_mac_default;
1446 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1447 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1448 iap = fec_mac_default;
1449 } else {
1450 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1451 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1452 iap = &tmpaddr[0];
1453 }
1454
1455 memcpy(dev->dev_addr, iap, ETH_ALEN);
1456
1457 /* Adjust MAC if using default MAC address */
1458 if (iap == fec_mac_default)
1459 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1460 }
1461
1462 static void __inline__ fec_disable_phy_intr(void)
1463 {
1464 }
1465
1466 static void __inline__ fec_phy_ack_intr(void)
1467 {
1468 }
1469
1470 /* ------------------------------------------------------------------------- */
1471
1472 #elif defined(CONFIG_M520x)
1473
1474 /*
1475 * Code specific to Coldfire 520x
1476 */
1477 static void __inline__ fec_request_intrs(struct net_device *dev)
1478 {
1479 struct fec_enet_private *fep;
1480 int b;
1481 static const struct idesc {
1482 char *name;
1483 unsigned short irq;
1484 } *idp, id[] = {
1485 { "fec(TXF)", 23 },
1486 { "fec(RXF)", 27 },
1487 { "fec(MII)", 29 },
1488 { NULL },
1489 };
1490
1491 fep = netdev_priv(dev);
1492 b = 64 + 13;
1493
1494 /* Setup interrupt handlers. */
1495 for (idp = id; idp->name; idp++) {
1496 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
1497 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1498 }
1499
1500 /* Unmask interrupts at ColdFire interrupt controller */
1501 {
1502 volatile unsigned char *icrp;
1503 volatile unsigned long *imrp;
1504
1505 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
1506 MCFINTC_ICR0);
1507 for (b = 36; (b < 49); b++)
1508 icrp[b] = 0x04;
1509 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
1510 MCFINTC_IMRH);
1511 *imrp &= ~0x0001FFF0;
1512 }
1513 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
1514 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
1515 }
1516
1517 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1518 {
1519 volatile fec_t *fecp;
1520
1521 fecp = fep->hwp;
1522 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1523 fecp->fec_x_cntrl = 0x00;
1524
1525 /*
1526 * Set MII speed to 2.5 MHz
1527 * See 5282 manual section 17.5.4.7: MSCR
1528 */
1529 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1530 fecp->fec_mii_speed = fep->phy_speed;
1531
1532 fec_restart(dev, 0);
1533 }
1534
1535 static void __inline__ fec_get_mac(struct net_device *dev)
1536 {
1537 struct fec_enet_private *fep = netdev_priv(dev);
1538 volatile fec_t *fecp;
1539 unsigned char *iap, tmpaddr[ETH_ALEN];
1540
1541 fecp = fep->hwp;
1542
1543 if (FEC_FLASHMAC) {
1544 /*
1545 * Get MAC address from FLASH.
1546 * If it is all 1's or 0's, use the default.
1547 */
1548 iap = FEC_FLASHMAC;
1549 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1550 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1551 iap = fec_mac_default;
1552 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1553 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1554 iap = fec_mac_default;
1555 } else {
1556 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1557 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1558 iap = &tmpaddr[0];
1559 }
1560
1561 memcpy(dev->dev_addr, iap, ETH_ALEN);
1562
1563 /* Adjust MAC if using default MAC address */
1564 if (iap == fec_mac_default)
1565 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1566 }
1567
1568 static void __inline__ fec_disable_phy_intr(void)
1569 {
1570 }
1571
1572 static void __inline__ fec_phy_ack_intr(void)
1573 {
1574 }
1575
1576 /* ------------------------------------------------------------------------- */
1577
1578 #elif defined(CONFIG_M532x)
1579 /*
1580 * Code specific for M532x
1581 */
1582 static void __inline__ fec_request_intrs(struct net_device *dev)
1583 {
1584 struct fec_enet_private *fep;
1585 int b;
1586 static const struct idesc {
1587 char *name;
1588 unsigned short irq;
1589 } *idp, id[] = {
1590 { "fec(TXF)", 36 },
1591 { "fec(RXF)", 40 },
1592 { "fec(MII)", 42 },
1593 { NULL },
1594 };
1595
1596 fep = netdev_priv(dev);
1597 b = (fep->index) ? 128 : 64;
1598
1599 /* Setup interrupt handlers. */
1600 for (idp = id; idp->name; idp++) {
1601 if (request_irq(b+idp->irq, fec_enet_interrupt, IRQF_DISABLED, idp->name,dev) != 0)
1602 printk("FEC: Could not allocate %s IRQ(%d)!\n",
1603 idp->name, b+idp->irq);
1604 }
1605
1606 /* Unmask interrupts */
1607 MCF_INTC0_ICR36 = 0x2;
1608 MCF_INTC0_ICR37 = 0x2;
1609 MCF_INTC0_ICR38 = 0x2;
1610 MCF_INTC0_ICR39 = 0x2;
1611 MCF_INTC0_ICR40 = 0x2;
1612 MCF_INTC0_ICR41 = 0x2;
1613 MCF_INTC0_ICR42 = 0x2;
1614 MCF_INTC0_ICR43 = 0x2;
1615 MCF_INTC0_ICR44 = 0x2;
1616 MCF_INTC0_ICR45 = 0x2;
1617 MCF_INTC0_ICR46 = 0x2;
1618 MCF_INTC0_ICR47 = 0x2;
1619 MCF_INTC0_ICR48 = 0x2;
1620
1621 MCF_INTC0_IMRH &= ~(
1622 MCF_INTC_IMRH_INT_MASK36 |
1623 MCF_INTC_IMRH_INT_MASK37 |
1624 MCF_INTC_IMRH_INT_MASK38 |
1625 MCF_INTC_IMRH_INT_MASK39 |
1626 MCF_INTC_IMRH_INT_MASK40 |
1627 MCF_INTC_IMRH_INT_MASK41 |
1628 MCF_INTC_IMRH_INT_MASK42 |
1629 MCF_INTC_IMRH_INT_MASK43 |
1630 MCF_INTC_IMRH_INT_MASK44 |
1631 MCF_INTC_IMRH_INT_MASK45 |
1632 MCF_INTC_IMRH_INT_MASK46 |
1633 MCF_INTC_IMRH_INT_MASK47 |
1634 MCF_INTC_IMRH_INT_MASK48 );
1635
1636 /* Set up gpio outputs for MII lines */
1637 MCF_GPIO_PAR_FECI2C |= (0 |
1638 MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
1639 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
1640 MCF_GPIO_PAR_FEC = (0 |
1641 MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
1642 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
1643 }
1644
1645 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1646 {
1647 volatile fec_t *fecp;
1648
1649 fecp = fep->hwp;
1650 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1651 fecp->fec_x_cntrl = 0x00;
1652
1653 /*
1654 * Set MII speed to 2.5 MHz
1655 */
1656 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1657 fecp->fec_mii_speed = fep->phy_speed;
1658
1659 fec_restart(dev, 0);
1660 }
1661
1662 static void __inline__ fec_get_mac(struct net_device *dev)
1663 {
1664 struct fec_enet_private *fep = netdev_priv(dev);
1665 volatile fec_t *fecp;
1666 unsigned char *iap, tmpaddr[ETH_ALEN];
1667
1668 fecp = fep->hwp;
1669
1670 if (FEC_FLASHMAC) {
1671 /*
1672 * Get MAC address from FLASH.
1673 * If it is all 1's or 0's, use the default.
1674 */
1675 iap = FEC_FLASHMAC;
1676 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1677 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1678 iap = fec_mac_default;
1679 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1680 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1681 iap = fec_mac_default;
1682 } else {
1683 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1684 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1685 iap = &tmpaddr[0];
1686 }
1687
1688 memcpy(dev->dev_addr, iap, ETH_ALEN);
1689
1690 /* Adjust MAC if using default MAC address */
1691 if (iap == fec_mac_default)
1692 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1693 }
1694
1695 static void __inline__ fec_disable_phy_intr(void)
1696 {
1697 }
1698
1699 static void __inline__ fec_phy_ack_intr(void)
1700 {
1701 }
1702
1703 #endif
1704
1705 /* ------------------------------------------------------------------------- */
1706
1707 static void mii_display_status(struct net_device *dev)
1708 {
1709 struct fec_enet_private *fep = netdev_priv(dev);
1710 volatile uint *s = &(fep->phy_status);
1711
1712 if (!fep->link && !fep->old_link) {
1713 /* Link is still down - don't print anything */
1714 return;
1715 }
1716
1717 printk("%s: status: ", dev->name);
1718
1719 if (!fep->link) {
1720 printk("link down");
1721 } else {
1722 printk("link up");
1723
1724 switch(*s & PHY_STAT_SPMASK) {
1725 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1726 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1727 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1728 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1729 default:
1730 printk(", Unknown speed/duplex");
1731 }
1732
1733 if (*s & PHY_STAT_ANC)
1734 printk(", auto-negotiation complete");
1735 }
1736
1737 if (*s & PHY_STAT_FAULT)
1738 printk(", remote fault");
1739
1740 printk(".\n");
1741 }
1742
1743 static void mii_display_config(struct work_struct *work)
1744 {
1745 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1746 struct net_device *dev = fep->netdev;
1747 uint status = fep->phy_status;
1748
1749 /*
1750 ** When we get here, phy_task is already removed from
1751 ** the workqueue. It is thus safe to allow to reuse it.
1752 */
1753 fep->mii_phy_task_queued = 0;
1754 printk("%s: config: auto-negotiation ", dev->name);
1755
1756 if (status & PHY_CONF_ANE)
1757 printk("on");
1758 else
1759 printk("off");
1760
1761 if (status & PHY_CONF_100FDX)
1762 printk(", 100FDX");
1763 if (status & PHY_CONF_100HDX)
1764 printk(", 100HDX");
1765 if (status & PHY_CONF_10FDX)
1766 printk(", 10FDX");
1767 if (status & PHY_CONF_10HDX)
1768 printk(", 10HDX");
1769 if (!(status & PHY_CONF_SPMASK))
1770 printk(", No speed/duplex selected?");
1771
1772 if (status & PHY_CONF_LOOP)
1773 printk(", loopback enabled");
1774
1775 printk(".\n");
1776
1777 fep->sequence_done = 1;
1778 }
1779
1780 static void mii_relink(struct work_struct *work)
1781 {
1782 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1783 struct net_device *dev = fep->netdev;
1784 int duplex;
1785
1786 /*
1787 ** When we get here, phy_task is already removed from
1788 ** the workqueue. It is thus safe to allow to reuse it.
1789 */
1790 fep->mii_phy_task_queued = 0;
1791 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
1792 mii_display_status(dev);
1793 fep->old_link = fep->link;
1794
1795 if (fep->link) {
1796 duplex = 0;
1797 if (fep->phy_status
1798 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
1799 duplex = 1;
1800 fec_restart(dev, duplex);
1801 } else
1802 fec_stop(dev);
1803
1804 #if 0
1805 enable_irq(fep->mii_irq);
1806 #endif
1807
1808 }
1809
1810 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
1811 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
1812 {
1813 struct fec_enet_private *fep = netdev_priv(dev);
1814
1815 /*
1816 ** We cannot queue phy_task twice in the workqueue. It
1817 ** would cause an endless loop in the workqueue.
1818 ** Fortunately, if the last mii_relink entry has not yet been
1819 ** executed now, it will do the job for the current interrupt,
1820 ** which is just what we want.
1821 */
1822 if (fep->mii_phy_task_queued)
1823 return;
1824
1825 fep->mii_phy_task_queued = 1;
1826 INIT_WORK(&fep->phy_task, mii_relink);
1827 schedule_work(&fep->phy_task);
1828 }
1829
1830 /* mii_queue_config is called in interrupt context from fec_enet_mii */
1831 static void mii_queue_config(uint mii_reg, struct net_device *dev)
1832 {
1833 struct fec_enet_private *fep = netdev_priv(dev);
1834
1835 if (fep->mii_phy_task_queued)
1836 return;
1837
1838 fep->mii_phy_task_queued = 1;
1839 INIT_WORK(&fep->phy_task, mii_display_config);
1840 schedule_work(&fep->phy_task);
1841 }
1842
1843 phy_cmd_t const phy_cmd_relink[] = {
1844 { mk_mii_read(MII_REG_CR), mii_queue_relink },
1845 { mk_mii_end, }
1846 };
1847 phy_cmd_t const phy_cmd_config[] = {
1848 { mk_mii_read(MII_REG_CR), mii_queue_config },
1849 { mk_mii_end, }
1850 };
1851
1852 /* Read remainder of PHY ID.
1853 */
1854 static void
1855 mii_discover_phy3(uint mii_reg, struct net_device *dev)
1856 {
1857 struct fec_enet_private *fep;
1858 int i;
1859
1860 fep = netdev_priv(dev);
1861 fep->phy_id |= (mii_reg & 0xffff);
1862 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
1863
1864 for(i = 0; phy_info[i]; i++) {
1865 if(phy_info[i]->id == (fep->phy_id >> 4))
1866 break;
1867 }
1868
1869 if (phy_info[i])
1870 printk(" -- %s\n", phy_info[i]->name);
1871 else
1872 printk(" -- unknown PHY!\n");
1873
1874 fep->phy = phy_info[i];
1875 fep->phy_id_done = 1;
1876 }
1877
1878 /* Scan all of the MII PHY addresses looking for someone to respond
1879 * with a valid ID. This usually happens quickly.
1880 */
1881 static void
1882 mii_discover_phy(uint mii_reg, struct net_device *dev)
1883 {
1884 struct fec_enet_private *fep;
1885 volatile fec_t *fecp;
1886 uint phytype;
1887
1888 fep = netdev_priv(dev);
1889 fecp = fep->hwp;
1890
1891 if (fep->phy_addr < 32) {
1892 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
1893
1894 /* Got first part of ID, now get remainder.
1895 */
1896 fep->phy_id = phytype << 16;
1897 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
1898 mii_discover_phy3);
1899 } else {
1900 fep->phy_addr++;
1901 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
1902 mii_discover_phy);
1903 }
1904 } else {
1905 printk("FEC: No PHY device found.\n");
1906 /* Disable external MII interface */
1907 fecp->fec_mii_speed = fep->phy_speed = 0;
1908 fec_disable_phy_intr();
1909 }
1910 }
1911
1912 /* This interrupt occurs when the PHY detects a link change.
1913 */
1914 #ifdef HAVE_mii_link_interrupt
1915 static irqreturn_t
1916 mii_link_interrupt(int irq, void * dev_id)
1917 {
1918 struct net_device *dev = dev_id;
1919 struct fec_enet_private *fep = netdev_priv(dev);
1920
1921 fec_phy_ack_intr();
1922
1923 #if 0
1924 disable_irq(fep->mii_irq); /* disable now, enable later */
1925 #endif
1926
1927 mii_do_cmd(dev, fep->phy->ack_int);
1928 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1929
1930 return IRQ_HANDLED;
1931 }
1932 #endif
1933
1934 static int
1935 fec_enet_open(struct net_device *dev)
1936 {
1937 struct fec_enet_private *fep = netdev_priv(dev);
1938
1939 /* I should reset the ring buffers here, but I don't yet know
1940 * a simple way to do that.
1941 */
1942 fec_set_mac_address(dev);
1943
1944 fep->sequence_done = 0;
1945 fep->link = 0;
1946
1947 if (fep->phy) {
1948 mii_do_cmd(dev, fep->phy->ack_int);
1949 mii_do_cmd(dev, fep->phy->config);
1950 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
1951
1952 /* Poll until the PHY tells us its configuration
1953 * (not link state).
1954 * Request is initiated by mii_do_cmd above, but answer
1955 * comes by interrupt.
1956 * This should take about 25 usec per register at 2.5 MHz,
1957 * and we read approximately 5 registers.
1958 */
1959 while(!fep->sequence_done)
1960 schedule();
1961
1962 mii_do_cmd(dev, fep->phy->startup);
1963
1964 /* Set the initial link state to true. A lot of hardware
1965 * based on this device does not implement a PHY interrupt,
1966 * so we are never notified of link change.
1967 */
1968 fep->link = 1;
1969 } else {
1970 fep->link = 1; /* lets just try it and see */
1971 /* no phy, go full duplex, it's most likely a hub chip */
1972 fec_restart(dev, 1);
1973 }
1974
1975 netif_start_queue(dev);
1976 fep->opened = 1;
1977 return 0; /* Success */
1978 }
1979
1980 static int
1981 fec_enet_close(struct net_device *dev)
1982 {
1983 struct fec_enet_private *fep = netdev_priv(dev);
1984
1985 /* Don't know what to do yet.
1986 */
1987 fep->opened = 0;
1988 netif_stop_queue(dev);
1989 fec_stop(dev);
1990
1991 return 0;
1992 }
1993
1994 /* Set or clear the multicast filter for this adaptor.
1995 * Skeleton taken from sunlance driver.
1996 * The CPM Ethernet implementation allows Multicast as well as individual
1997 * MAC address filtering. Some of the drivers check to make sure it is
1998 * a group multicast address, and discard those that are not. I guess I
1999 * will do the same for now, but just remove the test if you want
2000 * individual filtering as well (do the upper net layers want or support
2001 * this kind of feature?).
2002 */
2003
2004 #define HASH_BITS 6 /* #bits in hash */
2005 #define CRC32_POLY 0xEDB88320
2006
2007 static void set_multicast_list(struct net_device *dev)
2008 {
2009 struct fec_enet_private *fep;
2010 volatile fec_t *ep;
2011 struct dev_mc_list *dmi;
2012 unsigned int i, j, bit, data, crc;
2013 unsigned char hash;
2014
2015 fep = netdev_priv(dev);
2016 ep = fep->hwp;
2017
2018 if (dev->flags&IFF_PROMISC) {
2019 ep->fec_r_cntrl |= 0x0008;
2020 } else {
2021
2022 ep->fec_r_cntrl &= ~0x0008;
2023
2024 if (dev->flags & IFF_ALLMULTI) {
2025 /* Catch all multicast addresses, so set the
2026 * filter to all 1's.
2027 */
2028 ep->fec_grp_hash_table_high = 0xffffffff;
2029 ep->fec_grp_hash_table_low = 0xffffffff;
2030 } else {
2031 /* Clear filter and add the addresses in hash register.
2032 */
2033 ep->fec_grp_hash_table_high = 0;
2034 ep->fec_grp_hash_table_low = 0;
2035
2036 dmi = dev->mc_list;
2037
2038 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
2039 {
2040 /* Only support group multicast for now.
2041 */
2042 if (!(dmi->dmi_addr[0] & 1))
2043 continue;
2044
2045 /* calculate crc32 value of mac address
2046 */
2047 crc = 0xffffffff;
2048
2049 for (i = 0; i < dmi->dmi_addrlen; i++)
2050 {
2051 data = dmi->dmi_addr[i];
2052 for (bit = 0; bit < 8; bit++, data >>= 1)
2053 {
2054 crc = (crc >> 1) ^
2055 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2056 }
2057 }
2058
2059 /* only upper 6 bits (HASH_BITS) are used
2060 which point to specific bit in he hash registers
2061 */
2062 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2063
2064 if (hash > 31)
2065 ep->fec_grp_hash_table_high |= 1 << (hash - 32);
2066 else
2067 ep->fec_grp_hash_table_low |= 1 << hash;
2068 }
2069 }
2070 }
2071 }
2072
2073 /* Set a MAC change in hardware.
2074 */
2075 static void
2076 fec_set_mac_address(struct net_device *dev)
2077 {
2078 volatile fec_t *fecp;
2079
2080 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
2081
2082 /* Set station address. */
2083 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
2084 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
2085 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
2086 (dev->dev_addr[4] << 24);
2087
2088 }
2089
2090 /* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
2091 */
2092 /*
2093 * XXX: We need to clean up on failure exits here.
2094 */
2095 int __init fec_enet_init(struct net_device *dev)
2096 {
2097 struct fec_enet_private *fep = netdev_priv(dev);
2098 unsigned long mem_addr;
2099 volatile cbd_t *bdp;
2100 cbd_t *cbd_base;
2101 volatile fec_t *fecp;
2102 int i, j;
2103 static int index = 0;
2104
2105 /* Only allow us to be probed once. */
2106 if (index >= FEC_MAX_PORTS)
2107 return -ENXIO;
2108
2109 /* Allocate memory for buffer descriptors.
2110 */
2111 mem_addr = (unsigned long)dma_alloc_coherent(NULL, PAGE_SIZE,
2112 &fep->bd_dma, GFP_KERNEL);
2113 if (mem_addr == 0) {
2114 printk("FEC: allocate descriptor memory failed?\n");
2115 return -ENOMEM;
2116 }
2117
2118 spin_lock_init(&fep->hw_lock);
2119 spin_lock_init(&fep->mii_lock);
2120
2121 /* Create an Ethernet device instance.
2122 */
2123 fecp = (volatile fec_t *) fec_hw[index];
2124
2125 fep->index = index;
2126 fep->hwp = fecp;
2127 fep->netdev = dev;
2128
2129 /* Whack a reset. We should wait for this.
2130 */
2131 fecp->fec_ecntrl = 1;
2132 udelay(10);
2133
2134 /* Set the Ethernet address. If using multiple Enets on the 8xx,
2135 * this needs some work to get unique addresses.
2136 *
2137 * This is our default MAC address unless the user changes
2138 * it via eth_mac_addr (our dev->set_mac_addr handler).
2139 */
2140 fec_get_mac(dev);
2141
2142 cbd_base = (cbd_t *)mem_addr;
2143 /* XXX: missing check for allocation failure */
2144
2145 /* Set receive and transmit descriptor base.
2146 */
2147 fep->rx_bd_base = cbd_base;
2148 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
2149
2150 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2151 fep->cur_rx = fep->rx_bd_base;
2152
2153 fep->skb_cur = fep->skb_dirty = 0;
2154
2155 /* Initialize the receive buffer descriptors.
2156 */
2157 bdp = fep->rx_bd_base;
2158 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
2159
2160 /* Allocate a page.
2161 */
2162 mem_addr = __get_free_page(GFP_KERNEL);
2163 /* XXX: missing check for allocation failure */
2164
2165 /* Initialize the BD for every fragment in the page.
2166 */
2167 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2168 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2169 bdp->cbd_bufaddr = __pa(mem_addr);
2170 mem_addr += FEC_ENET_RX_FRSIZE;
2171 bdp++;
2172 }
2173 }
2174
2175 /* Set the last buffer to wrap.
2176 */
2177 bdp--;
2178 bdp->cbd_sc |= BD_SC_WRAP;
2179
2180 /* ...and the same for transmmit.
2181 */
2182 bdp = fep->tx_bd_base;
2183 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2184 if (j >= FEC_ENET_TX_FRPPG) {
2185 mem_addr = __get_free_page(GFP_KERNEL);
2186 j = 1;
2187 } else {
2188 mem_addr += FEC_ENET_TX_FRSIZE;
2189 j++;
2190 }
2191 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2192
2193 /* Initialize the BD for every fragment in the page.
2194 */
2195 bdp->cbd_sc = 0;
2196 bdp->cbd_bufaddr = 0;
2197 bdp++;
2198 }
2199
2200 /* Set the last buffer to wrap.
2201 */
2202 bdp--;
2203 bdp->cbd_sc |= BD_SC_WRAP;
2204
2205 /* Set receive and transmit descriptor base.
2206 */
2207 fecp->fec_r_des_start = fep->bd_dma;
2208 fecp->fec_x_des_start = (unsigned long)fep->bd_dma + sizeof(cbd_t)
2209 * RX_RING_SIZE;
2210
2211 /* Install our interrupt handlers. This varies depending on
2212 * the architecture.
2213 */
2214 fec_request_intrs(dev);
2215
2216 fecp->fec_grp_hash_table_high = 0;
2217 fecp->fec_grp_hash_table_low = 0;
2218 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2219 fecp->fec_ecntrl = 2;
2220 fecp->fec_r_des_active = 0;
2221 #ifndef CONFIG_M5272
2222 fecp->fec_hash_table_high = 0;
2223 fecp->fec_hash_table_low = 0;
2224 #endif
2225
2226 dev->base_addr = (unsigned long)fecp;
2227
2228 /* The FEC Ethernet specific entries in the device structure. */
2229 dev->open = fec_enet_open;
2230 dev->hard_start_xmit = fec_enet_start_xmit;
2231 dev->tx_timeout = fec_timeout;
2232 dev->watchdog_timeo = TX_TIMEOUT;
2233 dev->stop = fec_enet_close;
2234 dev->set_multicast_list = set_multicast_list;
2235
2236 for (i=0; i<NMII-1; i++)
2237 mii_cmds[i].mii_next = &mii_cmds[i+1];
2238 mii_free = mii_cmds;
2239
2240 /* setup MII interface */
2241 fec_set_mii(dev, fep);
2242
2243 /* Clear and enable interrupts */
2244 fecp->fec_ievent = 0xffc00000;
2245 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII);
2246
2247 /* Queue up command to detect the PHY and initialize the
2248 * remainder of the interface.
2249 */
2250 fep->phy_id_done = 0;
2251 fep->phy_addr = 0;
2252 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2253
2254 index++;
2255 return 0;
2256 }
2257
2258 /* This function is called to start or restart the FEC during a link
2259 * change. This only happens when switching between half and full
2260 * duplex.
2261 */
2262 static void
2263 fec_restart(struct net_device *dev, int duplex)
2264 {
2265 struct fec_enet_private *fep;
2266 volatile cbd_t *bdp;
2267 volatile fec_t *fecp;
2268 int i;
2269
2270 fep = netdev_priv(dev);
2271 fecp = fep->hwp;
2272
2273 /* Whack a reset. We should wait for this.
2274 */
2275 fecp->fec_ecntrl = 1;
2276 udelay(10);
2277
2278 /* Clear any outstanding interrupt.
2279 */
2280 fecp->fec_ievent = 0xffc00000;
2281
2282 /* Set station address.
2283 */
2284 fec_set_mac_address(dev);
2285
2286 /* Reset all multicast.
2287 */
2288 fecp->fec_grp_hash_table_high = 0;
2289 fecp->fec_grp_hash_table_low = 0;
2290
2291 /* Set maximum receive buffer size.
2292 */
2293 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2294
2295 /* Set receive and transmit descriptor base.
2296 */
2297 fecp->fec_r_des_start = fep->bd_dma;
2298 fecp->fec_x_des_start = (unsigned long)fep->bd_dma + sizeof(cbd_t)
2299 * RX_RING_SIZE;
2300
2301 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2302 fep->cur_rx = fep->rx_bd_base;
2303
2304 /* Reset SKB transmit buffers.
2305 */
2306 fep->skb_cur = fep->skb_dirty = 0;
2307 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2308 if (fep->tx_skbuff[i] != NULL) {
2309 dev_kfree_skb_any(fep->tx_skbuff[i]);
2310 fep->tx_skbuff[i] = NULL;
2311 }
2312 }
2313
2314 /* Initialize the receive buffer descriptors.
2315 */
2316 bdp = fep->rx_bd_base;
2317 for (i=0; i<RX_RING_SIZE; i++) {
2318
2319 /* Initialize the BD for every fragment in the page.
2320 */
2321 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2322 bdp++;
2323 }
2324
2325 /* Set the last buffer to wrap.
2326 */
2327 bdp--;
2328 bdp->cbd_sc |= BD_SC_WRAP;
2329
2330 /* ...and the same for transmmit.
2331 */
2332 bdp = fep->tx_bd_base;
2333 for (i=0; i<TX_RING_SIZE; i++) {
2334
2335 /* Initialize the BD for every fragment in the page.
2336 */
2337 bdp->cbd_sc = 0;
2338 bdp->cbd_bufaddr = 0;
2339 bdp++;
2340 }
2341
2342 /* Set the last buffer to wrap.
2343 */
2344 bdp--;
2345 bdp->cbd_sc |= BD_SC_WRAP;
2346
2347 /* Enable MII mode.
2348 */
2349 if (duplex) {
2350 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2351 fecp->fec_x_cntrl = 0x04; /* FD enable */
2352 } else {
2353 /* MII enable|No Rcv on Xmit */
2354 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2355 fecp->fec_x_cntrl = 0x00;
2356 }
2357 fep->full_duplex = duplex;
2358
2359 /* Set MII speed.
2360 */
2361 fecp->fec_mii_speed = fep->phy_speed;
2362
2363 /* And last, enable the transmit and receive processing.
2364 */
2365 fecp->fec_ecntrl = 2;
2366 fecp->fec_r_des_active = 0;
2367
2368 /* Enable interrupts we wish to service.
2369 */
2370 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII);
2371 }
2372
2373 static void
2374 fec_stop(struct net_device *dev)
2375 {
2376 volatile fec_t *fecp;
2377 struct fec_enet_private *fep;
2378
2379 fep = netdev_priv(dev);
2380 fecp = fep->hwp;
2381
2382 /*
2383 ** We cannot expect a graceful transmit stop without link !!!
2384 */
2385 if (fep->link)
2386 {
2387 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
2388 udelay(10);
2389 if (!(fecp->fec_ievent & FEC_ENET_GRA))
2390 printk("fec_stop : Graceful transmit stop did not complete !\n");
2391 }
2392
2393 /* Whack a reset. We should wait for this.
2394 */
2395 fecp->fec_ecntrl = 1;
2396 udelay(10);
2397
2398 /* Clear outstanding MII command interrupts.
2399 */
2400 fecp->fec_ievent = FEC_ENET_MII;
2401
2402 fecp->fec_imask = FEC_ENET_MII;
2403 fecp->fec_mii_speed = fep->phy_speed;
2404 }
2405
2406 static int __init fec_enet_module_init(void)
2407 {
2408 struct net_device *dev;
2409 int i, err;
2410
2411 printk("FEC ENET Version 0.2\n");
2412
2413 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2414 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2415 if (!dev)
2416 return -ENOMEM;
2417 err = fec_enet_init(dev);
2418 if (err) {
2419 free_netdev(dev);
2420 continue;
2421 }
2422 if (register_netdev(dev) != 0) {
2423 /* XXX: missing cleanup here */
2424 free_netdev(dev);
2425 return -EIO;
2426 }
2427
2428 printk("%s: ethernet %pM\n", dev->name, dev->dev_addr);
2429 }
2430 return 0;
2431 }
2432
2433 module_init(fec_enet_module_init);
2434
2435 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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