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setup and detect 2nd phy on MCF5275 in FEC driver
[deliverable/linux.git] / drivers / net / fec.c
1 /*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * This version of the driver is specific to the FADS implementation,
6 * since the board contains control registers external to the processor
7 * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
8 * describes connections using the internal parallel port I/O, which
9 * is basically all of Port D.
10 *
11 * Right now, I am very wasteful with the buffers. I allocate memory
12 * pages and then divide them into 2K frame buffers. This way I know I
13 * have buffers large enough to hold one frame within one buffer descriptor.
14 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
15 * will be much more memory efficient and will easily handle lots of
16 * small packets.
17 *
18 * Much better multiple PHY support by Magnus Damm.
19 * Copyright (c) 2000 Ericsson Radio Systems AB.
20 *
21 * Support for FEC controller of ColdFire processors.
22 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
23 *
24 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
25 * Copyright (c) 2004-2006 Macq Electronique SA.
26 */
27
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/string.h>
31 #include <linux/ptrace.h>
32 #include <linux/errno.h>
33 #include <linux/ioport.h>
34 #include <linux/slab.h>
35 #include <linux/interrupt.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/skbuff.h>
42 #include <linux/spinlock.h>
43 #include <linux/workqueue.h>
44 #include <linux/bitops.h>
45
46 #include <asm/irq.h>
47 #include <asm/uaccess.h>
48 #include <asm/io.h>
49 #include <asm/pgtable.h>
50 #include <asm/cacheflush.h>
51
52 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
53 defined(CONFIG_M5272) || defined(CONFIG_M528x) || \
54 defined(CONFIG_M520x) || defined(CONFIG_M532x)
55 #include <asm/coldfire.h>
56 #include <asm/mcfsim.h>
57 #include "fec.h"
58 #else
59 #include <asm/8xx_immap.h>
60 #include <asm/mpc8xx.h>
61 #include "commproc.h"
62 #endif
63
64 #if defined(CONFIG_FEC2)
65 #define FEC_MAX_PORTS 2
66 #else
67 #define FEC_MAX_PORTS 1
68 #endif
69
70 /*
71 * Define the fixed address of the FEC hardware.
72 */
73 static unsigned int fec_hw[] = {
74 #if defined(CONFIG_M5272)
75 (MCF_MBAR + 0x840),
76 #elif defined(CONFIG_M527x)
77 (MCF_MBAR + 0x1000),
78 (MCF_MBAR + 0x1800),
79 #elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
80 (MCF_MBAR + 0x1000),
81 #elif defined(CONFIG_M520x)
82 (MCF_MBAR+0x30000),
83 #elif defined(CONFIG_M532x)
84 (MCF_MBAR+0xfc030000),
85 #else
86 &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec),
87 #endif
88 };
89
90 static unsigned char fec_mac_default[] = {
91 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
92 };
93
94 /*
95 * Some hardware gets it MAC address out of local flash memory.
96 * if this is non-zero then assume it is the address to get MAC from.
97 */
98 #if defined(CONFIG_NETtel)
99 #define FEC_FLASHMAC 0xf0006006
100 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
101 #define FEC_FLASHMAC 0xf0006000
102 #elif defined(CONFIG_CANCam)
103 #define FEC_FLASHMAC 0xf0020000
104 #elif defined (CONFIG_M5272C3)
105 #define FEC_FLASHMAC (0xffe04000 + 4)
106 #elif defined(CONFIG_MOD5272)
107 #define FEC_FLASHMAC 0xffc0406b
108 #else
109 #define FEC_FLASHMAC 0
110 #endif
111
112 /* Forward declarations of some structures to support different PHYs
113 */
114
115 typedef struct {
116 uint mii_data;
117 void (*funct)(uint mii_reg, struct net_device *dev);
118 } phy_cmd_t;
119
120 typedef struct {
121 uint id;
122 char *name;
123
124 const phy_cmd_t *config;
125 const phy_cmd_t *startup;
126 const phy_cmd_t *ack_int;
127 const phy_cmd_t *shutdown;
128 } phy_info_t;
129
130 /* The number of Tx and Rx buffers. These are allocated from the page
131 * pool. The code may assume these are power of two, so it it best
132 * to keep them that size.
133 * We don't need to allocate pages for the transmitter. We just use
134 * the skbuffer directly.
135 */
136 #define FEC_ENET_RX_PAGES 8
137 #define FEC_ENET_RX_FRSIZE 2048
138 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
139 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
140 #define FEC_ENET_TX_FRSIZE 2048
141 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
142 #define TX_RING_SIZE 16 /* Must be power of two */
143 #define TX_RING_MOD_MASK 15 /* for this to work */
144
145 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
146 #error "FEC: descriptor ring size constants too large"
147 #endif
148
149 /* Interrupt events/masks.
150 */
151 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
152 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
153 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
154 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
155 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
156 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
157 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
158 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
159 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
160 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
161
162 /* The FEC stores dest/src/type, data, and checksum for receive packets.
163 */
164 #define PKT_MAXBUF_SIZE 1518
165 #define PKT_MINBUF_SIZE 64
166 #define PKT_MAXBLR_SIZE 1520
167
168
169 /*
170 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
171 * size bits. Other FEC hardware does not, so we need to take that into
172 * account when setting it.
173 */
174 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
175 defined(CONFIG_M520x) || defined(CONFIG_M532x)
176 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
177 #else
178 #define OPT_FRAME_SIZE 0
179 #endif
180
181 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
182 * tx_bd_base always point to the base of the buffer descriptors. The
183 * cur_rx and cur_tx point to the currently available buffer.
184 * The dirty_tx tracks the current buffer that is being sent by the
185 * controller. The cur_tx and dirty_tx are equal under both completely
186 * empty and completely full conditions. The empty/ready indicator in
187 * the buffer descriptor determines the actual condition.
188 */
189 struct fec_enet_private {
190 /* Hardware registers of the FEC device */
191 volatile fec_t *hwp;
192
193 struct net_device *netdev;
194
195 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
196 unsigned char *tx_bounce[TX_RING_SIZE];
197 struct sk_buff* tx_skbuff[TX_RING_SIZE];
198 ushort skb_cur;
199 ushort skb_dirty;
200
201 /* CPM dual port RAM relative addresses.
202 */
203 cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
204 cbd_t *tx_bd_base;
205 cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
206 cbd_t *dirty_tx; /* The ring entries to be free()ed. */
207 struct net_device_stats stats;
208 uint tx_full;
209 spinlock_t lock;
210
211 uint phy_id;
212 uint phy_id_done;
213 uint phy_status;
214 uint phy_speed;
215 phy_info_t const *phy;
216 struct work_struct phy_task;
217
218 uint sequence_done;
219 uint mii_phy_task_queued;
220
221 uint phy_addr;
222
223 int index;
224 int opened;
225 int link;
226 int old_link;
227 int full_duplex;
228 };
229
230 static int fec_enet_open(struct net_device *dev);
231 static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
232 static void fec_enet_mii(struct net_device *dev);
233 static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
234 static void fec_enet_tx(struct net_device *dev);
235 static void fec_enet_rx(struct net_device *dev);
236 static int fec_enet_close(struct net_device *dev);
237 static struct net_device_stats *fec_enet_get_stats(struct net_device *dev);
238 static void set_multicast_list(struct net_device *dev);
239 static void fec_restart(struct net_device *dev, int duplex);
240 static void fec_stop(struct net_device *dev);
241 static void fec_set_mac_address(struct net_device *dev);
242
243
244 /* MII processing. We keep this as simple as possible. Requests are
245 * placed on the list (if there is room). When the request is finished
246 * by the MII, an optional function may be called.
247 */
248 typedef struct mii_list {
249 uint mii_regval;
250 void (*mii_func)(uint val, struct net_device *dev);
251 struct mii_list *mii_next;
252 } mii_list_t;
253
254 #define NMII 20
255 static mii_list_t mii_cmds[NMII];
256 static mii_list_t *mii_free;
257 static mii_list_t *mii_head;
258 static mii_list_t *mii_tail;
259
260 static int mii_queue(struct net_device *dev, int request,
261 void (*func)(uint, struct net_device *));
262
263 /* Make MII read/write commands for the FEC.
264 */
265 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
266 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
267 (VAL & 0xffff))
268 #define mk_mii_end 0
269
270 /* Transmitter timeout.
271 */
272 #define TX_TIMEOUT (2*HZ)
273
274 /* Register definitions for the PHY.
275 */
276
277 #define MII_REG_CR 0 /* Control Register */
278 #define MII_REG_SR 1 /* Status Register */
279 #define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
280 #define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
281 #define MII_REG_ANAR 4 /* A-N Advertisement Register */
282 #define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
283 #define MII_REG_ANER 6 /* A-N Expansion Register */
284 #define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
285 #define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
286
287 /* values for phy_status */
288
289 #define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
290 #define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
291 #define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
292 #define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
293 #define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
294 #define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
295 #define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
296
297 #define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
298 #define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
299 #define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
300 #define PHY_STAT_SPMASK 0xf000 /* mask for speed */
301 #define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
302 #define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
303 #define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
304 #define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
305
306
307 static int
308 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
309 {
310 struct fec_enet_private *fep;
311 volatile fec_t *fecp;
312 volatile cbd_t *bdp;
313 unsigned short status;
314
315 fep = netdev_priv(dev);
316 fecp = (volatile fec_t*)dev->base_addr;
317
318 if (!fep->link) {
319 /* Link is down or autonegotiation is in progress. */
320 return 1;
321 }
322
323 /* Fill in a Tx ring entry */
324 bdp = fep->cur_tx;
325
326 status = bdp->cbd_sc;
327 #ifndef final_version
328 if (status & BD_ENET_TX_READY) {
329 /* Ooops. All transmit buffers are full. Bail out.
330 * This should not happen, since dev->tbusy should be set.
331 */
332 printk("%s: tx queue full!.\n", dev->name);
333 return 1;
334 }
335 #endif
336
337 /* Clear all of the status flags.
338 */
339 status &= ~BD_ENET_TX_STATS;
340
341 /* Set buffer length and buffer pointer.
342 */
343 bdp->cbd_bufaddr = __pa(skb->data);
344 bdp->cbd_datlen = skb->len;
345
346 /*
347 * On some FEC implementations data must be aligned on
348 * 4-byte boundaries. Use bounce buffers to copy data
349 * and get it aligned. Ugh.
350 */
351 if (bdp->cbd_bufaddr & 0x3) {
352 unsigned int index;
353 index = bdp - fep->tx_bd_base;
354 memcpy(fep->tx_bounce[index], (void *) bdp->cbd_bufaddr, bdp->cbd_datlen);
355 bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
356 }
357
358 /* Save skb pointer.
359 */
360 fep->tx_skbuff[fep->skb_cur] = skb;
361
362 fep->stats.tx_bytes += skb->len;
363 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
364
365 /* Push the data cache so the CPM does not get stale memory
366 * data.
367 */
368 flush_dcache_range((unsigned long)skb->data,
369 (unsigned long)skb->data + skb->len);
370
371 spin_lock_irq(&fep->lock);
372
373 /* Send it on its way. Tell FEC it's ready, interrupt when done,
374 * it's the last BD of the frame, and to put the CRC on the end.
375 */
376
377 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
378 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
379 bdp->cbd_sc = status;
380
381 dev->trans_start = jiffies;
382
383 /* Trigger transmission start */
384 fecp->fec_x_des_active = 0;
385
386 /* If this was the last BD in the ring, start at the beginning again.
387 */
388 if (status & BD_ENET_TX_WRAP) {
389 bdp = fep->tx_bd_base;
390 } else {
391 bdp++;
392 }
393
394 if (bdp == fep->dirty_tx) {
395 fep->tx_full = 1;
396 netif_stop_queue(dev);
397 }
398
399 fep->cur_tx = (cbd_t *)bdp;
400
401 spin_unlock_irq(&fep->lock);
402
403 return 0;
404 }
405
406 static void
407 fec_timeout(struct net_device *dev)
408 {
409 struct fec_enet_private *fep = netdev_priv(dev);
410
411 printk("%s: transmit timed out.\n", dev->name);
412 fep->stats.tx_errors++;
413 #ifndef final_version
414 {
415 int i;
416 cbd_t *bdp;
417
418 printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
419 (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
420 (unsigned long)fep->dirty_tx,
421 (unsigned long)fep->cur_rx);
422
423 bdp = fep->tx_bd_base;
424 printk(" tx: %u buffers\n", TX_RING_SIZE);
425 for (i = 0 ; i < TX_RING_SIZE; i++) {
426 printk(" %08x: %04x %04x %08x\n",
427 (uint) bdp,
428 bdp->cbd_sc,
429 bdp->cbd_datlen,
430 (int) bdp->cbd_bufaddr);
431 bdp++;
432 }
433
434 bdp = fep->rx_bd_base;
435 printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
436 for (i = 0 ; i < RX_RING_SIZE; i++) {
437 printk(" %08x: %04x %04x %08x\n",
438 (uint) bdp,
439 bdp->cbd_sc,
440 bdp->cbd_datlen,
441 (int) bdp->cbd_bufaddr);
442 bdp++;
443 }
444 }
445 #endif
446 fec_restart(dev, fep->full_duplex);
447 netif_wake_queue(dev);
448 }
449
450 /* The interrupt handler.
451 * This is called from the MPC core interrupt.
452 */
453 static irqreturn_t
454 fec_enet_interrupt(int irq, void * dev_id)
455 {
456 struct net_device *dev = dev_id;
457 volatile fec_t *fecp;
458 uint int_events;
459 int handled = 0;
460
461 fecp = (volatile fec_t*)dev->base_addr;
462
463 /* Get the interrupt events that caused us to be here.
464 */
465 while ((int_events = fecp->fec_ievent) != 0) {
466 fecp->fec_ievent = int_events;
467
468 /* Handle receive event in its own function.
469 */
470 if (int_events & FEC_ENET_RXF) {
471 handled = 1;
472 fec_enet_rx(dev);
473 }
474
475 /* Transmit OK, or non-fatal error. Update the buffer
476 descriptors. FEC handles all errors, we just discover
477 them as part of the transmit process.
478 */
479 if (int_events & FEC_ENET_TXF) {
480 handled = 1;
481 fec_enet_tx(dev);
482 }
483
484 if (int_events & FEC_ENET_MII) {
485 handled = 1;
486 fec_enet_mii(dev);
487 }
488
489 }
490 return IRQ_RETVAL(handled);
491 }
492
493
494 static void
495 fec_enet_tx(struct net_device *dev)
496 {
497 struct fec_enet_private *fep;
498 volatile cbd_t *bdp;
499 unsigned short status;
500 struct sk_buff *skb;
501
502 fep = netdev_priv(dev);
503 spin_lock(&fep->lock);
504 bdp = fep->dirty_tx;
505
506 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
507 if (bdp == fep->cur_tx && fep->tx_full == 0) break;
508
509 skb = fep->tx_skbuff[fep->skb_dirty];
510 /* Check for errors. */
511 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
512 BD_ENET_TX_RL | BD_ENET_TX_UN |
513 BD_ENET_TX_CSL)) {
514 fep->stats.tx_errors++;
515 if (status & BD_ENET_TX_HB) /* No heartbeat */
516 fep->stats.tx_heartbeat_errors++;
517 if (status & BD_ENET_TX_LC) /* Late collision */
518 fep->stats.tx_window_errors++;
519 if (status & BD_ENET_TX_RL) /* Retrans limit */
520 fep->stats.tx_aborted_errors++;
521 if (status & BD_ENET_TX_UN) /* Underrun */
522 fep->stats.tx_fifo_errors++;
523 if (status & BD_ENET_TX_CSL) /* Carrier lost */
524 fep->stats.tx_carrier_errors++;
525 } else {
526 fep->stats.tx_packets++;
527 }
528
529 #ifndef final_version
530 if (status & BD_ENET_TX_READY)
531 printk("HEY! Enet xmit interrupt and TX_READY.\n");
532 #endif
533 /* Deferred means some collisions occurred during transmit,
534 * but we eventually sent the packet OK.
535 */
536 if (status & BD_ENET_TX_DEF)
537 fep->stats.collisions++;
538
539 /* Free the sk buffer associated with this last transmit.
540 */
541 dev_kfree_skb_any(skb);
542 fep->tx_skbuff[fep->skb_dirty] = NULL;
543 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
544
545 /* Update pointer to next buffer descriptor to be transmitted.
546 */
547 if (status & BD_ENET_TX_WRAP)
548 bdp = fep->tx_bd_base;
549 else
550 bdp++;
551
552 /* Since we have freed up a buffer, the ring is no longer
553 * full.
554 */
555 if (fep->tx_full) {
556 fep->tx_full = 0;
557 if (netif_queue_stopped(dev))
558 netif_wake_queue(dev);
559 }
560 }
561 fep->dirty_tx = (cbd_t *)bdp;
562 spin_unlock(&fep->lock);
563 }
564
565
566 /* During a receive, the cur_rx points to the current incoming buffer.
567 * When we update through the ring, if the next incoming buffer has
568 * not been given to the system, we just set the empty indicator,
569 * effectively tossing the packet.
570 */
571 static void
572 fec_enet_rx(struct net_device *dev)
573 {
574 struct fec_enet_private *fep;
575 volatile fec_t *fecp;
576 volatile cbd_t *bdp;
577 unsigned short status;
578 struct sk_buff *skb;
579 ushort pkt_len;
580 __u8 *data;
581
582 #ifdef CONFIG_M532x
583 flush_cache_all();
584 #endif
585
586 fep = netdev_priv(dev);
587 fecp = (volatile fec_t*)dev->base_addr;
588
589 /* First, grab all of the stats for the incoming packet.
590 * These get messed up if we get called due to a busy condition.
591 */
592 bdp = fep->cur_rx;
593
594 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
595
596 #ifndef final_version
597 /* Since we have allocated space to hold a complete frame,
598 * the last indicator should be set.
599 */
600 if ((status & BD_ENET_RX_LAST) == 0)
601 printk("FEC ENET: rcv is not +last\n");
602 #endif
603
604 if (!fep->opened)
605 goto rx_processing_done;
606
607 /* Check for errors. */
608 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
609 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
610 fep->stats.rx_errors++;
611 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
612 /* Frame too long or too short. */
613 fep->stats.rx_length_errors++;
614 }
615 if (status & BD_ENET_RX_NO) /* Frame alignment */
616 fep->stats.rx_frame_errors++;
617 if (status & BD_ENET_RX_CR) /* CRC Error */
618 fep->stats.rx_crc_errors++;
619 if (status & BD_ENET_RX_OV) /* FIFO overrun */
620 fep->stats.rx_fifo_errors++;
621 }
622
623 /* Report late collisions as a frame error.
624 * On this error, the BD is closed, but we don't know what we
625 * have in the buffer. So, just drop this frame on the floor.
626 */
627 if (status & BD_ENET_RX_CL) {
628 fep->stats.rx_errors++;
629 fep->stats.rx_frame_errors++;
630 goto rx_processing_done;
631 }
632
633 /* Process the incoming frame.
634 */
635 fep->stats.rx_packets++;
636 pkt_len = bdp->cbd_datlen;
637 fep->stats.rx_bytes += pkt_len;
638 data = (__u8*)__va(bdp->cbd_bufaddr);
639
640 /* This does 16 byte alignment, exactly what we need.
641 * The packet length includes FCS, but we don't want to
642 * include that when passing upstream as it messes up
643 * bridging applications.
644 */
645 skb = dev_alloc_skb(pkt_len-4);
646
647 if (skb == NULL) {
648 printk("%s: Memory squeeze, dropping packet.\n", dev->name);
649 fep->stats.rx_dropped++;
650 } else {
651 skb_put(skb,pkt_len-4); /* Make room */
652 skb_copy_to_linear_data(skb, data, pkt_len-4);
653 skb->protocol=eth_type_trans(skb,dev);
654 netif_rx(skb);
655 }
656 rx_processing_done:
657
658 /* Clear the status flags for this buffer.
659 */
660 status &= ~BD_ENET_RX_STATS;
661
662 /* Mark the buffer empty.
663 */
664 status |= BD_ENET_RX_EMPTY;
665 bdp->cbd_sc = status;
666
667 /* Update BD pointer to next entry.
668 */
669 if (status & BD_ENET_RX_WRAP)
670 bdp = fep->rx_bd_base;
671 else
672 bdp++;
673
674 #if 1
675 /* Doing this here will keep the FEC running while we process
676 * incoming frames. On a heavily loaded network, we should be
677 * able to keep up at the expense of system resources.
678 */
679 fecp->fec_r_des_active = 0;
680 #endif
681 } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
682 fep->cur_rx = (cbd_t *)bdp;
683
684 #if 0
685 /* Doing this here will allow us to process all frames in the
686 * ring before the FEC is allowed to put more there. On a heavily
687 * loaded network, some frames may be lost. Unfortunately, this
688 * increases the interrupt overhead since we can potentially work
689 * our way back to the interrupt return only to come right back
690 * here.
691 */
692 fecp->fec_r_des_active = 0;
693 #endif
694 }
695
696
697 /* called from interrupt context */
698 static void
699 fec_enet_mii(struct net_device *dev)
700 {
701 struct fec_enet_private *fep;
702 volatile fec_t *ep;
703 mii_list_t *mip;
704 uint mii_reg;
705
706 fep = netdev_priv(dev);
707 ep = fep->hwp;
708 mii_reg = ep->fec_mii_data;
709
710 spin_lock(&fep->lock);
711
712 if ((mip = mii_head) == NULL) {
713 printk("MII and no head!\n");
714 goto unlock;
715 }
716
717 if (mip->mii_func != NULL)
718 (*(mip->mii_func))(mii_reg, dev);
719
720 mii_head = mip->mii_next;
721 mip->mii_next = mii_free;
722 mii_free = mip;
723
724 if ((mip = mii_head) != NULL)
725 ep->fec_mii_data = mip->mii_regval;
726
727 unlock:
728 spin_unlock(&fep->lock);
729 }
730
731 static int
732 mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
733 {
734 struct fec_enet_private *fep;
735 unsigned long flags;
736 mii_list_t *mip;
737 int retval;
738
739 /* Add PHY address to register command.
740 */
741 fep = netdev_priv(dev);
742 regval |= fep->phy_addr << 23;
743
744 retval = 0;
745
746 spin_lock_irqsave(&fep->lock,flags);
747
748 if ((mip = mii_free) != NULL) {
749 mii_free = mip->mii_next;
750 mip->mii_regval = regval;
751 mip->mii_func = func;
752 mip->mii_next = NULL;
753 if (mii_head) {
754 mii_tail->mii_next = mip;
755 mii_tail = mip;
756 }
757 else {
758 mii_head = mii_tail = mip;
759 fep->hwp->fec_mii_data = regval;
760 }
761 }
762 else {
763 retval = 1;
764 }
765
766 spin_unlock_irqrestore(&fep->lock,flags);
767
768 return(retval);
769 }
770
771 static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
772 {
773 int k;
774
775 if(!c)
776 return;
777
778 for(k = 0; (c+k)->mii_data != mk_mii_end; k++) {
779 mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
780 }
781 }
782
783 static void mii_parse_sr(uint mii_reg, struct net_device *dev)
784 {
785 struct fec_enet_private *fep = netdev_priv(dev);
786 volatile uint *s = &(fep->phy_status);
787 uint status;
788
789 status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
790
791 if (mii_reg & 0x0004)
792 status |= PHY_STAT_LINK;
793 if (mii_reg & 0x0010)
794 status |= PHY_STAT_FAULT;
795 if (mii_reg & 0x0020)
796 status |= PHY_STAT_ANC;
797
798 *s = status;
799 }
800
801 static void mii_parse_cr(uint mii_reg, struct net_device *dev)
802 {
803 struct fec_enet_private *fep = netdev_priv(dev);
804 volatile uint *s = &(fep->phy_status);
805 uint status;
806
807 status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
808
809 if (mii_reg & 0x1000)
810 status |= PHY_CONF_ANE;
811 if (mii_reg & 0x4000)
812 status |= PHY_CONF_LOOP;
813 *s = status;
814 }
815
816 static void mii_parse_anar(uint mii_reg, struct net_device *dev)
817 {
818 struct fec_enet_private *fep = netdev_priv(dev);
819 volatile uint *s = &(fep->phy_status);
820 uint status;
821
822 status = *s & ~(PHY_CONF_SPMASK);
823
824 if (mii_reg & 0x0020)
825 status |= PHY_CONF_10HDX;
826 if (mii_reg & 0x0040)
827 status |= PHY_CONF_10FDX;
828 if (mii_reg & 0x0080)
829 status |= PHY_CONF_100HDX;
830 if (mii_reg & 0x00100)
831 status |= PHY_CONF_100FDX;
832 *s = status;
833 }
834
835 /* ------------------------------------------------------------------------- */
836 /* The Level one LXT970 is used by many boards */
837
838 #define MII_LXT970_MIRROR 16 /* Mirror register */
839 #define MII_LXT970_IER 17 /* Interrupt Enable Register */
840 #define MII_LXT970_ISR 18 /* Interrupt Status Register */
841 #define MII_LXT970_CONFIG 19 /* Configuration Register */
842 #define MII_LXT970_CSR 20 /* Chip Status Register */
843
844 static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
845 {
846 struct fec_enet_private *fep = netdev_priv(dev);
847 volatile uint *s = &(fep->phy_status);
848 uint status;
849
850 status = *s & ~(PHY_STAT_SPMASK);
851 if (mii_reg & 0x0800) {
852 if (mii_reg & 0x1000)
853 status |= PHY_STAT_100FDX;
854 else
855 status |= PHY_STAT_100HDX;
856 } else {
857 if (mii_reg & 0x1000)
858 status |= PHY_STAT_10FDX;
859 else
860 status |= PHY_STAT_10HDX;
861 }
862 *s = status;
863 }
864
865 static phy_cmd_t const phy_cmd_lxt970_config[] = {
866 { mk_mii_read(MII_REG_CR), mii_parse_cr },
867 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
868 { mk_mii_end, }
869 };
870 static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
871 { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
872 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
873 { mk_mii_end, }
874 };
875 static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
876 /* read SR and ISR to acknowledge */
877 { mk_mii_read(MII_REG_SR), mii_parse_sr },
878 { mk_mii_read(MII_LXT970_ISR), NULL },
879
880 /* find out the current status */
881 { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
882 { mk_mii_end, }
883 };
884 static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
885 { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
886 { mk_mii_end, }
887 };
888 static phy_info_t const phy_info_lxt970 = {
889 .id = 0x07810000,
890 .name = "LXT970",
891 .config = phy_cmd_lxt970_config,
892 .startup = phy_cmd_lxt970_startup,
893 .ack_int = phy_cmd_lxt970_ack_int,
894 .shutdown = phy_cmd_lxt970_shutdown
895 };
896
897 /* ------------------------------------------------------------------------- */
898 /* The Level one LXT971 is used on some of my custom boards */
899
900 /* register definitions for the 971 */
901
902 #define MII_LXT971_PCR 16 /* Port Control Register */
903 #define MII_LXT971_SR2 17 /* Status Register 2 */
904 #define MII_LXT971_IER 18 /* Interrupt Enable Register */
905 #define MII_LXT971_ISR 19 /* Interrupt Status Register */
906 #define MII_LXT971_LCR 20 /* LED Control Register */
907 #define MII_LXT971_TCR 30 /* Transmit Control Register */
908
909 /*
910 * I had some nice ideas of running the MDIO faster...
911 * The 971 should support 8MHz and I tried it, but things acted really
912 * weird, so 2.5 MHz ought to be enough for anyone...
913 */
914
915 static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
916 {
917 struct fec_enet_private *fep = netdev_priv(dev);
918 volatile uint *s = &(fep->phy_status);
919 uint status;
920
921 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
922
923 if (mii_reg & 0x0400) {
924 fep->link = 1;
925 status |= PHY_STAT_LINK;
926 } else {
927 fep->link = 0;
928 }
929 if (mii_reg & 0x0080)
930 status |= PHY_STAT_ANC;
931 if (mii_reg & 0x4000) {
932 if (mii_reg & 0x0200)
933 status |= PHY_STAT_100FDX;
934 else
935 status |= PHY_STAT_100HDX;
936 } else {
937 if (mii_reg & 0x0200)
938 status |= PHY_STAT_10FDX;
939 else
940 status |= PHY_STAT_10HDX;
941 }
942 if (mii_reg & 0x0008)
943 status |= PHY_STAT_FAULT;
944
945 *s = status;
946 }
947
948 static phy_cmd_t const phy_cmd_lxt971_config[] = {
949 /* limit to 10MBit because my prototype board
950 * doesn't work with 100. */
951 { mk_mii_read(MII_REG_CR), mii_parse_cr },
952 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
953 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
954 { mk_mii_end, }
955 };
956 static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
957 { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
958 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
959 { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
960 /* Somehow does the 971 tell me that the link is down
961 * the first read after power-up.
962 * read here to get a valid value in ack_int */
963 { mk_mii_read(MII_REG_SR), mii_parse_sr },
964 { mk_mii_end, }
965 };
966 static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
967 /* acknowledge the int before reading status ! */
968 { mk_mii_read(MII_LXT971_ISR), NULL },
969 /* find out the current status */
970 { mk_mii_read(MII_REG_SR), mii_parse_sr },
971 { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
972 { mk_mii_end, }
973 };
974 static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
975 { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
976 { mk_mii_end, }
977 };
978 static phy_info_t const phy_info_lxt971 = {
979 .id = 0x0001378e,
980 .name = "LXT971",
981 .config = phy_cmd_lxt971_config,
982 .startup = phy_cmd_lxt971_startup,
983 .ack_int = phy_cmd_lxt971_ack_int,
984 .shutdown = phy_cmd_lxt971_shutdown
985 };
986
987 /* ------------------------------------------------------------------------- */
988 /* The Quality Semiconductor QS6612 is used on the RPX CLLF */
989
990 /* register definitions */
991
992 #define MII_QS6612_MCR 17 /* Mode Control Register */
993 #define MII_QS6612_FTR 27 /* Factory Test Register */
994 #define MII_QS6612_MCO 28 /* Misc. Control Register */
995 #define MII_QS6612_ISR 29 /* Interrupt Source Register */
996 #define MII_QS6612_IMR 30 /* Interrupt Mask Register */
997 #define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
998
999 static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
1000 {
1001 struct fec_enet_private *fep = netdev_priv(dev);
1002 volatile uint *s = &(fep->phy_status);
1003 uint status;
1004
1005 status = *s & ~(PHY_STAT_SPMASK);
1006
1007 switch((mii_reg >> 2) & 7) {
1008 case 1: status |= PHY_STAT_10HDX; break;
1009 case 2: status |= PHY_STAT_100HDX; break;
1010 case 5: status |= PHY_STAT_10FDX; break;
1011 case 6: status |= PHY_STAT_100FDX; break;
1012 }
1013
1014 *s = status;
1015 }
1016
1017 static phy_cmd_t const phy_cmd_qs6612_config[] = {
1018 /* The PHY powers up isolated on the RPX,
1019 * so send a command to allow operation.
1020 */
1021 { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
1022
1023 /* parse cr and anar to get some info */
1024 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1025 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1026 { mk_mii_end, }
1027 };
1028 static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
1029 { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
1030 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1031 { mk_mii_end, }
1032 };
1033 static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
1034 /* we need to read ISR, SR and ANER to acknowledge */
1035 { mk_mii_read(MII_QS6612_ISR), NULL },
1036 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1037 { mk_mii_read(MII_REG_ANER), NULL },
1038
1039 /* read pcr to get info */
1040 { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
1041 { mk_mii_end, }
1042 };
1043 static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
1044 { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
1045 { mk_mii_end, }
1046 };
1047 static phy_info_t const phy_info_qs6612 = {
1048 .id = 0x00181440,
1049 .name = "QS6612",
1050 .config = phy_cmd_qs6612_config,
1051 .startup = phy_cmd_qs6612_startup,
1052 .ack_int = phy_cmd_qs6612_ack_int,
1053 .shutdown = phy_cmd_qs6612_shutdown
1054 };
1055
1056 /* ------------------------------------------------------------------------- */
1057 /* AMD AM79C874 phy */
1058
1059 /* register definitions for the 874 */
1060
1061 #define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
1062 #define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
1063 #define MII_AM79C874_DR 18 /* Diagnostic Register */
1064 #define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
1065 #define MII_AM79C874_MCR 21 /* ModeControl Register */
1066 #define MII_AM79C874_DC 23 /* Disconnect Counter */
1067 #define MII_AM79C874_REC 24 /* Recieve Error Counter */
1068
1069 static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
1070 {
1071 struct fec_enet_private *fep = netdev_priv(dev);
1072 volatile uint *s = &(fep->phy_status);
1073 uint status;
1074
1075 status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
1076
1077 if (mii_reg & 0x0080)
1078 status |= PHY_STAT_ANC;
1079 if (mii_reg & 0x0400)
1080 status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
1081 else
1082 status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
1083
1084 *s = status;
1085 }
1086
1087 static phy_cmd_t const phy_cmd_am79c874_config[] = {
1088 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1089 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1090 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1091 { mk_mii_end, }
1092 };
1093 static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
1094 { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
1095 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1096 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1097 { mk_mii_end, }
1098 };
1099 static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
1100 /* find out the current status */
1101 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1102 { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
1103 /* we only need to read ISR to acknowledge */
1104 { mk_mii_read(MII_AM79C874_ICSR), NULL },
1105 { mk_mii_end, }
1106 };
1107 static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
1108 { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
1109 { mk_mii_end, }
1110 };
1111 static phy_info_t const phy_info_am79c874 = {
1112 .id = 0x00022561,
1113 .name = "AM79C874",
1114 .config = phy_cmd_am79c874_config,
1115 .startup = phy_cmd_am79c874_startup,
1116 .ack_int = phy_cmd_am79c874_ack_int,
1117 .shutdown = phy_cmd_am79c874_shutdown
1118 };
1119
1120
1121 /* ------------------------------------------------------------------------- */
1122 /* Kendin KS8721BL phy */
1123
1124 /* register definitions for the 8721 */
1125
1126 #define MII_KS8721BL_RXERCR 21
1127 #define MII_KS8721BL_ICSR 22
1128 #define MII_KS8721BL_PHYCR 31
1129
1130 static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
1131 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1132 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1133 { mk_mii_end, }
1134 };
1135 static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
1136 { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL },
1137 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1138 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1139 { mk_mii_end, }
1140 };
1141 static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
1142 /* find out the current status */
1143 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1144 /* we only need to read ISR to acknowledge */
1145 { mk_mii_read(MII_KS8721BL_ICSR), NULL },
1146 { mk_mii_end, }
1147 };
1148 static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
1149 { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
1150 { mk_mii_end, }
1151 };
1152 static phy_info_t const phy_info_ks8721bl = {
1153 .id = 0x00022161,
1154 .name = "KS8721BL",
1155 .config = phy_cmd_ks8721bl_config,
1156 .startup = phy_cmd_ks8721bl_startup,
1157 .ack_int = phy_cmd_ks8721bl_ack_int,
1158 .shutdown = phy_cmd_ks8721bl_shutdown
1159 };
1160
1161 /* ------------------------------------------------------------------------- */
1162 /* register definitions for the DP83848 */
1163
1164 #define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
1165
1166 static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
1167 {
1168 struct fec_enet_private *fep = dev->priv;
1169 volatile uint *s = &(fep->phy_status);
1170
1171 *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
1172
1173 /* Link up */
1174 if (mii_reg & 0x0001) {
1175 fep->link = 1;
1176 *s |= PHY_STAT_LINK;
1177 } else
1178 fep->link = 0;
1179 /* Status of link */
1180 if (mii_reg & 0x0010) /* Autonegotioation complete */
1181 *s |= PHY_STAT_ANC;
1182 if (mii_reg & 0x0002) { /* 10MBps? */
1183 if (mii_reg & 0x0004) /* Full Duplex? */
1184 *s |= PHY_STAT_10FDX;
1185 else
1186 *s |= PHY_STAT_10HDX;
1187 } else { /* 100 Mbps? */
1188 if (mii_reg & 0x0004) /* Full Duplex? */
1189 *s |= PHY_STAT_100FDX;
1190 else
1191 *s |= PHY_STAT_100HDX;
1192 }
1193 if (mii_reg & 0x0008)
1194 *s |= PHY_STAT_FAULT;
1195 }
1196
1197 static phy_info_t phy_info_dp83848= {
1198 0x020005c9,
1199 "DP83848",
1200
1201 (const phy_cmd_t []) { /* config */
1202 { mk_mii_read(MII_REG_CR), mii_parse_cr },
1203 { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
1204 { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
1205 { mk_mii_end, }
1206 },
1207 (const phy_cmd_t []) { /* startup - enable interrupts */
1208 { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
1209 { mk_mii_read(MII_REG_SR), mii_parse_sr },
1210 { mk_mii_end, }
1211 },
1212 (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
1213 { mk_mii_end, }
1214 },
1215 (const phy_cmd_t []) { /* shutdown */
1216 { mk_mii_end, }
1217 },
1218 };
1219
1220 /* ------------------------------------------------------------------------- */
1221
1222 static phy_info_t const * const phy_info[] = {
1223 &phy_info_lxt970,
1224 &phy_info_lxt971,
1225 &phy_info_qs6612,
1226 &phy_info_am79c874,
1227 &phy_info_ks8721bl,
1228 &phy_info_dp83848,
1229 NULL
1230 };
1231
1232 /* ------------------------------------------------------------------------- */
1233 #if !defined(CONFIG_M532x)
1234 #ifdef CONFIG_RPXCLASSIC
1235 static void
1236 mii_link_interrupt(void *dev_id);
1237 #else
1238 static irqreturn_t
1239 mii_link_interrupt(int irq, void * dev_id);
1240 #endif
1241 #endif
1242
1243 #if defined(CONFIG_M5272)
1244
1245 /*
1246 * Code specific to Coldfire 5272 setup.
1247 */
1248 static void __inline__ fec_request_intrs(struct net_device *dev)
1249 {
1250 volatile unsigned long *icrp;
1251 static const struct idesc {
1252 char *name;
1253 unsigned short irq;
1254 irq_handler_t handler;
1255 } *idp, id[] = {
1256 { "fec(RX)", 86, fec_enet_interrupt },
1257 { "fec(TX)", 87, fec_enet_interrupt },
1258 { "fec(OTHER)", 88, fec_enet_interrupt },
1259 { "fec(MII)", 66, mii_link_interrupt },
1260 { NULL },
1261 };
1262
1263 /* Setup interrupt handlers. */
1264 for (idp = id; idp->name; idp++) {
1265 if (request_irq(idp->irq, idp->handler, 0, idp->name, dev) != 0)
1266 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
1267 }
1268
1269 /* Unmask interrupt at ColdFire 5272 SIM */
1270 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
1271 *icrp = 0x00000ddd;
1272 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1273 *icrp = 0x0d000000;
1274 }
1275
1276 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1277 {
1278 volatile fec_t *fecp;
1279
1280 fecp = fep->hwp;
1281 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1282 fecp->fec_x_cntrl = 0x00;
1283
1284 /*
1285 * Set MII speed to 2.5 MHz
1286 * See 5272 manual section 11.5.8: MSCR
1287 */
1288 fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
1289 fecp->fec_mii_speed = fep->phy_speed;
1290
1291 fec_restart(dev, 0);
1292 }
1293
1294 static void __inline__ fec_get_mac(struct net_device *dev)
1295 {
1296 struct fec_enet_private *fep = netdev_priv(dev);
1297 volatile fec_t *fecp;
1298 unsigned char *iap, tmpaddr[ETH_ALEN];
1299
1300 fecp = fep->hwp;
1301
1302 if (FEC_FLASHMAC) {
1303 /*
1304 * Get MAC address from FLASH.
1305 * If it is all 1's or 0's, use the default.
1306 */
1307 iap = (unsigned char *)FEC_FLASHMAC;
1308 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1309 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1310 iap = fec_mac_default;
1311 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1312 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1313 iap = fec_mac_default;
1314 } else {
1315 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1316 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1317 iap = &tmpaddr[0];
1318 }
1319
1320 memcpy(dev->dev_addr, iap, ETH_ALEN);
1321
1322 /* Adjust MAC if using default MAC address */
1323 if (iap == fec_mac_default)
1324 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1325 }
1326
1327 static void __inline__ fec_enable_phy_intr(void)
1328 {
1329 }
1330
1331 static void __inline__ fec_disable_phy_intr(void)
1332 {
1333 volatile unsigned long *icrp;
1334 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1335 *icrp = 0x08000000;
1336 }
1337
1338 static void __inline__ fec_phy_ack_intr(void)
1339 {
1340 volatile unsigned long *icrp;
1341 /* Acknowledge the interrupt */
1342 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1343 *icrp = 0x0d000000;
1344 }
1345
1346 static void __inline__ fec_localhw_setup(void)
1347 {
1348 }
1349
1350 /*
1351 * Do not need to make region uncached on 5272.
1352 */
1353 static void __inline__ fec_uncache(unsigned long addr)
1354 {
1355 }
1356
1357 /* ------------------------------------------------------------------------- */
1358
1359 #elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
1360
1361 /*
1362 * Code specific to Coldfire 5230/5231/5232/5234/5235,
1363 * the 5270/5271/5274/5275 and 5280/5282 setups.
1364 */
1365 static void __inline__ fec_request_intrs(struct net_device *dev)
1366 {
1367 struct fec_enet_private *fep;
1368 int b;
1369 static const struct idesc {
1370 char *name;
1371 unsigned short irq;
1372 } *idp, id[] = {
1373 { "fec(TXF)", 23 },
1374 { "fec(TXB)", 24 },
1375 { "fec(TXFIFO)", 25 },
1376 { "fec(TXCR)", 26 },
1377 { "fec(RXF)", 27 },
1378 { "fec(RXB)", 28 },
1379 { "fec(MII)", 29 },
1380 { "fec(LC)", 30 },
1381 { "fec(HBERR)", 31 },
1382 { "fec(GRA)", 32 },
1383 { "fec(EBERR)", 33 },
1384 { "fec(BABT)", 34 },
1385 { "fec(BABR)", 35 },
1386 { NULL },
1387 };
1388
1389 fep = netdev_priv(dev);
1390 b = (fep->index) ? 128 : 64;
1391
1392 /* Setup interrupt handlers. */
1393 for (idp = id; idp->name; idp++) {
1394 if (request_irq(b+idp->irq, fec_enet_interrupt, 0, idp->name, dev) != 0)
1395 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1396 }
1397
1398 /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
1399 {
1400 volatile unsigned char *icrp;
1401 volatile unsigned long *imrp;
1402 int i, ilip;
1403
1404 b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
1405 icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
1406 MCFINTC_ICR0);
1407 for (i = 23, ilip = 0x28; (i < 36); i++)
1408 icrp[i] = ilip--;
1409
1410 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1411 MCFINTC_IMRH);
1412 *imrp &= ~0x0000000f;
1413 imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
1414 MCFINTC_IMRL);
1415 *imrp &= ~0xff800001;
1416 }
1417
1418 #if defined(CONFIG_M528x)
1419 /* Set up gpio outputs for MII lines */
1420 {
1421 volatile u16 *gpio_paspar;
1422 volatile u8 *gpio_pehlpar;
1423
1424 gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
1425 gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
1426 *gpio_paspar |= 0x0f00;
1427 *gpio_pehlpar = 0xc0;
1428 }
1429 #endif
1430
1431 #if defined(CONFIG_M527x)
1432 /* Set up gpio outputs for MII lines */
1433 {
1434 volatile u8 *gpio_par_fec;
1435 volatile u16 *gpio_par_feci2c;
1436
1437 gpio_par_feci2c = (volatile u16 *)(MCF_IPSBAR + 0x100082);
1438 /* Set up gpio outputs for FEC0 MII lines */
1439 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100078);
1440
1441 *gpio_par_feci2c |= 0x0f00;
1442 *gpio_par_fec |= 0xc0;
1443
1444 #if defined(CONFIG_FEC2)
1445 /* Set up gpio outputs for FEC1 MII lines */
1446 gpio_par_fec = (volatile u8 *)(MCF_IPSBAR + 0x100079);
1447
1448 *gpio_par_feci2c |= 0x00a0;
1449 *gpio_par_fec |= 0xc0;
1450 #endif /* CONFIG_FEC2 */
1451 }
1452 #endif /* CONFIG_M527x */
1453 }
1454
1455 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1456 {
1457 volatile fec_t *fecp;
1458
1459 fecp = fep->hwp;
1460 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1461 fecp->fec_x_cntrl = 0x00;
1462
1463 /*
1464 * Set MII speed to 2.5 MHz
1465 * See 5282 manual section 17.5.4.7: MSCR
1466 */
1467 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1468 fecp->fec_mii_speed = fep->phy_speed;
1469
1470 fec_restart(dev, 0);
1471 }
1472
1473 static void __inline__ fec_get_mac(struct net_device *dev)
1474 {
1475 struct fec_enet_private *fep = netdev_priv(dev);
1476 volatile fec_t *fecp;
1477 unsigned char *iap, tmpaddr[ETH_ALEN];
1478
1479 fecp = fep->hwp;
1480
1481 if (FEC_FLASHMAC) {
1482 /*
1483 * Get MAC address from FLASH.
1484 * If it is all 1's or 0's, use the default.
1485 */
1486 iap = FEC_FLASHMAC;
1487 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1488 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1489 iap = fec_mac_default;
1490 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1491 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1492 iap = fec_mac_default;
1493 } else {
1494 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1495 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1496 iap = &tmpaddr[0];
1497 }
1498
1499 memcpy(dev->dev_addr, iap, ETH_ALEN);
1500
1501 /* Adjust MAC if using default MAC address */
1502 if (iap == fec_mac_default)
1503 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1504 }
1505
1506 static void __inline__ fec_enable_phy_intr(void)
1507 {
1508 }
1509
1510 static void __inline__ fec_disable_phy_intr(void)
1511 {
1512 }
1513
1514 static void __inline__ fec_phy_ack_intr(void)
1515 {
1516 }
1517
1518 static void __inline__ fec_localhw_setup(void)
1519 {
1520 }
1521
1522 /*
1523 * Do not need to make region uncached on 5272.
1524 */
1525 static void __inline__ fec_uncache(unsigned long addr)
1526 {
1527 }
1528
1529 /* ------------------------------------------------------------------------- */
1530
1531 #elif defined(CONFIG_M520x)
1532
1533 /*
1534 * Code specific to Coldfire 520x
1535 */
1536 static void __inline__ fec_request_intrs(struct net_device *dev)
1537 {
1538 struct fec_enet_private *fep;
1539 int b;
1540 static const struct idesc {
1541 char *name;
1542 unsigned short irq;
1543 } *idp, id[] = {
1544 { "fec(TXF)", 23 },
1545 { "fec(TXB)", 24 },
1546 { "fec(TXFIFO)", 25 },
1547 { "fec(TXCR)", 26 },
1548 { "fec(RXF)", 27 },
1549 { "fec(RXB)", 28 },
1550 { "fec(MII)", 29 },
1551 { "fec(LC)", 30 },
1552 { "fec(HBERR)", 31 },
1553 { "fec(GRA)", 32 },
1554 { "fec(EBERR)", 33 },
1555 { "fec(BABT)", 34 },
1556 { "fec(BABR)", 35 },
1557 { NULL },
1558 };
1559
1560 fep = netdev_priv(dev);
1561 b = 64 + 13;
1562
1563 /* Setup interrupt handlers. */
1564 for (idp = id; idp->name; idp++) {
1565 if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
1566 printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
1567 }
1568
1569 /* Unmask interrupts at ColdFire interrupt controller */
1570 {
1571 volatile unsigned char *icrp;
1572 volatile unsigned long *imrp;
1573
1574 icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
1575 MCFINTC_ICR0);
1576 for (b = 36; (b < 49); b++)
1577 icrp[b] = 0x04;
1578 imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
1579 MCFINTC_IMRH);
1580 *imrp &= ~0x0001FFF0;
1581 }
1582 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
1583 *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
1584 }
1585
1586 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1587 {
1588 volatile fec_t *fecp;
1589
1590 fecp = fep->hwp;
1591 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1592 fecp->fec_x_cntrl = 0x00;
1593
1594 /*
1595 * Set MII speed to 2.5 MHz
1596 * See 5282 manual section 17.5.4.7: MSCR
1597 */
1598 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1599 fecp->fec_mii_speed = fep->phy_speed;
1600
1601 fec_restart(dev, 0);
1602 }
1603
1604 static void __inline__ fec_get_mac(struct net_device *dev)
1605 {
1606 struct fec_enet_private *fep = netdev_priv(dev);
1607 volatile fec_t *fecp;
1608 unsigned char *iap, tmpaddr[ETH_ALEN];
1609
1610 fecp = fep->hwp;
1611
1612 if (FEC_FLASHMAC) {
1613 /*
1614 * Get MAC address from FLASH.
1615 * If it is all 1's or 0's, use the default.
1616 */
1617 iap = FEC_FLASHMAC;
1618 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1619 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1620 iap = fec_mac_default;
1621 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1622 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1623 iap = fec_mac_default;
1624 } else {
1625 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1626 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1627 iap = &tmpaddr[0];
1628 }
1629
1630 memcpy(dev->dev_addr, iap, ETH_ALEN);
1631
1632 /* Adjust MAC if using default MAC address */
1633 if (iap == fec_mac_default)
1634 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1635 }
1636
1637 static void __inline__ fec_enable_phy_intr(void)
1638 {
1639 }
1640
1641 static void __inline__ fec_disable_phy_intr(void)
1642 {
1643 }
1644
1645 static void __inline__ fec_phy_ack_intr(void)
1646 {
1647 }
1648
1649 static void __inline__ fec_localhw_setup(void)
1650 {
1651 }
1652
1653 static void __inline__ fec_uncache(unsigned long addr)
1654 {
1655 }
1656
1657 /* ------------------------------------------------------------------------- */
1658
1659 #elif defined(CONFIG_M532x)
1660 /*
1661 * Code specific for M532x
1662 */
1663 static void __inline__ fec_request_intrs(struct net_device *dev)
1664 {
1665 struct fec_enet_private *fep;
1666 int b;
1667 static const struct idesc {
1668 char *name;
1669 unsigned short irq;
1670 } *idp, id[] = {
1671 { "fec(TXF)", 36 },
1672 { "fec(TXB)", 37 },
1673 { "fec(TXFIFO)", 38 },
1674 { "fec(TXCR)", 39 },
1675 { "fec(RXF)", 40 },
1676 { "fec(RXB)", 41 },
1677 { "fec(MII)", 42 },
1678 { "fec(LC)", 43 },
1679 { "fec(HBERR)", 44 },
1680 { "fec(GRA)", 45 },
1681 { "fec(EBERR)", 46 },
1682 { "fec(BABT)", 47 },
1683 { "fec(BABR)", 48 },
1684 { NULL },
1685 };
1686
1687 fep = netdev_priv(dev);
1688 b = (fep->index) ? 128 : 64;
1689
1690 /* Setup interrupt handlers. */
1691 for (idp = id; idp->name; idp++) {
1692 if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
1693 printk("FEC: Could not allocate %s IRQ(%d)!\n",
1694 idp->name, b+idp->irq);
1695 }
1696
1697 /* Unmask interrupts */
1698 MCF_INTC0_ICR36 = 0x2;
1699 MCF_INTC0_ICR37 = 0x2;
1700 MCF_INTC0_ICR38 = 0x2;
1701 MCF_INTC0_ICR39 = 0x2;
1702 MCF_INTC0_ICR40 = 0x2;
1703 MCF_INTC0_ICR41 = 0x2;
1704 MCF_INTC0_ICR42 = 0x2;
1705 MCF_INTC0_ICR43 = 0x2;
1706 MCF_INTC0_ICR44 = 0x2;
1707 MCF_INTC0_ICR45 = 0x2;
1708 MCF_INTC0_ICR46 = 0x2;
1709 MCF_INTC0_ICR47 = 0x2;
1710 MCF_INTC0_ICR48 = 0x2;
1711
1712 MCF_INTC0_IMRH &= ~(
1713 MCF_INTC_IMRH_INT_MASK36 |
1714 MCF_INTC_IMRH_INT_MASK37 |
1715 MCF_INTC_IMRH_INT_MASK38 |
1716 MCF_INTC_IMRH_INT_MASK39 |
1717 MCF_INTC_IMRH_INT_MASK40 |
1718 MCF_INTC_IMRH_INT_MASK41 |
1719 MCF_INTC_IMRH_INT_MASK42 |
1720 MCF_INTC_IMRH_INT_MASK43 |
1721 MCF_INTC_IMRH_INT_MASK44 |
1722 MCF_INTC_IMRH_INT_MASK45 |
1723 MCF_INTC_IMRH_INT_MASK46 |
1724 MCF_INTC_IMRH_INT_MASK47 |
1725 MCF_INTC_IMRH_INT_MASK48 );
1726
1727 /* Set up gpio outputs for MII lines */
1728 MCF_GPIO_PAR_FECI2C |= (0 |
1729 MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
1730 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
1731 MCF_GPIO_PAR_FEC = (0 |
1732 MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
1733 MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
1734 }
1735
1736 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1737 {
1738 volatile fec_t *fecp;
1739
1740 fecp = fep->hwp;
1741 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
1742 fecp->fec_x_cntrl = 0x00;
1743
1744 /*
1745 * Set MII speed to 2.5 MHz
1746 */
1747 fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
1748 fecp->fec_mii_speed = fep->phy_speed;
1749
1750 fec_restart(dev, 0);
1751 }
1752
1753 static void __inline__ fec_get_mac(struct net_device *dev)
1754 {
1755 struct fec_enet_private *fep = netdev_priv(dev);
1756 volatile fec_t *fecp;
1757 unsigned char *iap, tmpaddr[ETH_ALEN];
1758
1759 fecp = fep->hwp;
1760
1761 if (FEC_FLASHMAC) {
1762 /*
1763 * Get MAC address from FLASH.
1764 * If it is all 1's or 0's, use the default.
1765 */
1766 iap = FEC_FLASHMAC;
1767 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
1768 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
1769 iap = fec_mac_default;
1770 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
1771 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
1772 iap = fec_mac_default;
1773 } else {
1774 *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
1775 *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
1776 iap = &tmpaddr[0];
1777 }
1778
1779 memcpy(dev->dev_addr, iap, ETH_ALEN);
1780
1781 /* Adjust MAC if using default MAC address */
1782 if (iap == fec_mac_default)
1783 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
1784 }
1785
1786 static void __inline__ fec_enable_phy_intr(void)
1787 {
1788 }
1789
1790 static void __inline__ fec_disable_phy_intr(void)
1791 {
1792 }
1793
1794 static void __inline__ fec_phy_ack_intr(void)
1795 {
1796 }
1797
1798 static void __inline__ fec_localhw_setup(void)
1799 {
1800 }
1801
1802 /*
1803 * Do not need to make region uncached on 532x.
1804 */
1805 static void __inline__ fec_uncache(unsigned long addr)
1806 {
1807 }
1808
1809 /* ------------------------------------------------------------------------- */
1810
1811
1812 #else
1813
1814 /*
1815 * Code specific to the MPC860T setup.
1816 */
1817 static void __inline__ fec_request_intrs(struct net_device *dev)
1818 {
1819 volatile immap_t *immap;
1820
1821 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1822
1823 if (request_8xxirq(FEC_INTERRUPT, fec_enet_interrupt, 0, "fec", dev) != 0)
1824 panic("Could not allocate FEC IRQ!");
1825
1826 #ifdef CONFIG_RPXCLASSIC
1827 /* Make Port C, bit 15 an input that causes interrupts.
1828 */
1829 immap->im_ioport.iop_pcpar &= ~0x0001;
1830 immap->im_ioport.iop_pcdir &= ~0x0001;
1831 immap->im_ioport.iop_pcso &= ~0x0001;
1832 immap->im_ioport.iop_pcint |= 0x0001;
1833 cpm_install_handler(CPMVEC_PIO_PC15, mii_link_interrupt, dev);
1834
1835 /* Make LEDS reflect Link status.
1836 */
1837 *((uint *) RPX_CSR_ADDR) &= ~BCSR2_FETHLEDMODE;
1838 #endif
1839 #ifdef CONFIG_FADS
1840 if (request_8xxirq(SIU_IRQ2, mii_link_interrupt, 0, "mii", dev) != 0)
1841 panic("Could not allocate MII IRQ!");
1842 #endif
1843 }
1844
1845 static void __inline__ fec_get_mac(struct net_device *dev)
1846 {
1847 bd_t *bd;
1848
1849 bd = (bd_t *)__res;
1850 memcpy(dev->dev_addr, bd->bi_enetaddr, ETH_ALEN);
1851
1852 #ifdef CONFIG_RPXCLASSIC
1853 /* The Embedded Planet boards have only one MAC address in
1854 * the EEPROM, but can have two Ethernet ports. For the
1855 * FEC port, we create another address by setting one of
1856 * the address bits above something that would have (up to
1857 * now) been allocated.
1858 */
1859 dev->dev_adrd[3] |= 0x80;
1860 #endif
1861 }
1862
1863 static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
1864 {
1865 extern uint _get_IMMR(void);
1866 volatile immap_t *immap;
1867 volatile fec_t *fecp;
1868
1869 fecp = fep->hwp;
1870 immap = (immap_t *)IMAP_ADDR; /* pointer to internal registers */
1871
1872 /* Configure all of port D for MII.
1873 */
1874 immap->im_ioport.iop_pdpar = 0x1fff;
1875
1876 /* Bits moved from Rev. D onward.
1877 */
1878 if ((_get_IMMR() & 0xffff) < 0x0501)
1879 immap->im_ioport.iop_pddir = 0x1c58; /* Pre rev. D */
1880 else
1881 immap->im_ioport.iop_pddir = 0x1fff; /* Rev. D and later */
1882
1883 /* Set MII speed to 2.5 MHz
1884 */
1885 fecp->fec_mii_speed = fep->phy_speed =
1886 ((bd->bi_busfreq * 1000000) / 2500000) & 0x7e;
1887 }
1888
1889 static void __inline__ fec_enable_phy_intr(void)
1890 {
1891 volatile fec_t *fecp;
1892
1893 fecp = fep->hwp;
1894
1895 /* Enable MII command finished interrupt
1896 */
1897 fecp->fec_ivec = (FEC_INTERRUPT/2) << 29;
1898 }
1899
1900 static void __inline__ fec_disable_phy_intr(void)
1901 {
1902 }
1903
1904 static void __inline__ fec_phy_ack_intr(void)
1905 {
1906 }
1907
1908 static void __inline__ fec_localhw_setup(void)
1909 {
1910 volatile fec_t *fecp;
1911
1912 fecp = fep->hwp;
1913 fecp->fec_r_hash = PKT_MAXBUF_SIZE;
1914 /* Enable big endian and don't care about SDMA FC.
1915 */
1916 fecp->fec_fun_code = 0x78000000;
1917 }
1918
1919 static void __inline__ fec_uncache(unsigned long addr)
1920 {
1921 pte_t *pte;
1922 pte = va_to_pte(mem_addr);
1923 pte_val(*pte) |= _PAGE_NO_CACHE;
1924 flush_tlb_page(init_mm.mmap, mem_addr);
1925 }
1926
1927 #endif
1928
1929 /* ------------------------------------------------------------------------- */
1930
1931 static void mii_display_status(struct net_device *dev)
1932 {
1933 struct fec_enet_private *fep = netdev_priv(dev);
1934 volatile uint *s = &(fep->phy_status);
1935
1936 if (!fep->link && !fep->old_link) {
1937 /* Link is still down - don't print anything */
1938 return;
1939 }
1940
1941 printk("%s: status: ", dev->name);
1942
1943 if (!fep->link) {
1944 printk("link down");
1945 } else {
1946 printk("link up");
1947
1948 switch(*s & PHY_STAT_SPMASK) {
1949 case PHY_STAT_100FDX: printk(", 100MBit Full Duplex"); break;
1950 case PHY_STAT_100HDX: printk(", 100MBit Half Duplex"); break;
1951 case PHY_STAT_10FDX: printk(", 10MBit Full Duplex"); break;
1952 case PHY_STAT_10HDX: printk(", 10MBit Half Duplex"); break;
1953 default:
1954 printk(", Unknown speed/duplex");
1955 }
1956
1957 if (*s & PHY_STAT_ANC)
1958 printk(", auto-negotiation complete");
1959 }
1960
1961 if (*s & PHY_STAT_FAULT)
1962 printk(", remote fault");
1963
1964 printk(".\n");
1965 }
1966
1967 static void mii_display_config(struct work_struct *work)
1968 {
1969 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
1970 struct net_device *dev = fep->netdev;
1971 uint status = fep->phy_status;
1972
1973 /*
1974 ** When we get here, phy_task is already removed from
1975 ** the workqueue. It is thus safe to allow to reuse it.
1976 */
1977 fep->mii_phy_task_queued = 0;
1978 printk("%s: config: auto-negotiation ", dev->name);
1979
1980 if (status & PHY_CONF_ANE)
1981 printk("on");
1982 else
1983 printk("off");
1984
1985 if (status & PHY_CONF_100FDX)
1986 printk(", 100FDX");
1987 if (status & PHY_CONF_100HDX)
1988 printk(", 100HDX");
1989 if (status & PHY_CONF_10FDX)
1990 printk(", 10FDX");
1991 if (status & PHY_CONF_10HDX)
1992 printk(", 10HDX");
1993 if (!(status & PHY_CONF_SPMASK))
1994 printk(", No speed/duplex selected?");
1995
1996 if (status & PHY_CONF_LOOP)
1997 printk(", loopback enabled");
1998
1999 printk(".\n");
2000
2001 fep->sequence_done = 1;
2002 }
2003
2004 static void mii_relink(struct work_struct *work)
2005 {
2006 struct fec_enet_private *fep = container_of(work, struct fec_enet_private, phy_task);
2007 struct net_device *dev = fep->netdev;
2008 int duplex;
2009
2010 /*
2011 ** When we get here, phy_task is already removed from
2012 ** the workqueue. It is thus safe to allow to reuse it.
2013 */
2014 fep->mii_phy_task_queued = 0;
2015 fep->link = (fep->phy_status & PHY_STAT_LINK) ? 1 : 0;
2016 mii_display_status(dev);
2017 fep->old_link = fep->link;
2018
2019 if (fep->link) {
2020 duplex = 0;
2021 if (fep->phy_status
2022 & (PHY_STAT_100FDX | PHY_STAT_10FDX))
2023 duplex = 1;
2024 fec_restart(dev, duplex);
2025 }
2026 else
2027 fec_stop(dev);
2028
2029 #if 0
2030 enable_irq(fep->mii_irq);
2031 #endif
2032
2033 }
2034
2035 /* mii_queue_relink is called in interrupt context from mii_link_interrupt */
2036 static void mii_queue_relink(uint mii_reg, struct net_device *dev)
2037 {
2038 struct fec_enet_private *fep = netdev_priv(dev);
2039
2040 /*
2041 ** We cannot queue phy_task twice in the workqueue. It
2042 ** would cause an endless loop in the workqueue.
2043 ** Fortunately, if the last mii_relink entry has not yet been
2044 ** executed now, it will do the job for the current interrupt,
2045 ** which is just what we want.
2046 */
2047 if (fep->mii_phy_task_queued)
2048 return;
2049
2050 fep->mii_phy_task_queued = 1;
2051 INIT_WORK(&fep->phy_task, mii_relink);
2052 schedule_work(&fep->phy_task);
2053 }
2054
2055 /* mii_queue_config is called in interrupt context from fec_enet_mii */
2056 static void mii_queue_config(uint mii_reg, struct net_device *dev)
2057 {
2058 struct fec_enet_private *fep = netdev_priv(dev);
2059
2060 if (fep->mii_phy_task_queued)
2061 return;
2062
2063 fep->mii_phy_task_queued = 1;
2064 INIT_WORK(&fep->phy_task, mii_display_config);
2065 schedule_work(&fep->phy_task);
2066 }
2067
2068 phy_cmd_t const phy_cmd_relink[] = {
2069 { mk_mii_read(MII_REG_CR), mii_queue_relink },
2070 { mk_mii_end, }
2071 };
2072 phy_cmd_t const phy_cmd_config[] = {
2073 { mk_mii_read(MII_REG_CR), mii_queue_config },
2074 { mk_mii_end, }
2075 };
2076
2077 /* Read remainder of PHY ID.
2078 */
2079 static void
2080 mii_discover_phy3(uint mii_reg, struct net_device *dev)
2081 {
2082 struct fec_enet_private *fep;
2083 int i;
2084
2085 fep = netdev_priv(dev);
2086 fep->phy_id |= (mii_reg & 0xffff);
2087 printk("fec: PHY @ 0x%x, ID 0x%08x", fep->phy_addr, fep->phy_id);
2088
2089 for(i = 0; phy_info[i]; i++) {
2090 if(phy_info[i]->id == (fep->phy_id >> 4))
2091 break;
2092 }
2093
2094 if (phy_info[i])
2095 printk(" -- %s\n", phy_info[i]->name);
2096 else
2097 printk(" -- unknown PHY!\n");
2098
2099 fep->phy = phy_info[i];
2100 fep->phy_id_done = 1;
2101 }
2102
2103 /* Scan all of the MII PHY addresses looking for someone to respond
2104 * with a valid ID. This usually happens quickly.
2105 */
2106 static void
2107 mii_discover_phy(uint mii_reg, struct net_device *dev)
2108 {
2109 struct fec_enet_private *fep;
2110 volatile fec_t *fecp;
2111 uint phytype;
2112
2113 fep = netdev_priv(dev);
2114 fecp = fep->hwp;
2115
2116 if (fep->phy_addr < 32) {
2117 if ((phytype = (mii_reg & 0xffff)) != 0xffff && phytype != 0) {
2118
2119 /* Got first part of ID, now get remainder.
2120 */
2121 fep->phy_id = phytype << 16;
2122 mii_queue(dev, mk_mii_read(MII_REG_PHYIR2),
2123 mii_discover_phy3);
2124 }
2125 else {
2126 fep->phy_addr++;
2127 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1),
2128 mii_discover_phy);
2129 }
2130 } else {
2131 printk("FEC: No PHY device found.\n");
2132 /* Disable external MII interface */
2133 fecp->fec_mii_speed = fep->phy_speed = 0;
2134 fec_disable_phy_intr();
2135 }
2136 }
2137
2138 /* This interrupt occurs when the PHY detects a link change.
2139 */
2140 #ifdef CONFIG_RPXCLASSIC
2141 static void
2142 mii_link_interrupt(void *dev_id)
2143 #else
2144 static irqreturn_t
2145 mii_link_interrupt(int irq, void * dev_id)
2146 #endif
2147 {
2148 struct net_device *dev = dev_id;
2149 struct fec_enet_private *fep = netdev_priv(dev);
2150
2151 fec_phy_ack_intr();
2152
2153 #if 0
2154 disable_irq(fep->mii_irq); /* disable now, enable later */
2155 #endif
2156
2157 mii_do_cmd(dev, fep->phy->ack_int);
2158 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
2159
2160 return IRQ_HANDLED;
2161 }
2162
2163 static int
2164 fec_enet_open(struct net_device *dev)
2165 {
2166 struct fec_enet_private *fep = netdev_priv(dev);
2167
2168 /* I should reset the ring buffers here, but I don't yet know
2169 * a simple way to do that.
2170 */
2171 fec_set_mac_address(dev);
2172
2173 fep->sequence_done = 0;
2174 fep->link = 0;
2175
2176 if (fep->phy) {
2177 mii_do_cmd(dev, fep->phy->ack_int);
2178 mii_do_cmd(dev, fep->phy->config);
2179 mii_do_cmd(dev, phy_cmd_config); /* display configuration */
2180
2181 /* Poll until the PHY tells us its configuration
2182 * (not link state).
2183 * Request is initiated by mii_do_cmd above, but answer
2184 * comes by interrupt.
2185 * This should take about 25 usec per register at 2.5 MHz,
2186 * and we read approximately 5 registers.
2187 */
2188 while(!fep->sequence_done)
2189 schedule();
2190
2191 mii_do_cmd(dev, fep->phy->startup);
2192
2193 /* Set the initial link state to true. A lot of hardware
2194 * based on this device does not implement a PHY interrupt,
2195 * so we are never notified of link change.
2196 */
2197 fep->link = 1;
2198 } else {
2199 fep->link = 1; /* lets just try it and see */
2200 /* no phy, go full duplex, it's most likely a hub chip */
2201 fec_restart(dev, 1);
2202 }
2203
2204 netif_start_queue(dev);
2205 fep->opened = 1;
2206 return 0; /* Success */
2207 }
2208
2209 static int
2210 fec_enet_close(struct net_device *dev)
2211 {
2212 struct fec_enet_private *fep = netdev_priv(dev);
2213
2214 /* Don't know what to do yet.
2215 */
2216 fep->opened = 0;
2217 netif_stop_queue(dev);
2218 fec_stop(dev);
2219
2220 return 0;
2221 }
2222
2223 static struct net_device_stats *fec_enet_get_stats(struct net_device *dev)
2224 {
2225 struct fec_enet_private *fep = netdev_priv(dev);
2226
2227 return &fep->stats;
2228 }
2229
2230 /* Set or clear the multicast filter for this adaptor.
2231 * Skeleton taken from sunlance driver.
2232 * The CPM Ethernet implementation allows Multicast as well as individual
2233 * MAC address filtering. Some of the drivers check to make sure it is
2234 * a group multicast address, and discard those that are not. I guess I
2235 * will do the same for now, but just remove the test if you want
2236 * individual filtering as well (do the upper net layers want or support
2237 * this kind of feature?).
2238 */
2239
2240 #define HASH_BITS 6 /* #bits in hash */
2241 #define CRC32_POLY 0xEDB88320
2242
2243 static void set_multicast_list(struct net_device *dev)
2244 {
2245 struct fec_enet_private *fep;
2246 volatile fec_t *ep;
2247 struct dev_mc_list *dmi;
2248 unsigned int i, j, bit, data, crc;
2249 unsigned char hash;
2250
2251 fep = netdev_priv(dev);
2252 ep = fep->hwp;
2253
2254 if (dev->flags&IFF_PROMISC) {
2255 ep->fec_r_cntrl |= 0x0008;
2256 } else {
2257
2258 ep->fec_r_cntrl &= ~0x0008;
2259
2260 if (dev->flags & IFF_ALLMULTI) {
2261 /* Catch all multicast addresses, so set the
2262 * filter to all 1's.
2263 */
2264 ep->fec_hash_table_high = 0xffffffff;
2265 ep->fec_hash_table_low = 0xffffffff;
2266 } else {
2267 /* Clear filter and add the addresses in hash register.
2268 */
2269 ep->fec_hash_table_high = 0;
2270 ep->fec_hash_table_low = 0;
2271
2272 dmi = dev->mc_list;
2273
2274 for (j = 0; j < dev->mc_count; j++, dmi = dmi->next)
2275 {
2276 /* Only support group multicast for now.
2277 */
2278 if (!(dmi->dmi_addr[0] & 1))
2279 continue;
2280
2281 /* calculate crc32 value of mac address
2282 */
2283 crc = 0xffffffff;
2284
2285 for (i = 0; i < dmi->dmi_addrlen; i++)
2286 {
2287 data = dmi->dmi_addr[i];
2288 for (bit = 0; bit < 8; bit++, data >>= 1)
2289 {
2290 crc = (crc >> 1) ^
2291 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2292 }
2293 }
2294
2295 /* only upper 6 bits (HASH_BITS) are used
2296 which point to specific bit in he hash registers
2297 */
2298 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2299
2300 if (hash > 31)
2301 ep->fec_hash_table_high |= 1 << (hash - 32);
2302 else
2303 ep->fec_hash_table_low |= 1 << hash;
2304 }
2305 }
2306 }
2307 }
2308
2309 /* Set a MAC change in hardware.
2310 */
2311 static void
2312 fec_set_mac_address(struct net_device *dev)
2313 {
2314 volatile fec_t *fecp;
2315
2316 fecp = ((struct fec_enet_private *)netdev_priv(dev))->hwp;
2317
2318 /* Set station address. */
2319 fecp->fec_addr_low = dev->dev_addr[3] | (dev->dev_addr[2] << 8) |
2320 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24);
2321 fecp->fec_addr_high = (dev->dev_addr[5] << 16) |
2322 (dev->dev_addr[4] << 24);
2323
2324 }
2325
2326 /* Initialize the FEC Ethernet on 860T (or ColdFire 5272).
2327 */
2328 /*
2329 * XXX: We need to clean up on failure exits here.
2330 */
2331 int __init fec_enet_init(struct net_device *dev)
2332 {
2333 struct fec_enet_private *fep = netdev_priv(dev);
2334 unsigned long mem_addr;
2335 volatile cbd_t *bdp;
2336 cbd_t *cbd_base;
2337 volatile fec_t *fecp;
2338 int i, j;
2339 static int index = 0;
2340
2341 /* Only allow us to be probed once. */
2342 if (index >= FEC_MAX_PORTS)
2343 return -ENXIO;
2344
2345 /* Allocate memory for buffer descriptors.
2346 */
2347 mem_addr = __get_free_page(GFP_KERNEL);
2348 if (mem_addr == 0) {
2349 printk("FEC: allocate descriptor memory failed?\n");
2350 return -ENOMEM;
2351 }
2352
2353 /* Create an Ethernet device instance.
2354 */
2355 fecp = (volatile fec_t *) fec_hw[index];
2356
2357 fep->index = index;
2358 fep->hwp = fecp;
2359 fep->netdev = dev;
2360
2361 /* Whack a reset. We should wait for this.
2362 */
2363 fecp->fec_ecntrl = 1;
2364 udelay(10);
2365
2366 /* Set the Ethernet address. If using multiple Enets on the 8xx,
2367 * this needs some work to get unique addresses.
2368 *
2369 * This is our default MAC address unless the user changes
2370 * it via eth_mac_addr (our dev->set_mac_addr handler).
2371 */
2372 fec_get_mac(dev);
2373
2374 cbd_base = (cbd_t *)mem_addr;
2375 /* XXX: missing check for allocation failure */
2376
2377 fec_uncache(mem_addr);
2378
2379 /* Set receive and transmit descriptor base.
2380 */
2381 fep->rx_bd_base = cbd_base;
2382 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
2383
2384 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2385 fep->cur_rx = fep->rx_bd_base;
2386
2387 fep->skb_cur = fep->skb_dirty = 0;
2388
2389 /* Initialize the receive buffer descriptors.
2390 */
2391 bdp = fep->rx_bd_base;
2392 for (i=0; i<FEC_ENET_RX_PAGES; i++) {
2393
2394 /* Allocate a page.
2395 */
2396 mem_addr = __get_free_page(GFP_KERNEL);
2397 /* XXX: missing check for allocation failure */
2398
2399 fec_uncache(mem_addr);
2400
2401 /* Initialize the BD for every fragment in the page.
2402 */
2403 for (j=0; j<FEC_ENET_RX_FRPPG; j++) {
2404 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2405 bdp->cbd_bufaddr = __pa(mem_addr);
2406 mem_addr += FEC_ENET_RX_FRSIZE;
2407 bdp++;
2408 }
2409 }
2410
2411 /* Set the last buffer to wrap.
2412 */
2413 bdp--;
2414 bdp->cbd_sc |= BD_SC_WRAP;
2415
2416 /* ...and the same for transmmit.
2417 */
2418 bdp = fep->tx_bd_base;
2419 for (i=0, j=FEC_ENET_TX_FRPPG; i<TX_RING_SIZE; i++) {
2420 if (j >= FEC_ENET_TX_FRPPG) {
2421 mem_addr = __get_free_page(GFP_KERNEL);
2422 j = 1;
2423 } else {
2424 mem_addr += FEC_ENET_TX_FRSIZE;
2425 j++;
2426 }
2427 fep->tx_bounce[i] = (unsigned char *) mem_addr;
2428
2429 /* Initialize the BD for every fragment in the page.
2430 */
2431 bdp->cbd_sc = 0;
2432 bdp->cbd_bufaddr = 0;
2433 bdp++;
2434 }
2435
2436 /* Set the last buffer to wrap.
2437 */
2438 bdp--;
2439 bdp->cbd_sc |= BD_SC_WRAP;
2440
2441 /* Set receive and transmit descriptor base.
2442 */
2443 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2444 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2445
2446 /* Install our interrupt handlers. This varies depending on
2447 * the architecture.
2448 */
2449 fec_request_intrs(dev);
2450
2451 fecp->fec_hash_table_high = 0;
2452 fecp->fec_hash_table_low = 0;
2453 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2454 fecp->fec_ecntrl = 2;
2455 fecp->fec_r_des_active = 0;
2456
2457 dev->base_addr = (unsigned long)fecp;
2458
2459 /* The FEC Ethernet specific entries in the device structure. */
2460 dev->open = fec_enet_open;
2461 dev->hard_start_xmit = fec_enet_start_xmit;
2462 dev->tx_timeout = fec_timeout;
2463 dev->watchdog_timeo = TX_TIMEOUT;
2464 dev->stop = fec_enet_close;
2465 dev->get_stats = fec_enet_get_stats;
2466 dev->set_multicast_list = set_multicast_list;
2467
2468 for (i=0; i<NMII-1; i++)
2469 mii_cmds[i].mii_next = &mii_cmds[i+1];
2470 mii_free = mii_cmds;
2471
2472 /* setup MII interface */
2473 fec_set_mii(dev, fep);
2474
2475 /* Clear and enable interrupts */
2476 fecp->fec_ievent = 0xffc00000;
2477 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2478 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2479
2480 /* Queue up command to detect the PHY and initialize the
2481 * remainder of the interface.
2482 */
2483 fep->phy_id_done = 0;
2484 fep->phy_addr = 0;
2485 mii_queue(dev, mk_mii_read(MII_REG_PHYIR1), mii_discover_phy);
2486
2487 index++;
2488 return 0;
2489 }
2490
2491 /* This function is called to start or restart the FEC during a link
2492 * change. This only happens when switching between half and full
2493 * duplex.
2494 */
2495 static void
2496 fec_restart(struct net_device *dev, int duplex)
2497 {
2498 struct fec_enet_private *fep;
2499 volatile cbd_t *bdp;
2500 volatile fec_t *fecp;
2501 int i;
2502
2503 fep = netdev_priv(dev);
2504 fecp = fep->hwp;
2505
2506 /* Whack a reset. We should wait for this.
2507 */
2508 fecp->fec_ecntrl = 1;
2509 udelay(10);
2510
2511 /* Clear any outstanding interrupt.
2512 */
2513 fecp->fec_ievent = 0xffc00000;
2514 fec_enable_phy_intr();
2515
2516 /* Set station address.
2517 */
2518 fec_set_mac_address(dev);
2519
2520 /* Reset all multicast.
2521 */
2522 fecp->fec_hash_table_high = 0;
2523 fecp->fec_hash_table_low = 0;
2524
2525 /* Set maximum receive buffer size.
2526 */
2527 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
2528
2529 fec_localhw_setup();
2530
2531 /* Set receive and transmit descriptor base.
2532 */
2533 fecp->fec_r_des_start = __pa((uint)(fep->rx_bd_base));
2534 fecp->fec_x_des_start = __pa((uint)(fep->tx_bd_base));
2535
2536 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
2537 fep->cur_rx = fep->rx_bd_base;
2538
2539 /* Reset SKB transmit buffers.
2540 */
2541 fep->skb_cur = fep->skb_dirty = 0;
2542 for (i=0; i<=TX_RING_MOD_MASK; i++) {
2543 if (fep->tx_skbuff[i] != NULL) {
2544 dev_kfree_skb_any(fep->tx_skbuff[i]);
2545 fep->tx_skbuff[i] = NULL;
2546 }
2547 }
2548
2549 /* Initialize the receive buffer descriptors.
2550 */
2551 bdp = fep->rx_bd_base;
2552 for (i=0; i<RX_RING_SIZE; i++) {
2553
2554 /* Initialize the BD for every fragment in the page.
2555 */
2556 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2557 bdp++;
2558 }
2559
2560 /* Set the last buffer to wrap.
2561 */
2562 bdp--;
2563 bdp->cbd_sc |= BD_SC_WRAP;
2564
2565 /* ...and the same for transmmit.
2566 */
2567 bdp = fep->tx_bd_base;
2568 for (i=0; i<TX_RING_SIZE; i++) {
2569
2570 /* Initialize the BD for every fragment in the page.
2571 */
2572 bdp->cbd_sc = 0;
2573 bdp->cbd_bufaddr = 0;
2574 bdp++;
2575 }
2576
2577 /* Set the last buffer to wrap.
2578 */
2579 bdp--;
2580 bdp->cbd_sc |= BD_SC_WRAP;
2581
2582 /* Enable MII mode.
2583 */
2584 if (duplex) {
2585 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;/* MII enable */
2586 fecp->fec_x_cntrl = 0x04; /* FD enable */
2587 }
2588 else {
2589 /* MII enable|No Rcv on Xmit */
2590 fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x06;
2591 fecp->fec_x_cntrl = 0x00;
2592 }
2593 fep->full_duplex = duplex;
2594
2595 /* Set MII speed.
2596 */
2597 fecp->fec_mii_speed = fep->phy_speed;
2598
2599 /* And last, enable the transmit and receive processing.
2600 */
2601 fecp->fec_ecntrl = 2;
2602 fecp->fec_r_des_active = 0;
2603
2604 /* Enable interrupts we wish to service.
2605 */
2606 fecp->fec_imask = (FEC_ENET_TXF | FEC_ENET_TXB |
2607 FEC_ENET_RXF | FEC_ENET_RXB | FEC_ENET_MII);
2608 }
2609
2610 static void
2611 fec_stop(struct net_device *dev)
2612 {
2613 volatile fec_t *fecp;
2614 struct fec_enet_private *fep;
2615
2616 fep = netdev_priv(dev);
2617 fecp = fep->hwp;
2618
2619 /*
2620 ** We cannot expect a graceful transmit stop without link !!!
2621 */
2622 if (fep->link)
2623 {
2624 fecp->fec_x_cntrl = 0x01; /* Graceful transmit stop */
2625 udelay(10);
2626 if (!(fecp->fec_ievent & FEC_ENET_GRA))
2627 printk("fec_stop : Graceful transmit stop did not complete !\n");
2628 }
2629
2630 /* Whack a reset. We should wait for this.
2631 */
2632 fecp->fec_ecntrl = 1;
2633 udelay(10);
2634
2635 /* Clear outstanding MII command interrupts.
2636 */
2637 fecp->fec_ievent = FEC_ENET_MII;
2638 fec_enable_phy_intr();
2639
2640 fecp->fec_imask = FEC_ENET_MII;
2641 fecp->fec_mii_speed = fep->phy_speed;
2642 }
2643
2644 static int __init fec_enet_module_init(void)
2645 {
2646 struct net_device *dev;
2647 int i, j, err;
2648
2649 printk("FEC ENET Version 0.2\n");
2650
2651 for (i = 0; (i < FEC_MAX_PORTS); i++) {
2652 dev = alloc_etherdev(sizeof(struct fec_enet_private));
2653 if (!dev)
2654 return -ENOMEM;
2655 err = fec_enet_init(dev);
2656 if (err) {
2657 free_netdev(dev);
2658 continue;
2659 }
2660 if (register_netdev(dev) != 0) {
2661 /* XXX: missing cleanup here */
2662 free_netdev(dev);
2663 return -EIO;
2664 }
2665
2666 printk("%s: ethernet ", dev->name);
2667 for (j = 0; (j < 5); j++)
2668 printk("%02x:", dev->dev_addr[j]);
2669 printk("%02x\n", dev->dev_addr[5]);
2670 }
2671 return 0;
2672 }
2673
2674 module_init(fec_enet_module_init);
2675
2676 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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