drivers/net/fjes/fjes_hw.c

   1 /*
   2  *  FUJITSU Extended Socket Network Device driver
   3  *  Copyright (c) 2015 FUJITSU LIMITED
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, see <http://www.gnu.org/licenses/>.
  16  *
  17  * The full GNU General Public License is included in this distribution in
  18  * the file called "COPYING".
  19  *
  20  */
  21
  22 #include "fjes_hw.h"
  23 #include "fjes.h"
  24
  25 /* supported MTU list */
  26 const u32 fjes_support_mtu[] = {
  27         FJES_MTU_DEFINE(8 * 1024),
  28         FJES_MTU_DEFINE(16 * 1024),
  29         FJES_MTU_DEFINE(32 * 1024),
  30         FJES_MTU_DEFINE(64 * 1024),
  31         0
  32 };
  33
  34 u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg)
  35 {
  36         u8 *base = hw->base;
  37         u32 value = 0;
  38
  39         value = readl(&base[reg]);
  40
  41         return value;
  42 }
  43
  44 static u8 *fjes_hw_iomap(struct fjes_hw *hw)
  45 {
  46         u8 *base;
  47
  48         if (!request_mem_region(hw->hw_res.start, hw->hw_res.size,
  49                                 fjes_driver_name)) {
  50                 pr_err("request_mem_region failed\n");
  51                 return NULL;
  52         }
  53
  54         base = (u8 *)ioremap_nocache(hw->hw_res.start, hw->hw_res.size);
  55
  56         return base;
  57 }
  58
  59 int fjes_hw_reset(struct fjes_hw *hw)
  60 {
  61         union REG_DCTL dctl;
  62         int timeout;
  63
  64         dctl.reg = 0;
  65         dctl.bits.reset = 1;
  66         wr32(XSCT_DCTL, dctl.reg);
  67
  68         timeout = FJES_DEVICE_RESET_TIMEOUT * 1000;
  69         dctl.reg = rd32(XSCT_DCTL);
  70         while ((dctl.bits.reset == 1) && (timeout > 0)) {
  71                 msleep(1000);
  72                 dctl.reg = rd32(XSCT_DCTL);
  73                 timeout -= 1000;
  74         }
  75
  76         return timeout > 0 ? 0 : -EIO;
  77 }
  78
  79 static int fjes_hw_get_max_epid(struct fjes_hw *hw)
  80 {
  81         union REG_MAX_EP info;
  82
  83         info.reg = rd32(XSCT_MAX_EP);
  84
  85         return info.bits.maxep;
  86 }
  87
  88 static int fjes_hw_get_my_epid(struct fjes_hw *hw)
  89 {
  90         union REG_OWNER_EPID info;
  91
  92         info.reg = rd32(XSCT_OWNER_EPID);
  93
  94         return info.bits.epid;
  95 }
  96
  97 static int fjes_hw_alloc_shared_status_region(struct fjes_hw *hw)
  98 {
  99         size_t size;
 100
 101         size = sizeof(struct fjes_device_shared_info) +
 102             (sizeof(u8) * hw->max_epid);
 103         hw->hw_info.share = kzalloc(size, GFP_KERNEL);
 104         if (!hw->hw_info.share)
 105                 return -ENOMEM;
 106
 107         hw->hw_info.share->epnum = hw->max_epid;
 108
 109         return 0;
 110 }
 111
 112 static int fjes_hw_alloc_epbuf(struct epbuf_handler *epbh)
 113 {
 114         void *mem;
 115
 116         mem = vzalloc(EP_BUFFER_SIZE);
 117         if (!mem)
 118                 return -ENOMEM;
 119
 120         epbh->buffer = mem;
 121         epbh->size = EP_BUFFER_SIZE;
 122
 123         epbh->info = (union ep_buffer_info *)mem;
 124         epbh->ring = (u8 *)(mem + sizeof(union ep_buffer_info));
 125
 126         return 0;
 127 }
 128
 129 void fjes_hw_setup_epbuf(struct epbuf_handler *epbh, u8 *mac_addr, u32 mtu)
 130 {
 131         union ep_buffer_info *info = epbh->info;
 132         u16 vlan_id[EP_BUFFER_SUPPORT_VLAN_MAX];
 133         int i;
 134
 135         for (i = 0; i < EP_BUFFER_SUPPORT_VLAN_MAX; i++)
 136                 vlan_id[i] = info->v1i.vlan_id[i];
 137
 138         memset(info, 0, sizeof(union ep_buffer_info));
 139
 140         info->v1i.version = 0;  /* version 0 */
 141
 142         for (i = 0; i < ETH_ALEN; i++)
 143                 info->v1i.mac_addr[i] = mac_addr[i];
 144
 145         info->v1i.head = 0;
 146         info->v1i.tail = 1;
 147
 148         info->v1i.info_size = sizeof(union ep_buffer_info);
 149         info->v1i.buffer_size = epbh->size - info->v1i.info_size;
 150
 151         info->v1i.frame_max = FJES_MTU_TO_FRAME_SIZE(mtu);
 152         info->v1i.count_max =
 153             EP_RING_NUM(info->v1i.buffer_size, info->v1i.frame_max);
 154
 155         for (i = 0; i < EP_BUFFER_SUPPORT_VLAN_MAX; i++)
 156                 info->v1i.vlan_id[i] = vlan_id[i];
 157 }
 158
 159 void
 160 fjes_hw_init_command_registers(struct fjes_hw *hw,
 161                                struct fjes_device_command_param *param)
 162 {
 163         /* Request Buffer length */
 164         wr32(XSCT_REQBL, (__le32)(param->req_len));
 165         /* Response Buffer Length */
 166         wr32(XSCT_RESPBL, (__le32)(param->res_len));
 167
 168         /* Request Buffer Address */
 169         wr32(XSCT_REQBAL,
 170              (__le32)(param->req_start & GENMASK_ULL(31, 0)));
 171         wr32(XSCT_REQBAH,
 172              (__le32)((param->req_start & GENMASK_ULL(63, 32)) >> 32));
 173
 174         /* Response Buffer Address */
 175         wr32(XSCT_RESPBAL,
 176              (__le32)(param->res_start & GENMASK_ULL(31, 0)));
 177         wr32(XSCT_RESPBAH,
 178              (__le32)((param->res_start & GENMASK_ULL(63, 32)) >> 32));
 179
 180         /* Share status address */
 181         wr32(XSCT_SHSTSAL,
 182              (__le32)(param->share_start & GENMASK_ULL(31, 0)));
 183         wr32(XSCT_SHSTSAH,
 184              (__le32)((param->share_start & GENMASK_ULL(63, 32)) >> 32));
 185 }
 186
 187 static int fjes_hw_setup(struct fjes_hw *hw)
 188 {
 189         u8 mac[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
 190         struct fjes_device_command_param param;
 191         struct ep_share_mem_info *buf_pair;
 192         size_t mem_size;
 193         int result;
 194         int epidx;
 195         void *buf;
 196
 197         hw->hw_info.max_epid = &hw->max_epid;
 198         hw->hw_info.my_epid = &hw->my_epid;
 199
 200         buf = kcalloc(hw->max_epid, sizeof(struct ep_share_mem_info),
 201                       GFP_KERNEL);
 202         if (!buf)
 203                 return -ENOMEM;
 204
 205         hw->ep_shm_info = (struct ep_share_mem_info *)buf;
 206
 207         mem_size = FJES_DEV_REQ_BUF_SIZE(hw->max_epid);
 208         hw->hw_info.req_buf = kzalloc(mem_size, GFP_KERNEL);
 209         if (!(hw->hw_info.req_buf))
 210                 return -ENOMEM;
 211
 212         hw->hw_info.req_buf_size = mem_size;
 213
 214         mem_size = FJES_DEV_RES_BUF_SIZE(hw->max_epid);
 215         hw->hw_info.res_buf = kzalloc(mem_size, GFP_KERNEL);
 216         if (!(hw->hw_info.res_buf))
 217                 return -ENOMEM;
 218
 219         hw->hw_info.res_buf_size = mem_size;
 220
 221         result = fjes_hw_alloc_shared_status_region(hw);
 222         if (result)
 223                 return result;
 224
 225         hw->hw_info.buffer_share_bit = 0;
 226         hw->hw_info.buffer_unshare_reserve_bit = 0;
 227
 228         for (epidx = 0; epidx < hw->max_epid; epidx++) {
 229                 if (epidx != hw->my_epid) {
 230                         buf_pair = &hw->ep_shm_info[epidx];
 231
 232                         result = fjes_hw_alloc_epbuf(&buf_pair->tx);
 233                         if (result)
 234                                 return result;
 235
 236                         result = fjes_hw_alloc_epbuf(&buf_pair->rx);
 237                         if (result)
 238                                 return result;
 239
 240                         fjes_hw_setup_epbuf(&buf_pair->tx, mac,
 241                                             fjes_support_mtu[0]);
 242                         fjes_hw_setup_epbuf(&buf_pair->rx, mac,
 243                                             fjes_support_mtu[0]);
 244                 }
 245         }
 246
 247         memset(&param, 0, sizeof(param));
 248
 249         param.req_len = hw->hw_info.req_buf_size;
 250         param.req_start = __pa(hw->hw_info.req_buf);
 251         param.res_len = hw->hw_info.res_buf_size;
 252         param.res_start = __pa(hw->hw_info.res_buf);
 253
 254         param.share_start = __pa(hw->hw_info.share->ep_status);
 255
 256         fjes_hw_init_command_registers(hw, &param);
 257
 258         return 0;
 259 }
 260
 261 int fjes_hw_init(struct fjes_hw *hw)
 262 {
 263         int ret;
 264
 265         hw->base = fjes_hw_iomap(hw);
 266         if (!hw->base)
 267                 return -EIO;
 268
 269         ret = fjes_hw_reset(hw);
 270         if (ret)
 271                 return ret;
 272
 273         fjes_hw_set_irqmask(hw, REG_ICTL_MASK_ALL, true);
 274
 275         mutex_init(&hw->hw_info.lock);
 276
 277         hw->max_epid = fjes_hw_get_max_epid(hw);
 278         hw->my_epid = fjes_hw_get_my_epid(hw);
 279
 280         if ((hw->max_epid == 0) || (hw->my_epid >= hw->max_epid))
 281                 return -ENXIO;
 282
 283         ret = fjes_hw_setup(hw);
 284
 285         return ret;
 286 }
 287
 288 void fjes_hw_set_irqmask(struct fjes_hw *hw,
 289                          enum REG_ICTL_MASK intr_mask, bool mask)
 290 {
 291         if (mask)
 292                 wr32(XSCT_IMS, intr_mask);
 293         else
 294                 wr32(XSCT_IMC, intr_mask);
 295 }