2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4,5 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
92 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
93 * 0.40: 19 Jul 2005: Add support for mac address change.
94 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
96 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
97 * in the second (and later) nv_open call
98 * 0.43: 10 Aug 2005: Add support for tx checksum.
99 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
101 * 0.46: 20 Oct 2005: Add irq optimization modes.
102 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
103 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
104 * 0.49: 10 Dec 2005: Fix tso for large buffers.
105 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
106 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
107 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
108 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
109 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
110 * 0.55: 22 Mar 2006: Add flow control (pause frame).
111 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
112 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
115 * We suspect that on some hardware no TX done interrupts are generated.
116 * This means recovery from netif_stop_queue only happens if the hw timer
117 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
118 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
119 * If your hardware reliably generates tx done interrupts, then you can remove
120 * DEV_NEED_TIMERIRQ from the driver_data flags.
121 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
122 * superfluous timer interrupts from the nic.
124 #define FORCEDETH_VERSION "0.57"
125 #define DRV_NAME "forcedeth"
127 #include <linux/module.h>
128 #include <linux/types.h>
129 #include <linux/pci.h>
130 #include <linux/interrupt.h>
131 #include <linux/netdevice.h>
132 #include <linux/etherdevice.h>
133 #include <linux/delay.h>
134 #include <linux/spinlock.h>
135 #include <linux/ethtool.h>
136 #include <linux/timer.h>
137 #include <linux/skbuff.h>
138 #include <linux/mii.h>
139 #include <linux/random.h>
140 #include <linux/init.h>
141 #include <linux/if_vlan.h>
142 #include <linux/dma-mapping.h>
146 #include <asm/uaccess.h>
147 #include <asm/system.h>
150 #define dprintk printk
152 #define dprintk(x...) do { } while (0)
160 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
161 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
162 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
163 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
164 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
165 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
166 #define DEV_HAS_MSI 0x0040 /* device supports MSI */
167 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
168 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
169 #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
170 #define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
171 #define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */
174 NvRegIrqStatus
= 0x000,
175 #define NVREG_IRQSTAT_MIIEVENT 0x040
176 #define NVREG_IRQSTAT_MASK 0x1ff
177 NvRegIrqMask
= 0x004,
178 #define NVREG_IRQ_RX_ERROR 0x0001
179 #define NVREG_IRQ_RX 0x0002
180 #define NVREG_IRQ_RX_NOBUF 0x0004
181 #define NVREG_IRQ_TX_ERR 0x0008
182 #define NVREG_IRQ_TX_OK 0x0010
183 #define NVREG_IRQ_TIMER 0x0020
184 #define NVREG_IRQ_LINK 0x0040
185 #define NVREG_IRQ_RX_FORCED 0x0080
186 #define NVREG_IRQ_TX_FORCED 0x0100
187 #define NVREG_IRQMASK_THROUGHPUT 0x00df
188 #define NVREG_IRQMASK_CPU 0x0040
189 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
190 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
191 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
193 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
194 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
195 NVREG_IRQ_TX_FORCED))
197 NvRegUnknownSetupReg6
= 0x008,
198 #define NVREG_UNKSETUP6_VAL 3
201 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
202 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
204 NvRegPollingInterval
= 0x00c,
205 #define NVREG_POLL_DEFAULT_THROUGHPUT 970
206 #define NVREG_POLL_DEFAULT_CPU 13
207 NvRegMSIMap0
= 0x020,
208 NvRegMSIMap1
= 0x024,
209 NvRegMSIIrqMask
= 0x030,
210 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
212 #define NVREG_MISC1_PAUSE_TX 0x01
213 #define NVREG_MISC1_HD 0x02
214 #define NVREG_MISC1_FORCE 0x3b0f3c
216 NvRegMacReset
= 0x3c,
217 #define NVREG_MAC_RESET_ASSERT 0x0F3
218 NvRegTransmitterControl
= 0x084,
219 #define NVREG_XMITCTL_START 0x01
220 NvRegTransmitterStatus
= 0x088,
221 #define NVREG_XMITSTAT_BUSY 0x01
223 NvRegPacketFilterFlags
= 0x8c,
224 #define NVREG_PFF_PAUSE_RX 0x08
225 #define NVREG_PFF_ALWAYS 0x7F0000
226 #define NVREG_PFF_PROMISC 0x80
227 #define NVREG_PFF_MYADDR 0x20
228 #define NVREG_PFF_LOOPBACK 0x10
230 NvRegOffloadConfig
= 0x90,
231 #define NVREG_OFFLOAD_HOMEPHY 0x601
232 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
233 NvRegReceiverControl
= 0x094,
234 #define NVREG_RCVCTL_START 0x01
235 NvRegReceiverStatus
= 0x98,
236 #define NVREG_RCVSTAT_BUSY 0x01
238 NvRegRandomSeed
= 0x9c,
239 #define NVREG_RNDSEED_MASK 0x00ff
240 #define NVREG_RNDSEED_FORCE 0x7f00
241 #define NVREG_RNDSEED_FORCE2 0x2d00
242 #define NVREG_RNDSEED_FORCE3 0x7400
244 NvRegTxDeferral
= 0xA0,
245 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
246 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
247 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
248 NvRegRxDeferral
= 0xA4,
249 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
250 NvRegMacAddrA
= 0xA8,
251 NvRegMacAddrB
= 0xAC,
252 NvRegMulticastAddrA
= 0xB0,
253 #define NVREG_MCASTADDRA_FORCE 0x01
254 NvRegMulticastAddrB
= 0xB4,
255 NvRegMulticastMaskA
= 0xB8,
256 NvRegMulticastMaskB
= 0xBC,
258 NvRegPhyInterface
= 0xC0,
259 #define PHY_RGMII 0x10000000
261 NvRegTxRingPhysAddr
= 0x100,
262 NvRegRxRingPhysAddr
= 0x104,
263 NvRegRingSizes
= 0x108,
264 #define NVREG_RINGSZ_TXSHIFT 0
265 #define NVREG_RINGSZ_RXSHIFT 16
266 NvRegTransmitPoll
= 0x10c,
267 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
268 NvRegLinkSpeed
= 0x110,
269 #define NVREG_LINKSPEED_FORCE 0x10000
270 #define NVREG_LINKSPEED_10 1000
271 #define NVREG_LINKSPEED_100 100
272 #define NVREG_LINKSPEED_1000 50
273 #define NVREG_LINKSPEED_MASK (0xFFF)
274 NvRegUnknownSetupReg5
= 0x130,
275 #define NVREG_UNKSETUP5_BIT31 (1<<31)
276 NvRegTxWatermark
= 0x13c,
277 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
278 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
279 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
280 NvRegTxRxControl
= 0x144,
281 #define NVREG_TXRXCTL_KICK 0x0001
282 #define NVREG_TXRXCTL_BIT1 0x0002
283 #define NVREG_TXRXCTL_BIT2 0x0004
284 #define NVREG_TXRXCTL_IDLE 0x0008
285 #define NVREG_TXRXCTL_RESET 0x0010
286 #define NVREG_TXRXCTL_RXCHECK 0x0400
287 #define NVREG_TXRXCTL_DESC_1 0
288 #define NVREG_TXRXCTL_DESC_2 0x02100
289 #define NVREG_TXRXCTL_DESC_3 0x02200
290 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
291 #define NVREG_TXRXCTL_VLANINS 0x00080
292 NvRegTxRingPhysAddrHigh
= 0x148,
293 NvRegRxRingPhysAddrHigh
= 0x14C,
294 NvRegTxPauseFrame
= 0x170,
295 #define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080
296 #define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030
297 NvRegMIIStatus
= 0x180,
298 #define NVREG_MIISTAT_ERROR 0x0001
299 #define NVREG_MIISTAT_LINKCHANGE 0x0008
300 #define NVREG_MIISTAT_MASK 0x000f
301 #define NVREG_MIISTAT_MASK2 0x000f
302 NvRegUnknownSetupReg4
= 0x184,
303 #define NVREG_UNKSETUP4_VAL 8
305 NvRegAdapterControl
= 0x188,
306 #define NVREG_ADAPTCTL_START 0x02
307 #define NVREG_ADAPTCTL_LINKUP 0x04
308 #define NVREG_ADAPTCTL_PHYVALID 0x40000
309 #define NVREG_ADAPTCTL_RUNNING 0x100000
310 #define NVREG_ADAPTCTL_PHYSHIFT 24
311 NvRegMIISpeed
= 0x18c,
312 #define NVREG_MIISPEED_BIT8 (1<<8)
313 #define NVREG_MIIDELAY 5
314 NvRegMIIControl
= 0x190,
315 #define NVREG_MIICTL_INUSE 0x08000
316 #define NVREG_MIICTL_WRITE 0x00400
317 #define NVREG_MIICTL_ADDRSHIFT 5
318 NvRegMIIData
= 0x194,
319 NvRegWakeUpFlags
= 0x200,
320 #define NVREG_WAKEUPFLAGS_VAL 0x7770
321 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
322 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
323 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
324 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
325 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
326 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
327 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
328 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
329 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
330 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
332 NvRegPatternCRC
= 0x204,
333 NvRegPatternMask
= 0x208,
334 NvRegPowerCap
= 0x268,
335 #define NVREG_POWERCAP_D3SUPP (1<<30)
336 #define NVREG_POWERCAP_D2SUPP (1<<26)
337 #define NVREG_POWERCAP_D1SUPP (1<<25)
338 NvRegPowerState
= 0x26c,
339 #define NVREG_POWERSTATE_POWEREDUP 0x8000
340 #define NVREG_POWERSTATE_VALID 0x0100
341 #define NVREG_POWERSTATE_MASK 0x0003
342 #define NVREG_POWERSTATE_D0 0x0000
343 #define NVREG_POWERSTATE_D1 0x0001
344 #define NVREG_POWERSTATE_D2 0x0002
345 #define NVREG_POWERSTATE_D3 0x0003
347 NvRegTxZeroReXmt
= 0x284,
348 NvRegTxOneReXmt
= 0x288,
349 NvRegTxManyReXmt
= 0x28c,
350 NvRegTxLateCol
= 0x290,
351 NvRegTxUnderflow
= 0x294,
352 NvRegTxLossCarrier
= 0x298,
353 NvRegTxExcessDef
= 0x29c,
354 NvRegTxRetryErr
= 0x2a0,
355 NvRegRxFrameErr
= 0x2a4,
356 NvRegRxExtraByte
= 0x2a8,
357 NvRegRxLateCol
= 0x2ac,
359 NvRegRxFrameTooLong
= 0x2b4,
360 NvRegRxOverflow
= 0x2b8,
361 NvRegRxFCSErr
= 0x2bc,
362 NvRegRxFrameAlignErr
= 0x2c0,
363 NvRegRxLenErr
= 0x2c4,
364 NvRegRxUnicast
= 0x2c8,
365 NvRegRxMulticast
= 0x2cc,
366 NvRegRxBroadcast
= 0x2d0,
368 NvRegTxFrame
= 0x2d8,
370 NvRegTxPause
= 0x2e0,
371 NvRegRxPause
= 0x2e4,
372 NvRegRxDropFrame
= 0x2e8,
373 NvRegVlanControl
= 0x300,
374 #define NVREG_VLANCONTROL_ENABLE 0x2000
375 NvRegMSIXMap0
= 0x3e0,
376 NvRegMSIXMap1
= 0x3e4,
377 NvRegMSIXIrqStatus
= 0x3f0,
379 NvRegPowerState2
= 0x600,
380 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
381 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
384 /* Big endian: should work, but is untested */
390 struct ring_desc_ex
{
398 struct ring_desc
* orig
;
399 struct ring_desc_ex
* ex
;
402 #define FLAG_MASK_V1 0xffff0000
403 #define FLAG_MASK_V2 0xffffc000
404 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
405 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
407 #define NV_TX_LASTPACKET (1<<16)
408 #define NV_TX_RETRYERROR (1<<19)
409 #define NV_TX_FORCED_INTERRUPT (1<<24)
410 #define NV_TX_DEFERRED (1<<26)
411 #define NV_TX_CARRIERLOST (1<<27)
412 #define NV_TX_LATECOLLISION (1<<28)
413 #define NV_TX_UNDERFLOW (1<<29)
414 #define NV_TX_ERROR (1<<30)
415 #define NV_TX_VALID (1<<31)
417 #define NV_TX2_LASTPACKET (1<<29)
418 #define NV_TX2_RETRYERROR (1<<18)
419 #define NV_TX2_FORCED_INTERRUPT (1<<30)
420 #define NV_TX2_DEFERRED (1<<25)
421 #define NV_TX2_CARRIERLOST (1<<26)
422 #define NV_TX2_LATECOLLISION (1<<27)
423 #define NV_TX2_UNDERFLOW (1<<28)
424 /* error and valid are the same for both */
425 #define NV_TX2_ERROR (1<<30)
426 #define NV_TX2_VALID (1<<31)
427 #define NV_TX2_TSO (1<<28)
428 #define NV_TX2_TSO_SHIFT 14
429 #define NV_TX2_TSO_MAX_SHIFT 14
430 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
431 #define NV_TX2_CHECKSUM_L3 (1<<27)
432 #define NV_TX2_CHECKSUM_L4 (1<<26)
434 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
436 #define NV_RX_DESCRIPTORVALID (1<<16)
437 #define NV_RX_MISSEDFRAME (1<<17)
438 #define NV_RX_SUBSTRACT1 (1<<18)
439 #define NV_RX_ERROR1 (1<<23)
440 #define NV_RX_ERROR2 (1<<24)
441 #define NV_RX_ERROR3 (1<<25)
442 #define NV_RX_ERROR4 (1<<26)
443 #define NV_RX_CRCERR (1<<27)
444 #define NV_RX_OVERFLOW (1<<28)
445 #define NV_RX_FRAMINGERR (1<<29)
446 #define NV_RX_ERROR (1<<30)
447 #define NV_RX_AVAIL (1<<31)
449 #define NV_RX2_CHECKSUMMASK (0x1C000000)
450 #define NV_RX2_CHECKSUMOK1 (0x10000000)
451 #define NV_RX2_CHECKSUMOK2 (0x14000000)
452 #define NV_RX2_CHECKSUMOK3 (0x18000000)
453 #define NV_RX2_DESCRIPTORVALID (1<<29)
454 #define NV_RX2_SUBSTRACT1 (1<<25)
455 #define NV_RX2_ERROR1 (1<<18)
456 #define NV_RX2_ERROR2 (1<<19)
457 #define NV_RX2_ERROR3 (1<<20)
458 #define NV_RX2_ERROR4 (1<<21)
459 #define NV_RX2_CRCERR (1<<22)
460 #define NV_RX2_OVERFLOW (1<<23)
461 #define NV_RX2_FRAMINGERR (1<<24)
462 /* error and avail are the same for both */
463 #define NV_RX2_ERROR (1<<30)
464 #define NV_RX2_AVAIL (1<<31)
466 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
467 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
469 /* Miscelaneous hardware related defines: */
470 #define NV_PCI_REGSZ_VER1 0x270
471 #define NV_PCI_REGSZ_VER2 0x604
473 /* various timeout delays: all in usec */
474 #define NV_TXRX_RESET_DELAY 4
475 #define NV_TXSTOP_DELAY1 10
476 #define NV_TXSTOP_DELAY1MAX 500000
477 #define NV_TXSTOP_DELAY2 100
478 #define NV_RXSTOP_DELAY1 10
479 #define NV_RXSTOP_DELAY1MAX 500000
480 #define NV_RXSTOP_DELAY2 100
481 #define NV_SETUP5_DELAY 5
482 #define NV_SETUP5_DELAYMAX 50000
483 #define NV_POWERUP_DELAY 5
484 #define NV_POWERUP_DELAYMAX 5000
485 #define NV_MIIBUSY_DELAY 50
486 #define NV_MIIPHY_DELAY 10
487 #define NV_MIIPHY_DELAYMAX 10000
488 #define NV_MAC_RESET_DELAY 64
490 #define NV_WAKEUPPATTERNS 5
491 #define NV_WAKEUPMASKENTRIES 4
493 /* General driver defaults */
494 #define NV_WATCHDOG_TIMEO (5*HZ)
496 #define RX_RING_DEFAULT 128
497 #define TX_RING_DEFAULT 256
498 #define RX_RING_MIN 128
499 #define TX_RING_MIN 64
500 #define RING_MAX_DESC_VER_1 1024
501 #define RING_MAX_DESC_VER_2_3 16384
503 * Difference between the get and put pointers for the tx ring.
504 * This is used to throttle the amount of data outstanding in the
507 #define TX_LIMIT_DIFFERENCE 1
509 /* rx/tx mac addr + type + vlan + align + slack*/
510 #define NV_RX_HEADERS (64)
511 /* even more slack. */
512 #define NV_RX_ALLOC_PAD (64)
514 /* maximum mtu size */
515 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
516 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
518 #define OOM_REFILL (1+HZ/20)
519 #define POLL_WAIT (1+HZ/100)
520 #define LINK_TIMEOUT (3*HZ)
521 #define STATS_INTERVAL (10*HZ)
525 * The nic supports three different descriptor types:
526 * - DESC_VER_1: Original
527 * - DESC_VER_2: support for jumbo frames.
528 * - DESC_VER_3: 64-bit format.
535 #define PHY_OUI_MARVELL 0x5043
536 #define PHY_OUI_CICADA 0x03f1
537 #define PHYID1_OUI_MASK 0x03ff
538 #define PHYID1_OUI_SHFT 6
539 #define PHYID2_OUI_MASK 0xfc00
540 #define PHYID2_OUI_SHFT 10
541 #define PHY_INIT1 0x0f000
542 #define PHY_INIT2 0x0e00
543 #define PHY_INIT3 0x01000
544 #define PHY_INIT4 0x0200
545 #define PHY_INIT5 0x0004
546 #define PHY_INIT6 0x02000
547 #define PHY_GIGABIT 0x0100
549 #define PHY_TIMEOUT 0x1
550 #define PHY_ERROR 0x2
554 #define PHY_HALF 0x100
556 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
557 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
558 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
559 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
560 #define NV_PAUSEFRAME_RX_REQ 0x0010
561 #define NV_PAUSEFRAME_TX_REQ 0x0020
562 #define NV_PAUSEFRAME_AUTONEG 0x0040
564 /* MSI/MSI-X defines */
565 #define NV_MSI_X_MAX_VECTORS 8
566 #define NV_MSI_X_VECTORS_MASK 0x000f
567 #define NV_MSI_CAPABLE 0x0010
568 #define NV_MSI_X_CAPABLE 0x0020
569 #define NV_MSI_ENABLED 0x0040
570 #define NV_MSI_X_ENABLED 0x0080
572 #define NV_MSI_X_VECTOR_ALL 0x0
573 #define NV_MSI_X_VECTOR_RX 0x0
574 #define NV_MSI_X_VECTOR_TX 0x1
575 #define NV_MSI_X_VECTOR_OTHER 0x2
578 struct nv_ethtool_str
{
579 char name
[ETH_GSTRING_LEN
];
582 static const struct nv_ethtool_str nv_estats_str
[] = {
587 { "tx_late_collision" },
588 { "tx_fifo_errors" },
589 { "tx_carrier_errors" },
590 { "tx_excess_deferral" },
591 { "tx_retry_error" },
595 { "rx_frame_error" },
597 { "rx_late_collision" },
599 { "rx_frame_too_long" },
600 { "rx_over_errors" },
602 { "rx_frame_align_error" },
603 { "rx_length_error" },
611 { "rx_errors_total" }
614 struct nv_ethtool_stats
{
619 u64 tx_late_collision
;
621 u64 tx_carrier_errors
;
622 u64 tx_excess_deferral
;
629 u64 rx_late_collision
;
631 u64 rx_frame_too_long
;
634 u64 rx_frame_align_error
;
647 #define NV_TEST_COUNT_BASE 3
648 #define NV_TEST_COUNT_EXTENDED 4
650 static const struct nv_ethtool_str nv_etests_str
[] = {
651 { "link (online/offline)" },
652 { "register (offline) " },
653 { "interrupt (offline) " },
654 { "loopback (offline) " }
657 struct register_test
{
662 static const struct register_test nv_registers_test
[] = {
663 { NvRegUnknownSetupReg6
, 0x01 },
664 { NvRegMisc1
, 0x03c },
665 { NvRegOffloadConfig
, 0x03ff },
666 { NvRegMulticastAddrA
, 0xffffffff },
667 { NvRegTxWatermark
, 0x0ff },
668 { NvRegWakeUpFlags
, 0x07777 },
674 * All hardware access under dev->priv->lock, except the performance
676 * - rx is (pseudo-) lockless: it relies on the single-threading provided
677 * by the arch code for interrupts.
678 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
679 * needs dev->priv->lock :-(
680 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
683 /* in dev: base, irq */
688 * Locking: spin_lock(&np->lock); */
689 struct net_device_stats stats
;
690 struct nv_ethtool_stats estats
;
698 unsigned int phy_oui
;
702 /* General data: RO fields */
703 dma_addr_t ring_addr
;
704 struct pci_dev
*pci_dev
;
715 /* rx specific fields.
716 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
718 union ring_type rx_ring
;
719 unsigned int cur_rx
, refill_rx
;
720 struct sk_buff
**rx_skbuff
;
722 unsigned int rx_buf_sz
;
723 unsigned int pkt_limit
;
724 struct timer_list oom_kick
;
725 struct timer_list nic_poll
;
726 struct timer_list stats_poll
;
730 /* media detection workaround.
731 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
734 unsigned long link_timeout
;
736 * tx specific fields.
738 union ring_type tx_ring
;
739 unsigned int next_tx
, nic_tx
;
740 struct sk_buff
**tx_skbuff
;
742 unsigned int *tx_dma_len
;
749 struct vlan_group
*vlangrp
;
751 /* msi/msi-x fields */
753 struct msix_entry msi_x_entry
[NV_MSI_X_MAX_VECTORS
];
760 * Maximum number of loops until we assume that a bit in the irq mask
761 * is stuck. Overridable with module param.
763 static int max_interrupt_work
= 5;
766 * Optimization can be either throuput mode or cpu mode
768 * Throughput Mode: Every tx and rx packet will generate an interrupt.
769 * CPU Mode: Interrupts are controlled by a timer.
772 NV_OPTIMIZATION_MODE_THROUGHPUT
,
773 NV_OPTIMIZATION_MODE_CPU
775 static int optimization_mode
= NV_OPTIMIZATION_MODE_THROUGHPUT
;
778 * Poll interval for timer irq
780 * This interval determines how frequent an interrupt is generated.
781 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
782 * Min = 0, and Max = 65535
784 static int poll_interval
= -1;
793 static int msi
= NV_MSI_INT_ENABLED
;
799 NV_MSIX_INT_DISABLED
,
802 static int msix
= NV_MSIX_INT_ENABLED
;
808 NV_DMA_64BIT_DISABLED
,
811 static int dma_64bit
= NV_DMA_64BIT_ENABLED
;
813 static inline struct fe_priv
*get_nvpriv(struct net_device
*dev
)
815 return netdev_priv(dev
);
818 static inline u8 __iomem
*get_hwbase(struct net_device
*dev
)
820 return ((struct fe_priv
*)netdev_priv(dev
))->base
;
823 static inline void pci_push(u8 __iomem
*base
)
825 /* force out pending posted writes */
829 static inline u32
nv_descr_getlength(struct ring_desc
*prd
, u32 v
)
831 return le32_to_cpu(prd
->flaglen
)
832 & ((v
== DESC_VER_1
) ? LEN_MASK_V1
: LEN_MASK_V2
);
835 static inline u32
nv_descr_getlength_ex(struct ring_desc_ex
*prd
, u32 v
)
837 return le32_to_cpu(prd
->flaglen
) & LEN_MASK_V2
;
840 static int reg_delay(struct net_device
*dev
, int offset
, u32 mask
, u32 target
,
841 int delay
, int delaymax
, const char *msg
)
843 u8 __iomem
*base
= get_hwbase(dev
);
854 } while ((readl(base
+ offset
) & mask
) != target
);
858 #define NV_SETUP_RX_RING 0x01
859 #define NV_SETUP_TX_RING 0x02
861 static void setup_hw_rings(struct net_device
*dev
, int rxtx_flags
)
863 struct fe_priv
*np
= get_nvpriv(dev
);
864 u8 __iomem
*base
= get_hwbase(dev
);
866 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
867 if (rxtx_flags
& NV_SETUP_RX_RING
) {
868 writel((u32
) cpu_to_le64(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
870 if (rxtx_flags
& NV_SETUP_TX_RING
) {
871 writel((u32
) cpu_to_le64(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
874 if (rxtx_flags
& NV_SETUP_RX_RING
) {
875 writel((u32
) cpu_to_le64(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
876 writel((u32
) (cpu_to_le64(np
->ring_addr
) >> 32), base
+ NvRegRxRingPhysAddrHigh
);
878 if (rxtx_flags
& NV_SETUP_TX_RING
) {
879 writel((u32
) cpu_to_le64(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddr
);
880 writel((u32
) (cpu_to_le64(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)) >> 32), base
+ NvRegTxRingPhysAddrHigh
);
885 static void free_rings(struct net_device
*dev
)
887 struct fe_priv
*np
= get_nvpriv(dev
);
889 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
890 if (np
->rx_ring
.orig
)
891 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
892 np
->rx_ring
.orig
, np
->ring_addr
);
895 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
896 np
->rx_ring
.ex
, np
->ring_addr
);
899 kfree(np
->rx_skbuff
);
903 kfree(np
->tx_skbuff
);
907 kfree(np
->tx_dma_len
);
910 static int using_multi_irqs(struct net_device
*dev
)
912 struct fe_priv
*np
= get_nvpriv(dev
);
914 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
915 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
916 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1)))
922 static void nv_enable_irq(struct net_device
*dev
)
924 struct fe_priv
*np
= get_nvpriv(dev
);
926 if (!using_multi_irqs(dev
)) {
927 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
928 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
930 enable_irq(dev
->irq
);
932 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
933 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
934 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
938 static void nv_disable_irq(struct net_device
*dev
)
940 struct fe_priv
*np
= get_nvpriv(dev
);
942 if (!using_multi_irqs(dev
)) {
943 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
944 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
946 disable_irq(dev
->irq
);
948 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
949 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
950 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
954 /* In MSIX mode, a write to irqmask behaves as XOR */
955 static void nv_enable_hw_interrupts(struct net_device
*dev
, u32 mask
)
957 u8 __iomem
*base
= get_hwbase(dev
);
959 writel(mask
, base
+ NvRegIrqMask
);
962 static void nv_disable_hw_interrupts(struct net_device
*dev
, u32 mask
)
964 struct fe_priv
*np
= get_nvpriv(dev
);
965 u8 __iomem
*base
= get_hwbase(dev
);
967 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
968 writel(mask
, base
+ NvRegIrqMask
);
970 if (np
->msi_flags
& NV_MSI_ENABLED
)
971 writel(0, base
+ NvRegMSIIrqMask
);
972 writel(0, base
+ NvRegIrqMask
);
976 #define MII_READ (-1)
977 /* mii_rw: read/write a register on the PHY.
979 * Caller must guarantee serialization
981 static int mii_rw(struct net_device
*dev
, int addr
, int miireg
, int value
)
983 u8 __iomem
*base
= get_hwbase(dev
);
987 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
989 reg
= readl(base
+ NvRegMIIControl
);
990 if (reg
& NVREG_MIICTL_INUSE
) {
991 writel(NVREG_MIICTL_INUSE
, base
+ NvRegMIIControl
);
992 udelay(NV_MIIBUSY_DELAY
);
995 reg
= (addr
<< NVREG_MIICTL_ADDRSHIFT
) | miireg
;
996 if (value
!= MII_READ
) {
997 writel(value
, base
+ NvRegMIIData
);
998 reg
|= NVREG_MIICTL_WRITE
;
1000 writel(reg
, base
+ NvRegMIIControl
);
1002 if (reg_delay(dev
, NvRegMIIControl
, NVREG_MIICTL_INUSE
, 0,
1003 NV_MIIPHY_DELAY
, NV_MIIPHY_DELAYMAX
, NULL
)) {
1004 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d timed out.\n",
1005 dev
->name
, miireg
, addr
);
1007 } else if (value
!= MII_READ
) {
1008 /* it was a write operation - fewer failures are detectable */
1009 dprintk(KERN_DEBUG
"%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1010 dev
->name
, value
, miireg
, addr
);
1012 } else if (readl(base
+ NvRegMIIStatus
) & NVREG_MIISTAT_ERROR
) {
1013 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d failed.\n",
1014 dev
->name
, miireg
, addr
);
1017 retval
= readl(base
+ NvRegMIIData
);
1018 dprintk(KERN_DEBUG
"%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1019 dev
->name
, miireg
, addr
, retval
);
1025 static int phy_reset(struct net_device
*dev
)
1027 struct fe_priv
*np
= netdev_priv(dev
);
1029 unsigned int tries
= 0;
1031 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1032 miicontrol
|= BMCR_RESET
;
1033 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
)) {
1037 /* wait for 500ms */
1040 /* must wait till reset is deasserted */
1041 while (miicontrol
& BMCR_RESET
) {
1043 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1044 /* FIXME: 100 tries seem excessive */
1051 static int phy_init(struct net_device
*dev
)
1053 struct fe_priv
*np
= get_nvpriv(dev
);
1054 u8 __iomem
*base
= get_hwbase(dev
);
1055 u32 phyinterface
, phy_reserved
, mii_status
, mii_control
, mii_control_1000
,reg
;
1057 /* set advertise register */
1058 reg
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1059 reg
|= (ADVERTISE_10HALF
|ADVERTISE_10FULL
|ADVERTISE_100HALF
|ADVERTISE_100FULL
|ADVERTISE_PAUSE_ASYM
|ADVERTISE_PAUSE_CAP
);
1060 if (mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
)) {
1061 printk(KERN_INFO
"%s: phy write to advertise failed.\n", pci_name(np
->pci_dev
));
1065 /* get phy interface type */
1066 phyinterface
= readl(base
+ NvRegPhyInterface
);
1068 /* see if gigabit phy */
1069 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1070 if (mii_status
& PHY_GIGABIT
) {
1071 np
->gigabit
= PHY_GIGABIT
;
1072 mii_control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
1073 mii_control_1000
&= ~ADVERTISE_1000HALF
;
1074 if (phyinterface
& PHY_RGMII
)
1075 mii_control_1000
|= ADVERTISE_1000FULL
;
1077 mii_control_1000
&= ~ADVERTISE_1000FULL
;
1079 if (mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, mii_control_1000
)) {
1080 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1088 if (phy_reset(dev
)) {
1089 printk(KERN_INFO
"%s: phy reset failed\n", pci_name(np
->pci_dev
));
1093 /* phy vendor specific configuration */
1094 if ((np
->phy_oui
== PHY_OUI_CICADA
) && (phyinterface
& PHY_RGMII
) ) {
1095 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_RESV1
, MII_READ
);
1096 phy_reserved
&= ~(PHY_INIT1
| PHY_INIT2
);
1097 phy_reserved
|= (PHY_INIT3
| PHY_INIT4
);
1098 if (mii_rw(dev
, np
->phyaddr
, MII_RESV1
, phy_reserved
)) {
1099 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1102 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1103 phy_reserved
|= PHY_INIT5
;
1104 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, phy_reserved
)) {
1105 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1109 if (np
->phy_oui
== PHY_OUI_CICADA
) {
1110 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, MII_READ
);
1111 phy_reserved
|= PHY_INIT6
;
1112 if (mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, phy_reserved
)) {
1113 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1117 /* some phys clear out pause advertisment on reset, set it back */
1118 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
);
1120 /* restart auto negotiation */
1121 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1122 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
1123 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
1130 static void nv_start_rx(struct net_device
*dev
)
1132 struct fe_priv
*np
= netdev_priv(dev
);
1133 u8 __iomem
*base
= get_hwbase(dev
);
1135 dprintk(KERN_DEBUG
"%s: nv_start_rx\n", dev
->name
);
1136 /* Already running? Stop it. */
1137 if (readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) {
1138 writel(0, base
+ NvRegReceiverControl
);
1141 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1143 writel(NVREG_RCVCTL_START
, base
+ NvRegReceiverControl
);
1144 dprintk(KERN_DEBUG
"%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1145 dev
->name
, np
->duplex
, np
->linkspeed
);
1149 static void nv_stop_rx(struct net_device
*dev
)
1151 u8 __iomem
*base
= get_hwbase(dev
);
1153 dprintk(KERN_DEBUG
"%s: nv_stop_rx\n", dev
->name
);
1154 writel(0, base
+ NvRegReceiverControl
);
1155 reg_delay(dev
, NvRegReceiverStatus
, NVREG_RCVSTAT_BUSY
, 0,
1156 NV_RXSTOP_DELAY1
, NV_RXSTOP_DELAY1MAX
,
1157 KERN_INFO
"nv_stop_rx: ReceiverStatus remained busy");
1159 udelay(NV_RXSTOP_DELAY2
);
1160 writel(0, base
+ NvRegLinkSpeed
);
1163 static void nv_start_tx(struct net_device
*dev
)
1165 u8 __iomem
*base
= get_hwbase(dev
);
1167 dprintk(KERN_DEBUG
"%s: nv_start_tx\n", dev
->name
);
1168 writel(NVREG_XMITCTL_START
, base
+ NvRegTransmitterControl
);
1172 static void nv_stop_tx(struct net_device
*dev
)
1174 u8 __iomem
*base
= get_hwbase(dev
);
1176 dprintk(KERN_DEBUG
"%s: nv_stop_tx\n", dev
->name
);
1177 writel(0, base
+ NvRegTransmitterControl
);
1178 reg_delay(dev
, NvRegTransmitterStatus
, NVREG_XMITSTAT_BUSY
, 0,
1179 NV_TXSTOP_DELAY1
, NV_TXSTOP_DELAY1MAX
,
1180 KERN_INFO
"nv_stop_tx: TransmitterStatus remained busy");
1182 udelay(NV_TXSTOP_DELAY2
);
1183 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
1186 static void nv_txrx_reset(struct net_device
*dev
)
1188 struct fe_priv
*np
= netdev_priv(dev
);
1189 u8 __iomem
*base
= get_hwbase(dev
);
1191 dprintk(KERN_DEBUG
"%s: nv_txrx_reset\n", dev
->name
);
1192 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1194 udelay(NV_TXRX_RESET_DELAY
);
1195 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1199 static void nv_mac_reset(struct net_device
*dev
)
1201 struct fe_priv
*np
= netdev_priv(dev
);
1202 u8 __iomem
*base
= get_hwbase(dev
);
1204 dprintk(KERN_DEBUG
"%s: nv_mac_reset\n", dev
->name
);
1205 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1207 writel(NVREG_MAC_RESET_ASSERT
, base
+ NvRegMacReset
);
1209 udelay(NV_MAC_RESET_DELAY
);
1210 writel(0, base
+ NvRegMacReset
);
1212 udelay(NV_MAC_RESET_DELAY
);
1213 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1218 * nv_get_stats: dev->get_stats function
1219 * Get latest stats value from the nic.
1220 * Called with read_lock(&dev_base_lock) held for read -
1221 * only synchronized against unregister_netdevice.
1223 static struct net_device_stats
*nv_get_stats(struct net_device
*dev
)
1225 struct fe_priv
*np
= netdev_priv(dev
);
1227 /* It seems that the nic always generates interrupts and doesn't
1228 * accumulate errors internally. Thus the current values in np->stats
1229 * are already up to date.
1235 * nv_alloc_rx: fill rx ring entries.
1236 * Return 1 if the allocations for the skbs failed and the
1237 * rx engine is without Available descriptors
1239 static int nv_alloc_rx(struct net_device
*dev
)
1241 struct fe_priv
*np
= netdev_priv(dev
);
1242 unsigned int refill_rx
= np
->refill_rx
;
1245 while (np
->cur_rx
!= refill_rx
) {
1246 struct sk_buff
*skb
;
1248 nr
= refill_rx
% np
->rx_ring_size
;
1249 if (np
->rx_skbuff
[nr
] == NULL
) {
1251 skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1256 np
->rx_skbuff
[nr
] = skb
;
1258 skb
= np
->rx_skbuff
[nr
];
1260 np
->rx_dma
[nr
] = pci_map_single(np
->pci_dev
, skb
->data
,
1261 skb
->end
-skb
->data
, PCI_DMA_FROMDEVICE
);
1262 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1263 np
->rx_ring
.orig
[nr
].buf
= cpu_to_le32(np
->rx_dma
[nr
]);
1265 np
->rx_ring
.orig
[nr
].flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX_AVAIL
);
1267 np
->rx_ring
.ex
[nr
].bufhigh
= cpu_to_le64(np
->rx_dma
[nr
]) >> 32;
1268 np
->rx_ring
.ex
[nr
].buflow
= cpu_to_le64(np
->rx_dma
[nr
]) & 0x0FFFFFFFF;
1270 np
->rx_ring
.ex
[nr
].flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX2_AVAIL
);
1272 dprintk(KERN_DEBUG
"%s: nv_alloc_rx: Packet %d marked as Available\n",
1273 dev
->name
, refill_rx
);
1276 np
->refill_rx
= refill_rx
;
1277 if (np
->cur_rx
- refill_rx
== np
->rx_ring_size
)
1282 static void nv_do_rx_refill(unsigned long data
)
1284 struct net_device
*dev
= (struct net_device
*) data
;
1285 struct fe_priv
*np
= netdev_priv(dev
);
1287 if (!using_multi_irqs(dev
)) {
1288 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1289 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1291 disable_irq(dev
->irq
);
1293 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1295 if (nv_alloc_rx(dev
)) {
1296 spin_lock_irq(&np
->lock
);
1297 if (!np
->in_shutdown
)
1298 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1299 spin_unlock_irq(&np
->lock
);
1301 if (!using_multi_irqs(dev
)) {
1302 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1303 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1305 enable_irq(dev
->irq
);
1307 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1311 static void nv_init_rx(struct net_device
*dev
)
1313 struct fe_priv
*np
= netdev_priv(dev
);
1316 np
->cur_rx
= np
->rx_ring_size
;
1318 for (i
= 0; i
< np
->rx_ring_size
; i
++)
1319 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1320 np
->rx_ring
.orig
[i
].flaglen
= 0;
1322 np
->rx_ring
.ex
[i
].flaglen
= 0;
1325 static void nv_init_tx(struct net_device
*dev
)
1327 struct fe_priv
*np
= netdev_priv(dev
);
1330 np
->next_tx
= np
->nic_tx
= 0;
1331 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1332 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1333 np
->tx_ring
.orig
[i
].flaglen
= 0;
1335 np
->tx_ring
.ex
[i
].flaglen
= 0;
1336 np
->tx_skbuff
[i
] = NULL
;
1341 static int nv_init_ring(struct net_device
*dev
)
1345 return nv_alloc_rx(dev
);
1348 static int nv_release_txskb(struct net_device
*dev
, unsigned int skbnr
)
1350 struct fe_priv
*np
= netdev_priv(dev
);
1352 dprintk(KERN_INFO
"%s: nv_release_txskb for skbnr %d\n",
1355 if (np
->tx_dma
[skbnr
]) {
1356 pci_unmap_page(np
->pci_dev
, np
->tx_dma
[skbnr
],
1357 np
->tx_dma_len
[skbnr
],
1359 np
->tx_dma
[skbnr
] = 0;
1362 if (np
->tx_skbuff
[skbnr
]) {
1363 dev_kfree_skb_any(np
->tx_skbuff
[skbnr
]);
1364 np
->tx_skbuff
[skbnr
] = NULL
;
1371 static void nv_drain_tx(struct net_device
*dev
)
1373 struct fe_priv
*np
= netdev_priv(dev
);
1376 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1377 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1378 np
->tx_ring
.orig
[i
].flaglen
= 0;
1380 np
->tx_ring
.ex
[i
].flaglen
= 0;
1381 if (nv_release_txskb(dev
, i
))
1382 np
->stats
.tx_dropped
++;
1386 static void nv_drain_rx(struct net_device
*dev
)
1388 struct fe_priv
*np
= netdev_priv(dev
);
1390 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
1391 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1392 np
->rx_ring
.orig
[i
].flaglen
= 0;
1394 np
->rx_ring
.ex
[i
].flaglen
= 0;
1396 if (np
->rx_skbuff
[i
]) {
1397 pci_unmap_single(np
->pci_dev
, np
->rx_dma
[i
],
1398 np
->rx_skbuff
[i
]->end
-np
->rx_skbuff
[i
]->data
,
1399 PCI_DMA_FROMDEVICE
);
1400 dev_kfree_skb(np
->rx_skbuff
[i
]);
1401 np
->rx_skbuff
[i
] = NULL
;
1406 static void drain_ring(struct net_device
*dev
)
1413 * nv_start_xmit: dev->hard_start_xmit function
1414 * Called with netif_tx_lock held.
1416 static int nv_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1418 struct fe_priv
*np
= netdev_priv(dev
);
1420 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
1421 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
1422 unsigned int nr
= (np
->next_tx
- 1) % np
->tx_ring_size
;
1423 unsigned int start_nr
= np
->next_tx
% np
->tx_ring_size
;
1427 u32 size
= skb
->len
-skb
->data_len
;
1428 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
1429 u32 tx_flags_vlan
= 0;
1431 /* add fragments to entries count */
1432 for (i
= 0; i
< fragments
; i
++) {
1433 entries
+= (skb_shinfo(skb
)->frags
[i
].size
>> NV_TX2_TSO_MAX_SHIFT
) +
1434 ((skb_shinfo(skb
)->frags
[i
].size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
1437 spin_lock_irq(&np
->lock
);
1439 if ((np
->next_tx
- np
->nic_tx
+ entries
- 1) > np
->tx_limit_stop
) {
1440 spin_unlock_irq(&np
->lock
);
1441 netif_stop_queue(dev
);
1442 return NETDEV_TX_BUSY
;
1445 /* setup the header buffer */
1447 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
1448 nr
= (nr
+ 1) % np
->tx_ring_size
;
1450 np
->tx_dma
[nr
] = pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
1452 np
->tx_dma_len
[nr
] = bcnt
;
1454 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1455 np
->tx_ring
.orig
[nr
].buf
= cpu_to_le32(np
->tx_dma
[nr
]);
1456 np
->tx_ring
.orig
[nr
].flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1458 np
->tx_ring
.ex
[nr
].bufhigh
= cpu_to_le64(np
->tx_dma
[nr
]) >> 32;
1459 np
->tx_ring
.ex
[nr
].buflow
= cpu_to_le64(np
->tx_dma
[nr
]) & 0x0FFFFFFFF;
1460 np
->tx_ring
.ex
[nr
].flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1462 tx_flags
= np
->tx_flags
;
1467 /* setup the fragments */
1468 for (i
= 0; i
< fragments
; i
++) {
1469 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1470 u32 size
= frag
->size
;
1474 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
1475 nr
= (nr
+ 1) % np
->tx_ring_size
;
1477 np
->tx_dma
[nr
] = pci_map_page(np
->pci_dev
, frag
->page
, frag
->page_offset
+offset
, bcnt
,
1479 np
->tx_dma_len
[nr
] = bcnt
;
1481 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1482 np
->tx_ring
.orig
[nr
].buf
= cpu_to_le32(np
->tx_dma
[nr
]);
1483 np
->tx_ring
.orig
[nr
].flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1485 np
->tx_ring
.ex
[nr
].bufhigh
= cpu_to_le64(np
->tx_dma
[nr
]) >> 32;
1486 np
->tx_ring
.ex
[nr
].buflow
= cpu_to_le64(np
->tx_dma
[nr
]) & 0x0FFFFFFFF;
1487 np
->tx_ring
.ex
[nr
].flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1494 /* set last fragment flag */
1495 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1496 np
->tx_ring
.orig
[nr
].flaglen
|= cpu_to_le32(tx_flags_extra
);
1498 np
->tx_ring
.ex
[nr
].flaglen
|= cpu_to_le32(tx_flags_extra
);
1501 np
->tx_skbuff
[nr
] = skb
;
1504 if (skb_is_gso(skb
))
1505 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
1508 tx_flags_extra
= (skb
->ip_summed
== CHECKSUM_HW
? (NV_TX2_CHECKSUM_L3
|NV_TX2_CHECKSUM_L4
) : 0);
1511 if (np
->vlangrp
&& vlan_tx_tag_present(skb
)) {
1512 tx_flags_vlan
= NV_TX3_VLAN_TAG_PRESENT
| vlan_tx_tag_get(skb
);
1516 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1517 np
->tx_ring
.orig
[start_nr
].flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
1519 np
->tx_ring
.ex
[start_nr
].txvlan
= cpu_to_le32(tx_flags_vlan
);
1520 np
->tx_ring
.ex
[start_nr
].flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
1523 dprintk(KERN_DEBUG
"%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1524 dev
->name
, np
->next_tx
, entries
, tx_flags_extra
);
1527 for (j
=0; j
<64; j
++) {
1529 dprintk("\n%03x:", j
);
1530 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
1535 np
->next_tx
+= entries
;
1537 dev
->trans_start
= jiffies
;
1538 spin_unlock_irq(&np
->lock
);
1539 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
1540 pci_push(get_hwbase(dev
));
1541 return NETDEV_TX_OK
;
1545 * nv_tx_done: check for completed packets, release the skbs.
1547 * Caller must own np->lock.
1549 static void nv_tx_done(struct net_device
*dev
)
1551 struct fe_priv
*np
= netdev_priv(dev
);
1554 struct sk_buff
*skb
;
1556 while (np
->nic_tx
!= np
->next_tx
) {
1557 i
= np
->nic_tx
% np
->tx_ring_size
;
1559 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1560 flags
= le32_to_cpu(np
->tx_ring
.orig
[i
].flaglen
);
1562 flags
= le32_to_cpu(np
->tx_ring
.ex
[i
].flaglen
);
1564 dprintk(KERN_DEBUG
"%s: nv_tx_done: looking at packet %d, flags 0x%x.\n",
1565 dev
->name
, np
->nic_tx
, flags
);
1566 if (flags
& NV_TX_VALID
)
1568 if (np
->desc_ver
== DESC_VER_1
) {
1569 if (flags
& NV_TX_LASTPACKET
) {
1570 skb
= np
->tx_skbuff
[i
];
1571 if (flags
& (NV_TX_RETRYERROR
|NV_TX_CARRIERLOST
|NV_TX_LATECOLLISION
|
1572 NV_TX_UNDERFLOW
|NV_TX_ERROR
)) {
1573 if (flags
& NV_TX_UNDERFLOW
)
1574 np
->stats
.tx_fifo_errors
++;
1575 if (flags
& NV_TX_CARRIERLOST
)
1576 np
->stats
.tx_carrier_errors
++;
1577 np
->stats
.tx_errors
++;
1579 np
->stats
.tx_packets
++;
1580 np
->stats
.tx_bytes
+= skb
->len
;
1584 if (flags
& NV_TX2_LASTPACKET
) {
1585 skb
= np
->tx_skbuff
[i
];
1586 if (flags
& (NV_TX2_RETRYERROR
|NV_TX2_CARRIERLOST
|NV_TX2_LATECOLLISION
|
1587 NV_TX2_UNDERFLOW
|NV_TX2_ERROR
)) {
1588 if (flags
& NV_TX2_UNDERFLOW
)
1589 np
->stats
.tx_fifo_errors
++;
1590 if (flags
& NV_TX2_CARRIERLOST
)
1591 np
->stats
.tx_carrier_errors
++;
1592 np
->stats
.tx_errors
++;
1594 np
->stats
.tx_packets
++;
1595 np
->stats
.tx_bytes
+= skb
->len
;
1599 nv_release_txskb(dev
, i
);
1602 if (np
->next_tx
- np
->nic_tx
< np
->tx_limit_start
)
1603 netif_wake_queue(dev
);
1607 * nv_tx_timeout: dev->tx_timeout function
1608 * Called with netif_tx_lock held.
1610 static void nv_tx_timeout(struct net_device
*dev
)
1612 struct fe_priv
*np
= netdev_priv(dev
);
1613 u8 __iomem
*base
= get_hwbase(dev
);
1616 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1617 status
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
1619 status
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
1621 printk(KERN_INFO
"%s: Got tx_timeout. irq: %08x\n", dev
->name
, status
);
1626 printk(KERN_INFO
"%s: Ring at %lx: next %d nic %d\n",
1627 dev
->name
, (unsigned long)np
->ring_addr
,
1628 np
->next_tx
, np
->nic_tx
);
1629 printk(KERN_INFO
"%s: Dumping tx registers\n", dev
->name
);
1630 for (i
=0;i
<=np
->register_size
;i
+= 32) {
1631 printk(KERN_INFO
"%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1633 readl(base
+ i
+ 0), readl(base
+ i
+ 4),
1634 readl(base
+ i
+ 8), readl(base
+ i
+ 12),
1635 readl(base
+ i
+ 16), readl(base
+ i
+ 20),
1636 readl(base
+ i
+ 24), readl(base
+ i
+ 28));
1638 printk(KERN_INFO
"%s: Dumping tx ring\n", dev
->name
);
1639 for (i
=0;i
<np
->tx_ring_size
;i
+= 4) {
1640 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1641 printk(KERN_INFO
"%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1643 le32_to_cpu(np
->tx_ring
.orig
[i
].buf
),
1644 le32_to_cpu(np
->tx_ring
.orig
[i
].flaglen
),
1645 le32_to_cpu(np
->tx_ring
.orig
[i
+1].buf
),
1646 le32_to_cpu(np
->tx_ring
.orig
[i
+1].flaglen
),
1647 le32_to_cpu(np
->tx_ring
.orig
[i
+2].buf
),
1648 le32_to_cpu(np
->tx_ring
.orig
[i
+2].flaglen
),
1649 le32_to_cpu(np
->tx_ring
.orig
[i
+3].buf
),
1650 le32_to_cpu(np
->tx_ring
.orig
[i
+3].flaglen
));
1652 printk(KERN_INFO
"%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1654 le32_to_cpu(np
->tx_ring
.ex
[i
].bufhigh
),
1655 le32_to_cpu(np
->tx_ring
.ex
[i
].buflow
),
1656 le32_to_cpu(np
->tx_ring
.ex
[i
].flaglen
),
1657 le32_to_cpu(np
->tx_ring
.ex
[i
+1].bufhigh
),
1658 le32_to_cpu(np
->tx_ring
.ex
[i
+1].buflow
),
1659 le32_to_cpu(np
->tx_ring
.ex
[i
+1].flaglen
),
1660 le32_to_cpu(np
->tx_ring
.ex
[i
+2].bufhigh
),
1661 le32_to_cpu(np
->tx_ring
.ex
[i
+2].buflow
),
1662 le32_to_cpu(np
->tx_ring
.ex
[i
+2].flaglen
),
1663 le32_to_cpu(np
->tx_ring
.ex
[i
+3].bufhigh
),
1664 le32_to_cpu(np
->tx_ring
.ex
[i
+3].buflow
),
1665 le32_to_cpu(np
->tx_ring
.ex
[i
+3].flaglen
));
1670 spin_lock_irq(&np
->lock
);
1672 /* 1) stop tx engine */
1675 /* 2) check that the packets were not sent already: */
1678 /* 3) if there are dead entries: clear everything */
1679 if (np
->next_tx
!= np
->nic_tx
) {
1680 printk(KERN_DEBUG
"%s: tx_timeout: dead entries!\n", dev
->name
);
1682 np
->next_tx
= np
->nic_tx
= 0;
1683 setup_hw_rings(dev
, NV_SETUP_TX_RING
);
1684 netif_wake_queue(dev
);
1687 /* 4) restart tx engine */
1689 spin_unlock_irq(&np
->lock
);
1693 * Called when the nic notices a mismatch between the actual data len on the
1694 * wire and the len indicated in the 802 header
1696 static int nv_getlen(struct net_device
*dev
, void *packet
, int datalen
)
1698 int hdrlen
; /* length of the 802 header */
1699 int protolen
; /* length as stored in the proto field */
1701 /* 1) calculate len according to header */
1702 if ( ((struct vlan_ethhdr
*)packet
)->h_vlan_proto
== htons(ETH_P_8021Q
)) {
1703 protolen
= ntohs( ((struct vlan_ethhdr
*)packet
)->h_vlan_encapsulated_proto
);
1706 protolen
= ntohs( ((struct ethhdr
*)packet
)->h_proto
);
1709 dprintk(KERN_DEBUG
"%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1710 dev
->name
, datalen
, protolen
, hdrlen
);
1711 if (protolen
> ETH_DATA_LEN
)
1712 return datalen
; /* Value in proto field not a len, no checks possible */
1715 /* consistency checks: */
1716 if (datalen
> ETH_ZLEN
) {
1717 if (datalen
>= protolen
) {
1718 /* more data on wire than in 802 header, trim of
1721 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
1722 dev
->name
, protolen
);
1725 /* less data on wire than mentioned in header.
1726 * Discard the packet.
1728 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding long packet.\n",
1733 /* short packet. Accept only if 802 values are also short */
1734 if (protolen
> ETH_ZLEN
) {
1735 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding short packet.\n",
1739 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
1740 dev
->name
, datalen
);
1745 static void nv_rx_process(struct net_device
*dev
)
1747 struct fe_priv
*np
= netdev_priv(dev
);
1752 struct sk_buff
*skb
;
1755 if (np
->cur_rx
- np
->refill_rx
>= np
->rx_ring_size
)
1756 break; /* we scanned the whole ring - do not continue */
1758 i
= np
->cur_rx
% np
->rx_ring_size
;
1759 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1760 flags
= le32_to_cpu(np
->rx_ring
.orig
[i
].flaglen
);
1761 len
= nv_descr_getlength(&np
->rx_ring
.orig
[i
], np
->desc_ver
);
1763 flags
= le32_to_cpu(np
->rx_ring
.ex
[i
].flaglen
);
1764 len
= nv_descr_getlength_ex(&np
->rx_ring
.ex
[i
], np
->desc_ver
);
1765 vlanflags
= le32_to_cpu(np
->rx_ring
.ex
[i
].buflow
);
1768 dprintk(KERN_DEBUG
"%s: nv_rx_process: looking at packet %d, flags 0x%x.\n",
1769 dev
->name
, np
->cur_rx
, flags
);
1771 if (flags
& NV_RX_AVAIL
)
1772 break; /* still owned by hardware, */
1775 * the packet is for us - immediately tear down the pci mapping.
1776 * TODO: check if a prefetch of the first cacheline improves
1779 pci_unmap_single(np
->pci_dev
, np
->rx_dma
[i
],
1780 np
->rx_skbuff
[i
]->end
-np
->rx_skbuff
[i
]->data
,
1781 PCI_DMA_FROMDEVICE
);
1785 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",flags
);
1786 for (j
=0; j
<64; j
++) {
1788 dprintk("\n%03x:", j
);
1789 dprintk(" %02x", ((unsigned char*)np
->rx_skbuff
[i
]->data
)[j
]);
1793 /* look at what we actually got: */
1794 if (np
->desc_ver
== DESC_VER_1
) {
1795 if (!(flags
& NV_RX_DESCRIPTORVALID
))
1798 if (flags
& NV_RX_ERROR
) {
1799 if (flags
& NV_RX_MISSEDFRAME
) {
1800 np
->stats
.rx_missed_errors
++;
1801 np
->stats
.rx_errors
++;
1804 if (flags
& (NV_RX_ERROR1
|NV_RX_ERROR2
|NV_RX_ERROR3
)) {
1805 np
->stats
.rx_errors
++;
1808 if (flags
& NV_RX_CRCERR
) {
1809 np
->stats
.rx_crc_errors
++;
1810 np
->stats
.rx_errors
++;
1813 if (flags
& NV_RX_OVERFLOW
) {
1814 np
->stats
.rx_over_errors
++;
1815 np
->stats
.rx_errors
++;
1818 if (flags
& NV_RX_ERROR4
) {
1819 len
= nv_getlen(dev
, np
->rx_skbuff
[i
]->data
, len
);
1821 np
->stats
.rx_errors
++;
1825 /* framing errors are soft errors. */
1826 if (flags
& NV_RX_FRAMINGERR
) {
1827 if (flags
& NV_RX_SUBSTRACT1
) {
1833 if (!(flags
& NV_RX2_DESCRIPTORVALID
))
1836 if (flags
& NV_RX2_ERROR
) {
1837 if (flags
& (NV_RX2_ERROR1
|NV_RX2_ERROR2
|NV_RX2_ERROR3
)) {
1838 np
->stats
.rx_errors
++;
1841 if (flags
& NV_RX2_CRCERR
) {
1842 np
->stats
.rx_crc_errors
++;
1843 np
->stats
.rx_errors
++;
1846 if (flags
& NV_RX2_OVERFLOW
) {
1847 np
->stats
.rx_over_errors
++;
1848 np
->stats
.rx_errors
++;
1851 if (flags
& NV_RX2_ERROR4
) {
1852 len
= nv_getlen(dev
, np
->rx_skbuff
[i
]->data
, len
);
1854 np
->stats
.rx_errors
++;
1858 /* framing errors are soft errors */
1859 if (flags
& NV_RX2_FRAMINGERR
) {
1860 if (flags
& NV_RX2_SUBSTRACT1
) {
1865 if (np
->txrxctl_bits
& NVREG_TXRXCTL_RXCHECK
) {
1866 flags
&= NV_RX2_CHECKSUMMASK
;
1867 if (flags
== NV_RX2_CHECKSUMOK1
||
1868 flags
== NV_RX2_CHECKSUMOK2
||
1869 flags
== NV_RX2_CHECKSUMOK3
) {
1870 dprintk(KERN_DEBUG
"%s: hw checksum hit!.\n", dev
->name
);
1871 np
->rx_skbuff
[i
]->ip_summed
= CHECKSUM_UNNECESSARY
;
1873 dprintk(KERN_DEBUG
"%s: hwchecksum miss!.\n", dev
->name
);
1877 /* got a valid packet - forward it to the network core */
1878 skb
= np
->rx_skbuff
[i
];
1879 np
->rx_skbuff
[i
] = NULL
;
1882 skb
->protocol
= eth_type_trans(skb
, dev
);
1883 dprintk(KERN_DEBUG
"%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1884 dev
->name
, np
->cur_rx
, len
, skb
->protocol
);
1885 if (np
->vlangrp
&& (vlanflags
& NV_RX3_VLAN_TAG_PRESENT
)) {
1886 vlan_hwaccel_rx(skb
, np
->vlangrp
, vlanflags
& NV_RX3_VLAN_TAG_MASK
);
1890 dev
->last_rx
= jiffies
;
1891 np
->stats
.rx_packets
++;
1892 np
->stats
.rx_bytes
+= len
;
1898 static void set_bufsize(struct net_device
*dev
)
1900 struct fe_priv
*np
= netdev_priv(dev
);
1902 if (dev
->mtu
<= ETH_DATA_LEN
)
1903 np
->rx_buf_sz
= ETH_DATA_LEN
+ NV_RX_HEADERS
;
1905 np
->rx_buf_sz
= dev
->mtu
+ NV_RX_HEADERS
;
1909 * nv_change_mtu: dev->change_mtu function
1910 * Called with dev_base_lock held for read.
1912 static int nv_change_mtu(struct net_device
*dev
, int new_mtu
)
1914 struct fe_priv
*np
= netdev_priv(dev
);
1917 if (new_mtu
< 64 || new_mtu
> np
->pkt_limit
)
1923 /* return early if the buffer sizes will not change */
1924 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
1926 if (old_mtu
== new_mtu
)
1929 /* synchronized against open : rtnl_lock() held by caller */
1930 if (netif_running(dev
)) {
1931 u8 __iomem
*base
= get_hwbase(dev
);
1933 * It seems that the nic preloads valid ring entries into an
1934 * internal buffer. The procedure for flushing everything is
1935 * guessed, there is probably a simpler approach.
1936 * Changing the MTU is a rare event, it shouldn't matter.
1938 nv_disable_irq(dev
);
1939 netif_tx_lock_bh(dev
);
1940 spin_lock(&np
->lock
);
1945 /* drain rx queue */
1948 /* reinit driver view of the rx queue */
1950 if (nv_init_ring(dev
)) {
1951 if (!np
->in_shutdown
)
1952 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1954 /* reinit nic view of the rx queue */
1955 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
1956 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
1957 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
1958 base
+ NvRegRingSizes
);
1960 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
1963 /* restart rx engine */
1966 spin_unlock(&np
->lock
);
1967 netif_tx_unlock_bh(dev
);
1973 static void nv_copy_mac_to_hw(struct net_device
*dev
)
1975 u8 __iomem
*base
= get_hwbase(dev
);
1978 mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
1979 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
1980 mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
1982 writel(mac
[0], base
+ NvRegMacAddrA
);
1983 writel(mac
[1], base
+ NvRegMacAddrB
);
1987 * nv_set_mac_address: dev->set_mac_address function
1988 * Called with rtnl_lock() held.
1990 static int nv_set_mac_address(struct net_device
*dev
, void *addr
)
1992 struct fe_priv
*np
= netdev_priv(dev
);
1993 struct sockaddr
*macaddr
= (struct sockaddr
*)addr
;
1995 if (!is_valid_ether_addr(macaddr
->sa_data
))
1996 return -EADDRNOTAVAIL
;
1998 /* synchronized against open : rtnl_lock() held by caller */
1999 memcpy(dev
->dev_addr
, macaddr
->sa_data
, ETH_ALEN
);
2001 if (netif_running(dev
)) {
2002 netif_tx_lock_bh(dev
);
2003 spin_lock_irq(&np
->lock
);
2005 /* stop rx engine */
2008 /* set mac address */
2009 nv_copy_mac_to_hw(dev
);
2011 /* restart rx engine */
2013 spin_unlock_irq(&np
->lock
);
2014 netif_tx_unlock_bh(dev
);
2016 nv_copy_mac_to_hw(dev
);
2022 * nv_set_multicast: dev->set_multicast function
2023 * Called with netif_tx_lock held.
2025 static void nv_set_multicast(struct net_device
*dev
)
2027 struct fe_priv
*np
= netdev_priv(dev
);
2028 u8 __iomem
*base
= get_hwbase(dev
);
2031 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & NVREG_PFF_PAUSE_RX
;
2033 memset(addr
, 0, sizeof(addr
));
2034 memset(mask
, 0, sizeof(mask
));
2036 if (dev
->flags
& IFF_PROMISC
) {
2037 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n", dev
->name
);
2038 pff
|= NVREG_PFF_PROMISC
;
2040 pff
|= NVREG_PFF_MYADDR
;
2042 if (dev
->flags
& IFF_ALLMULTI
|| dev
->mc_list
) {
2046 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0xffffffff;
2047 if (dev
->flags
& IFF_ALLMULTI
) {
2048 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0;
2050 struct dev_mc_list
*walk
;
2052 walk
= dev
->mc_list
;
2053 while (walk
!= NULL
) {
2055 a
= le32_to_cpu(*(u32
*) walk
->dmi_addr
);
2056 b
= le16_to_cpu(*(u16
*) (&walk
->dmi_addr
[4]));
2064 addr
[0] = alwaysOn
[0];
2065 addr
[1] = alwaysOn
[1];
2066 mask
[0] = alwaysOn
[0] | alwaysOff
[0];
2067 mask
[1] = alwaysOn
[1] | alwaysOff
[1];
2070 addr
[0] |= NVREG_MCASTADDRA_FORCE
;
2071 pff
|= NVREG_PFF_ALWAYS
;
2072 spin_lock_irq(&np
->lock
);
2074 writel(addr
[0], base
+ NvRegMulticastAddrA
);
2075 writel(addr
[1], base
+ NvRegMulticastAddrB
);
2076 writel(mask
[0], base
+ NvRegMulticastMaskA
);
2077 writel(mask
[1], base
+ NvRegMulticastMaskB
);
2078 writel(pff
, base
+ NvRegPacketFilterFlags
);
2079 dprintk(KERN_INFO
"%s: reconfiguration for multicast lists.\n",
2082 spin_unlock_irq(&np
->lock
);
2085 static void nv_update_pause(struct net_device
*dev
, u32 pause_flags
)
2087 struct fe_priv
*np
= netdev_priv(dev
);
2088 u8 __iomem
*base
= get_hwbase(dev
);
2090 np
->pause_flags
&= ~(NV_PAUSEFRAME_TX_ENABLE
| NV_PAUSEFRAME_RX_ENABLE
);
2092 if (np
->pause_flags
& NV_PAUSEFRAME_RX_CAPABLE
) {
2093 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & ~NVREG_PFF_PAUSE_RX
;
2094 if (pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) {
2095 writel(pff
|NVREG_PFF_PAUSE_RX
, base
+ NvRegPacketFilterFlags
);
2096 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
2098 writel(pff
, base
+ NvRegPacketFilterFlags
);
2101 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
) {
2102 u32 regmisc
= readl(base
+ NvRegMisc1
) & ~NVREG_MISC1_PAUSE_TX
;
2103 if (pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) {
2104 writel(NVREG_TX_PAUSEFRAME_ENABLE
, base
+ NvRegTxPauseFrame
);
2105 writel(regmisc
|NVREG_MISC1_PAUSE_TX
, base
+ NvRegMisc1
);
2106 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
2108 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
2109 writel(regmisc
, base
+ NvRegMisc1
);
2115 * nv_update_linkspeed: Setup the MAC according to the link partner
2116 * @dev: Network device to be configured
2118 * The function queries the PHY and checks if there is a link partner.
2119 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2120 * set to 10 MBit HD.
2122 * The function returns 0 if there is no link partner and 1 if there is
2123 * a good link partner.
2125 static int nv_update_linkspeed(struct net_device
*dev
)
2127 struct fe_priv
*np
= netdev_priv(dev
);
2128 u8 __iomem
*base
= get_hwbase(dev
);
2131 int adv_lpa
, adv_pause
, lpa_pause
;
2132 int newls
= np
->linkspeed
;
2133 int newdup
= np
->duplex
;
2136 u32 control_1000
, status_1000
, phyreg
, pause_flags
, txreg
;
2138 /* BMSR_LSTATUS is latched, read it twice:
2139 * we want the current value.
2141 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
2142 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
2144 if (!(mii_status
& BMSR_LSTATUS
)) {
2145 dprintk(KERN_DEBUG
"%s: no link detected by phy - falling back to 10HD.\n",
2147 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2153 if (np
->autoneg
== 0) {
2154 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2155 dev
->name
, np
->fixed_mode
);
2156 if (np
->fixed_mode
& LPA_100FULL
) {
2157 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
2159 } else if (np
->fixed_mode
& LPA_100HALF
) {
2160 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
2162 } else if (np
->fixed_mode
& LPA_10FULL
) {
2163 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2166 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2172 /* check auto negotiation is complete */
2173 if (!(mii_status
& BMSR_ANEGCOMPLETE
)) {
2174 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2175 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2178 dprintk(KERN_DEBUG
"%s: autoneg not completed - falling back to 10HD.\n", dev
->name
);
2182 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
2183 lpa
= mii_rw(dev
, np
->phyaddr
, MII_LPA
, MII_READ
);
2184 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2185 dev
->name
, adv
, lpa
);
2188 if (np
->gigabit
== PHY_GIGABIT
) {
2189 control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
2190 status_1000
= mii_rw(dev
, np
->phyaddr
, MII_STAT1000
, MII_READ
);
2192 if ((control_1000
& ADVERTISE_1000FULL
) &&
2193 (status_1000
& LPA_1000FULL
)) {
2194 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: GBit ethernet detected.\n",
2196 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_1000
;
2202 /* FIXME: handle parallel detection properly */
2203 adv_lpa
= lpa
& adv
;
2204 if (adv_lpa
& LPA_100FULL
) {
2205 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
2207 } else if (adv_lpa
& LPA_100HALF
) {
2208 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
2210 } else if (adv_lpa
& LPA_10FULL
) {
2211 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2213 } else if (adv_lpa
& LPA_10HALF
) {
2214 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2217 dprintk(KERN_DEBUG
"%s: bad ability %04x - falling back to 10HD.\n", dev
->name
, adv_lpa
);
2218 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2223 if (np
->duplex
== newdup
&& np
->linkspeed
== newls
)
2226 dprintk(KERN_INFO
"%s: changing link setting from %d/%d to %d/%d.\n",
2227 dev
->name
, np
->linkspeed
, np
->duplex
, newls
, newdup
);
2229 np
->duplex
= newdup
;
2230 np
->linkspeed
= newls
;
2232 if (np
->gigabit
== PHY_GIGABIT
) {
2233 phyreg
= readl(base
+ NvRegRandomSeed
);
2234 phyreg
&= ~(0x3FF00);
2235 if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
)
2236 phyreg
|= NVREG_RNDSEED_FORCE3
;
2237 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
)
2238 phyreg
|= NVREG_RNDSEED_FORCE2
;
2239 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
2240 phyreg
|= NVREG_RNDSEED_FORCE
;
2241 writel(phyreg
, base
+ NvRegRandomSeed
);
2244 phyreg
= readl(base
+ NvRegPhyInterface
);
2245 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
2246 if (np
->duplex
== 0)
2248 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
2250 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
2252 writel(phyreg
, base
+ NvRegPhyInterface
);
2254 if (phyreg
& PHY_RGMII
) {
2255 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
2256 txreg
= NVREG_TX_DEFERRAL_RGMII_1000
;
2258 txreg
= NVREG_TX_DEFERRAL_RGMII_10_100
;
2260 txreg
= NVREG_TX_DEFERRAL_DEFAULT
;
2262 writel(txreg
, base
+ NvRegTxDeferral
);
2264 if (np
->desc_ver
== DESC_VER_1
) {
2265 txreg
= NVREG_TX_WM_DESC1_DEFAULT
;
2267 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
2268 txreg
= NVREG_TX_WM_DESC2_3_1000
;
2270 txreg
= NVREG_TX_WM_DESC2_3_DEFAULT
;
2272 writel(txreg
, base
+ NvRegTxWatermark
);
2274 writel(NVREG_MISC1_FORCE
| ( np
->duplex
? 0 : NVREG_MISC1_HD
),
2277 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
2281 /* setup pause frame */
2282 if (np
->duplex
!= 0) {
2283 if (np
->autoneg
&& np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) {
2284 adv_pause
= adv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2285 lpa_pause
= lpa
& (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
);
2287 switch (adv_pause
) {
2288 case ADVERTISE_PAUSE_CAP
:
2289 if (lpa_pause
& LPA_PAUSE_CAP
) {
2290 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
2291 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
2292 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
2295 case ADVERTISE_PAUSE_ASYM
:
2296 if (lpa_pause
== (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
))
2298 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
2301 case ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
:
2302 if (lpa_pause
& LPA_PAUSE_CAP
)
2304 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
2305 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
2306 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
2308 if (lpa_pause
== LPA_PAUSE_ASYM
)
2310 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
2315 pause_flags
= np
->pause_flags
;
2318 nv_update_pause(dev
, pause_flags
);
2323 static void nv_linkchange(struct net_device
*dev
)
2325 if (nv_update_linkspeed(dev
)) {
2326 if (!netif_carrier_ok(dev
)) {
2327 netif_carrier_on(dev
);
2328 printk(KERN_INFO
"%s: link up.\n", dev
->name
);
2332 if (netif_carrier_ok(dev
)) {
2333 netif_carrier_off(dev
);
2334 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
2340 static void nv_link_irq(struct net_device
*dev
)
2342 u8 __iomem
*base
= get_hwbase(dev
);
2345 miistat
= readl(base
+ NvRegMIIStatus
);
2346 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
2347 dprintk(KERN_INFO
"%s: link change irq, status 0x%x.\n", dev
->name
, miistat
);
2349 if (miistat
& (NVREG_MIISTAT_LINKCHANGE
))
2351 dprintk(KERN_DEBUG
"%s: link change notification done.\n", dev
->name
);
2354 static irqreturn_t
nv_nic_irq(int foo
, void *data
, struct pt_regs
*regs
)
2356 struct net_device
*dev
= (struct net_device
*) data
;
2357 struct fe_priv
*np
= netdev_priv(dev
);
2358 u8 __iomem
*base
= get_hwbase(dev
);
2362 dprintk(KERN_DEBUG
"%s: nv_nic_irq\n", dev
->name
);
2365 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
2366 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
2367 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
2369 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
2370 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
2373 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
2374 if (!(events
& np
->irqmask
))
2377 spin_lock(&np
->lock
);
2379 spin_unlock(&np
->lock
);
2382 if (nv_alloc_rx(dev
)) {
2383 spin_lock(&np
->lock
);
2384 if (!np
->in_shutdown
)
2385 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2386 spin_unlock(&np
->lock
);
2389 if (events
& NVREG_IRQ_LINK
) {
2390 spin_lock(&np
->lock
);
2392 spin_unlock(&np
->lock
);
2394 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
2395 spin_lock(&np
->lock
);
2397 spin_unlock(&np
->lock
);
2398 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
2400 if (events
& (NVREG_IRQ_TX_ERR
)) {
2401 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
2404 if (events
& (NVREG_IRQ_UNKNOWN
)) {
2405 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
2408 if (i
> max_interrupt_work
) {
2409 spin_lock(&np
->lock
);
2410 /* disable interrupts on the nic */
2411 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
2412 writel(0, base
+ NvRegIrqMask
);
2414 writel(np
->irqmask
, base
+ NvRegIrqMask
);
2417 if (!np
->in_shutdown
) {
2418 np
->nic_poll_irq
= np
->irqmask
;
2419 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2421 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq.\n", dev
->name
, i
);
2422 spin_unlock(&np
->lock
);
2427 dprintk(KERN_DEBUG
"%s: nv_nic_irq completed\n", dev
->name
);
2429 return IRQ_RETVAL(i
);
2432 static irqreturn_t
nv_nic_irq_tx(int foo
, void *data
, struct pt_regs
*regs
)
2434 struct net_device
*dev
= (struct net_device
*) data
;
2435 struct fe_priv
*np
= netdev_priv(dev
);
2436 u8 __iomem
*base
= get_hwbase(dev
);
2440 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx\n", dev
->name
);
2443 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_TX_ALL
;
2444 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegMSIXIrqStatus
);
2446 dprintk(KERN_DEBUG
"%s: tx irq: %08x\n", dev
->name
, events
);
2447 if (!(events
& np
->irqmask
))
2450 spin_lock_irq(&np
->lock
);
2452 spin_unlock_irq(&np
->lock
);
2454 if (events
& (NVREG_IRQ_TX_ERR
)) {
2455 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
2458 if (i
> max_interrupt_work
) {
2459 spin_lock_irq(&np
->lock
);
2460 /* disable interrupts on the nic */
2461 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegIrqMask
);
2464 if (!np
->in_shutdown
) {
2465 np
->nic_poll_irq
|= NVREG_IRQ_TX_ALL
;
2466 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2468 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev
->name
, i
);
2469 spin_unlock_irq(&np
->lock
);
2474 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx completed\n", dev
->name
);
2476 return IRQ_RETVAL(i
);
2479 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
, struct pt_regs
*regs
)
2481 struct net_device
*dev
= (struct net_device
*) data
;
2482 struct fe_priv
*np
= netdev_priv(dev
);
2483 u8 __iomem
*base
= get_hwbase(dev
);
2487 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx\n", dev
->name
);
2490 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
2491 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegMSIXIrqStatus
);
2493 dprintk(KERN_DEBUG
"%s: rx irq: %08x\n", dev
->name
, events
);
2494 if (!(events
& np
->irqmask
))
2498 if (nv_alloc_rx(dev
)) {
2499 spin_lock_irq(&np
->lock
);
2500 if (!np
->in_shutdown
)
2501 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2502 spin_unlock_irq(&np
->lock
);
2505 if (i
> max_interrupt_work
) {
2506 spin_lock_irq(&np
->lock
);
2507 /* disable interrupts on the nic */
2508 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
2511 if (!np
->in_shutdown
) {
2512 np
->nic_poll_irq
|= NVREG_IRQ_RX_ALL
;
2513 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2515 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev
->name
, i
);
2516 spin_unlock_irq(&np
->lock
);
2521 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx completed\n", dev
->name
);
2523 return IRQ_RETVAL(i
);
2526 static irqreturn_t
nv_nic_irq_other(int foo
, void *data
, struct pt_regs
*regs
)
2528 struct net_device
*dev
= (struct net_device
*) data
;
2529 struct fe_priv
*np
= netdev_priv(dev
);
2530 u8 __iomem
*base
= get_hwbase(dev
);
2534 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other\n", dev
->name
);
2537 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_OTHER
;
2538 writel(NVREG_IRQ_OTHER
, base
+ NvRegMSIXIrqStatus
);
2540 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
2541 if (!(events
& np
->irqmask
))
2544 if (events
& NVREG_IRQ_LINK
) {
2545 spin_lock_irq(&np
->lock
);
2547 spin_unlock_irq(&np
->lock
);
2549 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
2550 spin_lock_irq(&np
->lock
);
2552 spin_unlock_irq(&np
->lock
);
2553 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
2555 if (events
& (NVREG_IRQ_UNKNOWN
)) {
2556 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
2559 if (i
> max_interrupt_work
) {
2560 spin_lock_irq(&np
->lock
);
2561 /* disable interrupts on the nic */
2562 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
2565 if (!np
->in_shutdown
) {
2566 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
2567 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2569 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_other.\n", dev
->name
, i
);
2570 spin_unlock_irq(&np
->lock
);
2575 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other completed\n", dev
->name
);
2577 return IRQ_RETVAL(i
);
2580 static irqreturn_t
nv_nic_irq_test(int foo
, void *data
, struct pt_regs
*regs
)
2582 struct net_device
*dev
= (struct net_device
*) data
;
2583 struct fe_priv
*np
= netdev_priv(dev
);
2584 u8 __iomem
*base
= get_hwbase(dev
);
2587 dprintk(KERN_DEBUG
"%s: nv_nic_irq_test\n", dev
->name
);
2589 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
2590 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
2591 writel(NVREG_IRQ_TIMER
, base
+ NvRegIrqStatus
);
2593 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
2594 writel(NVREG_IRQ_TIMER
, base
+ NvRegMSIXIrqStatus
);
2597 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
2598 if (!(events
& NVREG_IRQ_TIMER
))
2599 return IRQ_RETVAL(0);
2601 spin_lock(&np
->lock
);
2603 spin_unlock(&np
->lock
);
2605 dprintk(KERN_DEBUG
"%s: nv_nic_irq_test completed\n", dev
->name
);
2607 return IRQ_RETVAL(1);
2610 static void set_msix_vector_map(struct net_device
*dev
, u32 vector
, u32 irqmask
)
2612 u8 __iomem
*base
= get_hwbase(dev
);
2616 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2617 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2618 * the remaining 8 interrupts.
2620 for (i
= 0; i
< 8; i
++) {
2621 if ((irqmask
>> i
) & 0x1) {
2622 msixmap
|= vector
<< (i
<< 2);
2625 writel(readl(base
+ NvRegMSIXMap0
) | msixmap
, base
+ NvRegMSIXMap0
);
2628 for (i
= 0; i
< 8; i
++) {
2629 if ((irqmask
>> (i
+ 8)) & 0x1) {
2630 msixmap
|= vector
<< (i
<< 2);
2633 writel(readl(base
+ NvRegMSIXMap1
) | msixmap
, base
+ NvRegMSIXMap1
);
2636 static int nv_request_irq(struct net_device
*dev
, int intr_test
)
2638 struct fe_priv
*np
= get_nvpriv(dev
);
2639 u8 __iomem
*base
= get_hwbase(dev
);
2643 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) {
2644 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
2645 np
->msi_x_entry
[i
].entry
= i
;
2647 if ((ret
= pci_enable_msix(np
->pci_dev
, np
->msi_x_entry
, (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
))) == 0) {
2648 np
->msi_flags
|= NV_MSI_X_ENABLED
;
2649 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
&& !intr_test
) {
2650 /* Request irq for rx handling */
2651 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, &nv_nic_irq_rx
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
2652 printk(KERN_INFO
"forcedeth: request_irq failed for rx %d\n", ret
);
2653 pci_disable_msix(np
->pci_dev
);
2654 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2657 /* Request irq for tx handling */
2658 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, &nv_nic_irq_tx
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
2659 printk(KERN_INFO
"forcedeth: request_irq failed for tx %d\n", ret
);
2660 pci_disable_msix(np
->pci_dev
);
2661 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2664 /* Request irq for link and timer handling */
2665 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
, &nv_nic_irq_other
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
2666 printk(KERN_INFO
"forcedeth: request_irq failed for link %d\n", ret
);
2667 pci_disable_msix(np
->pci_dev
);
2668 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2671 /* map interrupts to their respective vector */
2672 writel(0, base
+ NvRegMSIXMap0
);
2673 writel(0, base
+ NvRegMSIXMap1
);
2674 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_RX
, NVREG_IRQ_RX_ALL
);
2675 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_TX
, NVREG_IRQ_TX_ALL
);
2676 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_OTHER
, NVREG_IRQ_OTHER
);
2678 /* Request irq for all interrupts */
2680 request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
, &nv_nic_irq
, IRQF_SHARED
, dev
->name
, dev
) != 0) ||
2682 request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
, &nv_nic_irq_test
, IRQF_SHARED
, dev
->name
, dev
) != 0)) {
2683 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
2684 pci_disable_msix(np
->pci_dev
);
2685 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2689 /* map interrupts to vector 0 */
2690 writel(0, base
+ NvRegMSIXMap0
);
2691 writel(0, base
+ NvRegMSIXMap1
);
2695 if (ret
!= 0 && np
->msi_flags
& NV_MSI_CAPABLE
) {
2696 if ((ret
= pci_enable_msi(np
->pci_dev
)) == 0) {
2697 np
->msi_flags
|= NV_MSI_ENABLED
;
2698 if ((!intr_test
&& request_irq(np
->pci_dev
->irq
, &nv_nic_irq
, IRQF_SHARED
, dev
->name
, dev
) != 0) ||
2699 (intr_test
&& request_irq(np
->pci_dev
->irq
, &nv_nic_irq_test
, IRQF_SHARED
, dev
->name
, dev
) != 0)) {
2700 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
2701 pci_disable_msi(np
->pci_dev
);
2702 np
->msi_flags
&= ~NV_MSI_ENABLED
;
2706 /* map interrupts to vector 0 */
2707 writel(0, base
+ NvRegMSIMap0
);
2708 writel(0, base
+ NvRegMSIMap1
);
2709 /* enable msi vector 0 */
2710 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
2714 if ((!intr_test
&& request_irq(np
->pci_dev
->irq
, &nv_nic_irq
, IRQF_SHARED
, dev
->name
, dev
) != 0) ||
2715 (intr_test
&& request_irq(np
->pci_dev
->irq
, &nv_nic_irq_test
, IRQF_SHARED
, dev
->name
, dev
) != 0))
2722 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, dev
);
2724 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, dev
);
2729 static void nv_free_irq(struct net_device
*dev
)
2731 struct fe_priv
*np
= get_nvpriv(dev
);
2734 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
2735 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
2736 free_irq(np
->msi_x_entry
[i
].vector
, dev
);
2738 pci_disable_msix(np
->pci_dev
);
2739 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2741 free_irq(np
->pci_dev
->irq
, dev
);
2742 if (np
->msi_flags
& NV_MSI_ENABLED
) {
2743 pci_disable_msi(np
->pci_dev
);
2744 np
->msi_flags
&= ~NV_MSI_ENABLED
;
2749 static void nv_do_nic_poll(unsigned long data
)
2751 struct net_device
*dev
= (struct net_device
*) data
;
2752 struct fe_priv
*np
= netdev_priv(dev
);
2753 u8 __iomem
*base
= get_hwbase(dev
);
2757 * First disable irq(s) and then
2758 * reenable interrupts on the nic, we have to do this before calling
2759 * nv_nic_irq because that may decide to do otherwise
2762 if (!using_multi_irqs(dev
)) {
2763 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
2764 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
2766 disable_irq_lockdep(dev
->irq
);
2769 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
2770 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
2771 mask
|= NVREG_IRQ_RX_ALL
;
2773 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
2774 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
2775 mask
|= NVREG_IRQ_TX_ALL
;
2777 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
2778 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
2779 mask
|= NVREG_IRQ_OTHER
;
2782 np
->nic_poll_irq
= 0;
2784 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2786 writel(mask
, base
+ NvRegIrqMask
);
2789 if (!using_multi_irqs(dev
)) {
2790 nv_nic_irq(0, dev
, NULL
);
2791 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
2792 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
2794 enable_irq_lockdep(dev
->irq
);
2796 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
2797 nv_nic_irq_rx(0, dev
, NULL
);
2798 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
2800 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
2801 nv_nic_irq_tx(0, dev
, NULL
);
2802 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
2804 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
2805 nv_nic_irq_other(0, dev
, NULL
);
2806 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
2811 #ifdef CONFIG_NET_POLL_CONTROLLER
2812 static void nv_poll_controller(struct net_device
*dev
)
2814 nv_do_nic_poll((unsigned long) dev
);
2818 static void nv_do_stats_poll(unsigned long data
)
2820 struct net_device
*dev
= (struct net_device
*) data
;
2821 struct fe_priv
*np
= netdev_priv(dev
);
2822 u8 __iomem
*base
= get_hwbase(dev
);
2824 np
->estats
.tx_bytes
+= readl(base
+ NvRegTxCnt
);
2825 np
->estats
.tx_zero_rexmt
+= readl(base
+ NvRegTxZeroReXmt
);
2826 np
->estats
.tx_one_rexmt
+= readl(base
+ NvRegTxOneReXmt
);
2827 np
->estats
.tx_many_rexmt
+= readl(base
+ NvRegTxManyReXmt
);
2828 np
->estats
.tx_late_collision
+= readl(base
+ NvRegTxLateCol
);
2829 np
->estats
.tx_fifo_errors
+= readl(base
+ NvRegTxUnderflow
);
2830 np
->estats
.tx_carrier_errors
+= readl(base
+ NvRegTxLossCarrier
);
2831 np
->estats
.tx_excess_deferral
+= readl(base
+ NvRegTxExcessDef
);
2832 np
->estats
.tx_retry_error
+= readl(base
+ NvRegTxRetryErr
);
2833 np
->estats
.tx_deferral
+= readl(base
+ NvRegTxDef
);
2834 np
->estats
.tx_packets
+= readl(base
+ NvRegTxFrame
);
2835 np
->estats
.tx_pause
+= readl(base
+ NvRegTxPause
);
2836 np
->estats
.rx_frame_error
+= readl(base
+ NvRegRxFrameErr
);
2837 np
->estats
.rx_extra_byte
+= readl(base
+ NvRegRxExtraByte
);
2838 np
->estats
.rx_late_collision
+= readl(base
+ NvRegRxLateCol
);
2839 np
->estats
.rx_runt
+= readl(base
+ NvRegRxRunt
);
2840 np
->estats
.rx_frame_too_long
+= readl(base
+ NvRegRxFrameTooLong
);
2841 np
->estats
.rx_over_errors
+= readl(base
+ NvRegRxOverflow
);
2842 np
->estats
.rx_crc_errors
+= readl(base
+ NvRegRxFCSErr
);
2843 np
->estats
.rx_frame_align_error
+= readl(base
+ NvRegRxFrameAlignErr
);
2844 np
->estats
.rx_length_error
+= readl(base
+ NvRegRxLenErr
);
2845 np
->estats
.rx_unicast
+= readl(base
+ NvRegRxUnicast
);
2846 np
->estats
.rx_multicast
+= readl(base
+ NvRegRxMulticast
);
2847 np
->estats
.rx_broadcast
+= readl(base
+ NvRegRxBroadcast
);
2848 np
->estats
.rx_bytes
+= readl(base
+ NvRegRxCnt
);
2849 np
->estats
.rx_pause
+= readl(base
+ NvRegRxPause
);
2850 np
->estats
.rx_drop_frame
+= readl(base
+ NvRegRxDropFrame
);
2851 np
->estats
.rx_packets
=
2852 np
->estats
.rx_unicast
+
2853 np
->estats
.rx_multicast
+
2854 np
->estats
.rx_broadcast
;
2855 np
->estats
.rx_errors_total
=
2856 np
->estats
.rx_crc_errors
+
2857 np
->estats
.rx_over_errors
+
2858 np
->estats
.rx_frame_error
+
2859 (np
->estats
.rx_frame_align_error
- np
->estats
.rx_extra_byte
) +
2860 np
->estats
.rx_late_collision
+
2861 np
->estats
.rx_runt
+
2862 np
->estats
.rx_frame_too_long
;
2864 if (!np
->in_shutdown
)
2865 mod_timer(&np
->stats_poll
, jiffies
+ STATS_INTERVAL
);
2868 static void nv_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
2870 struct fe_priv
*np
= netdev_priv(dev
);
2871 strcpy(info
->driver
, "forcedeth");
2872 strcpy(info
->version
, FORCEDETH_VERSION
);
2873 strcpy(info
->bus_info
, pci_name(np
->pci_dev
));
2876 static void nv_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
2878 struct fe_priv
*np
= netdev_priv(dev
);
2879 wolinfo
->supported
= WAKE_MAGIC
;
2881 spin_lock_irq(&np
->lock
);
2883 wolinfo
->wolopts
= WAKE_MAGIC
;
2884 spin_unlock_irq(&np
->lock
);
2887 static int nv_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
2889 struct fe_priv
*np
= netdev_priv(dev
);
2890 u8 __iomem
*base
= get_hwbase(dev
);
2893 if (wolinfo
->wolopts
== 0) {
2895 } else if (wolinfo
->wolopts
& WAKE_MAGIC
) {
2897 flags
= NVREG_WAKEUPFLAGS_ENABLE
;
2899 if (netif_running(dev
)) {
2900 spin_lock_irq(&np
->lock
);
2901 writel(flags
, base
+ NvRegWakeUpFlags
);
2902 spin_unlock_irq(&np
->lock
);
2907 static int nv_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2909 struct fe_priv
*np
= netdev_priv(dev
);
2912 spin_lock_irq(&np
->lock
);
2913 ecmd
->port
= PORT_MII
;
2914 if (!netif_running(dev
)) {
2915 /* We do not track link speed / duplex setting if the
2916 * interface is disabled. Force a link check */
2917 if (nv_update_linkspeed(dev
)) {
2918 if (!netif_carrier_ok(dev
))
2919 netif_carrier_on(dev
);
2921 if (netif_carrier_ok(dev
))
2922 netif_carrier_off(dev
);
2926 if (netif_carrier_ok(dev
)) {
2927 switch(np
->linkspeed
& (NVREG_LINKSPEED_MASK
)) {
2928 case NVREG_LINKSPEED_10
:
2929 ecmd
->speed
= SPEED_10
;
2931 case NVREG_LINKSPEED_100
:
2932 ecmd
->speed
= SPEED_100
;
2934 case NVREG_LINKSPEED_1000
:
2935 ecmd
->speed
= SPEED_1000
;
2938 ecmd
->duplex
= DUPLEX_HALF
;
2940 ecmd
->duplex
= DUPLEX_FULL
;
2946 ecmd
->autoneg
= np
->autoneg
;
2948 ecmd
->advertising
= ADVERTISED_MII
;
2950 ecmd
->advertising
|= ADVERTISED_Autoneg
;
2951 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
2952 if (adv
& ADVERTISE_10HALF
)
2953 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
2954 if (adv
& ADVERTISE_10FULL
)
2955 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
2956 if (adv
& ADVERTISE_100HALF
)
2957 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
2958 if (adv
& ADVERTISE_100FULL
)
2959 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
2960 if (np
->gigabit
== PHY_GIGABIT
) {
2961 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
2962 if (adv
& ADVERTISE_1000FULL
)
2963 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
2966 ecmd
->supported
= (SUPPORTED_Autoneg
|
2967 SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
2968 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
2970 if (np
->gigabit
== PHY_GIGABIT
)
2971 ecmd
->supported
|= SUPPORTED_1000baseT_Full
;
2973 ecmd
->phy_address
= np
->phyaddr
;
2974 ecmd
->transceiver
= XCVR_EXTERNAL
;
2976 /* ignore maxtxpkt, maxrxpkt for now */
2977 spin_unlock_irq(&np
->lock
);
2981 static int nv_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2983 struct fe_priv
*np
= netdev_priv(dev
);
2985 if (ecmd
->port
!= PORT_MII
)
2987 if (ecmd
->transceiver
!= XCVR_EXTERNAL
)
2989 if (ecmd
->phy_address
!= np
->phyaddr
) {
2990 /* TODO: support switching between multiple phys. Should be
2991 * trivial, but not enabled due to lack of test hardware. */
2994 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2997 mask
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
2998 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
2999 if (np
->gigabit
== PHY_GIGABIT
)
3000 mask
|= ADVERTISED_1000baseT_Full
;
3002 if ((ecmd
->advertising
& mask
) == 0)
3005 } else if (ecmd
->autoneg
== AUTONEG_DISABLE
) {
3006 /* Note: autonegotiation disable, speed 1000 intentionally
3007 * forbidden - noone should need that. */
3009 if (ecmd
->speed
!= SPEED_10
&& ecmd
->speed
!= SPEED_100
)
3011 if (ecmd
->duplex
!= DUPLEX_HALF
&& ecmd
->duplex
!= DUPLEX_FULL
)
3017 netif_carrier_off(dev
);
3018 if (netif_running(dev
)) {
3019 nv_disable_irq(dev
);
3020 netif_tx_lock_bh(dev
);
3021 spin_lock(&np
->lock
);
3025 spin_unlock(&np
->lock
);
3026 netif_tx_unlock_bh(dev
);
3029 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
3034 /* advertise only what has been requested */
3035 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
3036 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3037 if (ecmd
->advertising
& ADVERTISED_10baseT_Half
)
3038 adv
|= ADVERTISE_10HALF
;
3039 if (ecmd
->advertising
& ADVERTISED_10baseT_Full
)
3040 adv
|= ADVERTISE_10FULL
;
3041 if (ecmd
->advertising
& ADVERTISED_100baseT_Half
)
3042 adv
|= ADVERTISE_100HALF
;
3043 if (ecmd
->advertising
& ADVERTISED_100baseT_Full
)
3044 adv
|= ADVERTISE_100FULL
;
3045 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisments but disable tx pause */
3046 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
3047 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3048 adv
|= ADVERTISE_PAUSE_ASYM
;
3049 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
3051 if (np
->gigabit
== PHY_GIGABIT
) {
3052 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
3053 adv
&= ~ADVERTISE_1000FULL
;
3054 if (ecmd
->advertising
& ADVERTISED_1000baseT_Full
)
3055 adv
|= ADVERTISE_1000FULL
;
3056 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
3059 if (netif_running(dev
))
3060 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
3061 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
3062 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
3063 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
3070 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
3071 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3072 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_HALF
)
3073 adv
|= ADVERTISE_10HALF
;
3074 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_FULL
)
3075 adv
|= ADVERTISE_10FULL
;
3076 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_HALF
)
3077 adv
|= ADVERTISE_100HALF
;
3078 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_FULL
)
3079 adv
|= ADVERTISE_100FULL
;
3080 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
3081 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) {/* for rx we set both advertisments but disable tx pause */
3082 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
3083 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3085 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
) {
3086 adv
|= ADVERTISE_PAUSE_ASYM
;
3087 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3089 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
3090 np
->fixed_mode
= adv
;
3092 if (np
->gigabit
== PHY_GIGABIT
) {
3093 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
3094 adv
&= ~ADVERTISE_1000FULL
;
3095 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
3098 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
3099 bmcr
&= ~(BMCR_ANENABLE
|BMCR_SPEED100
|BMCR_SPEED1000
|BMCR_FULLDPLX
);
3100 if (np
->fixed_mode
& (ADVERTISE_10FULL
|ADVERTISE_100FULL
))
3101 bmcr
|= BMCR_FULLDPLX
;
3102 if (np
->fixed_mode
& (ADVERTISE_100HALF
|ADVERTISE_100FULL
))
3103 bmcr
|= BMCR_SPEED100
;
3104 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
3105 if (np
->phy_oui
== PHY_OUI_MARVELL
) {
3107 if (phy_reset(dev
)) {
3108 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
3111 } else if (netif_running(dev
)) {
3112 /* Wait a bit and then reconfigure the nic. */
3118 if (netif_running(dev
)) {
3127 #define FORCEDETH_REGS_VER 1
3129 static int nv_get_regs_len(struct net_device
*dev
)
3131 struct fe_priv
*np
= netdev_priv(dev
);
3132 return np
->register_size
;
3135 static void nv_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
, void *buf
)
3137 struct fe_priv
*np
= netdev_priv(dev
);
3138 u8 __iomem
*base
= get_hwbase(dev
);
3142 regs
->version
= FORCEDETH_REGS_VER
;
3143 spin_lock_irq(&np
->lock
);
3144 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
3145 rbuf
[i
] = readl(base
+ i
*sizeof(u32
));
3146 spin_unlock_irq(&np
->lock
);
3149 static int nv_nway_reset(struct net_device
*dev
)
3151 struct fe_priv
*np
= netdev_priv(dev
);
3157 netif_carrier_off(dev
);
3158 if (netif_running(dev
)) {
3159 nv_disable_irq(dev
);
3160 netif_tx_lock_bh(dev
);
3161 spin_lock(&np
->lock
);
3165 spin_unlock(&np
->lock
);
3166 netif_tx_unlock_bh(dev
);
3167 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
3170 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
3171 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
3172 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
3174 if (netif_running(dev
)) {
3187 static int nv_set_tso(struct net_device
*dev
, u32 value
)
3189 struct fe_priv
*np
= netdev_priv(dev
);
3191 if ((np
->driver_data
& DEV_HAS_CHECKSUM
))
3192 return ethtool_op_set_tso(dev
, value
);
3197 static void nv_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
3199 struct fe_priv
*np
= netdev_priv(dev
);
3201 ring
->rx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
3202 ring
->rx_mini_max_pending
= 0;
3203 ring
->rx_jumbo_max_pending
= 0;
3204 ring
->tx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
3206 ring
->rx_pending
= np
->rx_ring_size
;
3207 ring
->rx_mini_pending
= 0;
3208 ring
->rx_jumbo_pending
= 0;
3209 ring
->tx_pending
= np
->tx_ring_size
;
3212 static int nv_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
3214 struct fe_priv
*np
= netdev_priv(dev
);
3215 u8 __iomem
*base
= get_hwbase(dev
);
3216 u8
*rxtx_ring
, *rx_skbuff
, *tx_skbuff
, *rx_dma
, *tx_dma
, *tx_dma_len
;
3217 dma_addr_t ring_addr
;
3219 if (ring
->rx_pending
< RX_RING_MIN
||
3220 ring
->tx_pending
< TX_RING_MIN
||
3221 ring
->rx_mini_pending
!= 0 ||
3222 ring
->rx_jumbo_pending
!= 0 ||
3223 (np
->desc_ver
== DESC_VER_1
&&
3224 (ring
->rx_pending
> RING_MAX_DESC_VER_1
||
3225 ring
->tx_pending
> RING_MAX_DESC_VER_1
)) ||
3226 (np
->desc_ver
!= DESC_VER_1
&&
3227 (ring
->rx_pending
> RING_MAX_DESC_VER_2_3
||
3228 ring
->tx_pending
> RING_MAX_DESC_VER_2_3
))) {
3232 /* allocate new rings */
3233 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
3234 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
3235 sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
3238 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
3239 sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
3242 rx_skbuff
= kmalloc(sizeof(struct sk_buff
*) * ring
->rx_pending
, GFP_KERNEL
);
3243 rx_dma
= kmalloc(sizeof(dma_addr_t
) * ring
->rx_pending
, GFP_KERNEL
);
3244 tx_skbuff
= kmalloc(sizeof(struct sk_buff
*) * ring
->tx_pending
, GFP_KERNEL
);
3245 tx_dma
= kmalloc(sizeof(dma_addr_t
) * ring
->tx_pending
, GFP_KERNEL
);
3246 tx_dma_len
= kmalloc(sizeof(unsigned int) * ring
->tx_pending
, GFP_KERNEL
);
3247 if (!rxtx_ring
|| !rx_skbuff
|| !rx_dma
|| !tx_skbuff
|| !tx_dma
|| !tx_dma_len
) {
3248 /* fall back to old rings */
3249 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
3251 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
3252 rxtx_ring
, ring_addr
);
3255 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
3256 rxtx_ring
, ring_addr
);
3271 if (netif_running(dev
)) {
3272 nv_disable_irq(dev
);
3273 netif_tx_lock_bh(dev
);
3274 spin_lock(&np
->lock
);
3286 /* set new values */
3287 np
->rx_ring_size
= ring
->rx_pending
;
3288 np
->tx_ring_size
= ring
->tx_pending
;
3289 np
->tx_limit_stop
= ring
->tx_pending
- TX_LIMIT_DIFFERENCE
;
3290 np
->tx_limit_start
= ring
->tx_pending
- TX_LIMIT_DIFFERENCE
- 1;
3291 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
3292 np
->rx_ring
.orig
= (struct ring_desc
*)rxtx_ring
;
3293 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
3295 np
->rx_ring
.ex
= (struct ring_desc_ex
*)rxtx_ring
;
3296 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
3298 np
->rx_skbuff
= (struct sk_buff
**)rx_skbuff
;
3299 np
->rx_dma
= (dma_addr_t
*)rx_dma
;
3300 np
->tx_skbuff
= (struct sk_buff
**)tx_skbuff
;
3301 np
->tx_dma
= (dma_addr_t
*)tx_dma
;
3302 np
->tx_dma_len
= (unsigned int*)tx_dma_len
;
3303 np
->ring_addr
= ring_addr
;
3305 memset(np
->rx_skbuff
, 0, sizeof(struct sk_buff
*) * np
->rx_ring_size
);
3306 memset(np
->rx_dma
, 0, sizeof(dma_addr_t
) * np
->rx_ring_size
);
3307 memset(np
->tx_skbuff
, 0, sizeof(struct sk_buff
*) * np
->tx_ring_size
);
3308 memset(np
->tx_dma
, 0, sizeof(dma_addr_t
) * np
->tx_ring_size
);
3309 memset(np
->tx_dma_len
, 0, sizeof(unsigned int) * np
->tx_ring_size
);
3311 if (netif_running(dev
)) {
3312 /* reinit driver view of the queues */
3314 if (nv_init_ring(dev
)) {
3315 if (!np
->in_shutdown
)
3316 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3319 /* reinit nic view of the queues */
3320 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
3321 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
3322 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
3323 base
+ NvRegRingSizes
);
3325 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
3328 /* restart engines */
3331 spin_unlock(&np
->lock
);
3332 netif_tx_unlock_bh(dev
);
3340 static void nv_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
3342 struct fe_priv
*np
= netdev_priv(dev
);
3344 pause
->autoneg
= (np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) != 0;
3345 pause
->rx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) != 0;
3346 pause
->tx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) != 0;
3349 static int nv_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
3351 struct fe_priv
*np
= netdev_priv(dev
);
3354 if ((!np
->autoneg
&& np
->duplex
== 0) ||
3355 (np
->autoneg
&& !pause
->autoneg
&& np
->duplex
== 0)) {
3356 printk(KERN_INFO
"%s: can not set pause settings when forced link is in half duplex.\n",
3360 if (pause
->tx_pause
&& !(np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)) {
3361 printk(KERN_INFO
"%s: hardware does not support tx pause frames.\n", dev
->name
);
3365 netif_carrier_off(dev
);
3366 if (netif_running(dev
)) {
3367 nv_disable_irq(dev
);
3368 netif_tx_lock_bh(dev
);
3369 spin_lock(&np
->lock
);
3373 spin_unlock(&np
->lock
);
3374 netif_tx_unlock_bh(dev
);
3377 np
->pause_flags
&= ~(NV_PAUSEFRAME_RX_REQ
|NV_PAUSEFRAME_TX_REQ
);
3378 if (pause
->rx_pause
)
3379 np
->pause_flags
|= NV_PAUSEFRAME_RX_REQ
;
3380 if (pause
->tx_pause
)
3381 np
->pause_flags
|= NV_PAUSEFRAME_TX_REQ
;
3383 if (np
->autoneg
&& pause
->autoneg
) {
3384 np
->pause_flags
|= NV_PAUSEFRAME_AUTONEG
;
3386 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
3387 adv
&= ~(ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3388 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisments but disable tx pause */
3389 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
3390 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3391 adv
|= ADVERTISE_PAUSE_ASYM
;
3392 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
3394 if (netif_running(dev
))
3395 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
3396 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
3397 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
3398 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
3400 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
3401 if (pause
->rx_pause
)
3402 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3403 if (pause
->tx_pause
)
3404 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3406 if (!netif_running(dev
))
3407 nv_update_linkspeed(dev
);
3409 nv_update_pause(dev
, np
->pause_flags
);
3412 if (netif_running(dev
)) {
3420 static u32
nv_get_rx_csum(struct net_device
*dev
)
3422 struct fe_priv
*np
= netdev_priv(dev
);
3423 return (np
->txrxctl_bits
& NVREG_TXRXCTL_RXCHECK
) != 0;
3426 static int nv_set_rx_csum(struct net_device
*dev
, u32 data
)
3428 struct fe_priv
*np
= netdev_priv(dev
);
3429 u8 __iomem
*base
= get_hwbase(dev
);
3432 if (np
->driver_data
& DEV_HAS_CHECKSUM
) {
3434 if (((np
->txrxctl_bits
& NVREG_TXRXCTL_RXCHECK
) && data
) ||
3435 (!(np
->txrxctl_bits
& NVREG_TXRXCTL_RXCHECK
) && !data
)) {
3436 /* already set or unset */
3441 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
3442 } else if (!(np
->vlanctl_bits
& NVREG_VLANCONTROL_ENABLE
)) {
3443 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_RXCHECK
;
3445 printk(KERN_INFO
"Can not disable rx checksum if vlan is enabled\n");
3449 if (netif_running(dev
)) {
3450 spin_lock_irq(&np
->lock
);
3451 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
3452 spin_unlock_irq(&np
->lock
);
3461 static int nv_set_tx_csum(struct net_device
*dev
, u32 data
)
3463 struct fe_priv
*np
= netdev_priv(dev
);
3465 if (np
->driver_data
& DEV_HAS_CHECKSUM
)
3466 return ethtool_op_set_tx_hw_csum(dev
, data
);
3471 static int nv_set_sg(struct net_device
*dev
, u32 data
)
3473 struct fe_priv
*np
= netdev_priv(dev
);
3475 if (np
->driver_data
& DEV_HAS_CHECKSUM
)
3476 return ethtool_op_set_sg(dev
, data
);
3481 static int nv_get_stats_count(struct net_device
*dev
)
3483 struct fe_priv
*np
= netdev_priv(dev
);
3485 if (np
->driver_data
& DEV_HAS_STATISTICS
)
3486 return sizeof(struct nv_ethtool_stats
)/sizeof(u64
);
3491 static void nv_get_ethtool_stats(struct net_device
*dev
, struct ethtool_stats
*estats
, u64
*buffer
)
3493 struct fe_priv
*np
= netdev_priv(dev
);
3496 nv_do_stats_poll((unsigned long)dev
);
3498 memcpy(buffer
, &np
->estats
, nv_get_stats_count(dev
)*sizeof(u64
));
3501 static int nv_self_test_count(struct net_device
*dev
)
3503 struct fe_priv
*np
= netdev_priv(dev
);
3505 if (np
->driver_data
& DEV_HAS_TEST_EXTENDED
)
3506 return NV_TEST_COUNT_EXTENDED
;
3508 return NV_TEST_COUNT_BASE
;
3511 static int nv_link_test(struct net_device
*dev
)
3513 struct fe_priv
*np
= netdev_priv(dev
);
3516 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3517 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3519 /* check phy link status */
3520 if (!(mii_status
& BMSR_LSTATUS
))
3526 static int nv_register_test(struct net_device
*dev
)
3528 u8 __iomem
*base
= get_hwbase(dev
);
3530 u32 orig_read
, new_read
;
3533 orig_read
= readl(base
+ nv_registers_test
[i
].reg
);
3535 /* xor with mask to toggle bits */
3536 orig_read
^= nv_registers_test
[i
].mask
;
3538 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
3540 new_read
= readl(base
+ nv_registers_test
[i
].reg
);
3542 if ((new_read
& nv_registers_test
[i
].mask
) != (orig_read
& nv_registers_test
[i
].mask
))
3545 /* restore original value */
3546 orig_read
^= nv_registers_test
[i
].mask
;
3547 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
3549 } while (nv_registers_test
[++i
].reg
!= 0);
3554 static int nv_interrupt_test(struct net_device
*dev
)
3556 struct fe_priv
*np
= netdev_priv(dev
);
3557 u8 __iomem
*base
= get_hwbase(dev
);
3560 u32 save_msi_flags
, save_poll_interval
= 0;
3562 if (netif_running(dev
)) {
3563 /* free current irq */
3565 save_poll_interval
= readl(base
+NvRegPollingInterval
);
3568 /* flag to test interrupt handler */
3571 /* setup test irq */
3572 save_msi_flags
= np
->msi_flags
;
3573 np
->msi_flags
&= ~NV_MSI_X_VECTORS_MASK
;
3574 np
->msi_flags
|= 0x001; /* setup 1 vector */
3575 if (nv_request_irq(dev
, 1))
3578 /* setup timer interrupt */
3579 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
3580 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
3582 nv_enable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
3584 /* wait for at least one interrupt */
3587 spin_lock_irq(&np
->lock
);
3589 /* flag should be set within ISR */
3590 testcnt
= np
->intr_test
;
3594 nv_disable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
3595 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3596 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
3598 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
3600 spin_unlock_irq(&np
->lock
);
3604 np
->msi_flags
= save_msi_flags
;
3606 if (netif_running(dev
)) {
3607 writel(save_poll_interval
, base
+ NvRegPollingInterval
);
3608 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
3609 /* restore original irq */
3610 if (nv_request_irq(dev
, 0))
3617 static int nv_loopback_test(struct net_device
*dev
)
3619 struct fe_priv
*np
= netdev_priv(dev
);
3620 u8 __iomem
*base
= get_hwbase(dev
);
3621 struct sk_buff
*tx_skb
, *rx_skb
;
3622 dma_addr_t test_dma_addr
;
3623 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
3625 int len
, i
, pkt_len
;
3627 u32 filter_flags
= 0;
3628 u32 misc1_flags
= 0;
3631 if (netif_running(dev
)) {
3632 nv_disable_irq(dev
);
3633 filter_flags
= readl(base
+ NvRegPacketFilterFlags
);
3634 misc1_flags
= readl(base
+ NvRegMisc1
);
3639 /* reinit driver view of the rx queue */
3643 /* setup hardware for loopback */
3644 writel(NVREG_MISC1_FORCE
, base
+ NvRegMisc1
);
3645 writel(NVREG_PFF_ALWAYS
| NVREG_PFF_LOOPBACK
, base
+ NvRegPacketFilterFlags
);
3647 /* reinit nic view of the rx queue */
3648 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
3649 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
3650 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
3651 base
+ NvRegRingSizes
);
3654 /* restart rx engine */
3658 /* setup packet for tx */
3659 pkt_len
= ETH_DATA_LEN
;
3660 tx_skb
= dev_alloc_skb(pkt_len
);
3661 pkt_data
= skb_put(tx_skb
, pkt_len
);
3662 for (i
= 0; i
< pkt_len
; i
++)
3663 pkt_data
[i
] = (u8
)(i
& 0xff);
3664 test_dma_addr
= pci_map_single(np
->pci_dev
, tx_skb
->data
,
3665 tx_skb
->end
-tx_skb
->data
, PCI_DMA_FROMDEVICE
);
3667 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
3668 np
->tx_ring
.orig
[0].buf
= cpu_to_le32(test_dma_addr
);
3669 np
->tx_ring
.orig
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
3671 np
->tx_ring
.ex
[0].bufhigh
= cpu_to_le64(test_dma_addr
) >> 32;
3672 np
->tx_ring
.ex
[0].buflow
= cpu_to_le64(test_dma_addr
) & 0x0FFFFFFFF;
3673 np
->tx_ring
.ex
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
3675 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
3676 pci_push(get_hwbase(dev
));
3680 /* check for rx of the packet */
3681 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
3682 flags
= le32_to_cpu(np
->rx_ring
.orig
[0].flaglen
);
3683 len
= nv_descr_getlength(&np
->rx_ring
.orig
[0], np
->desc_ver
);
3686 flags
= le32_to_cpu(np
->rx_ring
.ex
[0].flaglen
);
3687 len
= nv_descr_getlength_ex(&np
->rx_ring
.ex
[0], np
->desc_ver
);
3690 if (flags
& NV_RX_AVAIL
) {
3692 } else if (np
->desc_ver
== DESC_VER_1
) {
3693 if (flags
& NV_RX_ERROR
)
3696 if (flags
& NV_RX2_ERROR
) {
3702 if (len
!= pkt_len
) {
3704 dprintk(KERN_DEBUG
"%s: loopback len mismatch %d vs %d\n",
3705 dev
->name
, len
, pkt_len
);
3707 rx_skb
= np
->rx_skbuff
[0];
3708 for (i
= 0; i
< pkt_len
; i
++) {
3709 if (rx_skb
->data
[i
] != (u8
)(i
& 0xff)) {
3711 dprintk(KERN_DEBUG
"%s: loopback pattern check failed on byte %d\n",
3718 dprintk(KERN_DEBUG
"%s: loopback - did not receive test packet\n", dev
->name
);
3721 pci_unmap_page(np
->pci_dev
, test_dma_addr
,
3722 tx_skb
->end
-tx_skb
->data
,
3724 dev_kfree_skb_any(tx_skb
);
3730 /* drain rx queue */
3734 if (netif_running(dev
)) {
3735 writel(misc1_flags
, base
+ NvRegMisc1
);
3736 writel(filter_flags
, base
+ NvRegPacketFilterFlags
);
3743 static void nv_self_test(struct net_device
*dev
, struct ethtool_test
*test
, u64
*buffer
)
3745 struct fe_priv
*np
= netdev_priv(dev
);
3746 u8 __iomem
*base
= get_hwbase(dev
);
3748 memset(buffer
, 0, nv_self_test_count(dev
)*sizeof(u64
));
3750 if (!nv_link_test(dev
)) {
3751 test
->flags
|= ETH_TEST_FL_FAILED
;
3755 if (test
->flags
& ETH_TEST_FL_OFFLINE
) {
3756 if (netif_running(dev
)) {
3757 netif_stop_queue(dev
);
3758 netif_tx_lock_bh(dev
);
3759 spin_lock_irq(&np
->lock
);
3760 nv_disable_hw_interrupts(dev
, np
->irqmask
);
3761 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3762 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
3764 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
3770 /* drain rx queue */
3773 spin_unlock_irq(&np
->lock
);
3774 netif_tx_unlock_bh(dev
);
3777 if (!nv_register_test(dev
)) {
3778 test
->flags
|= ETH_TEST_FL_FAILED
;
3782 result
= nv_interrupt_test(dev
);
3784 test
->flags
|= ETH_TEST_FL_FAILED
;
3792 if (!nv_loopback_test(dev
)) {
3793 test
->flags
|= ETH_TEST_FL_FAILED
;
3797 if (netif_running(dev
)) {
3798 /* reinit driver view of the rx queue */
3800 if (nv_init_ring(dev
)) {
3801 if (!np
->in_shutdown
)
3802 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3804 /* reinit nic view of the rx queue */
3805 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
3806 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
3807 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
3808 base
+ NvRegRingSizes
);
3810 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
3812 /* restart rx engine */
3815 netif_start_queue(dev
);
3816 nv_enable_hw_interrupts(dev
, np
->irqmask
);
3821 static void nv_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buffer
)
3823 switch (stringset
) {
3825 memcpy(buffer
, &nv_estats_str
, nv_get_stats_count(dev
)*sizeof(struct nv_ethtool_str
));
3828 memcpy(buffer
, &nv_etests_str
, nv_self_test_count(dev
)*sizeof(struct nv_ethtool_str
));
3833 static struct ethtool_ops ops
= {
3834 .get_drvinfo
= nv_get_drvinfo
,
3835 .get_link
= ethtool_op_get_link
,
3836 .get_wol
= nv_get_wol
,
3837 .set_wol
= nv_set_wol
,
3838 .get_settings
= nv_get_settings
,
3839 .set_settings
= nv_set_settings
,
3840 .get_regs_len
= nv_get_regs_len
,
3841 .get_regs
= nv_get_regs
,
3842 .nway_reset
= nv_nway_reset
,
3843 .get_perm_addr
= ethtool_op_get_perm_addr
,
3844 .get_tso
= ethtool_op_get_tso
,
3845 .set_tso
= nv_set_tso
,
3846 .get_ringparam
= nv_get_ringparam
,
3847 .set_ringparam
= nv_set_ringparam
,
3848 .get_pauseparam
= nv_get_pauseparam
,
3849 .set_pauseparam
= nv_set_pauseparam
,
3850 .get_rx_csum
= nv_get_rx_csum
,
3851 .set_rx_csum
= nv_set_rx_csum
,
3852 .get_tx_csum
= ethtool_op_get_tx_csum
,
3853 .set_tx_csum
= nv_set_tx_csum
,
3854 .get_sg
= ethtool_op_get_sg
,
3855 .set_sg
= nv_set_sg
,
3856 .get_strings
= nv_get_strings
,
3857 .get_stats_count
= nv_get_stats_count
,
3858 .get_ethtool_stats
= nv_get_ethtool_stats
,
3859 .self_test_count
= nv_self_test_count
,
3860 .self_test
= nv_self_test
,
3863 static void nv_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
3865 struct fe_priv
*np
= get_nvpriv(dev
);
3867 spin_lock_irq(&np
->lock
);
3869 /* save vlan group */
3873 /* enable vlan on MAC */
3874 np
->txrxctl_bits
|= NVREG_TXRXCTL_VLANSTRIP
| NVREG_TXRXCTL_VLANINS
;
3876 /* disable vlan on MAC */
3877 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANSTRIP
;
3878 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANINS
;
3881 writel(np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
3883 spin_unlock_irq(&np
->lock
);
3886 static void nv_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
3891 static int nv_open(struct net_device
*dev
)
3893 struct fe_priv
*np
= netdev_priv(dev
);
3894 u8 __iomem
*base
= get_hwbase(dev
);
3898 dprintk(KERN_DEBUG
"nv_open: begin\n");
3900 /* erase previous misconfiguration */
3901 if (np
->driver_data
& DEV_HAS_POWER_CNTRL
)
3903 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
3904 writel(0, base
+ NvRegMulticastAddrB
);
3905 writel(0, base
+ NvRegMulticastMaskA
);
3906 writel(0, base
+ NvRegMulticastMaskB
);
3907 writel(0, base
+ NvRegPacketFilterFlags
);
3909 writel(0, base
+ NvRegTransmitterControl
);
3910 writel(0, base
+ NvRegReceiverControl
);
3912 writel(0, base
+ NvRegAdapterControl
);
3914 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)
3915 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
3917 /* initialize descriptor rings */
3919 oom
= nv_init_ring(dev
);
3921 writel(0, base
+ NvRegLinkSpeed
);
3922 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
3924 writel(0, base
+ NvRegUnknownSetupReg6
);
3926 np
->in_shutdown
= 0;
3929 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
3930 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
3931 base
+ NvRegRingSizes
);
3933 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
3934 if (np
->desc_ver
== DESC_VER_1
)
3935 writel(NVREG_TX_WM_DESC1_DEFAULT
, base
+ NvRegTxWatermark
);
3937 writel(NVREG_TX_WM_DESC2_3_DEFAULT
, base
+ NvRegTxWatermark
);
3938 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
3939 writel(np
->vlanctl_bits
, base
+ NvRegVlanControl
);
3941 writel(NVREG_TXRXCTL_BIT1
|np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
3942 reg_delay(dev
, NvRegUnknownSetupReg5
, NVREG_UNKSETUP5_BIT31
, NVREG_UNKSETUP5_BIT31
,
3943 NV_SETUP5_DELAY
, NV_SETUP5_DELAYMAX
,
3944 KERN_INFO
"open: SetupReg5, Bit 31 remained off\n");
3946 writel(0, base
+ NvRegUnknownSetupReg4
);
3947 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
3948 writel(NVREG_MIISTAT_MASK2
, base
+ NvRegMIIStatus
);
3950 writel(NVREG_MISC1_FORCE
| NVREG_MISC1_HD
, base
+ NvRegMisc1
);
3951 writel(readl(base
+ NvRegTransmitterStatus
), base
+ NvRegTransmitterStatus
);
3952 writel(NVREG_PFF_ALWAYS
, base
+ NvRegPacketFilterFlags
);
3953 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
3955 writel(readl(base
+ NvRegReceiverStatus
), base
+ NvRegReceiverStatus
);
3956 get_random_bytes(&i
, sizeof(i
));
3957 writel(NVREG_RNDSEED_FORCE
| (i
&NVREG_RNDSEED_MASK
), base
+ NvRegRandomSeed
);
3958 writel(NVREG_TX_DEFERRAL_DEFAULT
, base
+ NvRegTxDeferral
);
3959 writel(NVREG_RX_DEFERRAL_DEFAULT
, base
+ NvRegRxDeferral
);
3960 if (poll_interval
== -1) {
3961 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
)
3962 writel(NVREG_POLL_DEFAULT_THROUGHPUT
, base
+ NvRegPollingInterval
);
3964 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
3967 writel(poll_interval
& 0xFFFF, base
+ NvRegPollingInterval
);
3968 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
3969 writel((np
->phyaddr
<< NVREG_ADAPTCTL_PHYSHIFT
)|NVREG_ADAPTCTL_PHYVALID
|NVREG_ADAPTCTL_RUNNING
,
3970 base
+ NvRegAdapterControl
);
3971 writel(NVREG_MIISPEED_BIT8
|NVREG_MIIDELAY
, base
+ NvRegMIISpeed
);
3972 writel(NVREG_UNKSETUP4_VAL
, base
+ NvRegUnknownSetupReg4
);
3974 writel(NVREG_WAKEUPFLAGS_ENABLE
, base
+ NvRegWakeUpFlags
);
3976 i
= readl(base
+ NvRegPowerState
);
3977 if ( (i
& NVREG_POWERSTATE_POWEREDUP
) == 0)
3978 writel(NVREG_POWERSTATE_POWEREDUP
|i
, base
+ NvRegPowerState
);
3982 writel(readl(base
+ NvRegPowerState
) | NVREG_POWERSTATE_VALID
, base
+ NvRegPowerState
);
3984 nv_disable_hw_interrupts(dev
, np
->irqmask
);
3986 writel(NVREG_MIISTAT_MASK2
, base
+ NvRegMIIStatus
);
3987 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
3990 if (nv_request_irq(dev
, 0)) {
3994 /* ask for interrupts */
3995 nv_enable_hw_interrupts(dev
, np
->irqmask
);
3997 spin_lock_irq(&np
->lock
);
3998 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
3999 writel(0, base
+ NvRegMulticastAddrB
);
4000 writel(0, base
+ NvRegMulticastMaskA
);
4001 writel(0, base
+ NvRegMulticastMaskB
);
4002 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
4003 /* One manual link speed update: Interrupts are enabled, future link
4004 * speed changes cause interrupts and are handled by nv_link_irq().
4008 miistat
= readl(base
+ NvRegMIIStatus
);
4009 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
4010 dprintk(KERN_INFO
"startup: got 0x%08x.\n", miistat
);
4012 /* set linkspeed to invalid value, thus force nv_update_linkspeed
4015 ret
= nv_update_linkspeed(dev
);
4018 netif_start_queue(dev
);
4020 netif_carrier_on(dev
);
4022 printk("%s: no link during initialization.\n", dev
->name
);
4023 netif_carrier_off(dev
);
4026 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4028 /* start statistics timer */
4029 if (np
->driver_data
& DEV_HAS_STATISTICS
)
4030 mod_timer(&np
->stats_poll
, jiffies
+ STATS_INTERVAL
);
4032 spin_unlock_irq(&np
->lock
);
4040 static int nv_close(struct net_device
*dev
)
4042 struct fe_priv
*np
= netdev_priv(dev
);
4045 spin_lock_irq(&np
->lock
);
4046 np
->in_shutdown
= 1;
4047 spin_unlock_irq(&np
->lock
);
4048 synchronize_irq(dev
->irq
);
4050 del_timer_sync(&np
->oom_kick
);
4051 del_timer_sync(&np
->nic_poll
);
4052 del_timer_sync(&np
->stats_poll
);
4054 netif_stop_queue(dev
);
4055 spin_lock_irq(&np
->lock
);
4060 /* disable interrupts on the nic or we will lock up */
4061 base
= get_hwbase(dev
);
4062 nv_disable_hw_interrupts(dev
, np
->irqmask
);
4064 dprintk(KERN_INFO
"%s: Irqmask is zero again\n", dev
->name
);
4066 spin_unlock_irq(&np
->lock
);
4075 /* FIXME: power down nic */
4080 static int __devinit
nv_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
4082 struct net_device
*dev
;
4087 u32 powerstate
, txreg
;
4089 dev
= alloc_etherdev(sizeof(struct fe_priv
));
4094 np
= netdev_priv(dev
);
4095 np
->pci_dev
= pci_dev
;
4096 spin_lock_init(&np
->lock
);
4097 SET_MODULE_OWNER(dev
);
4098 SET_NETDEV_DEV(dev
, &pci_dev
->dev
);
4100 init_timer(&np
->oom_kick
);
4101 np
->oom_kick
.data
= (unsigned long) dev
;
4102 np
->oom_kick
.function
= &nv_do_rx_refill
; /* timer handler */
4103 init_timer(&np
->nic_poll
);
4104 np
->nic_poll
.data
= (unsigned long) dev
;
4105 np
->nic_poll
.function
= &nv_do_nic_poll
; /* timer handler */
4106 init_timer(&np
->stats_poll
);
4107 np
->stats_poll
.data
= (unsigned long) dev
;
4108 np
->stats_poll
.function
= &nv_do_stats_poll
; /* timer handler */
4110 err
= pci_enable_device(pci_dev
);
4112 printk(KERN_INFO
"forcedeth: pci_enable_dev failed (%d) for device %s\n",
4113 err
, pci_name(pci_dev
));
4117 pci_set_master(pci_dev
);
4119 err
= pci_request_regions(pci_dev
, DRV_NAME
);
4123 if (id
->driver_data
& (DEV_HAS_VLAN
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS
))
4124 np
->register_size
= NV_PCI_REGSZ_VER2
;
4126 np
->register_size
= NV_PCI_REGSZ_VER1
;
4130 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
4131 dprintk(KERN_DEBUG
"%s: resource %d start %p len %ld flags 0x%08lx.\n",
4132 pci_name(pci_dev
), i
, (void*)pci_resource_start(pci_dev
, i
),
4133 pci_resource_len(pci_dev
, i
),
4134 pci_resource_flags(pci_dev
, i
));
4135 if (pci_resource_flags(pci_dev
, i
) & IORESOURCE_MEM
&&
4136 pci_resource_len(pci_dev
, i
) >= np
->register_size
) {
4137 addr
= pci_resource_start(pci_dev
, i
);
4141 if (i
== DEVICE_COUNT_RESOURCE
) {
4142 printk(KERN_INFO
"forcedeth: Couldn't find register window for device %s.\n",
4147 /* copy of driver data */
4148 np
->driver_data
= id
->driver_data
;
4150 /* handle different descriptor versions */
4151 if (id
->driver_data
& DEV_HAS_HIGH_DMA
) {
4152 /* packet format 3: supports 40-bit addressing */
4153 np
->desc_ver
= DESC_VER_3
;
4154 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_3
;
4156 if (pci_set_dma_mask(pci_dev
, DMA_39BIT_MASK
)) {
4157 printk(KERN_INFO
"forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4160 dev
->features
|= NETIF_F_HIGHDMA
;
4161 printk(KERN_INFO
"forcedeth: using HIGHDMA\n");
4163 if (pci_set_consistent_dma_mask(pci_dev
, DMA_39BIT_MASK
)) {
4164 printk(KERN_INFO
"forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4168 } else if (id
->driver_data
& DEV_HAS_LARGEDESC
) {
4169 /* packet format 2: supports jumbo frames */
4170 np
->desc_ver
= DESC_VER_2
;
4171 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_2
;
4173 /* original packet format */
4174 np
->desc_ver
= DESC_VER_1
;
4175 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_1
;
4178 np
->pkt_limit
= NV_PKTLIMIT_1
;
4179 if (id
->driver_data
& DEV_HAS_LARGEDESC
)
4180 np
->pkt_limit
= NV_PKTLIMIT_2
;
4182 if (id
->driver_data
& DEV_HAS_CHECKSUM
) {
4183 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
4184 dev
->features
|= NETIF_F_HW_CSUM
| NETIF_F_SG
;
4186 dev
->features
|= NETIF_F_TSO
;
4190 np
->vlanctl_bits
= 0;
4191 if (id
->driver_data
& DEV_HAS_VLAN
) {
4192 np
->vlanctl_bits
= NVREG_VLANCONTROL_ENABLE
;
4193 dev
->features
|= NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
;
4194 dev
->vlan_rx_register
= nv_vlan_rx_register
;
4195 dev
->vlan_rx_kill_vid
= nv_vlan_rx_kill_vid
;
4199 if ((id
->driver_data
& DEV_HAS_MSI
) && msi
) {
4200 np
->msi_flags
|= NV_MSI_CAPABLE
;
4202 if ((id
->driver_data
& DEV_HAS_MSI_X
) && msix
) {
4203 np
->msi_flags
|= NV_MSI_X_CAPABLE
;
4206 np
->pause_flags
= NV_PAUSEFRAME_RX_CAPABLE
| NV_PAUSEFRAME_RX_REQ
| NV_PAUSEFRAME_AUTONEG
;
4207 if (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX
) {
4208 np
->pause_flags
|= NV_PAUSEFRAME_TX_CAPABLE
| NV_PAUSEFRAME_TX_REQ
;
4213 np
->base
= ioremap(addr
, np
->register_size
);
4216 dev
->base_addr
= (unsigned long)np
->base
;
4218 dev
->irq
= pci_dev
->irq
;
4220 np
->rx_ring_size
= RX_RING_DEFAULT
;
4221 np
->tx_ring_size
= TX_RING_DEFAULT
;
4222 np
->tx_limit_stop
= np
->tx_ring_size
- TX_LIMIT_DIFFERENCE
;
4223 np
->tx_limit_start
= np
->tx_ring_size
- TX_LIMIT_DIFFERENCE
- 1;
4225 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
4226 np
->rx_ring
.orig
= pci_alloc_consistent(pci_dev
,
4227 sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
4229 if (!np
->rx_ring
.orig
)
4231 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
4233 np
->rx_ring
.ex
= pci_alloc_consistent(pci_dev
,
4234 sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
4236 if (!np
->rx_ring
.ex
)
4238 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
4240 np
->rx_skbuff
= kmalloc(sizeof(struct sk_buff
*) * np
->rx_ring_size
, GFP_KERNEL
);
4241 np
->rx_dma
= kmalloc(sizeof(dma_addr_t
) * np
->rx_ring_size
, GFP_KERNEL
);
4242 np
->tx_skbuff
= kmalloc(sizeof(struct sk_buff
*) * np
->tx_ring_size
, GFP_KERNEL
);
4243 np
->tx_dma
= kmalloc(sizeof(dma_addr_t
) * np
->tx_ring_size
, GFP_KERNEL
);
4244 np
->tx_dma_len
= kmalloc(sizeof(unsigned int) * np
->tx_ring_size
, GFP_KERNEL
);
4245 if (!np
->rx_skbuff
|| !np
->rx_dma
|| !np
->tx_skbuff
|| !np
->tx_dma
|| !np
->tx_dma_len
)
4247 memset(np
->rx_skbuff
, 0, sizeof(struct sk_buff
*) * np
->rx_ring_size
);
4248 memset(np
->rx_dma
, 0, sizeof(dma_addr_t
) * np
->rx_ring_size
);
4249 memset(np
->tx_skbuff
, 0, sizeof(struct sk_buff
*) * np
->tx_ring_size
);
4250 memset(np
->tx_dma
, 0, sizeof(dma_addr_t
) * np
->tx_ring_size
);
4251 memset(np
->tx_dma_len
, 0, sizeof(unsigned int) * np
->tx_ring_size
);
4253 dev
->open
= nv_open
;
4254 dev
->stop
= nv_close
;
4255 dev
->hard_start_xmit
= nv_start_xmit
;
4256 dev
->get_stats
= nv_get_stats
;
4257 dev
->change_mtu
= nv_change_mtu
;
4258 dev
->set_mac_address
= nv_set_mac_address
;
4259 dev
->set_multicast_list
= nv_set_multicast
;
4260 #ifdef CONFIG_NET_POLL_CONTROLLER
4261 dev
->poll_controller
= nv_poll_controller
;
4263 SET_ETHTOOL_OPS(dev
, &ops
);
4264 dev
->tx_timeout
= nv_tx_timeout
;
4265 dev
->watchdog_timeo
= NV_WATCHDOG_TIMEO
;
4267 pci_set_drvdata(pci_dev
, dev
);
4269 /* read the mac address */
4270 base
= get_hwbase(dev
);
4271 np
->orig_mac
[0] = readl(base
+ NvRegMacAddrA
);
4272 np
->orig_mac
[1] = readl(base
+ NvRegMacAddrB
);
4274 /* check the workaround bit for correct mac address order */
4275 txreg
= readl(base
+ NvRegTransmitPoll
);
4276 if (txreg
& NVREG_TRANSMITPOLL_MAC_ADDR_REV
) {
4277 /* mac address is already in correct order */
4278 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
4279 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
4280 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
4281 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
4282 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
4283 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
4285 /* need to reverse mac address to correct order */
4286 dev
->dev_addr
[0] = (np
->orig_mac
[1] >> 8) & 0xff;
4287 dev
->dev_addr
[1] = (np
->orig_mac
[1] >> 0) & 0xff;
4288 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 24) & 0xff;
4289 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 16) & 0xff;
4290 dev
->dev_addr
[4] = (np
->orig_mac
[0] >> 8) & 0xff;
4291 dev
->dev_addr
[5] = (np
->orig_mac
[0] >> 0) & 0xff;
4292 /* set permanent address to be correct aswell */
4293 np
->orig_mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
4294 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
4295 np
->orig_mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
4296 writel(txreg
|NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
4298 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
4300 if (!is_valid_ether_addr(dev
->perm_addr
)) {
4302 * Bad mac address. At least one bios sets the mac address
4303 * to 01:23:45:67:89:ab
4305 printk(KERN_ERR
"%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4307 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
4308 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
4309 printk(KERN_ERR
"Please complain to your hardware vendor. Switching to a random MAC.\n");
4310 dev
->dev_addr
[0] = 0x00;
4311 dev
->dev_addr
[1] = 0x00;
4312 dev
->dev_addr
[2] = 0x6c;
4313 get_random_bytes(&dev
->dev_addr
[3], 3);
4316 dprintk(KERN_DEBUG
"%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev
),
4317 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
4318 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
4320 /* set mac address */
4321 nv_copy_mac_to_hw(dev
);
4324 writel(0, base
+ NvRegWakeUpFlags
);
4327 if (id
->driver_data
& DEV_HAS_POWER_CNTRL
) {
4329 pci_read_config_byte(pci_dev
, PCI_REVISION_ID
, &revision_id
);
4331 /* take phy and nic out of low power mode */
4332 powerstate
= readl(base
+ NvRegPowerState2
);
4333 powerstate
&= ~NVREG_POWERSTATE2_POWERUP_MASK
;
4334 if ((id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_12
||
4335 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_13
) &&
4336 revision_id
>= 0xA3)
4337 powerstate
|= NVREG_POWERSTATE2_POWERUP_REV_A3
;
4338 writel(powerstate
, base
+ NvRegPowerState2
);
4341 if (np
->desc_ver
== DESC_VER_1
) {
4342 np
->tx_flags
= NV_TX_VALID
;
4344 np
->tx_flags
= NV_TX2_VALID
;
4346 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
) {
4347 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
4348 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
4349 np
->msi_flags
|= 0x0003;
4351 np
->irqmask
= NVREG_IRQMASK_CPU
;
4352 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
4353 np
->msi_flags
|= 0x0001;
4356 if (id
->driver_data
& DEV_NEED_TIMERIRQ
)
4357 np
->irqmask
|= NVREG_IRQ_TIMER
;
4358 if (id
->driver_data
& DEV_NEED_LINKTIMER
) {
4359 dprintk(KERN_INFO
"%s: link timer on.\n", pci_name(pci_dev
));
4360 np
->need_linktimer
= 1;
4361 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
4363 dprintk(KERN_INFO
"%s: link timer off.\n", pci_name(pci_dev
));
4364 np
->need_linktimer
= 0;
4367 /* find a suitable phy */
4368 for (i
= 1; i
<= 32; i
++) {
4370 int phyaddr
= i
& 0x1F;
4372 spin_lock_irq(&np
->lock
);
4373 id1
= mii_rw(dev
, phyaddr
, MII_PHYSID1
, MII_READ
);
4374 spin_unlock_irq(&np
->lock
);
4375 if (id1
< 0 || id1
== 0xffff)
4377 spin_lock_irq(&np
->lock
);
4378 id2
= mii_rw(dev
, phyaddr
, MII_PHYSID2
, MII_READ
);
4379 spin_unlock_irq(&np
->lock
);
4380 if (id2
< 0 || id2
== 0xffff)
4383 id1
= (id1
& PHYID1_OUI_MASK
) << PHYID1_OUI_SHFT
;
4384 id2
= (id2
& PHYID2_OUI_MASK
) >> PHYID2_OUI_SHFT
;
4385 dprintk(KERN_DEBUG
"%s: open: Found PHY %04x:%04x at address %d.\n",
4386 pci_name(pci_dev
), id1
, id2
, phyaddr
);
4387 np
->phyaddr
= phyaddr
;
4388 np
->phy_oui
= id1
| id2
;
4392 printk(KERN_INFO
"%s: open: Could not find a valid PHY.\n",
4400 /* set default link speed settings */
4401 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
4405 err
= register_netdev(dev
);
4407 printk(KERN_INFO
"forcedeth: unable to register netdev: %d\n", err
);
4410 printk(KERN_INFO
"%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4411 dev
->name
, pci_dev
->subsystem_vendor
, pci_dev
->subsystem_device
,
4417 pci_set_drvdata(pci_dev
, NULL
);
4421 iounmap(get_hwbase(dev
));
4423 pci_release_regions(pci_dev
);
4425 pci_disable_device(pci_dev
);
4432 static void __devexit
nv_remove(struct pci_dev
*pci_dev
)
4434 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
4435 struct fe_priv
*np
= netdev_priv(dev
);
4436 u8 __iomem
*base
= get_hwbase(dev
);
4438 unregister_netdev(dev
);
4440 /* special op: write back the misordered MAC address - otherwise
4441 * the next nv_probe would see a wrong address.
4443 writel(np
->orig_mac
[0], base
+ NvRegMacAddrA
);
4444 writel(np
->orig_mac
[1], base
+ NvRegMacAddrB
);
4446 /* free all structures */
4448 iounmap(get_hwbase(dev
));
4449 pci_release_regions(pci_dev
);
4450 pci_disable_device(pci_dev
);
4452 pci_set_drvdata(pci_dev
, NULL
);
4455 static struct pci_device_id pci_tbl
[] = {
4456 { /* nForce Ethernet Controller */
4457 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_1
),
4458 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
4460 { /* nForce2 Ethernet Controller */
4461 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_2
),
4462 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
4464 { /* nForce3 Ethernet Controller */
4465 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_3
),
4466 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
4468 { /* nForce3 Ethernet Controller */
4469 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_4
),
4470 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
4472 { /* nForce3 Ethernet Controller */
4473 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_5
),
4474 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
4476 { /* nForce3 Ethernet Controller */
4477 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_6
),
4478 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
4480 { /* nForce3 Ethernet Controller */
4481 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_7
),
4482 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
4484 { /* CK804 Ethernet Controller */
4485 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_8
),
4486 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
4488 { /* CK804 Ethernet Controller */
4489 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_9
),
4490 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
4492 { /* MCP04 Ethernet Controller */
4493 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_10
),
4494 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
4496 { /* MCP04 Ethernet Controller */
4497 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_11
),
4498 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
4500 { /* MCP51 Ethernet Controller */
4501 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_12
),
4502 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
,
4504 { /* MCP51 Ethernet Controller */
4505 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_13
),
4506 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
,
4508 { /* MCP55 Ethernet Controller */
4509 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_14
),
4510 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
,
4512 { /* MCP55 Ethernet Controller */
4513 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_15
),
4514 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
,
4516 { /* MCP61 Ethernet Controller */
4517 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_16
),
4518 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
,
4520 { /* MCP61 Ethernet Controller */
4521 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_17
),
4522 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
,
4524 { /* MCP61 Ethernet Controller */
4525 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_18
),
4526 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
,
4528 { /* MCP61 Ethernet Controller */
4529 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_19
),
4530 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
,
4532 { /* MCP65 Ethernet Controller */
4533 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_20
),
4534 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
,
4536 { /* MCP65 Ethernet Controller */
4537 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_21
),
4538 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
,
4540 { /* MCP65 Ethernet Controller */
4541 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_22
),
4542 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
,
4544 { /* MCP65 Ethernet Controller */
4545 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_23
),
4546 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
,
4551 static struct pci_driver driver
= {
4552 .name
= "forcedeth",
4553 .id_table
= pci_tbl
,
4555 .remove
= __devexit_p(nv_remove
),
4559 static int __init
init_nic(void)
4561 printk(KERN_INFO
"forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION
);
4562 return pci_module_init(&driver
);
4565 static void __exit
exit_nic(void)
4567 pci_unregister_driver(&driver
);
4570 module_param(max_interrupt_work
, int, 0);
4571 MODULE_PARM_DESC(max_interrupt_work
, "forcedeth maximum events handled per interrupt");
4572 module_param(optimization_mode
, int, 0);
4573 MODULE_PARM_DESC(optimization_mode
, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
4574 module_param(poll_interval
, int, 0);
4575 MODULE_PARM_DESC(poll_interval
, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
4576 module_param(msi
, int, 0);
4577 MODULE_PARM_DESC(msi
, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
4578 module_param(msix
, int, 0);
4579 MODULE_PARM_DESC(msix
, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
4580 module_param(dma_64bit
, int, 0);
4581 MODULE_PARM_DESC(dma_64bit
, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
4583 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4584 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4585 MODULE_LICENSE("GPL");
4587 MODULE_DEVICE_TABLE(pci
, pci_tbl
);
4589 module_init(init_nic
);
4590 module_exit(exit_nic
);