2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,5,6 NVIDIA Corporation
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 * 0.01: 05 Oct 2003: First release that compiles without warnings.
34 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
35 * Check all PCI BARs for the register window.
36 * udelay added to mii_rw.
37 * 0.03: 06 Oct 2003: Initialize dev->irq.
38 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
39 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
40 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
42 * 0.07: 14 Oct 2003: Further irq mask updates.
43 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
44 * added into irq handler, NULL check for drain_ring.
45 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
46 * requested interrupt sources.
47 * 0.10: 20 Oct 2003: First cleanup for release.
48 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
49 * MAC Address init fix, set_multicast cleanup.
50 * 0.12: 23 Oct 2003: Cleanups for release.
51 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
52 * Set link speed correctly. start rx before starting
53 * tx (nv_start_rx sets the link speed).
54 * 0.14: 25 Oct 2003: Nic dependant irq mask.
55 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
57 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
58 * increased to 1628 bytes.
59 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
61 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
62 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
63 * addresses, really stop rx if already running
64 * in nv_start_rx, clean up a bit.
65 * 0.20: 07 Dec 2003: alloc fixes
66 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
67 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
69 * 0.23: 26 Jan 2004: various small cleanups
70 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
71 * 0.25: 09 Mar 2004: wol support
72 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
73 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
74 * added CK804/MCP04 device IDs, code fixes
75 * for registers, link status and other minor fixes.
76 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
77 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
78 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
79 * into nv_close, otherwise reenabling for wol can
80 * cause DMA to kfree'd memory.
81 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
83 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
84 * 0.33: 16 May 2005: Support for MCP51 added.
85 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
86 * 0.35: 26 Jun 2005: Support for MCP55 added.
87 * 0.36: 28 Jun 2005: Add jumbo frame support.
88 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
89 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
91 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
92 * 0.40: 19 Jul 2005: Add support for mac address change.
93 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
95 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
96 * in the second (and later) nv_open call
97 * 0.43: 10 Aug 2005: Add support for tx checksum.
98 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
99 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
100 * 0.46: 20 Oct 2005: Add irq optimization modes.
101 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
102 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
103 * 0.49: 10 Dec 2005: Fix tso for large buffers.
104 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
105 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
106 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
107 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
108 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
109 * 0.55: 22 Mar 2006: Add flow control (pause frame).
110 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
111 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
112 * 0.58: 30 Oct 2006: Added support for sideband management unit.
113 * 0.59: 30 Oct 2006: Added support for recoverable error.
116 * We suspect that on some hardware no TX done interrupts are generated.
117 * This means recovery from netif_stop_queue only happens if the hw timer
118 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
119 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
120 * If your hardware reliably generates tx done interrupts, then you can remove
121 * DEV_NEED_TIMERIRQ from the driver_data flags.
122 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
123 * superfluous timer interrupts from the nic.
125 #ifdef CONFIG_FORCEDETH_NAPI
126 #define DRIVERNAPI "-NAPI"
130 #define FORCEDETH_VERSION "0.59"
131 #define DRV_NAME "forcedeth"
133 #include <linux/module.h>
134 #include <linux/types.h>
135 #include <linux/pci.h>
136 #include <linux/interrupt.h>
137 #include <linux/netdevice.h>
138 #include <linux/etherdevice.h>
139 #include <linux/delay.h>
140 #include <linux/spinlock.h>
141 #include <linux/ethtool.h>
142 #include <linux/timer.h>
143 #include <linux/skbuff.h>
144 #include <linux/mii.h>
145 #include <linux/random.h>
146 #include <linux/init.h>
147 #include <linux/if_vlan.h>
148 #include <linux/dma-mapping.h>
152 #include <asm/uaccess.h>
153 #include <asm/system.h>
156 #define dprintk printk
158 #define dprintk(x...) do { } while (0)
166 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
167 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
168 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
169 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
170 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
171 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
172 #define DEV_HAS_MSI 0x0040 /* device supports MSI */
173 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
174 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
175 #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
176 #define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
177 #define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */
178 #define DEV_HAS_MGMT_UNIT 0x1000 /* device supports management unit */
181 NvRegIrqStatus
= 0x000,
182 #define NVREG_IRQSTAT_MIIEVENT 0x040
183 #define NVREG_IRQSTAT_MASK 0x81ff
184 NvRegIrqMask
= 0x004,
185 #define NVREG_IRQ_RX_ERROR 0x0001
186 #define NVREG_IRQ_RX 0x0002
187 #define NVREG_IRQ_RX_NOBUF 0x0004
188 #define NVREG_IRQ_TX_ERR 0x0008
189 #define NVREG_IRQ_TX_OK 0x0010
190 #define NVREG_IRQ_TIMER 0x0020
191 #define NVREG_IRQ_LINK 0x0040
192 #define NVREG_IRQ_RX_FORCED 0x0080
193 #define NVREG_IRQ_TX_FORCED 0x0100
194 #define NVREG_IRQ_RECOVER_ERROR 0x8000
195 #define NVREG_IRQMASK_THROUGHPUT 0x00df
196 #define NVREG_IRQMASK_CPU 0x0040
197 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
198 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
199 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
201 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
202 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
203 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
205 NvRegUnknownSetupReg6
= 0x008,
206 #define NVREG_UNKSETUP6_VAL 3
209 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
210 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
212 NvRegPollingInterval
= 0x00c,
213 #define NVREG_POLL_DEFAULT_THROUGHPUT 970
214 #define NVREG_POLL_DEFAULT_CPU 13
215 NvRegMSIMap0
= 0x020,
216 NvRegMSIMap1
= 0x024,
217 NvRegMSIIrqMask
= 0x030,
218 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
220 #define NVREG_MISC1_PAUSE_TX 0x01
221 #define NVREG_MISC1_HD 0x02
222 #define NVREG_MISC1_FORCE 0x3b0f3c
224 NvRegMacReset
= 0x3c,
225 #define NVREG_MAC_RESET_ASSERT 0x0F3
226 NvRegTransmitterControl
= 0x084,
227 #define NVREG_XMITCTL_START 0x01
228 #define NVREG_XMITCTL_MGMT_ST 0x40000000
229 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
230 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
231 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
232 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
233 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
234 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
235 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
236 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
237 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
238 NvRegTransmitterStatus
= 0x088,
239 #define NVREG_XMITSTAT_BUSY 0x01
241 NvRegPacketFilterFlags
= 0x8c,
242 #define NVREG_PFF_PAUSE_RX 0x08
243 #define NVREG_PFF_ALWAYS 0x7F0000
244 #define NVREG_PFF_PROMISC 0x80
245 #define NVREG_PFF_MYADDR 0x20
246 #define NVREG_PFF_LOOPBACK 0x10
248 NvRegOffloadConfig
= 0x90,
249 #define NVREG_OFFLOAD_HOMEPHY 0x601
250 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
251 NvRegReceiverControl
= 0x094,
252 #define NVREG_RCVCTL_START 0x01
253 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
254 NvRegReceiverStatus
= 0x98,
255 #define NVREG_RCVSTAT_BUSY 0x01
257 NvRegRandomSeed
= 0x9c,
258 #define NVREG_RNDSEED_MASK 0x00ff
259 #define NVREG_RNDSEED_FORCE 0x7f00
260 #define NVREG_RNDSEED_FORCE2 0x2d00
261 #define NVREG_RNDSEED_FORCE3 0x7400
263 NvRegTxDeferral
= 0xA0,
264 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
265 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
266 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
267 NvRegRxDeferral
= 0xA4,
268 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
269 NvRegMacAddrA
= 0xA8,
270 NvRegMacAddrB
= 0xAC,
271 NvRegMulticastAddrA
= 0xB0,
272 #define NVREG_MCASTADDRA_FORCE 0x01
273 NvRegMulticastAddrB
= 0xB4,
274 NvRegMulticastMaskA
= 0xB8,
275 NvRegMulticastMaskB
= 0xBC,
277 NvRegPhyInterface
= 0xC0,
278 #define PHY_RGMII 0x10000000
280 NvRegTxRingPhysAddr
= 0x100,
281 NvRegRxRingPhysAddr
= 0x104,
282 NvRegRingSizes
= 0x108,
283 #define NVREG_RINGSZ_TXSHIFT 0
284 #define NVREG_RINGSZ_RXSHIFT 16
285 NvRegTransmitPoll
= 0x10c,
286 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
287 NvRegLinkSpeed
= 0x110,
288 #define NVREG_LINKSPEED_FORCE 0x10000
289 #define NVREG_LINKSPEED_10 1000
290 #define NVREG_LINKSPEED_100 100
291 #define NVREG_LINKSPEED_1000 50
292 #define NVREG_LINKSPEED_MASK (0xFFF)
293 NvRegUnknownSetupReg5
= 0x130,
294 #define NVREG_UNKSETUP5_BIT31 (1<<31)
295 NvRegTxWatermark
= 0x13c,
296 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
297 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
298 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
299 NvRegTxRxControl
= 0x144,
300 #define NVREG_TXRXCTL_KICK 0x0001
301 #define NVREG_TXRXCTL_BIT1 0x0002
302 #define NVREG_TXRXCTL_BIT2 0x0004
303 #define NVREG_TXRXCTL_IDLE 0x0008
304 #define NVREG_TXRXCTL_RESET 0x0010
305 #define NVREG_TXRXCTL_RXCHECK 0x0400
306 #define NVREG_TXRXCTL_DESC_1 0
307 #define NVREG_TXRXCTL_DESC_2 0x02100
308 #define NVREG_TXRXCTL_DESC_3 0x02200
309 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
310 #define NVREG_TXRXCTL_VLANINS 0x00080
311 NvRegTxRingPhysAddrHigh
= 0x148,
312 NvRegRxRingPhysAddrHigh
= 0x14C,
313 NvRegTxPauseFrame
= 0x170,
314 #define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080
315 #define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030
316 NvRegMIIStatus
= 0x180,
317 #define NVREG_MIISTAT_ERROR 0x0001
318 #define NVREG_MIISTAT_LINKCHANGE 0x0008
319 #define NVREG_MIISTAT_MASK 0x000f
320 #define NVREG_MIISTAT_MASK2 0x000f
321 NvRegMIIMask
= 0x184,
322 #define NVREG_MII_LINKCHANGE 0x0008
324 NvRegAdapterControl
= 0x188,
325 #define NVREG_ADAPTCTL_START 0x02
326 #define NVREG_ADAPTCTL_LINKUP 0x04
327 #define NVREG_ADAPTCTL_PHYVALID 0x40000
328 #define NVREG_ADAPTCTL_RUNNING 0x100000
329 #define NVREG_ADAPTCTL_PHYSHIFT 24
330 NvRegMIISpeed
= 0x18c,
331 #define NVREG_MIISPEED_BIT8 (1<<8)
332 #define NVREG_MIIDELAY 5
333 NvRegMIIControl
= 0x190,
334 #define NVREG_MIICTL_INUSE 0x08000
335 #define NVREG_MIICTL_WRITE 0x00400
336 #define NVREG_MIICTL_ADDRSHIFT 5
337 NvRegMIIData
= 0x194,
338 NvRegWakeUpFlags
= 0x200,
339 #define NVREG_WAKEUPFLAGS_VAL 0x7770
340 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
341 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
342 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
343 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
344 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
345 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
346 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
347 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
348 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
349 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
351 NvRegPatternCRC
= 0x204,
352 NvRegPatternMask
= 0x208,
353 NvRegPowerCap
= 0x268,
354 #define NVREG_POWERCAP_D3SUPP (1<<30)
355 #define NVREG_POWERCAP_D2SUPP (1<<26)
356 #define NVREG_POWERCAP_D1SUPP (1<<25)
357 NvRegPowerState
= 0x26c,
358 #define NVREG_POWERSTATE_POWEREDUP 0x8000
359 #define NVREG_POWERSTATE_VALID 0x0100
360 #define NVREG_POWERSTATE_MASK 0x0003
361 #define NVREG_POWERSTATE_D0 0x0000
362 #define NVREG_POWERSTATE_D1 0x0001
363 #define NVREG_POWERSTATE_D2 0x0002
364 #define NVREG_POWERSTATE_D3 0x0003
366 NvRegTxZeroReXmt
= 0x284,
367 NvRegTxOneReXmt
= 0x288,
368 NvRegTxManyReXmt
= 0x28c,
369 NvRegTxLateCol
= 0x290,
370 NvRegTxUnderflow
= 0x294,
371 NvRegTxLossCarrier
= 0x298,
372 NvRegTxExcessDef
= 0x29c,
373 NvRegTxRetryErr
= 0x2a0,
374 NvRegRxFrameErr
= 0x2a4,
375 NvRegRxExtraByte
= 0x2a8,
376 NvRegRxLateCol
= 0x2ac,
378 NvRegRxFrameTooLong
= 0x2b4,
379 NvRegRxOverflow
= 0x2b8,
380 NvRegRxFCSErr
= 0x2bc,
381 NvRegRxFrameAlignErr
= 0x2c0,
382 NvRegRxLenErr
= 0x2c4,
383 NvRegRxUnicast
= 0x2c8,
384 NvRegRxMulticast
= 0x2cc,
385 NvRegRxBroadcast
= 0x2d0,
387 NvRegTxFrame
= 0x2d8,
389 NvRegTxPause
= 0x2e0,
390 NvRegRxPause
= 0x2e4,
391 NvRegRxDropFrame
= 0x2e8,
392 NvRegVlanControl
= 0x300,
393 #define NVREG_VLANCONTROL_ENABLE 0x2000
394 NvRegMSIXMap0
= 0x3e0,
395 NvRegMSIXMap1
= 0x3e4,
396 NvRegMSIXIrqStatus
= 0x3f0,
398 NvRegPowerState2
= 0x600,
399 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
400 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
403 /* Big endian: should work, but is untested */
409 struct ring_desc_ex
{
417 struct ring_desc
* orig
;
418 struct ring_desc_ex
* ex
;
421 #define FLAG_MASK_V1 0xffff0000
422 #define FLAG_MASK_V2 0xffffc000
423 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
424 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
426 #define NV_TX_LASTPACKET (1<<16)
427 #define NV_TX_RETRYERROR (1<<19)
428 #define NV_TX_FORCED_INTERRUPT (1<<24)
429 #define NV_TX_DEFERRED (1<<26)
430 #define NV_TX_CARRIERLOST (1<<27)
431 #define NV_TX_LATECOLLISION (1<<28)
432 #define NV_TX_UNDERFLOW (1<<29)
433 #define NV_TX_ERROR (1<<30)
434 #define NV_TX_VALID (1<<31)
436 #define NV_TX2_LASTPACKET (1<<29)
437 #define NV_TX2_RETRYERROR (1<<18)
438 #define NV_TX2_FORCED_INTERRUPT (1<<30)
439 #define NV_TX2_DEFERRED (1<<25)
440 #define NV_TX2_CARRIERLOST (1<<26)
441 #define NV_TX2_LATECOLLISION (1<<27)
442 #define NV_TX2_UNDERFLOW (1<<28)
443 /* error and valid are the same for both */
444 #define NV_TX2_ERROR (1<<30)
445 #define NV_TX2_VALID (1<<31)
446 #define NV_TX2_TSO (1<<28)
447 #define NV_TX2_TSO_SHIFT 14
448 #define NV_TX2_TSO_MAX_SHIFT 14
449 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
450 #define NV_TX2_CHECKSUM_L3 (1<<27)
451 #define NV_TX2_CHECKSUM_L4 (1<<26)
453 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
455 #define NV_RX_DESCRIPTORVALID (1<<16)
456 #define NV_RX_MISSEDFRAME (1<<17)
457 #define NV_RX_SUBSTRACT1 (1<<18)
458 #define NV_RX_ERROR1 (1<<23)
459 #define NV_RX_ERROR2 (1<<24)
460 #define NV_RX_ERROR3 (1<<25)
461 #define NV_RX_ERROR4 (1<<26)
462 #define NV_RX_CRCERR (1<<27)
463 #define NV_RX_OVERFLOW (1<<28)
464 #define NV_RX_FRAMINGERR (1<<29)
465 #define NV_RX_ERROR (1<<30)
466 #define NV_RX_AVAIL (1<<31)
468 #define NV_RX2_CHECKSUMMASK (0x1C000000)
469 #define NV_RX2_CHECKSUMOK1 (0x10000000)
470 #define NV_RX2_CHECKSUMOK2 (0x14000000)
471 #define NV_RX2_CHECKSUMOK3 (0x18000000)
472 #define NV_RX2_DESCRIPTORVALID (1<<29)
473 #define NV_RX2_SUBSTRACT1 (1<<25)
474 #define NV_RX2_ERROR1 (1<<18)
475 #define NV_RX2_ERROR2 (1<<19)
476 #define NV_RX2_ERROR3 (1<<20)
477 #define NV_RX2_ERROR4 (1<<21)
478 #define NV_RX2_CRCERR (1<<22)
479 #define NV_RX2_OVERFLOW (1<<23)
480 #define NV_RX2_FRAMINGERR (1<<24)
481 /* error and avail are the same for both */
482 #define NV_RX2_ERROR (1<<30)
483 #define NV_RX2_AVAIL (1<<31)
485 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
486 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
488 /* Miscelaneous hardware related defines: */
489 #define NV_PCI_REGSZ_VER1 0x270
490 #define NV_PCI_REGSZ_VER2 0x604
492 /* various timeout delays: all in usec */
493 #define NV_TXRX_RESET_DELAY 4
494 #define NV_TXSTOP_DELAY1 10
495 #define NV_TXSTOP_DELAY1MAX 500000
496 #define NV_TXSTOP_DELAY2 100
497 #define NV_RXSTOP_DELAY1 10
498 #define NV_RXSTOP_DELAY1MAX 500000
499 #define NV_RXSTOP_DELAY2 100
500 #define NV_SETUP5_DELAY 5
501 #define NV_SETUP5_DELAYMAX 50000
502 #define NV_POWERUP_DELAY 5
503 #define NV_POWERUP_DELAYMAX 5000
504 #define NV_MIIBUSY_DELAY 50
505 #define NV_MIIPHY_DELAY 10
506 #define NV_MIIPHY_DELAYMAX 10000
507 #define NV_MAC_RESET_DELAY 64
509 #define NV_WAKEUPPATTERNS 5
510 #define NV_WAKEUPMASKENTRIES 4
512 /* General driver defaults */
513 #define NV_WATCHDOG_TIMEO (5*HZ)
515 #define RX_RING_DEFAULT 128
516 #define TX_RING_DEFAULT 256
517 #define RX_RING_MIN 128
518 #define TX_RING_MIN 64
519 #define RING_MAX_DESC_VER_1 1024
520 #define RING_MAX_DESC_VER_2_3 16384
522 * Difference between the get and put pointers for the tx ring.
523 * This is used to throttle the amount of data outstanding in the
526 #define TX_LIMIT_DIFFERENCE 1
528 /* rx/tx mac addr + type + vlan + align + slack*/
529 #define NV_RX_HEADERS (64)
530 /* even more slack. */
531 #define NV_RX_ALLOC_PAD (64)
533 /* maximum mtu size */
534 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
535 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
537 #define OOM_REFILL (1+HZ/20)
538 #define POLL_WAIT (1+HZ/100)
539 #define LINK_TIMEOUT (3*HZ)
540 #define STATS_INTERVAL (10*HZ)
544 * The nic supports three different descriptor types:
545 * - DESC_VER_1: Original
546 * - DESC_VER_2: support for jumbo frames.
547 * - DESC_VER_3: 64-bit format.
554 #define PHY_OUI_MARVELL 0x5043
555 #define PHY_OUI_CICADA 0x03f1
556 #define PHYID1_OUI_MASK 0x03ff
557 #define PHYID1_OUI_SHFT 6
558 #define PHYID2_OUI_MASK 0xfc00
559 #define PHYID2_OUI_SHFT 10
560 #define PHYID2_MODEL_MASK 0x03f0
561 #define PHY_MODEL_MARVELL_E3016 0x220
562 #define PHY_MARVELL_E3016_INITMASK 0x0300
563 #define PHY_INIT1 0x0f000
564 #define PHY_INIT2 0x0e00
565 #define PHY_INIT3 0x01000
566 #define PHY_INIT4 0x0200
567 #define PHY_INIT5 0x0004
568 #define PHY_INIT6 0x02000
569 #define PHY_GIGABIT 0x0100
571 #define PHY_TIMEOUT 0x1
572 #define PHY_ERROR 0x2
576 #define PHY_HALF 0x100
578 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
579 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
580 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
581 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
582 #define NV_PAUSEFRAME_RX_REQ 0x0010
583 #define NV_PAUSEFRAME_TX_REQ 0x0020
584 #define NV_PAUSEFRAME_AUTONEG 0x0040
586 /* MSI/MSI-X defines */
587 #define NV_MSI_X_MAX_VECTORS 8
588 #define NV_MSI_X_VECTORS_MASK 0x000f
589 #define NV_MSI_CAPABLE 0x0010
590 #define NV_MSI_X_CAPABLE 0x0020
591 #define NV_MSI_ENABLED 0x0040
592 #define NV_MSI_X_ENABLED 0x0080
594 #define NV_MSI_X_VECTOR_ALL 0x0
595 #define NV_MSI_X_VECTOR_RX 0x0
596 #define NV_MSI_X_VECTOR_TX 0x1
597 #define NV_MSI_X_VECTOR_OTHER 0x2
600 struct nv_ethtool_str
{
601 char name
[ETH_GSTRING_LEN
];
604 static const struct nv_ethtool_str nv_estats_str
[] = {
609 { "tx_late_collision" },
610 { "tx_fifo_errors" },
611 { "tx_carrier_errors" },
612 { "tx_excess_deferral" },
613 { "tx_retry_error" },
617 { "rx_frame_error" },
619 { "rx_late_collision" },
621 { "rx_frame_too_long" },
622 { "rx_over_errors" },
624 { "rx_frame_align_error" },
625 { "rx_length_error" },
633 { "rx_errors_total" }
636 struct nv_ethtool_stats
{
641 u64 tx_late_collision
;
643 u64 tx_carrier_errors
;
644 u64 tx_excess_deferral
;
651 u64 rx_late_collision
;
653 u64 rx_frame_too_long
;
656 u64 rx_frame_align_error
;
669 #define NV_TEST_COUNT_BASE 3
670 #define NV_TEST_COUNT_EXTENDED 4
672 static const struct nv_ethtool_str nv_etests_str
[] = {
673 { "link (online/offline)" },
674 { "register (offline) " },
675 { "interrupt (offline) " },
676 { "loopback (offline) " }
679 struct register_test
{
684 static const struct register_test nv_registers_test
[] = {
685 { NvRegUnknownSetupReg6
, 0x01 },
686 { NvRegMisc1
, 0x03c },
687 { NvRegOffloadConfig
, 0x03ff },
688 { NvRegMulticastAddrA
, 0xffffffff },
689 { NvRegTxWatermark
, 0x0ff },
690 { NvRegWakeUpFlags
, 0x07777 },
696 * All hardware access under dev->priv->lock, except the performance
698 * - rx is (pseudo-) lockless: it relies on the single-threading provided
699 * by the arch code for interrupts.
700 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
701 * needs dev->priv->lock :-(
702 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
705 /* in dev: base, irq */
710 * Locking: spin_lock(&np->lock); */
711 struct net_device_stats stats
;
712 struct nv_ethtool_stats estats
;
720 unsigned int phy_oui
;
721 unsigned int phy_model
;
726 /* General data: RO fields */
727 dma_addr_t ring_addr
;
728 struct pci_dev
*pci_dev
;
741 /* rx specific fields.
742 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
744 union ring_type rx_ring
;
745 unsigned int cur_rx
, refill_rx
;
746 struct sk_buff
**rx_skbuff
;
748 unsigned int rx_buf_sz
;
749 unsigned int pkt_limit
;
750 struct timer_list oom_kick
;
751 struct timer_list nic_poll
;
752 struct timer_list stats_poll
;
756 /* media detection workaround.
757 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
760 unsigned long link_timeout
;
762 * tx specific fields.
764 union ring_type tx_ring
;
765 unsigned int next_tx
, nic_tx
;
766 struct sk_buff
**tx_skbuff
;
768 unsigned int *tx_dma_len
;
775 struct vlan_group
*vlangrp
;
777 /* msi/msi-x fields */
779 struct msix_entry msi_x_entry
[NV_MSI_X_MAX_VECTORS
];
786 * Maximum number of loops until we assume that a bit in the irq mask
787 * is stuck. Overridable with module param.
789 static int max_interrupt_work
= 5;
792 * Optimization can be either throuput mode or cpu mode
794 * Throughput Mode: Every tx and rx packet will generate an interrupt.
795 * CPU Mode: Interrupts are controlled by a timer.
798 NV_OPTIMIZATION_MODE_THROUGHPUT
,
799 NV_OPTIMIZATION_MODE_CPU
801 static int optimization_mode
= NV_OPTIMIZATION_MODE_THROUGHPUT
;
804 * Poll interval for timer irq
806 * This interval determines how frequent an interrupt is generated.
807 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
808 * Min = 0, and Max = 65535
810 static int poll_interval
= -1;
819 static int msi
= NV_MSI_INT_ENABLED
;
825 NV_MSIX_INT_DISABLED
,
828 static int msix
= NV_MSIX_INT_ENABLED
;
834 NV_DMA_64BIT_DISABLED
,
837 static int dma_64bit
= NV_DMA_64BIT_ENABLED
;
839 static inline struct fe_priv
*get_nvpriv(struct net_device
*dev
)
841 return netdev_priv(dev
);
844 static inline u8 __iomem
*get_hwbase(struct net_device
*dev
)
846 return ((struct fe_priv
*)netdev_priv(dev
))->base
;
849 static inline void pci_push(u8 __iomem
*base
)
851 /* force out pending posted writes */
855 static inline u32
nv_descr_getlength(struct ring_desc
*prd
, u32 v
)
857 return le32_to_cpu(prd
->flaglen
)
858 & ((v
== DESC_VER_1
) ? LEN_MASK_V1
: LEN_MASK_V2
);
861 static inline u32
nv_descr_getlength_ex(struct ring_desc_ex
*prd
, u32 v
)
863 return le32_to_cpu(prd
->flaglen
) & LEN_MASK_V2
;
866 static int reg_delay(struct net_device
*dev
, int offset
, u32 mask
, u32 target
,
867 int delay
, int delaymax
, const char *msg
)
869 u8 __iomem
*base
= get_hwbase(dev
);
880 } while ((readl(base
+ offset
) & mask
) != target
);
884 #define NV_SETUP_RX_RING 0x01
885 #define NV_SETUP_TX_RING 0x02
887 static void setup_hw_rings(struct net_device
*dev
, int rxtx_flags
)
889 struct fe_priv
*np
= get_nvpriv(dev
);
890 u8 __iomem
*base
= get_hwbase(dev
);
892 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
893 if (rxtx_flags
& NV_SETUP_RX_RING
) {
894 writel((u32
) cpu_to_le64(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
896 if (rxtx_flags
& NV_SETUP_TX_RING
) {
897 writel((u32
) cpu_to_le64(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
900 if (rxtx_flags
& NV_SETUP_RX_RING
) {
901 writel((u32
) cpu_to_le64(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
902 writel((u32
) (cpu_to_le64(np
->ring_addr
) >> 32), base
+ NvRegRxRingPhysAddrHigh
);
904 if (rxtx_flags
& NV_SETUP_TX_RING
) {
905 writel((u32
) cpu_to_le64(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddr
);
906 writel((u32
) (cpu_to_le64(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)) >> 32), base
+ NvRegTxRingPhysAddrHigh
);
911 static void free_rings(struct net_device
*dev
)
913 struct fe_priv
*np
= get_nvpriv(dev
);
915 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
916 if (np
->rx_ring
.orig
)
917 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
918 np
->rx_ring
.orig
, np
->ring_addr
);
921 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
922 np
->rx_ring
.ex
, np
->ring_addr
);
925 kfree(np
->rx_skbuff
);
929 kfree(np
->tx_skbuff
);
933 kfree(np
->tx_dma_len
);
936 static int using_multi_irqs(struct net_device
*dev
)
938 struct fe_priv
*np
= get_nvpriv(dev
);
940 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
941 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
942 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1)))
948 static void nv_enable_irq(struct net_device
*dev
)
950 struct fe_priv
*np
= get_nvpriv(dev
);
952 if (!using_multi_irqs(dev
)) {
953 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
954 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
956 enable_irq(dev
->irq
);
958 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
959 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
960 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
964 static void nv_disable_irq(struct net_device
*dev
)
966 struct fe_priv
*np
= get_nvpriv(dev
);
968 if (!using_multi_irqs(dev
)) {
969 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
970 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
972 disable_irq(dev
->irq
);
974 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
975 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
976 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
980 /* In MSIX mode, a write to irqmask behaves as XOR */
981 static void nv_enable_hw_interrupts(struct net_device
*dev
, u32 mask
)
983 u8 __iomem
*base
= get_hwbase(dev
);
985 writel(mask
, base
+ NvRegIrqMask
);
988 static void nv_disable_hw_interrupts(struct net_device
*dev
, u32 mask
)
990 struct fe_priv
*np
= get_nvpriv(dev
);
991 u8 __iomem
*base
= get_hwbase(dev
);
993 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
994 writel(mask
, base
+ NvRegIrqMask
);
996 if (np
->msi_flags
& NV_MSI_ENABLED
)
997 writel(0, base
+ NvRegMSIIrqMask
);
998 writel(0, base
+ NvRegIrqMask
);
1002 #define MII_READ (-1)
1003 /* mii_rw: read/write a register on the PHY.
1005 * Caller must guarantee serialization
1007 static int mii_rw(struct net_device
*dev
, int addr
, int miireg
, int value
)
1009 u8 __iomem
*base
= get_hwbase(dev
);
1013 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
1015 reg
= readl(base
+ NvRegMIIControl
);
1016 if (reg
& NVREG_MIICTL_INUSE
) {
1017 writel(NVREG_MIICTL_INUSE
, base
+ NvRegMIIControl
);
1018 udelay(NV_MIIBUSY_DELAY
);
1021 reg
= (addr
<< NVREG_MIICTL_ADDRSHIFT
) | miireg
;
1022 if (value
!= MII_READ
) {
1023 writel(value
, base
+ NvRegMIIData
);
1024 reg
|= NVREG_MIICTL_WRITE
;
1026 writel(reg
, base
+ NvRegMIIControl
);
1028 if (reg_delay(dev
, NvRegMIIControl
, NVREG_MIICTL_INUSE
, 0,
1029 NV_MIIPHY_DELAY
, NV_MIIPHY_DELAYMAX
, NULL
)) {
1030 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d timed out.\n",
1031 dev
->name
, miireg
, addr
);
1033 } else if (value
!= MII_READ
) {
1034 /* it was a write operation - fewer failures are detectable */
1035 dprintk(KERN_DEBUG
"%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1036 dev
->name
, value
, miireg
, addr
);
1038 } else if (readl(base
+ NvRegMIIStatus
) & NVREG_MIISTAT_ERROR
) {
1039 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d failed.\n",
1040 dev
->name
, miireg
, addr
);
1043 retval
= readl(base
+ NvRegMIIData
);
1044 dprintk(KERN_DEBUG
"%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1045 dev
->name
, miireg
, addr
, retval
);
1051 static int phy_reset(struct net_device
*dev
, u32 bmcr_setup
)
1053 struct fe_priv
*np
= netdev_priv(dev
);
1055 unsigned int tries
= 0;
1057 miicontrol
= BMCR_RESET
| bmcr_setup
;
1058 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
)) {
1062 /* wait for 500ms */
1065 /* must wait till reset is deasserted */
1066 while (miicontrol
& BMCR_RESET
) {
1068 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1069 /* FIXME: 100 tries seem excessive */
1076 static int phy_init(struct net_device
*dev
)
1078 struct fe_priv
*np
= get_nvpriv(dev
);
1079 u8 __iomem
*base
= get_hwbase(dev
);
1080 u32 phyinterface
, phy_reserved
, mii_status
, mii_control
, mii_control_1000
,reg
;
1082 /* phy errata for E3016 phy */
1083 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
1084 reg
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1085 reg
&= ~PHY_MARVELL_E3016_INITMASK
;
1086 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, reg
)) {
1087 printk(KERN_INFO
"%s: phy write to errata reg failed.\n", pci_name(np
->pci_dev
));
1092 /* set advertise register */
1093 reg
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1094 reg
|= (ADVERTISE_10HALF
|ADVERTISE_10FULL
|ADVERTISE_100HALF
|ADVERTISE_100FULL
|ADVERTISE_PAUSE_ASYM
|ADVERTISE_PAUSE_CAP
);
1095 if (mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
)) {
1096 printk(KERN_INFO
"%s: phy write to advertise failed.\n", pci_name(np
->pci_dev
));
1100 /* get phy interface type */
1101 phyinterface
= readl(base
+ NvRegPhyInterface
);
1103 /* see if gigabit phy */
1104 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1105 if (mii_status
& PHY_GIGABIT
) {
1106 np
->gigabit
= PHY_GIGABIT
;
1107 mii_control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
1108 mii_control_1000
&= ~ADVERTISE_1000HALF
;
1109 if (phyinterface
& PHY_RGMII
)
1110 mii_control_1000
|= ADVERTISE_1000FULL
;
1112 mii_control_1000
&= ~ADVERTISE_1000FULL
;
1114 if (mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, mii_control_1000
)) {
1115 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1122 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1123 mii_control
|= BMCR_ANENABLE
;
1126 * (certain phys need bmcr to be setup with reset)
1128 if (phy_reset(dev
, mii_control
)) {
1129 printk(KERN_INFO
"%s: phy reset failed\n", pci_name(np
->pci_dev
));
1133 /* phy vendor specific configuration */
1134 if ((np
->phy_oui
== PHY_OUI_CICADA
) && (phyinterface
& PHY_RGMII
) ) {
1135 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_RESV1
, MII_READ
);
1136 phy_reserved
&= ~(PHY_INIT1
| PHY_INIT2
);
1137 phy_reserved
|= (PHY_INIT3
| PHY_INIT4
);
1138 if (mii_rw(dev
, np
->phyaddr
, MII_RESV1
, phy_reserved
)) {
1139 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1142 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1143 phy_reserved
|= PHY_INIT5
;
1144 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, phy_reserved
)) {
1145 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1149 if (np
->phy_oui
== PHY_OUI_CICADA
) {
1150 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, MII_READ
);
1151 phy_reserved
|= PHY_INIT6
;
1152 if (mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, phy_reserved
)) {
1153 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1157 /* some phys clear out pause advertisment on reset, set it back */
1158 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
);
1160 /* restart auto negotiation */
1161 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1162 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
1163 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
1170 static void nv_start_rx(struct net_device
*dev
)
1172 struct fe_priv
*np
= netdev_priv(dev
);
1173 u8 __iomem
*base
= get_hwbase(dev
);
1174 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1176 dprintk(KERN_DEBUG
"%s: nv_start_rx\n", dev
->name
);
1177 /* Already running? Stop it. */
1178 if ((readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) && !np
->mac_in_use
) {
1179 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1180 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1183 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1185 rx_ctrl
|= NVREG_RCVCTL_START
;
1187 rx_ctrl
&= ~NVREG_RCVCTL_RX_PATH_EN
;
1188 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1189 dprintk(KERN_DEBUG
"%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1190 dev
->name
, np
->duplex
, np
->linkspeed
);
1194 static void nv_stop_rx(struct net_device
*dev
)
1196 struct fe_priv
*np
= netdev_priv(dev
);
1197 u8 __iomem
*base
= get_hwbase(dev
);
1198 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1200 dprintk(KERN_DEBUG
"%s: nv_stop_rx\n", dev
->name
);
1201 if (!np
->mac_in_use
)
1202 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1204 rx_ctrl
|= NVREG_RCVCTL_RX_PATH_EN
;
1205 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1206 reg_delay(dev
, NvRegReceiverStatus
, NVREG_RCVSTAT_BUSY
, 0,
1207 NV_RXSTOP_DELAY1
, NV_RXSTOP_DELAY1MAX
,
1208 KERN_INFO
"nv_stop_rx: ReceiverStatus remained busy");
1210 udelay(NV_RXSTOP_DELAY2
);
1211 if (!np
->mac_in_use
)
1212 writel(0, base
+ NvRegLinkSpeed
);
1215 static void nv_start_tx(struct net_device
*dev
)
1217 struct fe_priv
*np
= netdev_priv(dev
);
1218 u8 __iomem
*base
= get_hwbase(dev
);
1219 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1221 dprintk(KERN_DEBUG
"%s: nv_start_tx\n", dev
->name
);
1222 tx_ctrl
|= NVREG_XMITCTL_START
;
1224 tx_ctrl
&= ~NVREG_XMITCTL_TX_PATH_EN
;
1225 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1229 static void nv_stop_tx(struct net_device
*dev
)
1231 struct fe_priv
*np
= netdev_priv(dev
);
1232 u8 __iomem
*base
= get_hwbase(dev
);
1233 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1235 dprintk(KERN_DEBUG
"%s: nv_stop_tx\n", dev
->name
);
1236 if (!np
->mac_in_use
)
1237 tx_ctrl
&= ~NVREG_XMITCTL_START
;
1239 tx_ctrl
|= NVREG_XMITCTL_TX_PATH_EN
;
1240 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1241 reg_delay(dev
, NvRegTransmitterStatus
, NVREG_XMITSTAT_BUSY
, 0,
1242 NV_TXSTOP_DELAY1
, NV_TXSTOP_DELAY1MAX
,
1243 KERN_INFO
"nv_stop_tx: TransmitterStatus remained busy");
1245 udelay(NV_TXSTOP_DELAY2
);
1246 if (!np
->mac_in_use
)
1247 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
1248 base
+ NvRegTransmitPoll
);
1251 static void nv_txrx_reset(struct net_device
*dev
)
1253 struct fe_priv
*np
= netdev_priv(dev
);
1254 u8 __iomem
*base
= get_hwbase(dev
);
1256 dprintk(KERN_DEBUG
"%s: nv_txrx_reset\n", dev
->name
);
1257 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1259 udelay(NV_TXRX_RESET_DELAY
);
1260 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1264 static void nv_mac_reset(struct net_device
*dev
)
1266 struct fe_priv
*np
= netdev_priv(dev
);
1267 u8 __iomem
*base
= get_hwbase(dev
);
1269 dprintk(KERN_DEBUG
"%s: nv_mac_reset\n", dev
->name
);
1270 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1272 writel(NVREG_MAC_RESET_ASSERT
, base
+ NvRegMacReset
);
1274 udelay(NV_MAC_RESET_DELAY
);
1275 writel(0, base
+ NvRegMacReset
);
1277 udelay(NV_MAC_RESET_DELAY
);
1278 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1283 * nv_get_stats: dev->get_stats function
1284 * Get latest stats value from the nic.
1285 * Called with read_lock(&dev_base_lock) held for read -
1286 * only synchronized against unregister_netdevice.
1288 static struct net_device_stats
*nv_get_stats(struct net_device
*dev
)
1290 struct fe_priv
*np
= netdev_priv(dev
);
1292 /* It seems that the nic always generates interrupts and doesn't
1293 * accumulate errors internally. Thus the current values in np->stats
1294 * are already up to date.
1300 * nv_alloc_rx: fill rx ring entries.
1301 * Return 1 if the allocations for the skbs failed and the
1302 * rx engine is without Available descriptors
1304 static int nv_alloc_rx(struct net_device
*dev
)
1306 struct fe_priv
*np
= netdev_priv(dev
);
1307 unsigned int refill_rx
= np
->refill_rx
;
1310 while (np
->cur_rx
!= refill_rx
) {
1311 struct sk_buff
*skb
;
1313 nr
= refill_rx
% np
->rx_ring_size
;
1314 if (np
->rx_skbuff
[nr
] == NULL
) {
1316 skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1321 np
->rx_skbuff
[nr
] = skb
;
1323 skb
= np
->rx_skbuff
[nr
];
1325 np
->rx_dma
[nr
] = pci_map_single(np
->pci_dev
, skb
->data
,
1326 skb
->end
-skb
->data
, PCI_DMA_FROMDEVICE
);
1327 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1328 np
->rx_ring
.orig
[nr
].buf
= cpu_to_le32(np
->rx_dma
[nr
]);
1330 np
->rx_ring
.orig
[nr
].flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX_AVAIL
);
1332 np
->rx_ring
.ex
[nr
].bufhigh
= cpu_to_le64(np
->rx_dma
[nr
]) >> 32;
1333 np
->rx_ring
.ex
[nr
].buflow
= cpu_to_le64(np
->rx_dma
[nr
]) & 0x0FFFFFFFF;
1335 np
->rx_ring
.ex
[nr
].flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX2_AVAIL
);
1337 dprintk(KERN_DEBUG
"%s: nv_alloc_rx: Packet %d marked as Available\n",
1338 dev
->name
, refill_rx
);
1341 np
->refill_rx
= refill_rx
;
1342 if (np
->cur_rx
- refill_rx
== np
->rx_ring_size
)
1347 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1348 #ifdef CONFIG_FORCEDETH_NAPI
1349 static void nv_do_rx_refill(unsigned long data
)
1351 struct net_device
*dev
= (struct net_device
*) data
;
1353 /* Just reschedule NAPI rx processing */
1354 netif_rx_schedule(dev
);
1357 static void nv_do_rx_refill(unsigned long data
)
1359 struct net_device
*dev
= (struct net_device
*) data
;
1360 struct fe_priv
*np
= netdev_priv(dev
);
1362 if (!using_multi_irqs(dev
)) {
1363 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1364 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1366 disable_irq(dev
->irq
);
1368 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1370 if (nv_alloc_rx(dev
)) {
1371 spin_lock_irq(&np
->lock
);
1372 if (!np
->in_shutdown
)
1373 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1374 spin_unlock_irq(&np
->lock
);
1376 if (!using_multi_irqs(dev
)) {
1377 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1378 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1380 enable_irq(dev
->irq
);
1382 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1387 static void nv_init_rx(struct net_device
*dev
)
1389 struct fe_priv
*np
= netdev_priv(dev
);
1392 np
->cur_rx
= np
->rx_ring_size
;
1394 for (i
= 0; i
< np
->rx_ring_size
; i
++)
1395 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1396 np
->rx_ring
.orig
[i
].flaglen
= 0;
1398 np
->rx_ring
.ex
[i
].flaglen
= 0;
1401 static void nv_init_tx(struct net_device
*dev
)
1403 struct fe_priv
*np
= netdev_priv(dev
);
1406 np
->next_tx
= np
->nic_tx
= 0;
1407 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1408 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1409 np
->tx_ring
.orig
[i
].flaglen
= 0;
1411 np
->tx_ring
.ex
[i
].flaglen
= 0;
1412 np
->tx_skbuff
[i
] = NULL
;
1417 static int nv_init_ring(struct net_device
*dev
)
1421 return nv_alloc_rx(dev
);
1424 static int nv_release_txskb(struct net_device
*dev
, unsigned int skbnr
)
1426 struct fe_priv
*np
= netdev_priv(dev
);
1428 dprintk(KERN_INFO
"%s: nv_release_txskb for skbnr %d\n",
1431 if (np
->tx_dma
[skbnr
]) {
1432 pci_unmap_page(np
->pci_dev
, np
->tx_dma
[skbnr
],
1433 np
->tx_dma_len
[skbnr
],
1435 np
->tx_dma
[skbnr
] = 0;
1438 if (np
->tx_skbuff
[skbnr
]) {
1439 dev_kfree_skb_any(np
->tx_skbuff
[skbnr
]);
1440 np
->tx_skbuff
[skbnr
] = NULL
;
1447 static void nv_drain_tx(struct net_device
*dev
)
1449 struct fe_priv
*np
= netdev_priv(dev
);
1452 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1453 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1454 np
->tx_ring
.orig
[i
].flaglen
= 0;
1456 np
->tx_ring
.ex
[i
].flaglen
= 0;
1457 if (nv_release_txskb(dev
, i
))
1458 np
->stats
.tx_dropped
++;
1462 static void nv_drain_rx(struct net_device
*dev
)
1464 struct fe_priv
*np
= netdev_priv(dev
);
1466 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
1467 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1468 np
->rx_ring
.orig
[i
].flaglen
= 0;
1470 np
->rx_ring
.ex
[i
].flaglen
= 0;
1472 if (np
->rx_skbuff
[i
]) {
1473 pci_unmap_single(np
->pci_dev
, np
->rx_dma
[i
],
1474 np
->rx_skbuff
[i
]->end
-np
->rx_skbuff
[i
]->data
,
1475 PCI_DMA_FROMDEVICE
);
1476 dev_kfree_skb(np
->rx_skbuff
[i
]);
1477 np
->rx_skbuff
[i
] = NULL
;
1482 static void drain_ring(struct net_device
*dev
)
1489 * nv_start_xmit: dev->hard_start_xmit function
1490 * Called with netif_tx_lock held.
1492 static int nv_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1494 struct fe_priv
*np
= netdev_priv(dev
);
1496 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
1497 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
1498 unsigned int nr
= (np
->next_tx
- 1) % np
->tx_ring_size
;
1499 unsigned int start_nr
= np
->next_tx
% np
->tx_ring_size
;
1503 u32 size
= skb
->len
-skb
->data_len
;
1504 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
1505 u32 tx_flags_vlan
= 0;
1507 /* add fragments to entries count */
1508 for (i
= 0; i
< fragments
; i
++) {
1509 entries
+= (skb_shinfo(skb
)->frags
[i
].size
>> NV_TX2_TSO_MAX_SHIFT
) +
1510 ((skb_shinfo(skb
)->frags
[i
].size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
1513 spin_lock_irq(&np
->lock
);
1515 if ((np
->next_tx
- np
->nic_tx
+ entries
- 1) > np
->tx_limit_stop
) {
1516 spin_unlock_irq(&np
->lock
);
1517 netif_stop_queue(dev
);
1518 return NETDEV_TX_BUSY
;
1521 /* setup the header buffer */
1523 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
1524 nr
= (nr
+ 1) % np
->tx_ring_size
;
1526 np
->tx_dma
[nr
] = pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
1528 np
->tx_dma_len
[nr
] = bcnt
;
1530 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1531 np
->tx_ring
.orig
[nr
].buf
= cpu_to_le32(np
->tx_dma
[nr
]);
1532 np
->tx_ring
.orig
[nr
].flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1534 np
->tx_ring
.ex
[nr
].bufhigh
= cpu_to_le64(np
->tx_dma
[nr
]) >> 32;
1535 np
->tx_ring
.ex
[nr
].buflow
= cpu_to_le64(np
->tx_dma
[nr
]) & 0x0FFFFFFFF;
1536 np
->tx_ring
.ex
[nr
].flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1538 tx_flags
= np
->tx_flags
;
1543 /* setup the fragments */
1544 for (i
= 0; i
< fragments
; i
++) {
1545 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1546 u32 size
= frag
->size
;
1550 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
1551 nr
= (nr
+ 1) % np
->tx_ring_size
;
1553 np
->tx_dma
[nr
] = pci_map_page(np
->pci_dev
, frag
->page
, frag
->page_offset
+offset
, bcnt
,
1555 np
->tx_dma_len
[nr
] = bcnt
;
1557 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1558 np
->tx_ring
.orig
[nr
].buf
= cpu_to_le32(np
->tx_dma
[nr
]);
1559 np
->tx_ring
.orig
[nr
].flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1561 np
->tx_ring
.ex
[nr
].bufhigh
= cpu_to_le64(np
->tx_dma
[nr
]) >> 32;
1562 np
->tx_ring
.ex
[nr
].buflow
= cpu_to_le64(np
->tx_dma
[nr
]) & 0x0FFFFFFFF;
1563 np
->tx_ring
.ex
[nr
].flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1570 /* set last fragment flag */
1571 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1572 np
->tx_ring
.orig
[nr
].flaglen
|= cpu_to_le32(tx_flags_extra
);
1574 np
->tx_ring
.ex
[nr
].flaglen
|= cpu_to_le32(tx_flags_extra
);
1577 np
->tx_skbuff
[nr
] = skb
;
1579 if (skb_is_gso(skb
))
1580 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
1582 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
1583 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
1586 if (np
->vlangrp
&& vlan_tx_tag_present(skb
)) {
1587 tx_flags_vlan
= NV_TX3_VLAN_TAG_PRESENT
| vlan_tx_tag_get(skb
);
1591 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1592 np
->tx_ring
.orig
[start_nr
].flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
1594 np
->tx_ring
.ex
[start_nr
].txvlan
= cpu_to_le32(tx_flags_vlan
);
1595 np
->tx_ring
.ex
[start_nr
].flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
1598 dprintk(KERN_DEBUG
"%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1599 dev
->name
, np
->next_tx
, entries
, tx_flags_extra
);
1602 for (j
=0; j
<64; j
++) {
1604 dprintk("\n%03x:", j
);
1605 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
1610 np
->next_tx
+= entries
;
1612 dev
->trans_start
= jiffies
;
1613 spin_unlock_irq(&np
->lock
);
1614 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
1615 pci_push(get_hwbase(dev
));
1616 return NETDEV_TX_OK
;
1620 * nv_tx_done: check for completed packets, release the skbs.
1622 * Caller must own np->lock.
1624 static void nv_tx_done(struct net_device
*dev
)
1626 struct fe_priv
*np
= netdev_priv(dev
);
1629 struct sk_buff
*skb
;
1631 while (np
->nic_tx
!= np
->next_tx
) {
1632 i
= np
->nic_tx
% np
->tx_ring_size
;
1634 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1635 flags
= le32_to_cpu(np
->tx_ring
.orig
[i
].flaglen
);
1637 flags
= le32_to_cpu(np
->tx_ring
.ex
[i
].flaglen
);
1639 dprintk(KERN_DEBUG
"%s: nv_tx_done: looking at packet %d, flags 0x%x.\n",
1640 dev
->name
, np
->nic_tx
, flags
);
1641 if (flags
& NV_TX_VALID
)
1643 if (np
->desc_ver
== DESC_VER_1
) {
1644 if (flags
& NV_TX_LASTPACKET
) {
1645 skb
= np
->tx_skbuff
[i
];
1646 if (flags
& (NV_TX_RETRYERROR
|NV_TX_CARRIERLOST
|NV_TX_LATECOLLISION
|
1647 NV_TX_UNDERFLOW
|NV_TX_ERROR
)) {
1648 if (flags
& NV_TX_UNDERFLOW
)
1649 np
->stats
.tx_fifo_errors
++;
1650 if (flags
& NV_TX_CARRIERLOST
)
1651 np
->stats
.tx_carrier_errors
++;
1652 np
->stats
.tx_errors
++;
1654 np
->stats
.tx_packets
++;
1655 np
->stats
.tx_bytes
+= skb
->len
;
1659 if (flags
& NV_TX2_LASTPACKET
) {
1660 skb
= np
->tx_skbuff
[i
];
1661 if (flags
& (NV_TX2_RETRYERROR
|NV_TX2_CARRIERLOST
|NV_TX2_LATECOLLISION
|
1662 NV_TX2_UNDERFLOW
|NV_TX2_ERROR
)) {
1663 if (flags
& NV_TX2_UNDERFLOW
)
1664 np
->stats
.tx_fifo_errors
++;
1665 if (flags
& NV_TX2_CARRIERLOST
)
1666 np
->stats
.tx_carrier_errors
++;
1667 np
->stats
.tx_errors
++;
1669 np
->stats
.tx_packets
++;
1670 np
->stats
.tx_bytes
+= skb
->len
;
1674 nv_release_txskb(dev
, i
);
1677 if (np
->next_tx
- np
->nic_tx
< np
->tx_limit_start
)
1678 netif_wake_queue(dev
);
1682 * nv_tx_timeout: dev->tx_timeout function
1683 * Called with netif_tx_lock held.
1685 static void nv_tx_timeout(struct net_device
*dev
)
1687 struct fe_priv
*np
= netdev_priv(dev
);
1688 u8 __iomem
*base
= get_hwbase(dev
);
1691 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1692 status
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
1694 status
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
1696 printk(KERN_INFO
"%s: Got tx_timeout. irq: %08x\n", dev
->name
, status
);
1701 printk(KERN_INFO
"%s: Ring at %lx: next %d nic %d\n",
1702 dev
->name
, (unsigned long)np
->ring_addr
,
1703 np
->next_tx
, np
->nic_tx
);
1704 printk(KERN_INFO
"%s: Dumping tx registers\n", dev
->name
);
1705 for (i
=0;i
<=np
->register_size
;i
+= 32) {
1706 printk(KERN_INFO
"%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1708 readl(base
+ i
+ 0), readl(base
+ i
+ 4),
1709 readl(base
+ i
+ 8), readl(base
+ i
+ 12),
1710 readl(base
+ i
+ 16), readl(base
+ i
+ 20),
1711 readl(base
+ i
+ 24), readl(base
+ i
+ 28));
1713 printk(KERN_INFO
"%s: Dumping tx ring\n", dev
->name
);
1714 for (i
=0;i
<np
->tx_ring_size
;i
+= 4) {
1715 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1716 printk(KERN_INFO
"%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1718 le32_to_cpu(np
->tx_ring
.orig
[i
].buf
),
1719 le32_to_cpu(np
->tx_ring
.orig
[i
].flaglen
),
1720 le32_to_cpu(np
->tx_ring
.orig
[i
+1].buf
),
1721 le32_to_cpu(np
->tx_ring
.orig
[i
+1].flaglen
),
1722 le32_to_cpu(np
->tx_ring
.orig
[i
+2].buf
),
1723 le32_to_cpu(np
->tx_ring
.orig
[i
+2].flaglen
),
1724 le32_to_cpu(np
->tx_ring
.orig
[i
+3].buf
),
1725 le32_to_cpu(np
->tx_ring
.orig
[i
+3].flaglen
));
1727 printk(KERN_INFO
"%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1729 le32_to_cpu(np
->tx_ring
.ex
[i
].bufhigh
),
1730 le32_to_cpu(np
->tx_ring
.ex
[i
].buflow
),
1731 le32_to_cpu(np
->tx_ring
.ex
[i
].flaglen
),
1732 le32_to_cpu(np
->tx_ring
.ex
[i
+1].bufhigh
),
1733 le32_to_cpu(np
->tx_ring
.ex
[i
+1].buflow
),
1734 le32_to_cpu(np
->tx_ring
.ex
[i
+1].flaglen
),
1735 le32_to_cpu(np
->tx_ring
.ex
[i
+2].bufhigh
),
1736 le32_to_cpu(np
->tx_ring
.ex
[i
+2].buflow
),
1737 le32_to_cpu(np
->tx_ring
.ex
[i
+2].flaglen
),
1738 le32_to_cpu(np
->tx_ring
.ex
[i
+3].bufhigh
),
1739 le32_to_cpu(np
->tx_ring
.ex
[i
+3].buflow
),
1740 le32_to_cpu(np
->tx_ring
.ex
[i
+3].flaglen
));
1745 spin_lock_irq(&np
->lock
);
1747 /* 1) stop tx engine */
1750 /* 2) check that the packets were not sent already: */
1753 /* 3) if there are dead entries: clear everything */
1754 if (np
->next_tx
!= np
->nic_tx
) {
1755 printk(KERN_DEBUG
"%s: tx_timeout: dead entries!\n", dev
->name
);
1757 np
->next_tx
= np
->nic_tx
= 0;
1758 setup_hw_rings(dev
, NV_SETUP_TX_RING
);
1759 netif_wake_queue(dev
);
1762 /* 4) restart tx engine */
1764 spin_unlock_irq(&np
->lock
);
1768 * Called when the nic notices a mismatch between the actual data len on the
1769 * wire and the len indicated in the 802 header
1771 static int nv_getlen(struct net_device
*dev
, void *packet
, int datalen
)
1773 int hdrlen
; /* length of the 802 header */
1774 int protolen
; /* length as stored in the proto field */
1776 /* 1) calculate len according to header */
1777 if ( ((struct vlan_ethhdr
*)packet
)->h_vlan_proto
== htons(ETH_P_8021Q
)) {
1778 protolen
= ntohs( ((struct vlan_ethhdr
*)packet
)->h_vlan_encapsulated_proto
);
1781 protolen
= ntohs( ((struct ethhdr
*)packet
)->h_proto
);
1784 dprintk(KERN_DEBUG
"%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1785 dev
->name
, datalen
, protolen
, hdrlen
);
1786 if (protolen
> ETH_DATA_LEN
)
1787 return datalen
; /* Value in proto field not a len, no checks possible */
1790 /* consistency checks: */
1791 if (datalen
> ETH_ZLEN
) {
1792 if (datalen
>= protolen
) {
1793 /* more data on wire than in 802 header, trim of
1796 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
1797 dev
->name
, protolen
);
1800 /* less data on wire than mentioned in header.
1801 * Discard the packet.
1803 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding long packet.\n",
1808 /* short packet. Accept only if 802 values are also short */
1809 if (protolen
> ETH_ZLEN
) {
1810 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding short packet.\n",
1814 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
1815 dev
->name
, datalen
);
1820 static int nv_rx_process(struct net_device
*dev
, int limit
)
1822 struct fe_priv
*np
= netdev_priv(dev
);
1827 for (count
= 0; count
< limit
; ++count
) {
1828 struct sk_buff
*skb
;
1831 if (np
->cur_rx
- np
->refill_rx
>= np
->rx_ring_size
)
1832 break; /* we scanned the whole ring - do not continue */
1834 i
= np
->cur_rx
% np
->rx_ring_size
;
1835 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1836 flags
= le32_to_cpu(np
->rx_ring
.orig
[i
].flaglen
);
1837 len
= nv_descr_getlength(&np
->rx_ring
.orig
[i
], np
->desc_ver
);
1839 flags
= le32_to_cpu(np
->rx_ring
.ex
[i
].flaglen
);
1840 len
= nv_descr_getlength_ex(&np
->rx_ring
.ex
[i
], np
->desc_ver
);
1841 vlanflags
= le32_to_cpu(np
->rx_ring
.ex
[i
].buflow
);
1844 dprintk(KERN_DEBUG
"%s: nv_rx_process: looking at packet %d, flags 0x%x.\n",
1845 dev
->name
, np
->cur_rx
, flags
);
1847 if (flags
& NV_RX_AVAIL
)
1848 break; /* still owned by hardware, */
1851 * the packet is for us - immediately tear down the pci mapping.
1852 * TODO: check if a prefetch of the first cacheline improves
1855 pci_unmap_single(np
->pci_dev
, np
->rx_dma
[i
],
1856 np
->rx_skbuff
[i
]->end
-np
->rx_skbuff
[i
]->data
,
1857 PCI_DMA_FROMDEVICE
);
1861 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",flags
);
1862 for (j
=0; j
<64; j
++) {
1864 dprintk("\n%03x:", j
);
1865 dprintk(" %02x", ((unsigned char*)np
->rx_skbuff
[i
]->data
)[j
]);
1869 /* look at what we actually got: */
1870 if (np
->desc_ver
== DESC_VER_1
) {
1871 if (!(flags
& NV_RX_DESCRIPTORVALID
))
1874 if (flags
& NV_RX_ERROR
) {
1875 if (flags
& NV_RX_MISSEDFRAME
) {
1876 np
->stats
.rx_missed_errors
++;
1877 np
->stats
.rx_errors
++;
1880 if (flags
& (NV_RX_ERROR1
|NV_RX_ERROR2
|NV_RX_ERROR3
)) {
1881 np
->stats
.rx_errors
++;
1884 if (flags
& NV_RX_CRCERR
) {
1885 np
->stats
.rx_crc_errors
++;
1886 np
->stats
.rx_errors
++;
1889 if (flags
& NV_RX_OVERFLOW
) {
1890 np
->stats
.rx_over_errors
++;
1891 np
->stats
.rx_errors
++;
1894 if (flags
& NV_RX_ERROR4
) {
1895 len
= nv_getlen(dev
, np
->rx_skbuff
[i
]->data
, len
);
1897 np
->stats
.rx_errors
++;
1901 /* framing errors are soft errors. */
1902 if (flags
& NV_RX_FRAMINGERR
) {
1903 if (flags
& NV_RX_SUBSTRACT1
) {
1909 if (!(flags
& NV_RX2_DESCRIPTORVALID
))
1912 if (flags
& NV_RX2_ERROR
) {
1913 if (flags
& (NV_RX2_ERROR1
|NV_RX2_ERROR2
|NV_RX2_ERROR3
)) {
1914 np
->stats
.rx_errors
++;
1917 if (flags
& NV_RX2_CRCERR
) {
1918 np
->stats
.rx_crc_errors
++;
1919 np
->stats
.rx_errors
++;
1922 if (flags
& NV_RX2_OVERFLOW
) {
1923 np
->stats
.rx_over_errors
++;
1924 np
->stats
.rx_errors
++;
1927 if (flags
& NV_RX2_ERROR4
) {
1928 len
= nv_getlen(dev
, np
->rx_skbuff
[i
]->data
, len
);
1930 np
->stats
.rx_errors
++;
1934 /* framing errors are soft errors */
1935 if (flags
& NV_RX2_FRAMINGERR
) {
1936 if (flags
& NV_RX2_SUBSTRACT1
) {
1942 flags
&= NV_RX2_CHECKSUMMASK
;
1943 if (flags
== NV_RX2_CHECKSUMOK1
||
1944 flags
== NV_RX2_CHECKSUMOK2
||
1945 flags
== NV_RX2_CHECKSUMOK3
) {
1946 dprintk(KERN_DEBUG
"%s: hw checksum hit!.\n", dev
->name
);
1947 np
->rx_skbuff
[i
]->ip_summed
= CHECKSUM_UNNECESSARY
;
1949 dprintk(KERN_DEBUG
"%s: hwchecksum miss!.\n", dev
->name
);
1953 /* got a valid packet - forward it to the network core */
1954 skb
= np
->rx_skbuff
[i
];
1955 np
->rx_skbuff
[i
] = NULL
;
1958 skb
->protocol
= eth_type_trans(skb
, dev
);
1959 dprintk(KERN_DEBUG
"%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1960 dev
->name
, np
->cur_rx
, len
, skb
->protocol
);
1961 #ifdef CONFIG_FORCEDETH_NAPI
1962 if (np
->vlangrp
&& (vlanflags
& NV_RX3_VLAN_TAG_PRESENT
))
1963 vlan_hwaccel_receive_skb(skb
, np
->vlangrp
,
1964 vlanflags
& NV_RX3_VLAN_TAG_MASK
);
1966 netif_receive_skb(skb
);
1968 if (np
->vlangrp
&& (vlanflags
& NV_RX3_VLAN_TAG_PRESENT
))
1969 vlan_hwaccel_rx(skb
, np
->vlangrp
,
1970 vlanflags
& NV_RX3_VLAN_TAG_MASK
);
1974 dev
->last_rx
= jiffies
;
1975 np
->stats
.rx_packets
++;
1976 np
->stats
.rx_bytes
+= len
;
1984 static void set_bufsize(struct net_device
*dev
)
1986 struct fe_priv
*np
= netdev_priv(dev
);
1988 if (dev
->mtu
<= ETH_DATA_LEN
)
1989 np
->rx_buf_sz
= ETH_DATA_LEN
+ NV_RX_HEADERS
;
1991 np
->rx_buf_sz
= dev
->mtu
+ NV_RX_HEADERS
;
1995 * nv_change_mtu: dev->change_mtu function
1996 * Called with dev_base_lock held for read.
1998 static int nv_change_mtu(struct net_device
*dev
, int new_mtu
)
2000 struct fe_priv
*np
= netdev_priv(dev
);
2003 if (new_mtu
< 64 || new_mtu
> np
->pkt_limit
)
2009 /* return early if the buffer sizes will not change */
2010 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
2012 if (old_mtu
== new_mtu
)
2015 /* synchronized against open : rtnl_lock() held by caller */
2016 if (netif_running(dev
)) {
2017 u8 __iomem
*base
= get_hwbase(dev
);
2019 * It seems that the nic preloads valid ring entries into an
2020 * internal buffer. The procedure for flushing everything is
2021 * guessed, there is probably a simpler approach.
2022 * Changing the MTU is a rare event, it shouldn't matter.
2024 nv_disable_irq(dev
);
2025 netif_tx_lock_bh(dev
);
2026 spin_lock(&np
->lock
);
2031 /* drain rx queue */
2034 /* reinit driver view of the rx queue */
2036 if (nv_init_ring(dev
)) {
2037 if (!np
->in_shutdown
)
2038 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2040 /* reinit nic view of the rx queue */
2041 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
2042 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
2043 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
2044 base
+ NvRegRingSizes
);
2046 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2049 /* restart rx engine */
2052 spin_unlock(&np
->lock
);
2053 netif_tx_unlock_bh(dev
);
2059 static void nv_copy_mac_to_hw(struct net_device
*dev
)
2061 u8 __iomem
*base
= get_hwbase(dev
);
2064 mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
2065 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
2066 mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
2068 writel(mac
[0], base
+ NvRegMacAddrA
);
2069 writel(mac
[1], base
+ NvRegMacAddrB
);
2073 * nv_set_mac_address: dev->set_mac_address function
2074 * Called with rtnl_lock() held.
2076 static int nv_set_mac_address(struct net_device
*dev
, void *addr
)
2078 struct fe_priv
*np
= netdev_priv(dev
);
2079 struct sockaddr
*macaddr
= (struct sockaddr
*)addr
;
2081 if (!is_valid_ether_addr(macaddr
->sa_data
))
2082 return -EADDRNOTAVAIL
;
2084 /* synchronized against open : rtnl_lock() held by caller */
2085 memcpy(dev
->dev_addr
, macaddr
->sa_data
, ETH_ALEN
);
2087 if (netif_running(dev
)) {
2088 netif_tx_lock_bh(dev
);
2089 spin_lock_irq(&np
->lock
);
2091 /* stop rx engine */
2094 /* set mac address */
2095 nv_copy_mac_to_hw(dev
);
2097 /* restart rx engine */
2099 spin_unlock_irq(&np
->lock
);
2100 netif_tx_unlock_bh(dev
);
2102 nv_copy_mac_to_hw(dev
);
2108 * nv_set_multicast: dev->set_multicast function
2109 * Called with netif_tx_lock held.
2111 static void nv_set_multicast(struct net_device
*dev
)
2113 struct fe_priv
*np
= netdev_priv(dev
);
2114 u8 __iomem
*base
= get_hwbase(dev
);
2117 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & NVREG_PFF_PAUSE_RX
;
2119 memset(addr
, 0, sizeof(addr
));
2120 memset(mask
, 0, sizeof(mask
));
2122 if (dev
->flags
& IFF_PROMISC
) {
2123 pff
|= NVREG_PFF_PROMISC
;
2125 pff
|= NVREG_PFF_MYADDR
;
2127 if (dev
->flags
& IFF_ALLMULTI
|| dev
->mc_list
) {
2131 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0xffffffff;
2132 if (dev
->flags
& IFF_ALLMULTI
) {
2133 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0;
2135 struct dev_mc_list
*walk
;
2137 walk
= dev
->mc_list
;
2138 while (walk
!= NULL
) {
2140 a
= le32_to_cpu(*(u32
*) walk
->dmi_addr
);
2141 b
= le16_to_cpu(*(u16
*) (&walk
->dmi_addr
[4]));
2149 addr
[0] = alwaysOn
[0];
2150 addr
[1] = alwaysOn
[1];
2151 mask
[0] = alwaysOn
[0] | alwaysOff
[0];
2152 mask
[1] = alwaysOn
[1] | alwaysOff
[1];
2155 addr
[0] |= NVREG_MCASTADDRA_FORCE
;
2156 pff
|= NVREG_PFF_ALWAYS
;
2157 spin_lock_irq(&np
->lock
);
2159 writel(addr
[0], base
+ NvRegMulticastAddrA
);
2160 writel(addr
[1], base
+ NvRegMulticastAddrB
);
2161 writel(mask
[0], base
+ NvRegMulticastMaskA
);
2162 writel(mask
[1], base
+ NvRegMulticastMaskB
);
2163 writel(pff
, base
+ NvRegPacketFilterFlags
);
2164 dprintk(KERN_INFO
"%s: reconfiguration for multicast lists.\n",
2167 spin_unlock_irq(&np
->lock
);
2170 static void nv_update_pause(struct net_device
*dev
, u32 pause_flags
)
2172 struct fe_priv
*np
= netdev_priv(dev
);
2173 u8 __iomem
*base
= get_hwbase(dev
);
2175 np
->pause_flags
&= ~(NV_PAUSEFRAME_TX_ENABLE
| NV_PAUSEFRAME_RX_ENABLE
);
2177 if (np
->pause_flags
& NV_PAUSEFRAME_RX_CAPABLE
) {
2178 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & ~NVREG_PFF_PAUSE_RX
;
2179 if (pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) {
2180 writel(pff
|NVREG_PFF_PAUSE_RX
, base
+ NvRegPacketFilterFlags
);
2181 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
2183 writel(pff
, base
+ NvRegPacketFilterFlags
);
2186 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
) {
2187 u32 regmisc
= readl(base
+ NvRegMisc1
) & ~NVREG_MISC1_PAUSE_TX
;
2188 if (pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) {
2189 writel(NVREG_TX_PAUSEFRAME_ENABLE
, base
+ NvRegTxPauseFrame
);
2190 writel(regmisc
|NVREG_MISC1_PAUSE_TX
, base
+ NvRegMisc1
);
2191 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
2193 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
2194 writel(regmisc
, base
+ NvRegMisc1
);
2200 * nv_update_linkspeed: Setup the MAC according to the link partner
2201 * @dev: Network device to be configured
2203 * The function queries the PHY and checks if there is a link partner.
2204 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2205 * set to 10 MBit HD.
2207 * The function returns 0 if there is no link partner and 1 if there is
2208 * a good link partner.
2210 static int nv_update_linkspeed(struct net_device
*dev
)
2212 struct fe_priv
*np
= netdev_priv(dev
);
2213 u8 __iomem
*base
= get_hwbase(dev
);
2216 int adv_lpa
, adv_pause
, lpa_pause
;
2217 int newls
= np
->linkspeed
;
2218 int newdup
= np
->duplex
;
2221 u32 control_1000
, status_1000
, phyreg
, pause_flags
, txreg
;
2223 /* BMSR_LSTATUS is latched, read it twice:
2224 * we want the current value.
2226 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
2227 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
2229 if (!(mii_status
& BMSR_LSTATUS
)) {
2230 dprintk(KERN_DEBUG
"%s: no link detected by phy - falling back to 10HD.\n",
2232 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2238 if (np
->autoneg
== 0) {
2239 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2240 dev
->name
, np
->fixed_mode
);
2241 if (np
->fixed_mode
& LPA_100FULL
) {
2242 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
2244 } else if (np
->fixed_mode
& LPA_100HALF
) {
2245 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
2247 } else if (np
->fixed_mode
& LPA_10FULL
) {
2248 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2251 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2257 /* check auto negotiation is complete */
2258 if (!(mii_status
& BMSR_ANEGCOMPLETE
)) {
2259 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2260 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2263 dprintk(KERN_DEBUG
"%s: autoneg not completed - falling back to 10HD.\n", dev
->name
);
2267 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
2268 lpa
= mii_rw(dev
, np
->phyaddr
, MII_LPA
, MII_READ
);
2269 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2270 dev
->name
, adv
, lpa
);
2273 if (np
->gigabit
== PHY_GIGABIT
) {
2274 control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
2275 status_1000
= mii_rw(dev
, np
->phyaddr
, MII_STAT1000
, MII_READ
);
2277 if ((control_1000
& ADVERTISE_1000FULL
) &&
2278 (status_1000
& LPA_1000FULL
)) {
2279 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: GBit ethernet detected.\n",
2281 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_1000
;
2287 /* FIXME: handle parallel detection properly */
2288 adv_lpa
= lpa
& adv
;
2289 if (adv_lpa
& LPA_100FULL
) {
2290 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
2292 } else if (adv_lpa
& LPA_100HALF
) {
2293 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
2295 } else if (adv_lpa
& LPA_10FULL
) {
2296 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2298 } else if (adv_lpa
& LPA_10HALF
) {
2299 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2302 dprintk(KERN_DEBUG
"%s: bad ability %04x - falling back to 10HD.\n", dev
->name
, adv_lpa
);
2303 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
2308 if (np
->duplex
== newdup
&& np
->linkspeed
== newls
)
2311 dprintk(KERN_INFO
"%s: changing link setting from %d/%d to %d/%d.\n",
2312 dev
->name
, np
->linkspeed
, np
->duplex
, newls
, newdup
);
2314 np
->duplex
= newdup
;
2315 np
->linkspeed
= newls
;
2317 if (np
->gigabit
== PHY_GIGABIT
) {
2318 phyreg
= readl(base
+ NvRegRandomSeed
);
2319 phyreg
&= ~(0x3FF00);
2320 if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
)
2321 phyreg
|= NVREG_RNDSEED_FORCE3
;
2322 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
)
2323 phyreg
|= NVREG_RNDSEED_FORCE2
;
2324 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
2325 phyreg
|= NVREG_RNDSEED_FORCE
;
2326 writel(phyreg
, base
+ NvRegRandomSeed
);
2329 phyreg
= readl(base
+ NvRegPhyInterface
);
2330 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
2331 if (np
->duplex
== 0)
2333 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
2335 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
2337 writel(phyreg
, base
+ NvRegPhyInterface
);
2339 if (phyreg
& PHY_RGMII
) {
2340 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
2341 txreg
= NVREG_TX_DEFERRAL_RGMII_1000
;
2343 txreg
= NVREG_TX_DEFERRAL_RGMII_10_100
;
2345 txreg
= NVREG_TX_DEFERRAL_DEFAULT
;
2347 writel(txreg
, base
+ NvRegTxDeferral
);
2349 if (np
->desc_ver
== DESC_VER_1
) {
2350 txreg
= NVREG_TX_WM_DESC1_DEFAULT
;
2352 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
2353 txreg
= NVREG_TX_WM_DESC2_3_1000
;
2355 txreg
= NVREG_TX_WM_DESC2_3_DEFAULT
;
2357 writel(txreg
, base
+ NvRegTxWatermark
);
2359 writel(NVREG_MISC1_FORCE
| ( np
->duplex
? 0 : NVREG_MISC1_HD
),
2362 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
2366 /* setup pause frame */
2367 if (np
->duplex
!= 0) {
2368 if (np
->autoneg
&& np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) {
2369 adv_pause
= adv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2370 lpa_pause
= lpa
& (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
);
2372 switch (adv_pause
) {
2373 case ADVERTISE_PAUSE_CAP
:
2374 if (lpa_pause
& LPA_PAUSE_CAP
) {
2375 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
2376 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
2377 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
2380 case ADVERTISE_PAUSE_ASYM
:
2381 if (lpa_pause
== (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
))
2383 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
2386 case ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
:
2387 if (lpa_pause
& LPA_PAUSE_CAP
)
2389 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
2390 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
2391 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
2393 if (lpa_pause
== LPA_PAUSE_ASYM
)
2395 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
2400 pause_flags
= np
->pause_flags
;
2403 nv_update_pause(dev
, pause_flags
);
2408 static void nv_linkchange(struct net_device
*dev
)
2410 if (nv_update_linkspeed(dev
)) {
2411 if (!netif_carrier_ok(dev
)) {
2412 netif_carrier_on(dev
);
2413 printk(KERN_INFO
"%s: link up.\n", dev
->name
);
2417 if (netif_carrier_ok(dev
)) {
2418 netif_carrier_off(dev
);
2419 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
2425 static void nv_link_irq(struct net_device
*dev
)
2427 u8 __iomem
*base
= get_hwbase(dev
);
2430 miistat
= readl(base
+ NvRegMIIStatus
);
2431 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
2432 dprintk(KERN_INFO
"%s: link change irq, status 0x%x.\n", dev
->name
, miistat
);
2434 if (miistat
& (NVREG_MIISTAT_LINKCHANGE
))
2436 dprintk(KERN_DEBUG
"%s: link change notification done.\n", dev
->name
);
2439 static irqreturn_t
nv_nic_irq(int foo
, void *data
)
2441 struct net_device
*dev
= (struct net_device
*) data
;
2442 struct fe_priv
*np
= netdev_priv(dev
);
2443 u8 __iomem
*base
= get_hwbase(dev
);
2447 dprintk(KERN_DEBUG
"%s: nv_nic_irq\n", dev
->name
);
2450 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
2451 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
2452 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
2454 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
2455 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
2458 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
2459 if (!(events
& np
->irqmask
))
2462 spin_lock(&np
->lock
);
2464 spin_unlock(&np
->lock
);
2466 if (events
& NVREG_IRQ_LINK
) {
2467 spin_lock(&np
->lock
);
2469 spin_unlock(&np
->lock
);
2471 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
2472 spin_lock(&np
->lock
);
2474 spin_unlock(&np
->lock
);
2475 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
2477 if (events
& (NVREG_IRQ_TX_ERR
)) {
2478 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
2481 if (events
& (NVREG_IRQ_UNKNOWN
)) {
2482 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
2485 if (unlikely(events
& NVREG_IRQ_RECOVER_ERROR
)) {
2486 spin_lock(&np
->lock
);
2487 /* disable interrupts on the nic */
2488 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
2489 writel(0, base
+ NvRegIrqMask
);
2491 writel(np
->irqmask
, base
+ NvRegIrqMask
);
2494 if (!np
->in_shutdown
) {
2495 np
->nic_poll_irq
= np
->irqmask
;
2496 np
->recover_error
= 1;
2497 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2499 spin_unlock(&np
->lock
);
2502 #ifdef CONFIG_FORCEDETH_NAPI
2503 if (events
& NVREG_IRQ_RX_ALL
) {
2504 netif_rx_schedule(dev
);
2506 /* Disable furthur receive irq's */
2507 spin_lock(&np
->lock
);
2508 np
->irqmask
&= ~NVREG_IRQ_RX_ALL
;
2510 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
2511 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
2513 writel(np
->irqmask
, base
+ NvRegIrqMask
);
2514 spin_unlock(&np
->lock
);
2517 nv_rx_process(dev
, dev
->weight
);
2518 if (nv_alloc_rx(dev
)) {
2519 spin_lock(&np
->lock
);
2520 if (!np
->in_shutdown
)
2521 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2522 spin_unlock(&np
->lock
);
2525 if (i
> max_interrupt_work
) {
2526 spin_lock(&np
->lock
);
2527 /* disable interrupts on the nic */
2528 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
2529 writel(0, base
+ NvRegIrqMask
);
2531 writel(np
->irqmask
, base
+ NvRegIrqMask
);
2534 if (!np
->in_shutdown
) {
2535 np
->nic_poll_irq
= np
->irqmask
;
2536 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2538 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq.\n", dev
->name
, i
);
2539 spin_unlock(&np
->lock
);
2544 dprintk(KERN_DEBUG
"%s: nv_nic_irq completed\n", dev
->name
);
2546 return IRQ_RETVAL(i
);
2549 static irqreturn_t
nv_nic_irq_tx(int foo
, void *data
)
2551 struct net_device
*dev
= (struct net_device
*) data
;
2552 struct fe_priv
*np
= netdev_priv(dev
);
2553 u8 __iomem
*base
= get_hwbase(dev
);
2556 unsigned long flags
;
2558 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx\n", dev
->name
);
2561 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_TX_ALL
;
2562 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegMSIXIrqStatus
);
2564 dprintk(KERN_DEBUG
"%s: tx irq: %08x\n", dev
->name
, events
);
2565 if (!(events
& np
->irqmask
))
2568 spin_lock_irqsave(&np
->lock
, flags
);
2570 spin_unlock_irqrestore(&np
->lock
, flags
);
2572 if (events
& (NVREG_IRQ_TX_ERR
)) {
2573 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
2576 if (i
> max_interrupt_work
) {
2577 spin_lock_irqsave(&np
->lock
, flags
);
2578 /* disable interrupts on the nic */
2579 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegIrqMask
);
2582 if (!np
->in_shutdown
) {
2583 np
->nic_poll_irq
|= NVREG_IRQ_TX_ALL
;
2584 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2586 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev
->name
, i
);
2587 spin_unlock_irqrestore(&np
->lock
, flags
);
2592 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx completed\n", dev
->name
);
2594 return IRQ_RETVAL(i
);
2597 #ifdef CONFIG_FORCEDETH_NAPI
2598 static int nv_napi_poll(struct net_device
*dev
, int *budget
)
2600 int pkts
, limit
= min(*budget
, dev
->quota
);
2601 struct fe_priv
*np
= netdev_priv(dev
);
2602 u8 __iomem
*base
= get_hwbase(dev
);
2603 unsigned long flags
;
2605 pkts
= nv_rx_process(dev
, limit
);
2607 if (nv_alloc_rx(dev
)) {
2608 spin_lock_irqsave(&np
->lock
, flags
);
2609 if (!np
->in_shutdown
)
2610 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2611 spin_unlock_irqrestore(&np
->lock
, flags
);
2615 /* all done, no more packets present */
2616 netif_rx_complete(dev
);
2618 /* re-enable receive interrupts */
2619 spin_lock_irqsave(&np
->lock
, flags
);
2621 np
->irqmask
|= NVREG_IRQ_RX_ALL
;
2622 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
2623 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
2625 writel(np
->irqmask
, base
+ NvRegIrqMask
);
2627 spin_unlock_irqrestore(&np
->lock
, flags
);
2630 /* used up our quantum, so reschedule */
2638 #ifdef CONFIG_FORCEDETH_NAPI
2639 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
)
2641 struct net_device
*dev
= (struct net_device
*) data
;
2642 u8 __iomem
*base
= get_hwbase(dev
);
2645 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
2646 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegMSIXIrqStatus
);
2649 netif_rx_schedule(dev
);
2650 /* disable receive interrupts on the nic */
2651 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
2657 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
)
2659 struct net_device
*dev
= (struct net_device
*) data
;
2660 struct fe_priv
*np
= netdev_priv(dev
);
2661 u8 __iomem
*base
= get_hwbase(dev
);
2664 unsigned long flags
;
2666 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx\n", dev
->name
);
2669 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
2670 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegMSIXIrqStatus
);
2672 dprintk(KERN_DEBUG
"%s: rx irq: %08x\n", dev
->name
, events
);
2673 if (!(events
& np
->irqmask
))
2676 nv_rx_process(dev
, dev
->weight
);
2677 if (nv_alloc_rx(dev
)) {
2678 spin_lock_irqsave(&np
->lock
, flags
);
2679 if (!np
->in_shutdown
)
2680 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2681 spin_unlock_irqrestore(&np
->lock
, flags
);
2684 if (i
> max_interrupt_work
) {
2685 spin_lock_irqsave(&np
->lock
, flags
);
2686 /* disable interrupts on the nic */
2687 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
2690 if (!np
->in_shutdown
) {
2691 np
->nic_poll_irq
|= NVREG_IRQ_RX_ALL
;
2692 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2694 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev
->name
, i
);
2695 spin_unlock_irqrestore(&np
->lock
, flags
);
2699 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx completed\n", dev
->name
);
2701 return IRQ_RETVAL(i
);
2705 static irqreturn_t
nv_nic_irq_other(int foo
, void *data
)
2707 struct net_device
*dev
= (struct net_device
*) data
;
2708 struct fe_priv
*np
= netdev_priv(dev
);
2709 u8 __iomem
*base
= get_hwbase(dev
);
2712 unsigned long flags
;
2714 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other\n", dev
->name
);
2717 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_OTHER
;
2718 writel(NVREG_IRQ_OTHER
, base
+ NvRegMSIXIrqStatus
);
2720 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
2721 if (!(events
& np
->irqmask
))
2724 if (events
& NVREG_IRQ_LINK
) {
2725 spin_lock_irqsave(&np
->lock
, flags
);
2727 spin_unlock_irqrestore(&np
->lock
, flags
);
2729 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
2730 spin_lock_irqsave(&np
->lock
, flags
);
2732 spin_unlock_irqrestore(&np
->lock
, flags
);
2733 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
2735 if (events
& NVREG_IRQ_RECOVER_ERROR
) {
2736 spin_lock_irq(&np
->lock
);
2737 /* disable interrupts on the nic */
2738 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
2741 if (!np
->in_shutdown
) {
2742 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
2743 np
->recover_error
= 1;
2744 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2746 spin_unlock_irq(&np
->lock
);
2749 if (events
& (NVREG_IRQ_UNKNOWN
)) {
2750 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
2753 if (i
> max_interrupt_work
) {
2754 spin_lock_irqsave(&np
->lock
, flags
);
2755 /* disable interrupts on the nic */
2756 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
2759 if (!np
->in_shutdown
) {
2760 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
2761 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2763 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_other.\n", dev
->name
, i
);
2764 spin_unlock_irqrestore(&np
->lock
, flags
);
2769 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other completed\n", dev
->name
);
2771 return IRQ_RETVAL(i
);
2774 static irqreturn_t
nv_nic_irq_test(int foo
, void *data
)
2776 struct net_device
*dev
= (struct net_device
*) data
;
2777 struct fe_priv
*np
= netdev_priv(dev
);
2778 u8 __iomem
*base
= get_hwbase(dev
);
2781 dprintk(KERN_DEBUG
"%s: nv_nic_irq_test\n", dev
->name
);
2783 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
2784 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
2785 writel(NVREG_IRQ_TIMER
, base
+ NvRegIrqStatus
);
2787 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
2788 writel(NVREG_IRQ_TIMER
, base
+ NvRegMSIXIrqStatus
);
2791 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
2792 if (!(events
& NVREG_IRQ_TIMER
))
2793 return IRQ_RETVAL(0);
2795 spin_lock(&np
->lock
);
2797 spin_unlock(&np
->lock
);
2799 dprintk(KERN_DEBUG
"%s: nv_nic_irq_test completed\n", dev
->name
);
2801 return IRQ_RETVAL(1);
2804 static void set_msix_vector_map(struct net_device
*dev
, u32 vector
, u32 irqmask
)
2806 u8 __iomem
*base
= get_hwbase(dev
);
2810 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2811 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2812 * the remaining 8 interrupts.
2814 for (i
= 0; i
< 8; i
++) {
2815 if ((irqmask
>> i
) & 0x1) {
2816 msixmap
|= vector
<< (i
<< 2);
2819 writel(readl(base
+ NvRegMSIXMap0
) | msixmap
, base
+ NvRegMSIXMap0
);
2822 for (i
= 0; i
< 8; i
++) {
2823 if ((irqmask
>> (i
+ 8)) & 0x1) {
2824 msixmap
|= vector
<< (i
<< 2);
2827 writel(readl(base
+ NvRegMSIXMap1
) | msixmap
, base
+ NvRegMSIXMap1
);
2830 static int nv_request_irq(struct net_device
*dev
, int intr_test
)
2832 struct fe_priv
*np
= get_nvpriv(dev
);
2833 u8 __iomem
*base
= get_hwbase(dev
);
2837 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) {
2838 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
2839 np
->msi_x_entry
[i
].entry
= i
;
2841 if ((ret
= pci_enable_msix(np
->pci_dev
, np
->msi_x_entry
, (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
))) == 0) {
2842 np
->msi_flags
|= NV_MSI_X_ENABLED
;
2843 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
&& !intr_test
) {
2844 /* Request irq for rx handling */
2845 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, &nv_nic_irq_rx
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
2846 printk(KERN_INFO
"forcedeth: request_irq failed for rx %d\n", ret
);
2847 pci_disable_msix(np
->pci_dev
);
2848 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2851 /* Request irq for tx handling */
2852 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, &nv_nic_irq_tx
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
2853 printk(KERN_INFO
"forcedeth: request_irq failed for tx %d\n", ret
);
2854 pci_disable_msix(np
->pci_dev
);
2855 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2858 /* Request irq for link and timer handling */
2859 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
, &nv_nic_irq_other
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
2860 printk(KERN_INFO
"forcedeth: request_irq failed for link %d\n", ret
);
2861 pci_disable_msix(np
->pci_dev
);
2862 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2865 /* map interrupts to their respective vector */
2866 writel(0, base
+ NvRegMSIXMap0
);
2867 writel(0, base
+ NvRegMSIXMap1
);
2868 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_RX
, NVREG_IRQ_RX_ALL
);
2869 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_TX
, NVREG_IRQ_TX_ALL
);
2870 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_OTHER
, NVREG_IRQ_OTHER
);
2872 /* Request irq for all interrupts */
2874 request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
, &nv_nic_irq
, IRQF_SHARED
, dev
->name
, dev
) != 0) ||
2876 request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
, &nv_nic_irq_test
, IRQF_SHARED
, dev
->name
, dev
) != 0)) {
2877 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
2878 pci_disable_msix(np
->pci_dev
);
2879 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2883 /* map interrupts to vector 0 */
2884 writel(0, base
+ NvRegMSIXMap0
);
2885 writel(0, base
+ NvRegMSIXMap1
);
2889 if (ret
!= 0 && np
->msi_flags
& NV_MSI_CAPABLE
) {
2890 if ((ret
= pci_enable_msi(np
->pci_dev
)) == 0) {
2891 np
->msi_flags
|= NV_MSI_ENABLED
;
2892 if ((!intr_test
&& request_irq(np
->pci_dev
->irq
, &nv_nic_irq
, IRQF_SHARED
, dev
->name
, dev
) != 0) ||
2893 (intr_test
&& request_irq(np
->pci_dev
->irq
, &nv_nic_irq_test
, IRQF_SHARED
, dev
->name
, dev
) != 0)) {
2894 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
2895 pci_disable_msi(np
->pci_dev
);
2896 np
->msi_flags
&= ~NV_MSI_ENABLED
;
2900 /* map interrupts to vector 0 */
2901 writel(0, base
+ NvRegMSIMap0
);
2902 writel(0, base
+ NvRegMSIMap1
);
2903 /* enable msi vector 0 */
2904 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
2908 if ((!intr_test
&& request_irq(np
->pci_dev
->irq
, &nv_nic_irq
, IRQF_SHARED
, dev
->name
, dev
) != 0) ||
2909 (intr_test
&& request_irq(np
->pci_dev
->irq
, &nv_nic_irq_test
, IRQF_SHARED
, dev
->name
, dev
) != 0))
2916 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, dev
);
2918 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, dev
);
2923 static void nv_free_irq(struct net_device
*dev
)
2925 struct fe_priv
*np
= get_nvpriv(dev
);
2928 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
2929 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
2930 free_irq(np
->msi_x_entry
[i
].vector
, dev
);
2932 pci_disable_msix(np
->pci_dev
);
2933 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2935 free_irq(np
->pci_dev
->irq
, dev
);
2936 if (np
->msi_flags
& NV_MSI_ENABLED
) {
2937 pci_disable_msi(np
->pci_dev
);
2938 np
->msi_flags
&= ~NV_MSI_ENABLED
;
2943 static void nv_do_nic_poll(unsigned long data
)
2945 struct net_device
*dev
= (struct net_device
*) data
;
2946 struct fe_priv
*np
= netdev_priv(dev
);
2947 u8 __iomem
*base
= get_hwbase(dev
);
2951 * First disable irq(s) and then
2952 * reenable interrupts on the nic, we have to do this before calling
2953 * nv_nic_irq because that may decide to do otherwise
2956 if (!using_multi_irqs(dev
)) {
2957 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
2958 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
2960 disable_irq_lockdep(dev
->irq
);
2963 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
2964 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
2965 mask
|= NVREG_IRQ_RX_ALL
;
2967 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
2968 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
2969 mask
|= NVREG_IRQ_TX_ALL
;
2971 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
2972 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
2973 mask
|= NVREG_IRQ_OTHER
;
2976 np
->nic_poll_irq
= 0;
2978 if (np
->recover_error
) {
2979 np
->recover_error
= 0;
2980 printk(KERN_INFO
"forcedeth: MAC in recoverable error state\n");
2981 if (netif_running(dev
)) {
2982 netif_tx_lock_bh(dev
);
2983 spin_lock(&np
->lock
);
2988 /* drain rx queue */
2991 /* reinit driver view of the rx queue */
2993 if (nv_init_ring(dev
)) {
2994 if (!np
->in_shutdown
)
2995 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2997 /* reinit nic view of the rx queue */
2998 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
2999 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
3000 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
3001 base
+ NvRegRingSizes
);
3003 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
3006 /* restart rx engine */
3009 spin_unlock(&np
->lock
);
3010 netif_tx_unlock_bh(dev
);
3014 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
3016 writel(mask
, base
+ NvRegIrqMask
);
3019 if (!using_multi_irqs(dev
)) {
3021 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
3022 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
3024 enable_irq_lockdep(dev
->irq
);
3026 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
3027 nv_nic_irq_rx(0, dev
);
3028 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
3030 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
3031 nv_nic_irq_tx(0, dev
);
3032 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
3034 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
3035 nv_nic_irq_other(0, dev
);
3036 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
3041 #ifdef CONFIG_NET_POLL_CONTROLLER
3042 static void nv_poll_controller(struct net_device
*dev
)
3044 nv_do_nic_poll((unsigned long) dev
);
3048 static void nv_do_stats_poll(unsigned long data
)
3050 struct net_device
*dev
= (struct net_device
*) data
;
3051 struct fe_priv
*np
= netdev_priv(dev
);
3052 u8 __iomem
*base
= get_hwbase(dev
);
3054 np
->estats
.tx_bytes
+= readl(base
+ NvRegTxCnt
);
3055 np
->estats
.tx_zero_rexmt
+= readl(base
+ NvRegTxZeroReXmt
);
3056 np
->estats
.tx_one_rexmt
+= readl(base
+ NvRegTxOneReXmt
);
3057 np
->estats
.tx_many_rexmt
+= readl(base
+ NvRegTxManyReXmt
);
3058 np
->estats
.tx_late_collision
+= readl(base
+ NvRegTxLateCol
);
3059 np
->estats
.tx_fifo_errors
+= readl(base
+ NvRegTxUnderflow
);
3060 np
->estats
.tx_carrier_errors
+= readl(base
+ NvRegTxLossCarrier
);
3061 np
->estats
.tx_excess_deferral
+= readl(base
+ NvRegTxExcessDef
);
3062 np
->estats
.tx_retry_error
+= readl(base
+ NvRegTxRetryErr
);
3063 np
->estats
.tx_deferral
+= readl(base
+ NvRegTxDef
);
3064 np
->estats
.tx_packets
+= readl(base
+ NvRegTxFrame
);
3065 np
->estats
.tx_pause
+= readl(base
+ NvRegTxPause
);
3066 np
->estats
.rx_frame_error
+= readl(base
+ NvRegRxFrameErr
);
3067 np
->estats
.rx_extra_byte
+= readl(base
+ NvRegRxExtraByte
);
3068 np
->estats
.rx_late_collision
+= readl(base
+ NvRegRxLateCol
);
3069 np
->estats
.rx_runt
+= readl(base
+ NvRegRxRunt
);
3070 np
->estats
.rx_frame_too_long
+= readl(base
+ NvRegRxFrameTooLong
);
3071 np
->estats
.rx_over_errors
+= readl(base
+ NvRegRxOverflow
);
3072 np
->estats
.rx_crc_errors
+= readl(base
+ NvRegRxFCSErr
);
3073 np
->estats
.rx_frame_align_error
+= readl(base
+ NvRegRxFrameAlignErr
);
3074 np
->estats
.rx_length_error
+= readl(base
+ NvRegRxLenErr
);
3075 np
->estats
.rx_unicast
+= readl(base
+ NvRegRxUnicast
);
3076 np
->estats
.rx_multicast
+= readl(base
+ NvRegRxMulticast
);
3077 np
->estats
.rx_broadcast
+= readl(base
+ NvRegRxBroadcast
);
3078 np
->estats
.rx_bytes
+= readl(base
+ NvRegRxCnt
);
3079 np
->estats
.rx_pause
+= readl(base
+ NvRegRxPause
);
3080 np
->estats
.rx_drop_frame
+= readl(base
+ NvRegRxDropFrame
);
3081 np
->estats
.rx_packets
=
3082 np
->estats
.rx_unicast
+
3083 np
->estats
.rx_multicast
+
3084 np
->estats
.rx_broadcast
;
3085 np
->estats
.rx_errors_total
=
3086 np
->estats
.rx_crc_errors
+
3087 np
->estats
.rx_over_errors
+
3088 np
->estats
.rx_frame_error
+
3089 (np
->estats
.rx_frame_align_error
- np
->estats
.rx_extra_byte
) +
3090 np
->estats
.rx_late_collision
+
3091 np
->estats
.rx_runt
+
3092 np
->estats
.rx_frame_too_long
;
3094 if (!np
->in_shutdown
)
3095 mod_timer(&np
->stats_poll
, jiffies
+ STATS_INTERVAL
);
3098 static void nv_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
3100 struct fe_priv
*np
= netdev_priv(dev
);
3101 strcpy(info
->driver
, "forcedeth");
3102 strcpy(info
->version
, FORCEDETH_VERSION
);
3103 strcpy(info
->bus_info
, pci_name(np
->pci_dev
));
3106 static void nv_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
3108 struct fe_priv
*np
= netdev_priv(dev
);
3109 wolinfo
->supported
= WAKE_MAGIC
;
3111 spin_lock_irq(&np
->lock
);
3113 wolinfo
->wolopts
= WAKE_MAGIC
;
3114 spin_unlock_irq(&np
->lock
);
3117 static int nv_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
3119 struct fe_priv
*np
= netdev_priv(dev
);
3120 u8 __iomem
*base
= get_hwbase(dev
);
3123 if (wolinfo
->wolopts
== 0) {
3125 } else if (wolinfo
->wolopts
& WAKE_MAGIC
) {
3127 flags
= NVREG_WAKEUPFLAGS_ENABLE
;
3129 if (netif_running(dev
)) {
3130 spin_lock_irq(&np
->lock
);
3131 writel(flags
, base
+ NvRegWakeUpFlags
);
3132 spin_unlock_irq(&np
->lock
);
3137 static int nv_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3139 struct fe_priv
*np
= netdev_priv(dev
);
3142 spin_lock_irq(&np
->lock
);
3143 ecmd
->port
= PORT_MII
;
3144 if (!netif_running(dev
)) {
3145 /* We do not track link speed / duplex setting if the
3146 * interface is disabled. Force a link check */
3147 if (nv_update_linkspeed(dev
)) {
3148 if (!netif_carrier_ok(dev
))
3149 netif_carrier_on(dev
);
3151 if (netif_carrier_ok(dev
))
3152 netif_carrier_off(dev
);
3156 if (netif_carrier_ok(dev
)) {
3157 switch(np
->linkspeed
& (NVREG_LINKSPEED_MASK
)) {
3158 case NVREG_LINKSPEED_10
:
3159 ecmd
->speed
= SPEED_10
;
3161 case NVREG_LINKSPEED_100
:
3162 ecmd
->speed
= SPEED_100
;
3164 case NVREG_LINKSPEED_1000
:
3165 ecmd
->speed
= SPEED_1000
;
3168 ecmd
->duplex
= DUPLEX_HALF
;
3170 ecmd
->duplex
= DUPLEX_FULL
;
3176 ecmd
->autoneg
= np
->autoneg
;
3178 ecmd
->advertising
= ADVERTISED_MII
;
3180 ecmd
->advertising
|= ADVERTISED_Autoneg
;
3181 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
3182 if (adv
& ADVERTISE_10HALF
)
3183 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
3184 if (adv
& ADVERTISE_10FULL
)
3185 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
3186 if (adv
& ADVERTISE_100HALF
)
3187 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
3188 if (adv
& ADVERTISE_100FULL
)
3189 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
3190 if (np
->gigabit
== PHY_GIGABIT
) {
3191 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
3192 if (adv
& ADVERTISE_1000FULL
)
3193 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
3196 ecmd
->supported
= (SUPPORTED_Autoneg
|
3197 SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
3198 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
3200 if (np
->gigabit
== PHY_GIGABIT
)
3201 ecmd
->supported
|= SUPPORTED_1000baseT_Full
;
3203 ecmd
->phy_address
= np
->phyaddr
;
3204 ecmd
->transceiver
= XCVR_EXTERNAL
;
3206 /* ignore maxtxpkt, maxrxpkt for now */
3207 spin_unlock_irq(&np
->lock
);
3211 static int nv_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3213 struct fe_priv
*np
= netdev_priv(dev
);
3215 if (ecmd
->port
!= PORT_MII
)
3217 if (ecmd
->transceiver
!= XCVR_EXTERNAL
)
3219 if (ecmd
->phy_address
!= np
->phyaddr
) {
3220 /* TODO: support switching between multiple phys. Should be
3221 * trivial, but not enabled due to lack of test hardware. */
3224 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
3227 mask
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
3228 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
3229 if (np
->gigabit
== PHY_GIGABIT
)
3230 mask
|= ADVERTISED_1000baseT_Full
;
3232 if ((ecmd
->advertising
& mask
) == 0)
3235 } else if (ecmd
->autoneg
== AUTONEG_DISABLE
) {
3236 /* Note: autonegotiation disable, speed 1000 intentionally
3237 * forbidden - noone should need that. */
3239 if (ecmd
->speed
!= SPEED_10
&& ecmd
->speed
!= SPEED_100
)
3241 if (ecmd
->duplex
!= DUPLEX_HALF
&& ecmd
->duplex
!= DUPLEX_FULL
)
3247 netif_carrier_off(dev
);
3248 if (netif_running(dev
)) {
3249 nv_disable_irq(dev
);
3250 netif_tx_lock_bh(dev
);
3251 spin_lock(&np
->lock
);
3255 spin_unlock(&np
->lock
);
3256 netif_tx_unlock_bh(dev
);
3259 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
3264 /* advertise only what has been requested */
3265 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
3266 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3267 if (ecmd
->advertising
& ADVERTISED_10baseT_Half
)
3268 adv
|= ADVERTISE_10HALF
;
3269 if (ecmd
->advertising
& ADVERTISED_10baseT_Full
)
3270 adv
|= ADVERTISE_10FULL
;
3271 if (ecmd
->advertising
& ADVERTISED_100baseT_Half
)
3272 adv
|= ADVERTISE_100HALF
;
3273 if (ecmd
->advertising
& ADVERTISED_100baseT_Full
)
3274 adv
|= ADVERTISE_100FULL
;
3275 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisments but disable tx pause */
3276 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
3277 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3278 adv
|= ADVERTISE_PAUSE_ASYM
;
3279 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
3281 if (np
->gigabit
== PHY_GIGABIT
) {
3282 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
3283 adv
&= ~ADVERTISE_1000FULL
;
3284 if (ecmd
->advertising
& ADVERTISED_1000baseT_Full
)
3285 adv
|= ADVERTISE_1000FULL
;
3286 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
3289 if (netif_running(dev
))
3290 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
3291 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
3292 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
3293 bmcr
|= BMCR_ANENABLE
;
3294 /* reset the phy in order for settings to stick,
3295 * and cause autoneg to start */
3296 if (phy_reset(dev
, bmcr
)) {
3297 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
3301 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
3302 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
3309 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
3310 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3311 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_HALF
)
3312 adv
|= ADVERTISE_10HALF
;
3313 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_FULL
)
3314 adv
|= ADVERTISE_10FULL
;
3315 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_HALF
)
3316 adv
|= ADVERTISE_100HALF
;
3317 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_FULL
)
3318 adv
|= ADVERTISE_100FULL
;
3319 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
3320 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) {/* for rx we set both advertisments but disable tx pause */
3321 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
3322 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3324 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
) {
3325 adv
|= ADVERTISE_PAUSE_ASYM
;
3326 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3328 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
3329 np
->fixed_mode
= adv
;
3331 if (np
->gigabit
== PHY_GIGABIT
) {
3332 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
3333 adv
&= ~ADVERTISE_1000FULL
;
3334 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
3337 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
3338 bmcr
&= ~(BMCR_ANENABLE
|BMCR_SPEED100
|BMCR_SPEED1000
|BMCR_FULLDPLX
);
3339 if (np
->fixed_mode
& (ADVERTISE_10FULL
|ADVERTISE_100FULL
))
3340 bmcr
|= BMCR_FULLDPLX
;
3341 if (np
->fixed_mode
& (ADVERTISE_100HALF
|ADVERTISE_100FULL
))
3342 bmcr
|= BMCR_SPEED100
;
3343 if (np
->phy_oui
== PHY_OUI_MARVELL
) {
3344 /* reset the phy in order for forced mode settings to stick */
3345 if (phy_reset(dev
, bmcr
)) {
3346 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
3350 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
3351 if (netif_running(dev
)) {
3352 /* Wait a bit and then reconfigure the nic. */
3359 if (netif_running(dev
)) {
3368 #define FORCEDETH_REGS_VER 1
3370 static int nv_get_regs_len(struct net_device
*dev
)
3372 struct fe_priv
*np
= netdev_priv(dev
);
3373 return np
->register_size
;
3376 static void nv_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
, void *buf
)
3378 struct fe_priv
*np
= netdev_priv(dev
);
3379 u8 __iomem
*base
= get_hwbase(dev
);
3383 regs
->version
= FORCEDETH_REGS_VER
;
3384 spin_lock_irq(&np
->lock
);
3385 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
3386 rbuf
[i
] = readl(base
+ i
*sizeof(u32
));
3387 spin_unlock_irq(&np
->lock
);
3390 static int nv_nway_reset(struct net_device
*dev
)
3392 struct fe_priv
*np
= netdev_priv(dev
);
3398 netif_carrier_off(dev
);
3399 if (netif_running(dev
)) {
3400 nv_disable_irq(dev
);
3401 netif_tx_lock_bh(dev
);
3402 spin_lock(&np
->lock
);
3406 spin_unlock(&np
->lock
);
3407 netif_tx_unlock_bh(dev
);
3408 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
3411 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
3412 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
3413 bmcr
|= BMCR_ANENABLE
;
3414 /* reset the phy in order for settings to stick*/
3415 if (phy_reset(dev
, bmcr
)) {
3416 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
3420 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
3421 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
3424 if (netif_running(dev
)) {
3437 static int nv_set_tso(struct net_device
*dev
, u32 value
)
3439 struct fe_priv
*np
= netdev_priv(dev
);
3441 if ((np
->driver_data
& DEV_HAS_CHECKSUM
))
3442 return ethtool_op_set_tso(dev
, value
);
3447 static void nv_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
3449 struct fe_priv
*np
= netdev_priv(dev
);
3451 ring
->rx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
3452 ring
->rx_mini_max_pending
= 0;
3453 ring
->rx_jumbo_max_pending
= 0;
3454 ring
->tx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
3456 ring
->rx_pending
= np
->rx_ring_size
;
3457 ring
->rx_mini_pending
= 0;
3458 ring
->rx_jumbo_pending
= 0;
3459 ring
->tx_pending
= np
->tx_ring_size
;
3462 static int nv_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
3464 struct fe_priv
*np
= netdev_priv(dev
);
3465 u8 __iomem
*base
= get_hwbase(dev
);
3466 u8
*rxtx_ring
, *rx_skbuff
, *tx_skbuff
, *rx_dma
, *tx_dma
, *tx_dma_len
;
3467 dma_addr_t ring_addr
;
3469 if (ring
->rx_pending
< RX_RING_MIN
||
3470 ring
->tx_pending
< TX_RING_MIN
||
3471 ring
->rx_mini_pending
!= 0 ||
3472 ring
->rx_jumbo_pending
!= 0 ||
3473 (np
->desc_ver
== DESC_VER_1
&&
3474 (ring
->rx_pending
> RING_MAX_DESC_VER_1
||
3475 ring
->tx_pending
> RING_MAX_DESC_VER_1
)) ||
3476 (np
->desc_ver
!= DESC_VER_1
&&
3477 (ring
->rx_pending
> RING_MAX_DESC_VER_2_3
||
3478 ring
->tx_pending
> RING_MAX_DESC_VER_2_3
))) {
3482 /* allocate new rings */
3483 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
3484 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
3485 sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
3488 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
3489 sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
3492 rx_skbuff
= kmalloc(sizeof(struct sk_buff
*) * ring
->rx_pending
, GFP_KERNEL
);
3493 rx_dma
= kmalloc(sizeof(dma_addr_t
) * ring
->rx_pending
, GFP_KERNEL
);
3494 tx_skbuff
= kmalloc(sizeof(struct sk_buff
*) * ring
->tx_pending
, GFP_KERNEL
);
3495 tx_dma
= kmalloc(sizeof(dma_addr_t
) * ring
->tx_pending
, GFP_KERNEL
);
3496 tx_dma_len
= kmalloc(sizeof(unsigned int) * ring
->tx_pending
, GFP_KERNEL
);
3497 if (!rxtx_ring
|| !rx_skbuff
|| !rx_dma
|| !tx_skbuff
|| !tx_dma
|| !tx_dma_len
) {
3498 /* fall back to old rings */
3499 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
3501 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
3502 rxtx_ring
, ring_addr
);
3505 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
3506 rxtx_ring
, ring_addr
);
3521 if (netif_running(dev
)) {
3522 nv_disable_irq(dev
);
3523 netif_tx_lock_bh(dev
);
3524 spin_lock(&np
->lock
);
3536 /* set new values */
3537 np
->rx_ring_size
= ring
->rx_pending
;
3538 np
->tx_ring_size
= ring
->tx_pending
;
3539 np
->tx_limit_stop
= ring
->tx_pending
- TX_LIMIT_DIFFERENCE
;
3540 np
->tx_limit_start
= ring
->tx_pending
- TX_LIMIT_DIFFERENCE
- 1;
3541 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
3542 np
->rx_ring
.orig
= (struct ring_desc
*)rxtx_ring
;
3543 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
3545 np
->rx_ring
.ex
= (struct ring_desc_ex
*)rxtx_ring
;
3546 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
3548 np
->rx_skbuff
= (struct sk_buff
**)rx_skbuff
;
3549 np
->rx_dma
= (dma_addr_t
*)rx_dma
;
3550 np
->tx_skbuff
= (struct sk_buff
**)tx_skbuff
;
3551 np
->tx_dma
= (dma_addr_t
*)tx_dma
;
3552 np
->tx_dma_len
= (unsigned int*)tx_dma_len
;
3553 np
->ring_addr
= ring_addr
;
3555 memset(np
->rx_skbuff
, 0, sizeof(struct sk_buff
*) * np
->rx_ring_size
);
3556 memset(np
->rx_dma
, 0, sizeof(dma_addr_t
) * np
->rx_ring_size
);
3557 memset(np
->tx_skbuff
, 0, sizeof(struct sk_buff
*) * np
->tx_ring_size
);
3558 memset(np
->tx_dma
, 0, sizeof(dma_addr_t
) * np
->tx_ring_size
);
3559 memset(np
->tx_dma_len
, 0, sizeof(unsigned int) * np
->tx_ring_size
);
3561 if (netif_running(dev
)) {
3562 /* reinit driver view of the queues */
3564 if (nv_init_ring(dev
)) {
3565 if (!np
->in_shutdown
)
3566 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3569 /* reinit nic view of the queues */
3570 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
3571 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
3572 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
3573 base
+ NvRegRingSizes
);
3575 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
3578 /* restart engines */
3581 spin_unlock(&np
->lock
);
3582 netif_tx_unlock_bh(dev
);
3590 static void nv_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
3592 struct fe_priv
*np
= netdev_priv(dev
);
3594 pause
->autoneg
= (np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) != 0;
3595 pause
->rx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) != 0;
3596 pause
->tx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) != 0;
3599 static int nv_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
3601 struct fe_priv
*np
= netdev_priv(dev
);
3604 if ((!np
->autoneg
&& np
->duplex
== 0) ||
3605 (np
->autoneg
&& !pause
->autoneg
&& np
->duplex
== 0)) {
3606 printk(KERN_INFO
"%s: can not set pause settings when forced link is in half duplex.\n",
3610 if (pause
->tx_pause
&& !(np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)) {
3611 printk(KERN_INFO
"%s: hardware does not support tx pause frames.\n", dev
->name
);
3615 netif_carrier_off(dev
);
3616 if (netif_running(dev
)) {
3617 nv_disable_irq(dev
);
3618 netif_tx_lock_bh(dev
);
3619 spin_lock(&np
->lock
);
3623 spin_unlock(&np
->lock
);
3624 netif_tx_unlock_bh(dev
);
3627 np
->pause_flags
&= ~(NV_PAUSEFRAME_RX_REQ
|NV_PAUSEFRAME_TX_REQ
);
3628 if (pause
->rx_pause
)
3629 np
->pause_flags
|= NV_PAUSEFRAME_RX_REQ
;
3630 if (pause
->tx_pause
)
3631 np
->pause_flags
|= NV_PAUSEFRAME_TX_REQ
;
3633 if (np
->autoneg
&& pause
->autoneg
) {
3634 np
->pause_flags
|= NV_PAUSEFRAME_AUTONEG
;
3636 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
3637 adv
&= ~(ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3638 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisments but disable tx pause */
3639 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
3640 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3641 adv
|= ADVERTISE_PAUSE_ASYM
;
3642 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
3644 if (netif_running(dev
))
3645 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
3646 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
3647 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
3648 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
3650 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
3651 if (pause
->rx_pause
)
3652 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3653 if (pause
->tx_pause
)
3654 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3656 if (!netif_running(dev
))
3657 nv_update_linkspeed(dev
);
3659 nv_update_pause(dev
, np
->pause_flags
);
3662 if (netif_running(dev
)) {
3670 static u32
nv_get_rx_csum(struct net_device
*dev
)
3672 struct fe_priv
*np
= netdev_priv(dev
);
3673 return (np
->rx_csum
) != 0;
3676 static int nv_set_rx_csum(struct net_device
*dev
, u32 data
)
3678 struct fe_priv
*np
= netdev_priv(dev
);
3679 u8 __iomem
*base
= get_hwbase(dev
);
3682 if (np
->driver_data
& DEV_HAS_CHECKSUM
) {
3685 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
3688 /* vlan is dependent on rx checksum offload */
3689 if (!(np
->vlanctl_bits
& NVREG_VLANCONTROL_ENABLE
))
3690 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_RXCHECK
;
3692 if (netif_running(dev
)) {
3693 spin_lock_irq(&np
->lock
);
3694 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
3695 spin_unlock_irq(&np
->lock
);
3704 static int nv_set_tx_csum(struct net_device
*dev
, u32 data
)
3706 struct fe_priv
*np
= netdev_priv(dev
);
3708 if (np
->driver_data
& DEV_HAS_CHECKSUM
)
3709 return ethtool_op_set_tx_hw_csum(dev
, data
);
3714 static int nv_set_sg(struct net_device
*dev
, u32 data
)
3716 struct fe_priv
*np
= netdev_priv(dev
);
3718 if (np
->driver_data
& DEV_HAS_CHECKSUM
)
3719 return ethtool_op_set_sg(dev
, data
);
3724 static int nv_get_stats_count(struct net_device
*dev
)
3726 struct fe_priv
*np
= netdev_priv(dev
);
3728 if (np
->driver_data
& DEV_HAS_STATISTICS
)
3729 return sizeof(struct nv_ethtool_stats
)/sizeof(u64
);
3734 static void nv_get_ethtool_stats(struct net_device
*dev
, struct ethtool_stats
*estats
, u64
*buffer
)
3736 struct fe_priv
*np
= netdev_priv(dev
);
3739 nv_do_stats_poll((unsigned long)dev
);
3741 memcpy(buffer
, &np
->estats
, nv_get_stats_count(dev
)*sizeof(u64
));
3744 static int nv_self_test_count(struct net_device
*dev
)
3746 struct fe_priv
*np
= netdev_priv(dev
);
3748 if (np
->driver_data
& DEV_HAS_TEST_EXTENDED
)
3749 return NV_TEST_COUNT_EXTENDED
;
3751 return NV_TEST_COUNT_BASE
;
3754 static int nv_link_test(struct net_device
*dev
)
3756 struct fe_priv
*np
= netdev_priv(dev
);
3759 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3760 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3762 /* check phy link status */
3763 if (!(mii_status
& BMSR_LSTATUS
))
3769 static int nv_register_test(struct net_device
*dev
)
3771 u8 __iomem
*base
= get_hwbase(dev
);
3773 u32 orig_read
, new_read
;
3776 orig_read
= readl(base
+ nv_registers_test
[i
].reg
);
3778 /* xor with mask to toggle bits */
3779 orig_read
^= nv_registers_test
[i
].mask
;
3781 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
3783 new_read
= readl(base
+ nv_registers_test
[i
].reg
);
3785 if ((new_read
& nv_registers_test
[i
].mask
) != (orig_read
& nv_registers_test
[i
].mask
))
3788 /* restore original value */
3789 orig_read
^= nv_registers_test
[i
].mask
;
3790 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
3792 } while (nv_registers_test
[++i
].reg
!= 0);
3797 static int nv_interrupt_test(struct net_device
*dev
)
3799 struct fe_priv
*np
= netdev_priv(dev
);
3800 u8 __iomem
*base
= get_hwbase(dev
);
3803 u32 save_msi_flags
, save_poll_interval
= 0;
3805 if (netif_running(dev
)) {
3806 /* free current irq */
3808 save_poll_interval
= readl(base
+NvRegPollingInterval
);
3811 /* flag to test interrupt handler */
3814 /* setup test irq */
3815 save_msi_flags
= np
->msi_flags
;
3816 np
->msi_flags
&= ~NV_MSI_X_VECTORS_MASK
;
3817 np
->msi_flags
|= 0x001; /* setup 1 vector */
3818 if (nv_request_irq(dev
, 1))
3821 /* setup timer interrupt */
3822 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
3823 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
3825 nv_enable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
3827 /* wait for at least one interrupt */
3830 spin_lock_irq(&np
->lock
);
3832 /* flag should be set within ISR */
3833 testcnt
= np
->intr_test
;
3837 nv_disable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
3838 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3839 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
3841 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
3843 spin_unlock_irq(&np
->lock
);
3847 np
->msi_flags
= save_msi_flags
;
3849 if (netif_running(dev
)) {
3850 writel(save_poll_interval
, base
+ NvRegPollingInterval
);
3851 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
3852 /* restore original irq */
3853 if (nv_request_irq(dev
, 0))
3860 static int nv_loopback_test(struct net_device
*dev
)
3862 struct fe_priv
*np
= netdev_priv(dev
);
3863 u8 __iomem
*base
= get_hwbase(dev
);
3864 struct sk_buff
*tx_skb
, *rx_skb
;
3865 dma_addr_t test_dma_addr
;
3866 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
3868 int len
, i
, pkt_len
;
3870 u32 filter_flags
= 0;
3871 u32 misc1_flags
= 0;
3874 if (netif_running(dev
)) {
3875 nv_disable_irq(dev
);
3876 filter_flags
= readl(base
+ NvRegPacketFilterFlags
);
3877 misc1_flags
= readl(base
+ NvRegMisc1
);
3882 /* reinit driver view of the rx queue */
3886 /* setup hardware for loopback */
3887 writel(NVREG_MISC1_FORCE
, base
+ NvRegMisc1
);
3888 writel(NVREG_PFF_ALWAYS
| NVREG_PFF_LOOPBACK
, base
+ NvRegPacketFilterFlags
);
3890 /* reinit nic view of the rx queue */
3891 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
3892 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
3893 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
3894 base
+ NvRegRingSizes
);
3897 /* restart rx engine */
3901 /* setup packet for tx */
3902 pkt_len
= ETH_DATA_LEN
;
3903 tx_skb
= dev_alloc_skb(pkt_len
);
3905 printk(KERN_ERR
"dev_alloc_skb() failed during loopback test"
3906 " of %s\n", dev
->name
);
3910 pkt_data
= skb_put(tx_skb
, pkt_len
);
3911 for (i
= 0; i
< pkt_len
; i
++)
3912 pkt_data
[i
] = (u8
)(i
& 0xff);
3913 test_dma_addr
= pci_map_single(np
->pci_dev
, tx_skb
->data
,
3914 tx_skb
->end
-tx_skb
->data
, PCI_DMA_FROMDEVICE
);
3916 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
3917 np
->tx_ring
.orig
[0].buf
= cpu_to_le32(test_dma_addr
);
3918 np
->tx_ring
.orig
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
3920 np
->tx_ring
.ex
[0].bufhigh
= cpu_to_le64(test_dma_addr
) >> 32;
3921 np
->tx_ring
.ex
[0].buflow
= cpu_to_le64(test_dma_addr
) & 0x0FFFFFFFF;
3922 np
->tx_ring
.ex
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
3924 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
3925 pci_push(get_hwbase(dev
));
3929 /* check for rx of the packet */
3930 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
3931 flags
= le32_to_cpu(np
->rx_ring
.orig
[0].flaglen
);
3932 len
= nv_descr_getlength(&np
->rx_ring
.orig
[0], np
->desc_ver
);
3935 flags
= le32_to_cpu(np
->rx_ring
.ex
[0].flaglen
);
3936 len
= nv_descr_getlength_ex(&np
->rx_ring
.ex
[0], np
->desc_ver
);
3939 if (flags
& NV_RX_AVAIL
) {
3941 } else if (np
->desc_ver
== DESC_VER_1
) {
3942 if (flags
& NV_RX_ERROR
)
3945 if (flags
& NV_RX2_ERROR
) {
3951 if (len
!= pkt_len
) {
3953 dprintk(KERN_DEBUG
"%s: loopback len mismatch %d vs %d\n",
3954 dev
->name
, len
, pkt_len
);
3956 rx_skb
= np
->rx_skbuff
[0];
3957 for (i
= 0; i
< pkt_len
; i
++) {
3958 if (rx_skb
->data
[i
] != (u8
)(i
& 0xff)) {
3960 dprintk(KERN_DEBUG
"%s: loopback pattern check failed on byte %d\n",
3967 dprintk(KERN_DEBUG
"%s: loopback - did not receive test packet\n", dev
->name
);
3970 pci_unmap_page(np
->pci_dev
, test_dma_addr
,
3971 tx_skb
->end
-tx_skb
->data
,
3973 dev_kfree_skb_any(tx_skb
);
3979 /* drain rx queue */
3983 if (netif_running(dev
)) {
3984 writel(misc1_flags
, base
+ NvRegMisc1
);
3985 writel(filter_flags
, base
+ NvRegPacketFilterFlags
);
3992 static void nv_self_test(struct net_device
*dev
, struct ethtool_test
*test
, u64
*buffer
)
3994 struct fe_priv
*np
= netdev_priv(dev
);
3995 u8 __iomem
*base
= get_hwbase(dev
);
3997 memset(buffer
, 0, nv_self_test_count(dev
)*sizeof(u64
));
3999 if (!nv_link_test(dev
)) {
4000 test
->flags
|= ETH_TEST_FL_FAILED
;
4004 if (test
->flags
& ETH_TEST_FL_OFFLINE
) {
4005 if (netif_running(dev
)) {
4006 netif_stop_queue(dev
);
4007 netif_poll_disable(dev
);
4008 netif_tx_lock_bh(dev
);
4009 spin_lock_irq(&np
->lock
);
4010 nv_disable_hw_interrupts(dev
, np
->irqmask
);
4011 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
4012 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4014 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
4020 /* drain rx queue */
4023 spin_unlock_irq(&np
->lock
);
4024 netif_tx_unlock_bh(dev
);
4027 if (!nv_register_test(dev
)) {
4028 test
->flags
|= ETH_TEST_FL_FAILED
;
4032 result
= nv_interrupt_test(dev
);
4034 test
->flags
|= ETH_TEST_FL_FAILED
;
4042 if (!nv_loopback_test(dev
)) {
4043 test
->flags
|= ETH_TEST_FL_FAILED
;
4047 if (netif_running(dev
)) {
4048 /* reinit driver view of the rx queue */
4050 if (nv_init_ring(dev
)) {
4051 if (!np
->in_shutdown
)
4052 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4054 /* reinit nic view of the rx queue */
4055 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4056 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4057 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4058 base
+ NvRegRingSizes
);
4060 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4062 /* restart rx engine */
4065 netif_start_queue(dev
);
4066 netif_poll_enable(dev
);
4067 nv_enable_hw_interrupts(dev
, np
->irqmask
);
4072 static void nv_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buffer
)
4074 switch (stringset
) {
4076 memcpy(buffer
, &nv_estats_str
, nv_get_stats_count(dev
)*sizeof(struct nv_ethtool_str
));
4079 memcpy(buffer
, &nv_etests_str
, nv_self_test_count(dev
)*sizeof(struct nv_ethtool_str
));
4084 static const struct ethtool_ops ops
= {
4085 .get_drvinfo
= nv_get_drvinfo
,
4086 .get_link
= ethtool_op_get_link
,
4087 .get_wol
= nv_get_wol
,
4088 .set_wol
= nv_set_wol
,
4089 .get_settings
= nv_get_settings
,
4090 .set_settings
= nv_set_settings
,
4091 .get_regs_len
= nv_get_regs_len
,
4092 .get_regs
= nv_get_regs
,
4093 .nway_reset
= nv_nway_reset
,
4094 .get_perm_addr
= ethtool_op_get_perm_addr
,
4095 .get_tso
= ethtool_op_get_tso
,
4096 .set_tso
= nv_set_tso
,
4097 .get_ringparam
= nv_get_ringparam
,
4098 .set_ringparam
= nv_set_ringparam
,
4099 .get_pauseparam
= nv_get_pauseparam
,
4100 .set_pauseparam
= nv_set_pauseparam
,
4101 .get_rx_csum
= nv_get_rx_csum
,
4102 .set_rx_csum
= nv_set_rx_csum
,
4103 .get_tx_csum
= ethtool_op_get_tx_csum
,
4104 .set_tx_csum
= nv_set_tx_csum
,
4105 .get_sg
= ethtool_op_get_sg
,
4106 .set_sg
= nv_set_sg
,
4107 .get_strings
= nv_get_strings
,
4108 .get_stats_count
= nv_get_stats_count
,
4109 .get_ethtool_stats
= nv_get_ethtool_stats
,
4110 .self_test_count
= nv_self_test_count
,
4111 .self_test
= nv_self_test
,
4114 static void nv_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
4116 struct fe_priv
*np
= get_nvpriv(dev
);
4118 spin_lock_irq(&np
->lock
);
4120 /* save vlan group */
4124 /* enable vlan on MAC */
4125 np
->txrxctl_bits
|= NVREG_TXRXCTL_VLANSTRIP
| NVREG_TXRXCTL_VLANINS
;
4127 /* disable vlan on MAC */
4128 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANSTRIP
;
4129 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANINS
;
4132 writel(np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4134 spin_unlock_irq(&np
->lock
);
4137 static void nv_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
4142 /* The mgmt unit and driver use a semaphore to access the phy during init */
4143 static int nv_mgmt_acquire_sema(struct net_device
*dev
)
4145 u8 __iomem
*base
= get_hwbase(dev
);
4147 u32 tx_ctrl
, mgmt_sema
;
4149 for (i
= 0; i
< 10; i
++) {
4150 mgmt_sema
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_SEMA_MASK
;
4151 if (mgmt_sema
== NVREG_XMITCTL_MGMT_SEMA_FREE
)
4156 if (mgmt_sema
!= NVREG_XMITCTL_MGMT_SEMA_FREE
)
4159 for (i
= 0; i
< 2; i
++) {
4160 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
4161 tx_ctrl
|= NVREG_XMITCTL_HOST_SEMA_ACQ
;
4162 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
4164 /* verify that semaphore was acquired */
4165 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
4166 if (((tx_ctrl
& NVREG_XMITCTL_HOST_SEMA_MASK
) == NVREG_XMITCTL_HOST_SEMA_ACQ
) &&
4167 ((tx_ctrl
& NVREG_XMITCTL_MGMT_SEMA_MASK
) == NVREG_XMITCTL_MGMT_SEMA_FREE
))
4176 static int nv_open(struct net_device
*dev
)
4178 struct fe_priv
*np
= netdev_priv(dev
);
4179 u8 __iomem
*base
= get_hwbase(dev
);
4183 dprintk(KERN_DEBUG
"nv_open: begin\n");
4185 /* erase previous misconfiguration */
4186 if (np
->driver_data
& DEV_HAS_POWER_CNTRL
)
4188 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
4189 writel(0, base
+ NvRegMulticastAddrB
);
4190 writel(0, base
+ NvRegMulticastMaskA
);
4191 writel(0, base
+ NvRegMulticastMaskB
);
4192 writel(0, base
+ NvRegPacketFilterFlags
);
4194 writel(0, base
+ NvRegTransmitterControl
);
4195 writel(0, base
+ NvRegReceiverControl
);
4197 writel(0, base
+ NvRegAdapterControl
);
4199 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)
4200 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
4202 /* initialize descriptor rings */
4204 oom
= nv_init_ring(dev
);
4206 writel(0, base
+ NvRegLinkSpeed
);
4207 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
4209 writel(0, base
+ NvRegUnknownSetupReg6
);
4211 np
->in_shutdown
= 0;
4214 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4215 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4216 base
+ NvRegRingSizes
);
4218 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
4219 if (np
->desc_ver
== DESC_VER_1
)
4220 writel(NVREG_TX_WM_DESC1_DEFAULT
, base
+ NvRegTxWatermark
);
4222 writel(NVREG_TX_WM_DESC2_3_DEFAULT
, base
+ NvRegTxWatermark
);
4223 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
4224 writel(np
->vlanctl_bits
, base
+ NvRegVlanControl
);
4226 writel(NVREG_TXRXCTL_BIT1
|np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
4227 reg_delay(dev
, NvRegUnknownSetupReg5
, NVREG_UNKSETUP5_BIT31
, NVREG_UNKSETUP5_BIT31
,
4228 NV_SETUP5_DELAY
, NV_SETUP5_DELAYMAX
,
4229 KERN_INFO
"open: SetupReg5, Bit 31 remained off\n");
4231 writel(0, base
+ NvRegMIIMask
);
4232 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4233 writel(NVREG_MIISTAT_MASK2
, base
+ NvRegMIIStatus
);
4235 writel(NVREG_MISC1_FORCE
| NVREG_MISC1_HD
, base
+ NvRegMisc1
);
4236 writel(readl(base
+ NvRegTransmitterStatus
), base
+ NvRegTransmitterStatus
);
4237 writel(NVREG_PFF_ALWAYS
, base
+ NvRegPacketFilterFlags
);
4238 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4240 writel(readl(base
+ NvRegReceiverStatus
), base
+ NvRegReceiverStatus
);
4241 get_random_bytes(&i
, sizeof(i
));
4242 writel(NVREG_RNDSEED_FORCE
| (i
&NVREG_RNDSEED_MASK
), base
+ NvRegRandomSeed
);
4243 writel(NVREG_TX_DEFERRAL_DEFAULT
, base
+ NvRegTxDeferral
);
4244 writel(NVREG_RX_DEFERRAL_DEFAULT
, base
+ NvRegRxDeferral
);
4245 if (poll_interval
== -1) {
4246 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
)
4247 writel(NVREG_POLL_DEFAULT_THROUGHPUT
, base
+ NvRegPollingInterval
);
4249 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
4252 writel(poll_interval
& 0xFFFF, base
+ NvRegPollingInterval
);
4253 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
4254 writel((np
->phyaddr
<< NVREG_ADAPTCTL_PHYSHIFT
)|NVREG_ADAPTCTL_PHYVALID
|NVREG_ADAPTCTL_RUNNING
,
4255 base
+ NvRegAdapterControl
);
4256 writel(NVREG_MIISPEED_BIT8
|NVREG_MIIDELAY
, base
+ NvRegMIISpeed
);
4257 writel(NVREG_MII_LINKCHANGE
, base
+ NvRegMIIMask
);
4259 writel(NVREG_WAKEUPFLAGS_ENABLE
, base
+ NvRegWakeUpFlags
);
4261 i
= readl(base
+ NvRegPowerState
);
4262 if ( (i
& NVREG_POWERSTATE_POWEREDUP
) == 0)
4263 writel(NVREG_POWERSTATE_POWEREDUP
|i
, base
+ NvRegPowerState
);
4267 writel(readl(base
+ NvRegPowerState
) | NVREG_POWERSTATE_VALID
, base
+ NvRegPowerState
);
4269 nv_disable_hw_interrupts(dev
, np
->irqmask
);
4271 writel(NVREG_MIISTAT_MASK2
, base
+ NvRegMIIStatus
);
4272 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4275 if (nv_request_irq(dev
, 0)) {
4279 /* ask for interrupts */
4280 nv_enable_hw_interrupts(dev
, np
->irqmask
);
4282 spin_lock_irq(&np
->lock
);
4283 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
4284 writel(0, base
+ NvRegMulticastAddrB
);
4285 writel(0, base
+ NvRegMulticastMaskA
);
4286 writel(0, base
+ NvRegMulticastMaskB
);
4287 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
4288 /* One manual link speed update: Interrupts are enabled, future link
4289 * speed changes cause interrupts and are handled by nv_link_irq().
4293 miistat
= readl(base
+ NvRegMIIStatus
);
4294 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
4295 dprintk(KERN_INFO
"startup: got 0x%08x.\n", miistat
);
4297 /* set linkspeed to invalid value, thus force nv_update_linkspeed
4300 ret
= nv_update_linkspeed(dev
);
4303 netif_start_queue(dev
);
4304 netif_poll_enable(dev
);
4307 netif_carrier_on(dev
);
4309 printk("%s: no link during initialization.\n", dev
->name
);
4310 netif_carrier_off(dev
);
4313 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4315 /* start statistics timer */
4316 if (np
->driver_data
& DEV_HAS_STATISTICS
)
4317 mod_timer(&np
->stats_poll
, jiffies
+ STATS_INTERVAL
);
4319 spin_unlock_irq(&np
->lock
);
4327 static int nv_close(struct net_device
*dev
)
4329 struct fe_priv
*np
= netdev_priv(dev
);
4332 spin_lock_irq(&np
->lock
);
4333 np
->in_shutdown
= 1;
4334 spin_unlock_irq(&np
->lock
);
4335 netif_poll_disable(dev
);
4336 synchronize_irq(dev
->irq
);
4338 del_timer_sync(&np
->oom_kick
);
4339 del_timer_sync(&np
->nic_poll
);
4340 del_timer_sync(&np
->stats_poll
);
4342 netif_stop_queue(dev
);
4343 spin_lock_irq(&np
->lock
);
4348 /* disable interrupts on the nic or we will lock up */
4349 base
= get_hwbase(dev
);
4350 nv_disable_hw_interrupts(dev
, np
->irqmask
);
4352 dprintk(KERN_INFO
"%s: Irqmask is zero again\n", dev
->name
);
4354 spin_unlock_irq(&np
->lock
);
4363 /* FIXME: power down nic */
4368 static int __devinit
nv_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
4370 struct net_device
*dev
;
4375 u32 powerstate
, txreg
;
4376 u32 phystate_orig
= 0, phystate
;
4377 int phyinitialized
= 0;
4379 dev
= alloc_etherdev(sizeof(struct fe_priv
));
4384 np
= netdev_priv(dev
);
4385 np
->pci_dev
= pci_dev
;
4386 spin_lock_init(&np
->lock
);
4387 SET_MODULE_OWNER(dev
);
4388 SET_NETDEV_DEV(dev
, &pci_dev
->dev
);
4390 init_timer(&np
->oom_kick
);
4391 np
->oom_kick
.data
= (unsigned long) dev
;
4392 np
->oom_kick
.function
= &nv_do_rx_refill
; /* timer handler */
4393 init_timer(&np
->nic_poll
);
4394 np
->nic_poll
.data
= (unsigned long) dev
;
4395 np
->nic_poll
.function
= &nv_do_nic_poll
; /* timer handler */
4396 init_timer(&np
->stats_poll
);
4397 np
->stats_poll
.data
= (unsigned long) dev
;
4398 np
->stats_poll
.function
= &nv_do_stats_poll
; /* timer handler */
4400 err
= pci_enable_device(pci_dev
);
4402 printk(KERN_INFO
"forcedeth: pci_enable_dev failed (%d) for device %s\n",
4403 err
, pci_name(pci_dev
));
4407 pci_set_master(pci_dev
);
4409 err
= pci_request_regions(pci_dev
, DRV_NAME
);
4413 if (id
->driver_data
& (DEV_HAS_VLAN
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS
))
4414 np
->register_size
= NV_PCI_REGSZ_VER2
;
4416 np
->register_size
= NV_PCI_REGSZ_VER1
;
4420 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
4421 dprintk(KERN_DEBUG
"%s: resource %d start %p len %ld flags 0x%08lx.\n",
4422 pci_name(pci_dev
), i
, (void*)pci_resource_start(pci_dev
, i
),
4423 pci_resource_len(pci_dev
, i
),
4424 pci_resource_flags(pci_dev
, i
));
4425 if (pci_resource_flags(pci_dev
, i
) & IORESOURCE_MEM
&&
4426 pci_resource_len(pci_dev
, i
) >= np
->register_size
) {
4427 addr
= pci_resource_start(pci_dev
, i
);
4431 if (i
== DEVICE_COUNT_RESOURCE
) {
4432 printk(KERN_INFO
"forcedeth: Couldn't find register window for device %s.\n",
4437 /* copy of driver data */
4438 np
->driver_data
= id
->driver_data
;
4440 /* handle different descriptor versions */
4441 if (id
->driver_data
& DEV_HAS_HIGH_DMA
) {
4442 /* packet format 3: supports 40-bit addressing */
4443 np
->desc_ver
= DESC_VER_3
;
4444 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_3
;
4446 if (pci_set_dma_mask(pci_dev
, DMA_39BIT_MASK
)) {
4447 printk(KERN_INFO
"forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4450 dev
->features
|= NETIF_F_HIGHDMA
;
4451 printk(KERN_INFO
"forcedeth: using HIGHDMA\n");
4453 if (pci_set_consistent_dma_mask(pci_dev
, DMA_39BIT_MASK
)) {
4454 printk(KERN_INFO
"forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4458 } else if (id
->driver_data
& DEV_HAS_LARGEDESC
) {
4459 /* packet format 2: supports jumbo frames */
4460 np
->desc_ver
= DESC_VER_2
;
4461 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_2
;
4463 /* original packet format */
4464 np
->desc_ver
= DESC_VER_1
;
4465 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_1
;
4468 np
->pkt_limit
= NV_PKTLIMIT_1
;
4469 if (id
->driver_data
& DEV_HAS_LARGEDESC
)
4470 np
->pkt_limit
= NV_PKTLIMIT_2
;
4472 if (id
->driver_data
& DEV_HAS_CHECKSUM
) {
4474 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
4475 dev
->features
|= NETIF_F_HW_CSUM
| NETIF_F_SG
;
4476 dev
->features
|= NETIF_F_TSO
;
4479 np
->vlanctl_bits
= 0;
4480 if (id
->driver_data
& DEV_HAS_VLAN
) {
4481 np
->vlanctl_bits
= NVREG_VLANCONTROL_ENABLE
;
4482 dev
->features
|= NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
;
4483 dev
->vlan_rx_register
= nv_vlan_rx_register
;
4484 dev
->vlan_rx_kill_vid
= nv_vlan_rx_kill_vid
;
4488 if ((id
->driver_data
& DEV_HAS_MSI
) && msi
) {
4489 np
->msi_flags
|= NV_MSI_CAPABLE
;
4491 if ((id
->driver_data
& DEV_HAS_MSI_X
) && msix
) {
4492 np
->msi_flags
|= NV_MSI_X_CAPABLE
;
4495 np
->pause_flags
= NV_PAUSEFRAME_RX_CAPABLE
| NV_PAUSEFRAME_RX_REQ
| NV_PAUSEFRAME_AUTONEG
;
4496 if (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX
) {
4497 np
->pause_flags
|= NV_PAUSEFRAME_TX_CAPABLE
| NV_PAUSEFRAME_TX_REQ
;
4502 np
->base
= ioremap(addr
, np
->register_size
);
4505 dev
->base_addr
= (unsigned long)np
->base
;
4507 dev
->irq
= pci_dev
->irq
;
4509 np
->rx_ring_size
= RX_RING_DEFAULT
;
4510 np
->tx_ring_size
= TX_RING_DEFAULT
;
4511 np
->tx_limit_stop
= np
->tx_ring_size
- TX_LIMIT_DIFFERENCE
;
4512 np
->tx_limit_start
= np
->tx_ring_size
- TX_LIMIT_DIFFERENCE
- 1;
4514 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
4515 np
->rx_ring
.orig
= pci_alloc_consistent(pci_dev
,
4516 sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
4518 if (!np
->rx_ring
.orig
)
4520 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
4522 np
->rx_ring
.ex
= pci_alloc_consistent(pci_dev
,
4523 sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
4525 if (!np
->rx_ring
.ex
)
4527 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
4529 np
->rx_skbuff
= kmalloc(sizeof(struct sk_buff
*) * np
->rx_ring_size
, GFP_KERNEL
);
4530 np
->rx_dma
= kmalloc(sizeof(dma_addr_t
) * np
->rx_ring_size
, GFP_KERNEL
);
4531 np
->tx_skbuff
= kmalloc(sizeof(struct sk_buff
*) * np
->tx_ring_size
, GFP_KERNEL
);
4532 np
->tx_dma
= kmalloc(sizeof(dma_addr_t
) * np
->tx_ring_size
, GFP_KERNEL
);
4533 np
->tx_dma_len
= kmalloc(sizeof(unsigned int) * np
->tx_ring_size
, GFP_KERNEL
);
4534 if (!np
->rx_skbuff
|| !np
->rx_dma
|| !np
->tx_skbuff
|| !np
->tx_dma
|| !np
->tx_dma_len
)
4536 memset(np
->rx_skbuff
, 0, sizeof(struct sk_buff
*) * np
->rx_ring_size
);
4537 memset(np
->rx_dma
, 0, sizeof(dma_addr_t
) * np
->rx_ring_size
);
4538 memset(np
->tx_skbuff
, 0, sizeof(struct sk_buff
*) * np
->tx_ring_size
);
4539 memset(np
->tx_dma
, 0, sizeof(dma_addr_t
) * np
->tx_ring_size
);
4540 memset(np
->tx_dma_len
, 0, sizeof(unsigned int) * np
->tx_ring_size
);
4542 dev
->open
= nv_open
;
4543 dev
->stop
= nv_close
;
4544 dev
->hard_start_xmit
= nv_start_xmit
;
4545 dev
->get_stats
= nv_get_stats
;
4546 dev
->change_mtu
= nv_change_mtu
;
4547 dev
->set_mac_address
= nv_set_mac_address
;
4548 dev
->set_multicast_list
= nv_set_multicast
;
4549 #ifdef CONFIG_NET_POLL_CONTROLLER
4550 dev
->poll_controller
= nv_poll_controller
;
4553 #ifdef CONFIG_FORCEDETH_NAPI
4554 dev
->poll
= nv_napi_poll
;
4556 SET_ETHTOOL_OPS(dev
, &ops
);
4557 dev
->tx_timeout
= nv_tx_timeout
;
4558 dev
->watchdog_timeo
= NV_WATCHDOG_TIMEO
;
4560 pci_set_drvdata(pci_dev
, dev
);
4562 /* read the mac address */
4563 base
= get_hwbase(dev
);
4564 np
->orig_mac
[0] = readl(base
+ NvRegMacAddrA
);
4565 np
->orig_mac
[1] = readl(base
+ NvRegMacAddrB
);
4567 /* check the workaround bit for correct mac address order */
4568 txreg
= readl(base
+ NvRegTransmitPoll
);
4569 if (txreg
& NVREG_TRANSMITPOLL_MAC_ADDR_REV
) {
4570 /* mac address is already in correct order */
4571 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
4572 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
4573 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
4574 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
4575 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
4576 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
4578 /* need to reverse mac address to correct order */
4579 dev
->dev_addr
[0] = (np
->orig_mac
[1] >> 8) & 0xff;
4580 dev
->dev_addr
[1] = (np
->orig_mac
[1] >> 0) & 0xff;
4581 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 24) & 0xff;
4582 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 16) & 0xff;
4583 dev
->dev_addr
[4] = (np
->orig_mac
[0] >> 8) & 0xff;
4584 dev
->dev_addr
[5] = (np
->orig_mac
[0] >> 0) & 0xff;
4585 /* set permanent address to be correct aswell */
4586 np
->orig_mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
4587 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
4588 np
->orig_mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
4589 writel(txreg
|NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
4591 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
4593 if (!is_valid_ether_addr(dev
->perm_addr
)) {
4595 * Bad mac address. At least one bios sets the mac address
4596 * to 01:23:45:67:89:ab
4598 printk(KERN_ERR
"%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4600 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
4601 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
4602 printk(KERN_ERR
"Please complain to your hardware vendor. Switching to a random MAC.\n");
4603 dev
->dev_addr
[0] = 0x00;
4604 dev
->dev_addr
[1] = 0x00;
4605 dev
->dev_addr
[2] = 0x6c;
4606 get_random_bytes(&dev
->dev_addr
[3], 3);
4609 dprintk(KERN_DEBUG
"%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev
),
4610 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
4611 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
4613 /* set mac address */
4614 nv_copy_mac_to_hw(dev
);
4617 writel(0, base
+ NvRegWakeUpFlags
);
4620 if (id
->driver_data
& DEV_HAS_POWER_CNTRL
) {
4622 pci_read_config_byte(pci_dev
, PCI_REVISION_ID
, &revision_id
);
4624 /* take phy and nic out of low power mode */
4625 powerstate
= readl(base
+ NvRegPowerState2
);
4626 powerstate
&= ~NVREG_POWERSTATE2_POWERUP_MASK
;
4627 if ((id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_12
||
4628 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_13
) &&
4629 revision_id
>= 0xA3)
4630 powerstate
|= NVREG_POWERSTATE2_POWERUP_REV_A3
;
4631 writel(powerstate
, base
+ NvRegPowerState2
);
4634 if (np
->desc_ver
== DESC_VER_1
) {
4635 np
->tx_flags
= NV_TX_VALID
;
4637 np
->tx_flags
= NV_TX2_VALID
;
4639 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
) {
4640 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
4641 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
4642 np
->msi_flags
|= 0x0003;
4644 np
->irqmask
= NVREG_IRQMASK_CPU
;
4645 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
4646 np
->msi_flags
|= 0x0001;
4649 if (id
->driver_data
& DEV_NEED_TIMERIRQ
)
4650 np
->irqmask
|= NVREG_IRQ_TIMER
;
4651 if (id
->driver_data
& DEV_NEED_LINKTIMER
) {
4652 dprintk(KERN_INFO
"%s: link timer on.\n", pci_name(pci_dev
));
4653 np
->need_linktimer
= 1;
4654 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
4656 dprintk(KERN_INFO
"%s: link timer off.\n", pci_name(pci_dev
));
4657 np
->need_linktimer
= 0;
4660 /* clear phy state and temporarily halt phy interrupts */
4661 writel(0, base
+ NvRegMIIMask
);
4662 phystate
= readl(base
+ NvRegAdapterControl
);
4663 if (phystate
& NVREG_ADAPTCTL_RUNNING
) {
4665 phystate
&= ~NVREG_ADAPTCTL_RUNNING
;
4666 writel(phystate
, base
+ NvRegAdapterControl
);
4668 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
4670 if (id
->driver_data
& DEV_HAS_MGMT_UNIT
) {
4671 /* management unit running on the mac? */
4672 if (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_PHY_INIT
) {
4673 np
->mac_in_use
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_ST
;
4674 dprintk(KERN_INFO
"%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev
), np
->mac_in_use
);
4675 for (i
= 0; i
< 5000; i
++) {
4677 if (nv_mgmt_acquire_sema(dev
)) {
4678 /* management unit setup the phy already? */
4679 if ((readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_MASK
) ==
4680 NVREG_XMITCTL_SYNC_PHY_INIT
) {
4681 /* phy is inited by mgmt unit */
4683 dprintk(KERN_INFO
"%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev
));
4685 /* we need to init the phy */
4693 /* find a suitable phy */
4694 for (i
= 1; i
<= 32; i
++) {
4696 int phyaddr
= i
& 0x1F;
4698 spin_lock_irq(&np
->lock
);
4699 id1
= mii_rw(dev
, phyaddr
, MII_PHYSID1
, MII_READ
);
4700 spin_unlock_irq(&np
->lock
);
4701 if (id1
< 0 || id1
== 0xffff)
4703 spin_lock_irq(&np
->lock
);
4704 id2
= mii_rw(dev
, phyaddr
, MII_PHYSID2
, MII_READ
);
4705 spin_unlock_irq(&np
->lock
);
4706 if (id2
< 0 || id2
== 0xffff)
4709 np
->phy_model
= id2
& PHYID2_MODEL_MASK
;
4710 id1
= (id1
& PHYID1_OUI_MASK
) << PHYID1_OUI_SHFT
;
4711 id2
= (id2
& PHYID2_OUI_MASK
) >> PHYID2_OUI_SHFT
;
4712 dprintk(KERN_DEBUG
"%s: open: Found PHY %04x:%04x at address %d.\n",
4713 pci_name(pci_dev
), id1
, id2
, phyaddr
);
4714 np
->phyaddr
= phyaddr
;
4715 np
->phy_oui
= id1
| id2
;
4719 printk(KERN_INFO
"%s: open: Could not find a valid PHY.\n",
4724 if (!phyinitialized
) {
4728 /* see if it is a gigabit phy */
4729 u32 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4730 if (mii_status
& PHY_GIGABIT
) {
4731 np
->gigabit
= PHY_GIGABIT
;
4735 /* set default link speed settings */
4736 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
4740 err
= register_netdev(dev
);
4742 printk(KERN_INFO
"forcedeth: unable to register netdev: %d\n", err
);
4745 printk(KERN_INFO
"%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4746 dev
->name
, pci_dev
->subsystem_vendor
, pci_dev
->subsystem_device
,
4753 writel(phystate
|NVREG_ADAPTCTL_RUNNING
, base
+ NvRegAdapterControl
);
4754 pci_set_drvdata(pci_dev
, NULL
);
4758 iounmap(get_hwbase(dev
));
4760 pci_release_regions(pci_dev
);
4762 pci_disable_device(pci_dev
);
4769 static void __devexit
nv_remove(struct pci_dev
*pci_dev
)
4771 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
4772 struct fe_priv
*np
= netdev_priv(dev
);
4773 u8 __iomem
*base
= get_hwbase(dev
);
4775 unregister_netdev(dev
);
4777 /* special op: write back the misordered MAC address - otherwise
4778 * the next nv_probe would see a wrong address.
4780 writel(np
->orig_mac
[0], base
+ NvRegMacAddrA
);
4781 writel(np
->orig_mac
[1], base
+ NvRegMacAddrB
);
4783 /* free all structures */
4785 iounmap(get_hwbase(dev
));
4786 pci_release_regions(pci_dev
);
4787 pci_disable_device(pci_dev
);
4789 pci_set_drvdata(pci_dev
, NULL
);
4793 static int nv_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4795 struct net_device
*dev
= pci_get_drvdata(pdev
);
4796 struct fe_priv
*np
= netdev_priv(dev
);
4798 if (!netif_running(dev
))
4801 netif_device_detach(dev
);
4806 pci_save_state(pdev
);
4807 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), np
->wolenabled
);
4808 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
4813 static int nv_resume(struct pci_dev
*pdev
)
4815 struct net_device
*dev
= pci_get_drvdata(pdev
);
4818 if (!netif_running(dev
))
4821 netif_device_attach(dev
);
4823 pci_set_power_state(pdev
, PCI_D0
);
4824 pci_restore_state(pdev
);
4825 pci_enable_wake(pdev
, PCI_D0
, 0);
4832 #define nv_suspend NULL
4833 #define nv_resume NULL
4834 #endif /* CONFIG_PM */
4836 static struct pci_device_id pci_tbl
[] = {
4837 { /* nForce Ethernet Controller */
4838 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_1
),
4839 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
4841 { /* nForce2 Ethernet Controller */
4842 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_2
),
4843 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
4845 { /* nForce3 Ethernet Controller */
4846 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_3
),
4847 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
4849 { /* nForce3 Ethernet Controller */
4850 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_4
),
4851 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
4853 { /* nForce3 Ethernet Controller */
4854 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_5
),
4855 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
4857 { /* nForce3 Ethernet Controller */
4858 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_6
),
4859 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
4861 { /* nForce3 Ethernet Controller */
4862 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_7
),
4863 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
4865 { /* CK804 Ethernet Controller */
4866 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_8
),
4867 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
4869 { /* CK804 Ethernet Controller */
4870 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_9
),
4871 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
4873 { /* MCP04 Ethernet Controller */
4874 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_10
),
4875 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
4877 { /* MCP04 Ethernet Controller */
4878 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_11
),
4879 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
4881 { /* MCP51 Ethernet Controller */
4882 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_12
),
4883 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
,
4885 { /* MCP51 Ethernet Controller */
4886 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_13
),
4887 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
,
4889 { /* MCP55 Ethernet Controller */
4890 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_14
),
4891 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
,
4893 { /* MCP55 Ethernet Controller */
4894 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_15
),
4895 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
,
4897 { /* MCP61 Ethernet Controller */
4898 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_16
),
4899 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
,
4901 { /* MCP61 Ethernet Controller */
4902 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_17
),
4903 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
,
4905 { /* MCP61 Ethernet Controller */
4906 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_18
),
4907 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
,
4909 { /* MCP61 Ethernet Controller */
4910 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_19
),
4911 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
,
4913 { /* MCP65 Ethernet Controller */
4914 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_20
),
4915 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
,
4917 { /* MCP65 Ethernet Controller */
4918 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_21
),
4919 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
,
4921 { /* MCP65 Ethernet Controller */
4922 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_22
),
4923 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
,
4925 { /* MCP65 Ethernet Controller */
4926 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_23
),
4927 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
,
4929 { /* MCP67 Ethernet Controller */
4930 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_24
),
4931 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
,
4933 { /* MCP67 Ethernet Controller */
4934 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_25
),
4935 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
,
4937 { /* MCP67 Ethernet Controller */
4938 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_26
),
4939 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
,
4941 { /* MCP67 Ethernet Controller */
4942 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_27
),
4943 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX
|DEV_HAS_STATISTICS
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
,
4948 static struct pci_driver driver
= {
4949 .name
= "forcedeth",
4950 .id_table
= pci_tbl
,
4952 .remove
= __devexit_p(nv_remove
),
4953 .suspend
= nv_suspend
,
4954 .resume
= nv_resume
,
4957 static int __init
init_nic(void)
4959 printk(KERN_INFO
"forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION
);
4960 return pci_register_driver(&driver
);
4963 static void __exit
exit_nic(void)
4965 pci_unregister_driver(&driver
);
4968 module_param(max_interrupt_work
, int, 0);
4969 MODULE_PARM_DESC(max_interrupt_work
, "forcedeth maximum events handled per interrupt");
4970 module_param(optimization_mode
, int, 0);
4971 MODULE_PARM_DESC(optimization_mode
, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
4972 module_param(poll_interval
, int, 0);
4973 MODULE_PARM_DESC(poll_interval
, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
4974 module_param(msi
, int, 0);
4975 MODULE_PARM_DESC(msi
, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
4976 module_param(msix
, int, 0);
4977 MODULE_PARM_DESC(msix
, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
4978 module_param(dma_64bit
, int, 0);
4979 MODULE_PARM_DESC(dma_64bit
, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
4981 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4982 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4983 MODULE_LICENSE("GPL");
4985 MODULE_DEVICE_TABLE(pci
, pci_tbl
);
4987 module_init(init_nic
);
4988 module_exit(exit_nic
);