2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
42 #define FORCEDETH_VERSION "0.61"
43 #define DRV_NAME "forcedeth"
45 #include <linux/module.h>
46 #include <linux/types.h>
47 #include <linux/pci.h>
48 #include <linux/interrupt.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/delay.h>
52 #include <linux/spinlock.h>
53 #include <linux/ethtool.h>
54 #include <linux/timer.h>
55 #include <linux/skbuff.h>
56 #include <linux/mii.h>
57 #include <linux/random.h>
58 #include <linux/init.h>
59 #include <linux/if_vlan.h>
60 #include <linux/dma-mapping.h>
64 #include <asm/uaccess.h>
65 #include <asm/system.h>
68 #define dprintk printk
70 #define dprintk(x...) do { } while (0)
73 #define TX_WORK_PER_LOOP 64
74 #define RX_WORK_PER_LOOP 64
80 #define DEV_NEED_TIMERIRQ 0x00001 /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER 0x00002 /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC 0x00004 /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA 0x00008 /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM 0x00010 /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN 0x00020 /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI 0x00040 /* device supports MSI */
87 #define DEV_HAS_MSI_X 0x00080 /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL 0x00100 /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1 0x00200 /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2 0x00400 /* device supports hw statistics version 2 */
91 #define DEV_HAS_TEST_EXTENDED 0x00800 /* device supports extended diagnostic test */
92 #define DEV_HAS_MGMT_UNIT 0x01000 /* device supports management unit */
93 #define DEV_HAS_CORRECT_MACADDR 0x02000 /* device supports correct mac address order */
94 #define DEV_HAS_COLLISION_FIX 0x04000 /* device supports tx collision fix */
95 #define DEV_HAS_PAUSEFRAME_TX_V1 0x08000 /* device supports tx pause frames version 1 */
96 #define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */
97 #define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */
98 #define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */
99 #define DEV_HAS_GEAR_MODE 0x80000 /* device supports gear mode */
102 NvRegIrqStatus
= 0x000,
103 #define NVREG_IRQSTAT_MIIEVENT 0x040
104 #define NVREG_IRQSTAT_MASK 0x81ff
105 NvRegIrqMask
= 0x004,
106 #define NVREG_IRQ_RX_ERROR 0x0001
107 #define NVREG_IRQ_RX 0x0002
108 #define NVREG_IRQ_RX_NOBUF 0x0004
109 #define NVREG_IRQ_TX_ERR 0x0008
110 #define NVREG_IRQ_TX_OK 0x0010
111 #define NVREG_IRQ_TIMER 0x0020
112 #define NVREG_IRQ_LINK 0x0040
113 #define NVREG_IRQ_RX_FORCED 0x0080
114 #define NVREG_IRQ_TX_FORCED 0x0100
115 #define NVREG_IRQ_RECOVER_ERROR 0x8000
116 #define NVREG_IRQMASK_THROUGHPUT 0x00df
117 #define NVREG_IRQMASK_CPU 0x0060
118 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
119 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
120 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
122 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
123 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
124 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
126 NvRegUnknownSetupReg6
= 0x008,
127 #define NVREG_UNKSETUP6_VAL 3
130 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
131 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
133 NvRegPollingInterval
= 0x00c,
134 #define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */
135 #define NVREG_POLL_DEFAULT_CPU 13
136 NvRegMSIMap0
= 0x020,
137 NvRegMSIMap1
= 0x024,
138 NvRegMSIIrqMask
= 0x030,
139 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
141 #define NVREG_MISC1_PAUSE_TX 0x01
142 #define NVREG_MISC1_HD 0x02
143 #define NVREG_MISC1_FORCE 0x3b0f3c
145 NvRegMacReset
= 0x34,
146 #define NVREG_MAC_RESET_ASSERT 0x0F3
147 NvRegTransmitterControl
= 0x084,
148 #define NVREG_XMITCTL_START 0x01
149 #define NVREG_XMITCTL_MGMT_ST 0x40000000
150 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
151 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
152 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
153 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
154 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
155 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
156 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
157 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
158 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
159 NvRegTransmitterStatus
= 0x088,
160 #define NVREG_XMITSTAT_BUSY 0x01
162 NvRegPacketFilterFlags
= 0x8c,
163 #define NVREG_PFF_PAUSE_RX 0x08
164 #define NVREG_PFF_ALWAYS 0x7F0000
165 #define NVREG_PFF_PROMISC 0x80
166 #define NVREG_PFF_MYADDR 0x20
167 #define NVREG_PFF_LOOPBACK 0x10
169 NvRegOffloadConfig
= 0x90,
170 #define NVREG_OFFLOAD_HOMEPHY 0x601
171 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
172 NvRegReceiverControl
= 0x094,
173 #define NVREG_RCVCTL_START 0x01
174 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
175 NvRegReceiverStatus
= 0x98,
176 #define NVREG_RCVSTAT_BUSY 0x01
178 NvRegSlotTime
= 0x9c,
179 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
180 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
181 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
182 #define NVREG_SLOTTIME_HALF 0x0000ff00
183 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
184 #define NVREG_SLOTTIME_MASK 0x000000ff
186 NvRegTxDeferral
= 0xA0,
187 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
188 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
189 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
190 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
191 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
192 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
193 NvRegRxDeferral
= 0xA4,
194 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
195 NvRegMacAddrA
= 0xA8,
196 NvRegMacAddrB
= 0xAC,
197 NvRegMulticastAddrA
= 0xB0,
198 #define NVREG_MCASTADDRA_FORCE 0x01
199 NvRegMulticastAddrB
= 0xB4,
200 NvRegMulticastMaskA
= 0xB8,
201 #define NVREG_MCASTMASKA_NONE 0xffffffff
202 NvRegMulticastMaskB
= 0xBC,
203 #define NVREG_MCASTMASKB_NONE 0xffff
205 NvRegPhyInterface
= 0xC0,
206 #define PHY_RGMII 0x10000000
207 NvRegBackOffControl
= 0xC4,
208 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
209 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
210 #define NVREG_BKOFFCTRL_SELECT 24
211 #define NVREG_BKOFFCTRL_GEAR 12
213 NvRegTxRingPhysAddr
= 0x100,
214 NvRegRxRingPhysAddr
= 0x104,
215 NvRegRingSizes
= 0x108,
216 #define NVREG_RINGSZ_TXSHIFT 0
217 #define NVREG_RINGSZ_RXSHIFT 16
218 NvRegTransmitPoll
= 0x10c,
219 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
220 NvRegLinkSpeed
= 0x110,
221 #define NVREG_LINKSPEED_FORCE 0x10000
222 #define NVREG_LINKSPEED_10 1000
223 #define NVREG_LINKSPEED_100 100
224 #define NVREG_LINKSPEED_1000 50
225 #define NVREG_LINKSPEED_MASK (0xFFF)
226 NvRegUnknownSetupReg5
= 0x130,
227 #define NVREG_UNKSETUP5_BIT31 (1<<31)
228 NvRegTxWatermark
= 0x13c,
229 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
230 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
231 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
232 NvRegTxRxControl
= 0x144,
233 #define NVREG_TXRXCTL_KICK 0x0001
234 #define NVREG_TXRXCTL_BIT1 0x0002
235 #define NVREG_TXRXCTL_BIT2 0x0004
236 #define NVREG_TXRXCTL_IDLE 0x0008
237 #define NVREG_TXRXCTL_RESET 0x0010
238 #define NVREG_TXRXCTL_RXCHECK 0x0400
239 #define NVREG_TXRXCTL_DESC_1 0
240 #define NVREG_TXRXCTL_DESC_2 0x002100
241 #define NVREG_TXRXCTL_DESC_3 0xc02200
242 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
243 #define NVREG_TXRXCTL_VLANINS 0x00080
244 NvRegTxRingPhysAddrHigh
= 0x148,
245 NvRegRxRingPhysAddrHigh
= 0x14C,
246 NvRegTxPauseFrame
= 0x170,
247 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
248 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
249 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
250 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
251 NvRegMIIStatus
= 0x180,
252 #define NVREG_MIISTAT_ERROR 0x0001
253 #define NVREG_MIISTAT_LINKCHANGE 0x0008
254 #define NVREG_MIISTAT_MASK_RW 0x0007
255 #define NVREG_MIISTAT_MASK_ALL 0x000f
256 NvRegMIIMask
= 0x184,
257 #define NVREG_MII_LINKCHANGE 0x0008
259 NvRegAdapterControl
= 0x188,
260 #define NVREG_ADAPTCTL_START 0x02
261 #define NVREG_ADAPTCTL_LINKUP 0x04
262 #define NVREG_ADAPTCTL_PHYVALID 0x40000
263 #define NVREG_ADAPTCTL_RUNNING 0x100000
264 #define NVREG_ADAPTCTL_PHYSHIFT 24
265 NvRegMIISpeed
= 0x18c,
266 #define NVREG_MIISPEED_BIT8 (1<<8)
267 #define NVREG_MIIDELAY 5
268 NvRegMIIControl
= 0x190,
269 #define NVREG_MIICTL_INUSE 0x08000
270 #define NVREG_MIICTL_WRITE 0x00400
271 #define NVREG_MIICTL_ADDRSHIFT 5
272 NvRegMIIData
= 0x194,
273 NvRegWakeUpFlags
= 0x200,
274 #define NVREG_WAKEUPFLAGS_VAL 0x7770
275 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
276 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
277 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
278 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
279 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
280 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
281 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
282 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
283 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
284 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
286 NvRegPatternCRC
= 0x204,
287 NvRegPatternMask
= 0x208,
288 NvRegPowerCap
= 0x268,
289 #define NVREG_POWERCAP_D3SUPP (1<<30)
290 #define NVREG_POWERCAP_D2SUPP (1<<26)
291 #define NVREG_POWERCAP_D1SUPP (1<<25)
292 NvRegPowerState
= 0x26c,
293 #define NVREG_POWERSTATE_POWEREDUP 0x8000
294 #define NVREG_POWERSTATE_VALID 0x0100
295 #define NVREG_POWERSTATE_MASK 0x0003
296 #define NVREG_POWERSTATE_D0 0x0000
297 #define NVREG_POWERSTATE_D1 0x0001
298 #define NVREG_POWERSTATE_D2 0x0002
299 #define NVREG_POWERSTATE_D3 0x0003
301 NvRegTxZeroReXmt
= 0x284,
302 NvRegTxOneReXmt
= 0x288,
303 NvRegTxManyReXmt
= 0x28c,
304 NvRegTxLateCol
= 0x290,
305 NvRegTxUnderflow
= 0x294,
306 NvRegTxLossCarrier
= 0x298,
307 NvRegTxExcessDef
= 0x29c,
308 NvRegTxRetryErr
= 0x2a0,
309 NvRegRxFrameErr
= 0x2a4,
310 NvRegRxExtraByte
= 0x2a8,
311 NvRegRxLateCol
= 0x2ac,
313 NvRegRxFrameTooLong
= 0x2b4,
314 NvRegRxOverflow
= 0x2b8,
315 NvRegRxFCSErr
= 0x2bc,
316 NvRegRxFrameAlignErr
= 0x2c0,
317 NvRegRxLenErr
= 0x2c4,
318 NvRegRxUnicast
= 0x2c8,
319 NvRegRxMulticast
= 0x2cc,
320 NvRegRxBroadcast
= 0x2d0,
322 NvRegTxFrame
= 0x2d8,
324 NvRegTxPause
= 0x2e0,
325 NvRegRxPause
= 0x2e4,
326 NvRegRxDropFrame
= 0x2e8,
327 NvRegVlanControl
= 0x300,
328 #define NVREG_VLANCONTROL_ENABLE 0x2000
329 NvRegMSIXMap0
= 0x3e0,
330 NvRegMSIXMap1
= 0x3e4,
331 NvRegMSIXIrqStatus
= 0x3f0,
333 NvRegPowerState2
= 0x600,
334 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
335 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
336 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
339 /* Big endian: should work, but is untested */
345 struct ring_desc_ex
{
353 struct ring_desc
* orig
;
354 struct ring_desc_ex
* ex
;
357 #define FLAG_MASK_V1 0xffff0000
358 #define FLAG_MASK_V2 0xffffc000
359 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
360 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
362 #define NV_TX_LASTPACKET (1<<16)
363 #define NV_TX_RETRYERROR (1<<19)
364 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
365 #define NV_TX_FORCED_INTERRUPT (1<<24)
366 #define NV_TX_DEFERRED (1<<26)
367 #define NV_TX_CARRIERLOST (1<<27)
368 #define NV_TX_LATECOLLISION (1<<28)
369 #define NV_TX_UNDERFLOW (1<<29)
370 #define NV_TX_ERROR (1<<30)
371 #define NV_TX_VALID (1<<31)
373 #define NV_TX2_LASTPACKET (1<<29)
374 #define NV_TX2_RETRYERROR (1<<18)
375 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
376 #define NV_TX2_FORCED_INTERRUPT (1<<30)
377 #define NV_TX2_DEFERRED (1<<25)
378 #define NV_TX2_CARRIERLOST (1<<26)
379 #define NV_TX2_LATECOLLISION (1<<27)
380 #define NV_TX2_UNDERFLOW (1<<28)
381 /* error and valid are the same for both */
382 #define NV_TX2_ERROR (1<<30)
383 #define NV_TX2_VALID (1<<31)
384 #define NV_TX2_TSO (1<<28)
385 #define NV_TX2_TSO_SHIFT 14
386 #define NV_TX2_TSO_MAX_SHIFT 14
387 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
388 #define NV_TX2_CHECKSUM_L3 (1<<27)
389 #define NV_TX2_CHECKSUM_L4 (1<<26)
391 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
393 #define NV_RX_DESCRIPTORVALID (1<<16)
394 #define NV_RX_MISSEDFRAME (1<<17)
395 #define NV_RX_SUBSTRACT1 (1<<18)
396 #define NV_RX_ERROR1 (1<<23)
397 #define NV_RX_ERROR2 (1<<24)
398 #define NV_RX_ERROR3 (1<<25)
399 #define NV_RX_ERROR4 (1<<26)
400 #define NV_RX_CRCERR (1<<27)
401 #define NV_RX_OVERFLOW (1<<28)
402 #define NV_RX_FRAMINGERR (1<<29)
403 #define NV_RX_ERROR (1<<30)
404 #define NV_RX_AVAIL (1<<31)
405 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
407 #define NV_RX2_CHECKSUMMASK (0x1C000000)
408 #define NV_RX2_CHECKSUM_IP (0x10000000)
409 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
410 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
411 #define NV_RX2_DESCRIPTORVALID (1<<29)
412 #define NV_RX2_SUBSTRACT1 (1<<25)
413 #define NV_RX2_ERROR1 (1<<18)
414 #define NV_RX2_ERROR2 (1<<19)
415 #define NV_RX2_ERROR3 (1<<20)
416 #define NV_RX2_ERROR4 (1<<21)
417 #define NV_RX2_CRCERR (1<<22)
418 #define NV_RX2_OVERFLOW (1<<23)
419 #define NV_RX2_FRAMINGERR (1<<24)
420 /* error and avail are the same for both */
421 #define NV_RX2_ERROR (1<<30)
422 #define NV_RX2_AVAIL (1<<31)
423 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
425 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
426 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
428 /* Miscelaneous hardware related defines: */
429 #define NV_PCI_REGSZ_VER1 0x270
430 #define NV_PCI_REGSZ_VER2 0x2d4
431 #define NV_PCI_REGSZ_VER3 0x604
432 #define NV_PCI_REGSZ_MAX 0x604
434 /* various timeout delays: all in usec */
435 #define NV_TXRX_RESET_DELAY 4
436 #define NV_TXSTOP_DELAY1 10
437 #define NV_TXSTOP_DELAY1MAX 500000
438 #define NV_TXSTOP_DELAY2 100
439 #define NV_RXSTOP_DELAY1 10
440 #define NV_RXSTOP_DELAY1MAX 500000
441 #define NV_RXSTOP_DELAY2 100
442 #define NV_SETUP5_DELAY 5
443 #define NV_SETUP5_DELAYMAX 50000
444 #define NV_POWERUP_DELAY 5
445 #define NV_POWERUP_DELAYMAX 5000
446 #define NV_MIIBUSY_DELAY 50
447 #define NV_MIIPHY_DELAY 10
448 #define NV_MIIPHY_DELAYMAX 10000
449 #define NV_MAC_RESET_DELAY 64
451 #define NV_WAKEUPPATTERNS 5
452 #define NV_WAKEUPMASKENTRIES 4
454 /* General driver defaults */
455 #define NV_WATCHDOG_TIMEO (5*HZ)
457 #define RX_RING_DEFAULT 128
458 #define TX_RING_DEFAULT 256
459 #define RX_RING_MIN 128
460 #define TX_RING_MIN 64
461 #define RING_MAX_DESC_VER_1 1024
462 #define RING_MAX_DESC_VER_2_3 16384
464 /* rx/tx mac addr + type + vlan + align + slack*/
465 #define NV_RX_HEADERS (64)
466 /* even more slack. */
467 #define NV_RX_ALLOC_PAD (64)
469 /* maximum mtu size */
470 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
471 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
473 #define OOM_REFILL (1+HZ/20)
474 #define POLL_WAIT (1+HZ/100)
475 #define LINK_TIMEOUT (3*HZ)
476 #define STATS_INTERVAL (10*HZ)
480 * The nic supports three different descriptor types:
481 * - DESC_VER_1: Original
482 * - DESC_VER_2: support for jumbo frames.
483 * - DESC_VER_3: 64-bit format.
490 #define PHY_OUI_MARVELL 0x5043
491 #define PHY_OUI_CICADA 0x03f1
492 #define PHY_OUI_VITESSE 0x01c1
493 #define PHY_OUI_REALTEK 0x0732
494 #define PHY_OUI_REALTEK2 0x0020
495 #define PHYID1_OUI_MASK 0x03ff
496 #define PHYID1_OUI_SHFT 6
497 #define PHYID2_OUI_MASK 0xfc00
498 #define PHYID2_OUI_SHFT 10
499 #define PHYID2_MODEL_MASK 0x03f0
500 #define PHY_MODEL_REALTEK_8211 0x0110
501 #define PHY_REV_MASK 0x0001
502 #define PHY_REV_REALTEK_8211B 0x0000
503 #define PHY_REV_REALTEK_8211C 0x0001
504 #define PHY_MODEL_REALTEK_8201 0x0200
505 #define PHY_MODEL_MARVELL_E3016 0x0220
506 #define PHY_MARVELL_E3016_INITMASK 0x0300
507 #define PHY_CICADA_INIT1 0x0f000
508 #define PHY_CICADA_INIT2 0x0e00
509 #define PHY_CICADA_INIT3 0x01000
510 #define PHY_CICADA_INIT4 0x0200
511 #define PHY_CICADA_INIT5 0x0004
512 #define PHY_CICADA_INIT6 0x02000
513 #define PHY_VITESSE_INIT_REG1 0x1f
514 #define PHY_VITESSE_INIT_REG2 0x10
515 #define PHY_VITESSE_INIT_REG3 0x11
516 #define PHY_VITESSE_INIT_REG4 0x12
517 #define PHY_VITESSE_INIT_MSK1 0xc
518 #define PHY_VITESSE_INIT_MSK2 0x0180
519 #define PHY_VITESSE_INIT1 0x52b5
520 #define PHY_VITESSE_INIT2 0xaf8a
521 #define PHY_VITESSE_INIT3 0x8
522 #define PHY_VITESSE_INIT4 0x8f8a
523 #define PHY_VITESSE_INIT5 0xaf86
524 #define PHY_VITESSE_INIT6 0x8f86
525 #define PHY_VITESSE_INIT7 0xaf82
526 #define PHY_VITESSE_INIT8 0x0100
527 #define PHY_VITESSE_INIT9 0x8f82
528 #define PHY_VITESSE_INIT10 0x0
529 #define PHY_REALTEK_INIT_REG1 0x1f
530 #define PHY_REALTEK_INIT_REG2 0x19
531 #define PHY_REALTEK_INIT_REG3 0x13
532 #define PHY_REALTEK_INIT_REG4 0x14
533 #define PHY_REALTEK_INIT_REG5 0x18
534 #define PHY_REALTEK_INIT_REG6 0x11
535 #define PHY_REALTEK_INIT_REG7 0x01
536 #define PHY_REALTEK_INIT1 0x0000
537 #define PHY_REALTEK_INIT2 0x8e00
538 #define PHY_REALTEK_INIT3 0x0001
539 #define PHY_REALTEK_INIT4 0xad17
540 #define PHY_REALTEK_INIT5 0xfb54
541 #define PHY_REALTEK_INIT6 0xf5c7
542 #define PHY_REALTEK_INIT7 0x1000
543 #define PHY_REALTEK_INIT8 0x0003
544 #define PHY_REALTEK_INIT9 0x0008
545 #define PHY_REALTEK_INIT10 0x0005
546 #define PHY_REALTEK_INIT11 0x0200
547 #define PHY_REALTEK_INIT_MSK1 0x0003
549 #define PHY_GIGABIT 0x0100
551 #define PHY_TIMEOUT 0x1
552 #define PHY_ERROR 0x2
556 #define PHY_HALF 0x100
558 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
559 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
560 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
561 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
562 #define NV_PAUSEFRAME_RX_REQ 0x0010
563 #define NV_PAUSEFRAME_TX_REQ 0x0020
564 #define NV_PAUSEFRAME_AUTONEG 0x0040
566 /* MSI/MSI-X defines */
567 #define NV_MSI_X_MAX_VECTORS 8
568 #define NV_MSI_X_VECTORS_MASK 0x000f
569 #define NV_MSI_CAPABLE 0x0010
570 #define NV_MSI_X_CAPABLE 0x0020
571 #define NV_MSI_ENABLED 0x0040
572 #define NV_MSI_X_ENABLED 0x0080
574 #define NV_MSI_X_VECTOR_ALL 0x0
575 #define NV_MSI_X_VECTOR_RX 0x0
576 #define NV_MSI_X_VECTOR_TX 0x1
577 #define NV_MSI_X_VECTOR_OTHER 0x2
579 #define NV_RESTART_TX 0x1
580 #define NV_RESTART_RX 0x2
582 #define NV_TX_LIMIT_COUNT 16
585 struct nv_ethtool_str
{
586 char name
[ETH_GSTRING_LEN
];
589 static const struct nv_ethtool_str nv_estats_str
[] = {
594 { "tx_late_collision" },
595 { "tx_fifo_errors" },
596 { "tx_carrier_errors" },
597 { "tx_excess_deferral" },
598 { "tx_retry_error" },
599 { "rx_frame_error" },
601 { "rx_late_collision" },
603 { "rx_frame_too_long" },
604 { "rx_over_errors" },
606 { "rx_frame_align_error" },
607 { "rx_length_error" },
612 { "rx_errors_total" },
613 { "tx_errors_total" },
615 /* version 2 stats */
624 struct nv_ethtool_stats
{
629 u64 tx_late_collision
;
631 u64 tx_carrier_errors
;
632 u64 tx_excess_deferral
;
636 u64 rx_late_collision
;
638 u64 rx_frame_too_long
;
641 u64 rx_frame_align_error
;
650 /* version 2 stats */
659 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
660 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
663 #define NV_TEST_COUNT_BASE 3
664 #define NV_TEST_COUNT_EXTENDED 4
666 static const struct nv_ethtool_str nv_etests_str
[] = {
667 { "link (online/offline)" },
668 { "register (offline) " },
669 { "interrupt (offline) " },
670 { "loopback (offline) " }
673 struct register_test
{
678 static const struct register_test nv_registers_test
[] = {
679 { NvRegUnknownSetupReg6
, 0x01 },
680 { NvRegMisc1
, 0x03c },
681 { NvRegOffloadConfig
, 0x03ff },
682 { NvRegMulticastAddrA
, 0xffffffff },
683 { NvRegTxWatermark
, 0x0ff },
684 { NvRegWakeUpFlags
, 0x07777 },
691 unsigned int dma_len
;
692 struct ring_desc_ex
*first_tx_desc
;
693 struct nv_skb_map
*next_tx_ctx
;
698 * All hardware access under dev->priv->lock, except the performance
700 * - rx is (pseudo-) lockless: it relies on the single-threading provided
701 * by the arch code for interrupts.
702 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
703 * needs dev->priv->lock :-(
704 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
707 /* in dev: base, irq */
711 struct net_device
*dev
;
712 struct napi_struct napi
;
715 * Locking: spin_lock(&np->lock); */
716 struct nv_ethtool_stats estats
;
724 unsigned int phy_oui
;
725 unsigned int phy_model
;
726 unsigned int phy_rev
;
731 /* General data: RO fields */
732 dma_addr_t ring_addr
;
733 struct pci_dev
*pci_dev
;
747 /* rx specific fields.
748 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
750 union ring_type get_rx
, put_rx
, first_rx
, last_rx
;
751 struct nv_skb_map
*get_rx_ctx
, *put_rx_ctx
;
752 struct nv_skb_map
*first_rx_ctx
, *last_rx_ctx
;
753 struct nv_skb_map
*rx_skb
;
755 union ring_type rx_ring
;
756 unsigned int rx_buf_sz
;
757 unsigned int pkt_limit
;
758 struct timer_list oom_kick
;
759 struct timer_list nic_poll
;
760 struct timer_list stats_poll
;
764 /* media detection workaround.
765 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
768 unsigned long link_timeout
;
770 * tx specific fields.
772 union ring_type get_tx
, put_tx
, first_tx
, last_tx
;
773 struct nv_skb_map
*get_tx_ctx
, *put_tx_ctx
;
774 struct nv_skb_map
*first_tx_ctx
, *last_tx_ctx
;
775 struct nv_skb_map
*tx_skb
;
777 union ring_type tx_ring
;
781 u32 tx_pkts_in_progress
;
782 struct nv_skb_map
*tx_change_owner
;
783 struct nv_skb_map
*tx_end_flip
;
787 struct vlan_group
*vlangrp
;
789 /* msi/msi-x fields */
791 struct msix_entry msi_x_entry
[NV_MSI_X_MAX_VECTORS
];
796 /* power saved state */
797 u32 saved_config_space
[NV_PCI_REGSZ_MAX
/4];
801 * Maximum number of loops until we assume that a bit in the irq mask
802 * is stuck. Overridable with module param.
804 static int max_interrupt_work
= 5;
807 * Optimization can be either throuput mode or cpu mode
809 * Throughput Mode: Every tx and rx packet will generate an interrupt.
810 * CPU Mode: Interrupts are controlled by a timer.
813 NV_OPTIMIZATION_MODE_THROUGHPUT
,
814 NV_OPTIMIZATION_MODE_CPU
816 static int optimization_mode
= NV_OPTIMIZATION_MODE_THROUGHPUT
;
819 * Poll interval for timer irq
821 * This interval determines how frequent an interrupt is generated.
822 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
823 * Min = 0, and Max = 65535
825 static int poll_interval
= -1;
834 static int msi
= NV_MSI_INT_ENABLED
;
840 NV_MSIX_INT_DISABLED
,
843 static int msix
= NV_MSIX_INT_DISABLED
;
849 NV_DMA_64BIT_DISABLED
,
852 static int dma_64bit
= NV_DMA_64BIT_ENABLED
;
855 * Crossover Detection
856 * Realtek 8201 phy + some OEM boards do not work properly.
859 NV_CROSSOVER_DETECTION_DISABLED
,
860 NV_CROSSOVER_DETECTION_ENABLED
862 static int phy_cross
= NV_CROSSOVER_DETECTION_DISABLED
;
864 static inline struct fe_priv
*get_nvpriv(struct net_device
*dev
)
866 return netdev_priv(dev
);
869 static inline u8 __iomem
*get_hwbase(struct net_device
*dev
)
871 return ((struct fe_priv
*)netdev_priv(dev
))->base
;
874 static inline void pci_push(u8 __iomem
*base
)
876 /* force out pending posted writes */
880 static inline u32
nv_descr_getlength(struct ring_desc
*prd
, u32 v
)
882 return le32_to_cpu(prd
->flaglen
)
883 & ((v
== DESC_VER_1
) ? LEN_MASK_V1
: LEN_MASK_V2
);
886 static inline u32
nv_descr_getlength_ex(struct ring_desc_ex
*prd
, u32 v
)
888 return le32_to_cpu(prd
->flaglen
) & LEN_MASK_V2
;
891 static bool nv_optimized(struct fe_priv
*np
)
893 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
898 static int reg_delay(struct net_device
*dev
, int offset
, u32 mask
, u32 target
,
899 int delay
, int delaymax
, const char *msg
)
901 u8 __iomem
*base
= get_hwbase(dev
);
912 } while ((readl(base
+ offset
) & mask
) != target
);
916 #define NV_SETUP_RX_RING 0x01
917 #define NV_SETUP_TX_RING 0x02
919 static inline u32
dma_low(dma_addr_t addr
)
924 static inline u32
dma_high(dma_addr_t addr
)
926 return addr
>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
929 static void setup_hw_rings(struct net_device
*dev
, int rxtx_flags
)
931 struct fe_priv
*np
= get_nvpriv(dev
);
932 u8 __iomem
*base
= get_hwbase(dev
);
934 if (!nv_optimized(np
)) {
935 if (rxtx_flags
& NV_SETUP_RX_RING
) {
936 writel(dma_low(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
938 if (rxtx_flags
& NV_SETUP_TX_RING
) {
939 writel(dma_low(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
942 if (rxtx_flags
& NV_SETUP_RX_RING
) {
943 writel(dma_low(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
944 writel(dma_high(np
->ring_addr
), base
+ NvRegRxRingPhysAddrHigh
);
946 if (rxtx_flags
& NV_SETUP_TX_RING
) {
947 writel(dma_low(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddr
);
948 writel(dma_high(np
->ring_addr
+ np
->rx_ring_size
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddrHigh
);
953 static void free_rings(struct net_device
*dev
)
955 struct fe_priv
*np
= get_nvpriv(dev
);
957 if (!nv_optimized(np
)) {
958 if (np
->rx_ring
.orig
)
959 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
960 np
->rx_ring
.orig
, np
->ring_addr
);
963 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
964 np
->rx_ring
.ex
, np
->ring_addr
);
972 static int using_multi_irqs(struct net_device
*dev
)
974 struct fe_priv
*np
= get_nvpriv(dev
);
976 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
977 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
978 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1)))
984 static void nv_enable_irq(struct net_device
*dev
)
986 struct fe_priv
*np
= get_nvpriv(dev
);
988 if (!using_multi_irqs(dev
)) {
989 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
990 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
992 enable_irq(np
->pci_dev
->irq
);
994 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
995 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
996 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1000 static void nv_disable_irq(struct net_device
*dev
)
1002 struct fe_priv
*np
= get_nvpriv(dev
);
1004 if (!using_multi_irqs(dev
)) {
1005 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1006 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1008 disable_irq(np
->pci_dev
->irq
);
1010 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1011 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1012 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1016 /* In MSIX mode, a write to irqmask behaves as XOR */
1017 static void nv_enable_hw_interrupts(struct net_device
*dev
, u32 mask
)
1019 u8 __iomem
*base
= get_hwbase(dev
);
1021 writel(mask
, base
+ NvRegIrqMask
);
1024 static void nv_disable_hw_interrupts(struct net_device
*dev
, u32 mask
)
1026 struct fe_priv
*np
= get_nvpriv(dev
);
1027 u8 __iomem
*base
= get_hwbase(dev
);
1029 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
1030 writel(mask
, base
+ NvRegIrqMask
);
1032 if (np
->msi_flags
& NV_MSI_ENABLED
)
1033 writel(0, base
+ NvRegMSIIrqMask
);
1034 writel(0, base
+ NvRegIrqMask
);
1038 #define MII_READ (-1)
1039 /* mii_rw: read/write a register on the PHY.
1041 * Caller must guarantee serialization
1043 static int mii_rw(struct net_device
*dev
, int addr
, int miireg
, int value
)
1045 u8 __iomem
*base
= get_hwbase(dev
);
1049 writel(NVREG_MIISTAT_MASK_RW
, base
+ NvRegMIIStatus
);
1051 reg
= readl(base
+ NvRegMIIControl
);
1052 if (reg
& NVREG_MIICTL_INUSE
) {
1053 writel(NVREG_MIICTL_INUSE
, base
+ NvRegMIIControl
);
1054 udelay(NV_MIIBUSY_DELAY
);
1057 reg
= (addr
<< NVREG_MIICTL_ADDRSHIFT
) | miireg
;
1058 if (value
!= MII_READ
) {
1059 writel(value
, base
+ NvRegMIIData
);
1060 reg
|= NVREG_MIICTL_WRITE
;
1062 writel(reg
, base
+ NvRegMIIControl
);
1064 if (reg_delay(dev
, NvRegMIIControl
, NVREG_MIICTL_INUSE
, 0,
1065 NV_MIIPHY_DELAY
, NV_MIIPHY_DELAYMAX
, NULL
)) {
1066 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d timed out.\n",
1067 dev
->name
, miireg
, addr
);
1069 } else if (value
!= MII_READ
) {
1070 /* it was a write operation - fewer failures are detectable */
1071 dprintk(KERN_DEBUG
"%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1072 dev
->name
, value
, miireg
, addr
);
1074 } else if (readl(base
+ NvRegMIIStatus
) & NVREG_MIISTAT_ERROR
) {
1075 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d failed.\n",
1076 dev
->name
, miireg
, addr
);
1079 retval
= readl(base
+ NvRegMIIData
);
1080 dprintk(KERN_DEBUG
"%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1081 dev
->name
, miireg
, addr
, retval
);
1087 static int phy_reset(struct net_device
*dev
, u32 bmcr_setup
)
1089 struct fe_priv
*np
= netdev_priv(dev
);
1091 unsigned int tries
= 0;
1093 miicontrol
= BMCR_RESET
| bmcr_setup
;
1094 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
)) {
1098 /* wait for 500ms */
1101 /* must wait till reset is deasserted */
1102 while (miicontrol
& BMCR_RESET
) {
1104 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1105 /* FIXME: 100 tries seem excessive */
1112 static int phy_init(struct net_device
*dev
)
1114 struct fe_priv
*np
= get_nvpriv(dev
);
1115 u8 __iomem
*base
= get_hwbase(dev
);
1116 u32 phyinterface
, phy_reserved
, mii_status
, mii_control
, mii_control_1000
,reg
;
1118 /* phy errata for E3016 phy */
1119 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
1120 reg
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1121 reg
&= ~PHY_MARVELL_E3016_INITMASK
;
1122 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, reg
)) {
1123 printk(KERN_INFO
"%s: phy write to errata reg failed.\n", pci_name(np
->pci_dev
));
1127 if (np
->phy_oui
== PHY_OUI_REALTEK
) {
1128 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1129 np
->phy_rev
== PHY_REV_REALTEK_8211B
) {
1130 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1131 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1134 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, PHY_REALTEK_INIT2
)) {
1135 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1138 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1139 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1142 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG3
, PHY_REALTEK_INIT4
)) {
1143 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1146 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG4
, PHY_REALTEK_INIT5
)) {
1147 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1150 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG5
, PHY_REALTEK_INIT6
)) {
1151 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1154 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1155 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1159 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1160 np
->phy_rev
== PHY_REV_REALTEK_8211C
) {
1161 u32 powerstate
= readl(base
+ NvRegPowerState2
);
1163 /* need to perform hw phy reset */
1164 powerstate
|= NVREG_POWERSTATE2_PHY_RESET
;
1165 writel(powerstate
, base
+ NvRegPowerState2
);
1168 powerstate
&= ~NVREG_POWERSTATE2_PHY_RESET
;
1169 writel(powerstate
, base
+ NvRegPowerState2
);
1172 reg
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1173 reg
|= PHY_REALTEK_INIT9
;
1174 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, reg
)) {
1175 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1178 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT10
)) {
1179 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1182 reg
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG7
, MII_READ
);
1183 if (!(reg
& PHY_REALTEK_INIT11
)) {
1184 reg
|= PHY_REALTEK_INIT11
;
1185 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG7
, reg
)) {
1186 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1190 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1191 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1195 if (np
->phy_model
== PHY_MODEL_REALTEK_8201
) {
1196 if (np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_32
||
1197 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_33
||
1198 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_34
||
1199 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_35
||
1200 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_36
||
1201 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_37
||
1202 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_38
||
1203 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_39
) {
1204 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1205 phy_reserved
|= PHY_REALTEK_INIT7
;
1206 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, phy_reserved
)) {
1207 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1214 /* set advertise register */
1215 reg
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1216 reg
|= (ADVERTISE_10HALF
|ADVERTISE_10FULL
|ADVERTISE_100HALF
|ADVERTISE_100FULL
|ADVERTISE_PAUSE_ASYM
|ADVERTISE_PAUSE_CAP
);
1217 if (mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
)) {
1218 printk(KERN_INFO
"%s: phy write to advertise failed.\n", pci_name(np
->pci_dev
));
1222 /* get phy interface type */
1223 phyinterface
= readl(base
+ NvRegPhyInterface
);
1225 /* see if gigabit phy */
1226 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1227 if (mii_status
& PHY_GIGABIT
) {
1228 np
->gigabit
= PHY_GIGABIT
;
1229 mii_control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
1230 mii_control_1000
&= ~ADVERTISE_1000HALF
;
1231 if (phyinterface
& PHY_RGMII
)
1232 mii_control_1000
|= ADVERTISE_1000FULL
;
1234 mii_control_1000
&= ~ADVERTISE_1000FULL
;
1236 if (mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, mii_control_1000
)) {
1237 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1244 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1245 mii_control
|= BMCR_ANENABLE
;
1247 if (np
->phy_oui
== PHY_OUI_REALTEK
&&
1248 np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1249 np
->phy_rev
== PHY_REV_REALTEK_8211C
) {
1250 /* start autoneg since we already performed hw reset above */
1251 mii_control
|= BMCR_ANRESTART
;
1252 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
1253 printk(KERN_INFO
"%s: phy init failed\n", pci_name(np
->pci_dev
));
1258 * (certain phys need bmcr to be setup with reset)
1260 if (phy_reset(dev
, mii_control
)) {
1261 printk(KERN_INFO
"%s: phy reset failed\n", pci_name(np
->pci_dev
));
1266 /* phy vendor specific configuration */
1267 if ((np
->phy_oui
== PHY_OUI_CICADA
) && (phyinterface
& PHY_RGMII
) ) {
1268 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_RESV1
, MII_READ
);
1269 phy_reserved
&= ~(PHY_CICADA_INIT1
| PHY_CICADA_INIT2
);
1270 phy_reserved
|= (PHY_CICADA_INIT3
| PHY_CICADA_INIT4
);
1271 if (mii_rw(dev
, np
->phyaddr
, MII_RESV1
, phy_reserved
)) {
1272 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1275 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
1276 phy_reserved
|= PHY_CICADA_INIT5
;
1277 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, phy_reserved
)) {
1278 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1282 if (np
->phy_oui
== PHY_OUI_CICADA
) {
1283 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, MII_READ
);
1284 phy_reserved
|= PHY_CICADA_INIT6
;
1285 if (mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, phy_reserved
)) {
1286 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1290 if (np
->phy_oui
== PHY_OUI_VITESSE
) {
1291 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG1
, PHY_VITESSE_INIT1
)) {
1292 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1295 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT2
)) {
1296 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1299 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1300 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1301 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1304 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1305 phy_reserved
&= ~PHY_VITESSE_INIT_MSK1
;
1306 phy_reserved
|= PHY_VITESSE_INIT3
;
1307 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1308 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1311 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT4
)) {
1312 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1315 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT5
)) {
1316 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1319 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1320 phy_reserved
&= ~PHY_VITESSE_INIT_MSK1
;
1321 phy_reserved
|= PHY_VITESSE_INIT3
;
1322 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1323 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1326 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1327 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1328 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1331 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT6
)) {
1332 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1335 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT7
)) {
1336 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1339 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, MII_READ
);
1340 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG4
, phy_reserved
)) {
1341 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1344 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, MII_READ
);
1345 phy_reserved
&= ~PHY_VITESSE_INIT_MSK2
;
1346 phy_reserved
|= PHY_VITESSE_INIT8
;
1347 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG3
, phy_reserved
)) {
1348 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1351 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG2
, PHY_VITESSE_INIT9
)) {
1352 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1355 if (mii_rw(dev
, np
->phyaddr
, PHY_VITESSE_INIT_REG1
, PHY_VITESSE_INIT10
)) {
1356 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1360 if (np
->phy_oui
== PHY_OUI_REALTEK
) {
1361 if (np
->phy_model
== PHY_MODEL_REALTEK_8211
&&
1362 np
->phy_rev
== PHY_REV_REALTEK_8211B
) {
1363 /* reset could have cleared these out, set them back */
1364 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1365 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1368 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, PHY_REALTEK_INIT2
)) {
1369 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1372 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1373 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1376 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG3
, PHY_REALTEK_INIT4
)) {
1377 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1380 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG4
, PHY_REALTEK_INIT5
)) {
1381 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1384 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG5
, PHY_REALTEK_INIT6
)) {
1385 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1388 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1389 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1393 if (np
->phy_model
== PHY_MODEL_REALTEK_8201
) {
1394 if (np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_32
||
1395 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_33
||
1396 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_34
||
1397 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_35
||
1398 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_36
||
1399 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_37
||
1400 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_38
||
1401 np
->device_id
== PCI_DEVICE_ID_NVIDIA_NVENET_39
) {
1402 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, MII_READ
);
1403 phy_reserved
|= PHY_REALTEK_INIT7
;
1404 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG6
, phy_reserved
)) {
1405 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1409 if (phy_cross
== NV_CROSSOVER_DETECTION_DISABLED
) {
1410 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
)) {
1411 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1414 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, MII_READ
);
1415 phy_reserved
&= ~PHY_REALTEK_INIT_MSK1
;
1416 phy_reserved
|= PHY_REALTEK_INIT3
;
1417 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, phy_reserved
)) {
1418 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1421 if (mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
)) {
1422 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
1429 /* some phys clear out pause advertisment on reset, set it back */
1430 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
);
1432 /* restart auto negotiation */
1433 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
1434 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
1435 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
1442 static void nv_start_rx(struct net_device
*dev
)
1444 struct fe_priv
*np
= netdev_priv(dev
);
1445 u8 __iomem
*base
= get_hwbase(dev
);
1446 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1448 dprintk(KERN_DEBUG
"%s: nv_start_rx\n", dev
->name
);
1449 /* Already running? Stop it. */
1450 if ((readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) && !np
->mac_in_use
) {
1451 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1452 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1455 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1457 rx_ctrl
|= NVREG_RCVCTL_START
;
1459 rx_ctrl
&= ~NVREG_RCVCTL_RX_PATH_EN
;
1460 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1461 dprintk(KERN_DEBUG
"%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1462 dev
->name
, np
->duplex
, np
->linkspeed
);
1466 static void nv_stop_rx(struct net_device
*dev
)
1468 struct fe_priv
*np
= netdev_priv(dev
);
1469 u8 __iomem
*base
= get_hwbase(dev
);
1470 u32 rx_ctrl
= readl(base
+ NvRegReceiverControl
);
1472 dprintk(KERN_DEBUG
"%s: nv_stop_rx\n", dev
->name
);
1473 if (!np
->mac_in_use
)
1474 rx_ctrl
&= ~NVREG_RCVCTL_START
;
1476 rx_ctrl
|= NVREG_RCVCTL_RX_PATH_EN
;
1477 writel(rx_ctrl
, base
+ NvRegReceiverControl
);
1478 reg_delay(dev
, NvRegReceiverStatus
, NVREG_RCVSTAT_BUSY
, 0,
1479 NV_RXSTOP_DELAY1
, NV_RXSTOP_DELAY1MAX
,
1480 KERN_INFO
"nv_stop_rx: ReceiverStatus remained busy");
1482 udelay(NV_RXSTOP_DELAY2
);
1483 if (!np
->mac_in_use
)
1484 writel(0, base
+ NvRegLinkSpeed
);
1487 static void nv_start_tx(struct net_device
*dev
)
1489 struct fe_priv
*np
= netdev_priv(dev
);
1490 u8 __iomem
*base
= get_hwbase(dev
);
1491 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1493 dprintk(KERN_DEBUG
"%s: nv_start_tx\n", dev
->name
);
1494 tx_ctrl
|= NVREG_XMITCTL_START
;
1496 tx_ctrl
&= ~NVREG_XMITCTL_TX_PATH_EN
;
1497 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1501 static void nv_stop_tx(struct net_device
*dev
)
1503 struct fe_priv
*np
= netdev_priv(dev
);
1504 u8 __iomem
*base
= get_hwbase(dev
);
1505 u32 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
1507 dprintk(KERN_DEBUG
"%s: nv_stop_tx\n", dev
->name
);
1508 if (!np
->mac_in_use
)
1509 tx_ctrl
&= ~NVREG_XMITCTL_START
;
1511 tx_ctrl
|= NVREG_XMITCTL_TX_PATH_EN
;
1512 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
1513 reg_delay(dev
, NvRegTransmitterStatus
, NVREG_XMITSTAT_BUSY
, 0,
1514 NV_TXSTOP_DELAY1
, NV_TXSTOP_DELAY1MAX
,
1515 KERN_INFO
"nv_stop_tx: TransmitterStatus remained busy");
1517 udelay(NV_TXSTOP_DELAY2
);
1518 if (!np
->mac_in_use
)
1519 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
1520 base
+ NvRegTransmitPoll
);
1523 static void nv_start_rxtx(struct net_device
*dev
)
1529 static void nv_stop_rxtx(struct net_device
*dev
)
1535 static void nv_txrx_reset(struct net_device
*dev
)
1537 struct fe_priv
*np
= netdev_priv(dev
);
1538 u8 __iomem
*base
= get_hwbase(dev
);
1540 dprintk(KERN_DEBUG
"%s: nv_txrx_reset\n", dev
->name
);
1541 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1543 udelay(NV_TXRX_RESET_DELAY
);
1544 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1548 static void nv_mac_reset(struct net_device
*dev
)
1550 struct fe_priv
*np
= netdev_priv(dev
);
1551 u8 __iomem
*base
= get_hwbase(dev
);
1552 u32 temp1
, temp2
, temp3
;
1554 dprintk(KERN_DEBUG
"%s: nv_mac_reset\n", dev
->name
);
1556 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1559 /* save registers since they will be cleared on reset */
1560 temp1
= readl(base
+ NvRegMacAddrA
);
1561 temp2
= readl(base
+ NvRegMacAddrB
);
1562 temp3
= readl(base
+ NvRegTransmitPoll
);
1564 writel(NVREG_MAC_RESET_ASSERT
, base
+ NvRegMacReset
);
1566 udelay(NV_MAC_RESET_DELAY
);
1567 writel(0, base
+ NvRegMacReset
);
1569 udelay(NV_MAC_RESET_DELAY
);
1571 /* restore saved registers */
1572 writel(temp1
, base
+ NvRegMacAddrA
);
1573 writel(temp2
, base
+ NvRegMacAddrB
);
1574 writel(temp3
, base
+ NvRegTransmitPoll
);
1576 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
1580 static void nv_get_hw_stats(struct net_device
*dev
)
1582 struct fe_priv
*np
= netdev_priv(dev
);
1583 u8 __iomem
*base
= get_hwbase(dev
);
1585 np
->estats
.tx_bytes
+= readl(base
+ NvRegTxCnt
);
1586 np
->estats
.tx_zero_rexmt
+= readl(base
+ NvRegTxZeroReXmt
);
1587 np
->estats
.tx_one_rexmt
+= readl(base
+ NvRegTxOneReXmt
);
1588 np
->estats
.tx_many_rexmt
+= readl(base
+ NvRegTxManyReXmt
);
1589 np
->estats
.tx_late_collision
+= readl(base
+ NvRegTxLateCol
);
1590 np
->estats
.tx_fifo_errors
+= readl(base
+ NvRegTxUnderflow
);
1591 np
->estats
.tx_carrier_errors
+= readl(base
+ NvRegTxLossCarrier
);
1592 np
->estats
.tx_excess_deferral
+= readl(base
+ NvRegTxExcessDef
);
1593 np
->estats
.tx_retry_error
+= readl(base
+ NvRegTxRetryErr
);
1594 np
->estats
.rx_frame_error
+= readl(base
+ NvRegRxFrameErr
);
1595 np
->estats
.rx_extra_byte
+= readl(base
+ NvRegRxExtraByte
);
1596 np
->estats
.rx_late_collision
+= readl(base
+ NvRegRxLateCol
);
1597 np
->estats
.rx_runt
+= readl(base
+ NvRegRxRunt
);
1598 np
->estats
.rx_frame_too_long
+= readl(base
+ NvRegRxFrameTooLong
);
1599 np
->estats
.rx_over_errors
+= readl(base
+ NvRegRxOverflow
);
1600 np
->estats
.rx_crc_errors
+= readl(base
+ NvRegRxFCSErr
);
1601 np
->estats
.rx_frame_align_error
+= readl(base
+ NvRegRxFrameAlignErr
);
1602 np
->estats
.rx_length_error
+= readl(base
+ NvRegRxLenErr
);
1603 np
->estats
.rx_unicast
+= readl(base
+ NvRegRxUnicast
);
1604 np
->estats
.rx_multicast
+= readl(base
+ NvRegRxMulticast
);
1605 np
->estats
.rx_broadcast
+= readl(base
+ NvRegRxBroadcast
);
1606 np
->estats
.rx_packets
=
1607 np
->estats
.rx_unicast
+
1608 np
->estats
.rx_multicast
+
1609 np
->estats
.rx_broadcast
;
1610 np
->estats
.rx_errors_total
=
1611 np
->estats
.rx_crc_errors
+
1612 np
->estats
.rx_over_errors
+
1613 np
->estats
.rx_frame_error
+
1614 (np
->estats
.rx_frame_align_error
- np
->estats
.rx_extra_byte
) +
1615 np
->estats
.rx_late_collision
+
1616 np
->estats
.rx_runt
+
1617 np
->estats
.rx_frame_too_long
;
1618 np
->estats
.tx_errors_total
=
1619 np
->estats
.tx_late_collision
+
1620 np
->estats
.tx_fifo_errors
+
1621 np
->estats
.tx_carrier_errors
+
1622 np
->estats
.tx_excess_deferral
+
1623 np
->estats
.tx_retry_error
;
1625 if (np
->driver_data
& DEV_HAS_STATISTICS_V2
) {
1626 np
->estats
.tx_deferral
+= readl(base
+ NvRegTxDef
);
1627 np
->estats
.tx_packets
+= readl(base
+ NvRegTxFrame
);
1628 np
->estats
.rx_bytes
+= readl(base
+ NvRegRxCnt
);
1629 np
->estats
.tx_pause
+= readl(base
+ NvRegTxPause
);
1630 np
->estats
.rx_pause
+= readl(base
+ NvRegRxPause
);
1631 np
->estats
.rx_drop_frame
+= readl(base
+ NvRegRxDropFrame
);
1636 * nv_get_stats: dev->get_stats function
1637 * Get latest stats value from the nic.
1638 * Called with read_lock(&dev_base_lock) held for read -
1639 * only synchronized against unregister_netdevice.
1641 static struct net_device_stats
*nv_get_stats(struct net_device
*dev
)
1643 struct fe_priv
*np
= netdev_priv(dev
);
1645 /* If the nic supports hw counters then retrieve latest values */
1646 if (np
->driver_data
& (DEV_HAS_STATISTICS_V1
|DEV_HAS_STATISTICS_V2
)) {
1647 nv_get_hw_stats(dev
);
1649 /* copy to net_device stats */
1650 dev
->stats
.tx_bytes
= np
->estats
.tx_bytes
;
1651 dev
->stats
.tx_fifo_errors
= np
->estats
.tx_fifo_errors
;
1652 dev
->stats
.tx_carrier_errors
= np
->estats
.tx_carrier_errors
;
1653 dev
->stats
.rx_crc_errors
= np
->estats
.rx_crc_errors
;
1654 dev
->stats
.rx_over_errors
= np
->estats
.rx_over_errors
;
1655 dev
->stats
.rx_errors
= np
->estats
.rx_errors_total
;
1656 dev
->stats
.tx_errors
= np
->estats
.tx_errors_total
;
1663 * nv_alloc_rx: fill rx ring entries.
1664 * Return 1 if the allocations for the skbs failed and the
1665 * rx engine is without Available descriptors
1667 static int nv_alloc_rx(struct net_device
*dev
)
1669 struct fe_priv
*np
= netdev_priv(dev
);
1670 struct ring_desc
* less_rx
;
1672 less_rx
= np
->get_rx
.orig
;
1673 if (less_rx
-- == np
->first_rx
.orig
)
1674 less_rx
= np
->last_rx
.orig
;
1676 while (np
->put_rx
.orig
!= less_rx
) {
1677 struct sk_buff
*skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1679 np
->put_rx_ctx
->skb
= skb
;
1680 np
->put_rx_ctx
->dma
= pci_map_single(np
->pci_dev
,
1683 PCI_DMA_FROMDEVICE
);
1684 np
->put_rx_ctx
->dma_len
= skb_tailroom(skb
);
1685 np
->put_rx
.orig
->buf
= cpu_to_le32(np
->put_rx_ctx
->dma
);
1687 np
->put_rx
.orig
->flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX_AVAIL
);
1688 if (unlikely(np
->put_rx
.orig
++ == np
->last_rx
.orig
))
1689 np
->put_rx
.orig
= np
->first_rx
.orig
;
1690 if (unlikely(np
->put_rx_ctx
++ == np
->last_rx_ctx
))
1691 np
->put_rx_ctx
= np
->first_rx_ctx
;
1699 static int nv_alloc_rx_optimized(struct net_device
*dev
)
1701 struct fe_priv
*np
= netdev_priv(dev
);
1702 struct ring_desc_ex
* less_rx
;
1704 less_rx
= np
->get_rx
.ex
;
1705 if (less_rx
-- == np
->first_rx
.ex
)
1706 less_rx
= np
->last_rx
.ex
;
1708 while (np
->put_rx
.ex
!= less_rx
) {
1709 struct sk_buff
*skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
1711 np
->put_rx_ctx
->skb
= skb
;
1712 np
->put_rx_ctx
->dma
= pci_map_single(np
->pci_dev
,
1715 PCI_DMA_FROMDEVICE
);
1716 np
->put_rx_ctx
->dma_len
= skb_tailroom(skb
);
1717 np
->put_rx
.ex
->bufhigh
= cpu_to_le32(dma_high(np
->put_rx_ctx
->dma
));
1718 np
->put_rx
.ex
->buflow
= cpu_to_le32(dma_low(np
->put_rx_ctx
->dma
));
1720 np
->put_rx
.ex
->flaglen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX2_AVAIL
);
1721 if (unlikely(np
->put_rx
.ex
++ == np
->last_rx
.ex
))
1722 np
->put_rx
.ex
= np
->first_rx
.ex
;
1723 if (unlikely(np
->put_rx_ctx
++ == np
->last_rx_ctx
))
1724 np
->put_rx_ctx
= np
->first_rx_ctx
;
1732 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1733 #ifdef CONFIG_FORCEDETH_NAPI
1734 static void nv_do_rx_refill(unsigned long data
)
1736 struct net_device
*dev
= (struct net_device
*) data
;
1737 struct fe_priv
*np
= netdev_priv(dev
);
1739 /* Just reschedule NAPI rx processing */
1740 netif_rx_schedule(dev
, &np
->napi
);
1743 static void nv_do_rx_refill(unsigned long data
)
1745 struct net_device
*dev
= (struct net_device
*) data
;
1746 struct fe_priv
*np
= netdev_priv(dev
);
1749 if (!using_multi_irqs(dev
)) {
1750 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1751 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1753 disable_irq(np
->pci_dev
->irq
);
1755 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1757 if (!nv_optimized(np
))
1758 retcode
= nv_alloc_rx(dev
);
1760 retcode
= nv_alloc_rx_optimized(dev
);
1762 spin_lock_irq(&np
->lock
);
1763 if (!np
->in_shutdown
)
1764 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1765 spin_unlock_irq(&np
->lock
);
1767 if (!using_multi_irqs(dev
)) {
1768 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1769 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
1771 enable_irq(np
->pci_dev
->irq
);
1773 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1778 static void nv_init_rx(struct net_device
*dev
)
1780 struct fe_priv
*np
= netdev_priv(dev
);
1783 np
->get_rx
= np
->put_rx
= np
->first_rx
= np
->rx_ring
;
1785 if (!nv_optimized(np
))
1786 np
->last_rx
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
-1];
1788 np
->last_rx
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
-1];
1789 np
->get_rx_ctx
= np
->put_rx_ctx
= np
->first_rx_ctx
= np
->rx_skb
;
1790 np
->last_rx_ctx
= &np
->rx_skb
[np
->rx_ring_size
-1];
1792 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
1793 if (!nv_optimized(np
)) {
1794 np
->rx_ring
.orig
[i
].flaglen
= 0;
1795 np
->rx_ring
.orig
[i
].buf
= 0;
1797 np
->rx_ring
.ex
[i
].flaglen
= 0;
1798 np
->rx_ring
.ex
[i
].txvlan
= 0;
1799 np
->rx_ring
.ex
[i
].bufhigh
= 0;
1800 np
->rx_ring
.ex
[i
].buflow
= 0;
1802 np
->rx_skb
[i
].skb
= NULL
;
1803 np
->rx_skb
[i
].dma
= 0;
1807 static void nv_init_tx(struct net_device
*dev
)
1809 struct fe_priv
*np
= netdev_priv(dev
);
1812 np
->get_tx
= np
->put_tx
= np
->first_tx
= np
->tx_ring
;
1814 if (!nv_optimized(np
))
1815 np
->last_tx
.orig
= &np
->tx_ring
.orig
[np
->tx_ring_size
-1];
1817 np
->last_tx
.ex
= &np
->tx_ring
.ex
[np
->tx_ring_size
-1];
1818 np
->get_tx_ctx
= np
->put_tx_ctx
= np
->first_tx_ctx
= np
->tx_skb
;
1819 np
->last_tx_ctx
= &np
->tx_skb
[np
->tx_ring_size
-1];
1820 np
->tx_pkts_in_progress
= 0;
1821 np
->tx_change_owner
= NULL
;
1822 np
->tx_end_flip
= NULL
;
1824 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1825 if (!nv_optimized(np
)) {
1826 np
->tx_ring
.orig
[i
].flaglen
= 0;
1827 np
->tx_ring
.orig
[i
].buf
= 0;
1829 np
->tx_ring
.ex
[i
].flaglen
= 0;
1830 np
->tx_ring
.ex
[i
].txvlan
= 0;
1831 np
->tx_ring
.ex
[i
].bufhigh
= 0;
1832 np
->tx_ring
.ex
[i
].buflow
= 0;
1834 np
->tx_skb
[i
].skb
= NULL
;
1835 np
->tx_skb
[i
].dma
= 0;
1836 np
->tx_skb
[i
].dma_len
= 0;
1837 np
->tx_skb
[i
].first_tx_desc
= NULL
;
1838 np
->tx_skb
[i
].next_tx_ctx
= NULL
;
1842 static int nv_init_ring(struct net_device
*dev
)
1844 struct fe_priv
*np
= netdev_priv(dev
);
1849 if (!nv_optimized(np
))
1850 return nv_alloc_rx(dev
);
1852 return nv_alloc_rx_optimized(dev
);
1855 static int nv_release_txskb(struct net_device
*dev
, struct nv_skb_map
* tx_skb
)
1857 struct fe_priv
*np
= netdev_priv(dev
);
1860 pci_unmap_page(np
->pci_dev
, tx_skb
->dma
,
1866 dev_kfree_skb_any(tx_skb
->skb
);
1874 static void nv_drain_tx(struct net_device
*dev
)
1876 struct fe_priv
*np
= netdev_priv(dev
);
1879 for (i
= 0; i
< np
->tx_ring_size
; i
++) {
1880 if (!nv_optimized(np
)) {
1881 np
->tx_ring
.orig
[i
].flaglen
= 0;
1882 np
->tx_ring
.orig
[i
].buf
= 0;
1884 np
->tx_ring
.ex
[i
].flaglen
= 0;
1885 np
->tx_ring
.ex
[i
].txvlan
= 0;
1886 np
->tx_ring
.ex
[i
].bufhigh
= 0;
1887 np
->tx_ring
.ex
[i
].buflow
= 0;
1889 if (nv_release_txskb(dev
, &np
->tx_skb
[i
]))
1890 dev
->stats
.tx_dropped
++;
1891 np
->tx_skb
[i
].dma
= 0;
1892 np
->tx_skb
[i
].dma_len
= 0;
1893 np
->tx_skb
[i
].first_tx_desc
= NULL
;
1894 np
->tx_skb
[i
].next_tx_ctx
= NULL
;
1896 np
->tx_pkts_in_progress
= 0;
1897 np
->tx_change_owner
= NULL
;
1898 np
->tx_end_flip
= NULL
;
1901 static void nv_drain_rx(struct net_device
*dev
)
1903 struct fe_priv
*np
= netdev_priv(dev
);
1906 for (i
= 0; i
< np
->rx_ring_size
; i
++) {
1907 if (!nv_optimized(np
)) {
1908 np
->rx_ring
.orig
[i
].flaglen
= 0;
1909 np
->rx_ring
.orig
[i
].buf
= 0;
1911 np
->rx_ring
.ex
[i
].flaglen
= 0;
1912 np
->rx_ring
.ex
[i
].txvlan
= 0;
1913 np
->rx_ring
.ex
[i
].bufhigh
= 0;
1914 np
->rx_ring
.ex
[i
].buflow
= 0;
1917 if (np
->rx_skb
[i
].skb
) {
1918 pci_unmap_single(np
->pci_dev
, np
->rx_skb
[i
].dma
,
1919 (skb_end_pointer(np
->rx_skb
[i
].skb
) -
1920 np
->rx_skb
[i
].skb
->data
),
1921 PCI_DMA_FROMDEVICE
);
1922 dev_kfree_skb(np
->rx_skb
[i
].skb
);
1923 np
->rx_skb
[i
].skb
= NULL
;
1928 static void nv_drain_rxtx(struct net_device
*dev
)
1934 static inline u32
nv_get_empty_tx_slots(struct fe_priv
*np
)
1936 return (u32
)(np
->tx_ring_size
- ((np
->tx_ring_size
+ (np
->put_tx_ctx
- np
->get_tx_ctx
)) % np
->tx_ring_size
));
1939 static void nv_legacybackoff_reseed(struct net_device
*dev
)
1941 u8 __iomem
*base
= get_hwbase(dev
);
1946 reg
= readl(base
+ NvRegSlotTime
) & ~NVREG_SLOTTIME_MASK
;
1947 get_random_bytes(&low
, sizeof(low
));
1948 reg
|= low
& NVREG_SLOTTIME_MASK
;
1950 /* Need to stop tx before change takes effect.
1951 * Caller has already gained np->lock.
1953 tx_status
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_START
;
1957 writel(reg
, base
+ NvRegSlotTime
);
1963 /* Gear Backoff Seeds */
1964 #define BACKOFF_SEEDSET_ROWS 8
1965 #define BACKOFF_SEEDSET_LFSRS 15
1967 /* Known Good seed sets */
1968 static const u32 main_seedset
[BACKOFF_SEEDSET_ROWS
][BACKOFF_SEEDSET_LFSRS
] = {
1969 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1970 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
1971 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
1972 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
1973 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
1974 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
1975 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
1976 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
1978 static const u32 gear_seedset
[BACKOFF_SEEDSET_ROWS
][BACKOFF_SEEDSET_LFSRS
] = {
1979 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1980 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1981 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
1982 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1983 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
1984 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1985 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
1986 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
1988 static void nv_gear_backoff_reseed(struct net_device
*dev
)
1990 u8 __iomem
*base
= get_hwbase(dev
);
1991 u32 miniseed1
, miniseed2
, miniseed2_reversed
, miniseed3
, miniseed3_reversed
;
1992 u32 temp
, seedset
, combinedSeed
;
1995 /* Setup seed for free running LFSR */
1996 /* We are going to read the time stamp counter 3 times
1997 and swizzle bits around to increase randomness */
1998 get_random_bytes(&miniseed1
, sizeof(miniseed1
));
1999 miniseed1
&= 0x0fff;
2003 get_random_bytes(&miniseed2
, sizeof(miniseed2
));
2004 miniseed2
&= 0x0fff;
2007 miniseed2_reversed
=
2008 ((miniseed2
& 0xF00) >> 8) |
2009 (miniseed2
& 0x0F0) |
2010 ((miniseed2
& 0x00F) << 8);
2012 get_random_bytes(&miniseed3
, sizeof(miniseed3
));
2013 miniseed3
&= 0x0fff;
2016 miniseed3_reversed
=
2017 ((miniseed3
& 0xF00) >> 8) |
2018 (miniseed3
& 0x0F0) |
2019 ((miniseed3
& 0x00F) << 8);
2021 combinedSeed
= ((miniseed1
^ miniseed2_reversed
) << 12) |
2022 (miniseed2
^ miniseed3_reversed
);
2024 /* Seeds can not be zero */
2025 if ((combinedSeed
& NVREG_BKOFFCTRL_SEED_MASK
) == 0)
2026 combinedSeed
|= 0x08;
2027 if ((combinedSeed
& (NVREG_BKOFFCTRL_SEED_MASK
<< NVREG_BKOFFCTRL_GEAR
)) == 0)
2028 combinedSeed
|= 0x8000;
2030 /* No need to disable tx here */
2031 temp
= NVREG_BKOFFCTRL_DEFAULT
| (0 << NVREG_BKOFFCTRL_SELECT
);
2032 temp
|= combinedSeed
& NVREG_BKOFFCTRL_SEED_MASK
;
2033 temp
|= combinedSeed
>> NVREG_BKOFFCTRL_GEAR
;
2034 writel(temp
,base
+ NvRegBackOffControl
);
2036 /* Setup seeds for all gear LFSRs. */
2037 get_random_bytes(&seedset
, sizeof(seedset
));
2038 seedset
= seedset
% BACKOFF_SEEDSET_ROWS
;
2039 for (i
= 1; i
<= BACKOFF_SEEDSET_LFSRS
; i
++)
2041 temp
= NVREG_BKOFFCTRL_DEFAULT
| (i
<< NVREG_BKOFFCTRL_SELECT
);
2042 temp
|= main_seedset
[seedset
][i
-1] & 0x3ff;
2043 temp
|= ((gear_seedset
[seedset
][i
-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR
);
2044 writel(temp
, base
+ NvRegBackOffControl
);
2049 * nv_start_xmit: dev->hard_start_xmit function
2050 * Called with netif_tx_lock held.
2052 static int nv_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2054 struct fe_priv
*np
= netdev_priv(dev
);
2056 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
2057 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
2061 u32 size
= skb
->len
-skb
->data_len
;
2062 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2064 struct ring_desc
* put_tx
;
2065 struct ring_desc
* start_tx
;
2066 struct ring_desc
* prev_tx
;
2067 struct nv_skb_map
* prev_tx_ctx
;
2068 unsigned long flags
;
2070 /* add fragments to entries count */
2071 for (i
= 0; i
< fragments
; i
++) {
2072 entries
+= (skb_shinfo(skb
)->frags
[i
].size
>> NV_TX2_TSO_MAX_SHIFT
) +
2073 ((skb_shinfo(skb
)->frags
[i
].size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2076 empty_slots
= nv_get_empty_tx_slots(np
);
2077 if (unlikely(empty_slots
<= entries
)) {
2078 spin_lock_irqsave(&np
->lock
, flags
);
2079 netif_stop_queue(dev
);
2081 spin_unlock_irqrestore(&np
->lock
, flags
);
2082 return NETDEV_TX_BUSY
;
2085 start_tx
= put_tx
= np
->put_tx
.orig
;
2087 /* setup the header buffer */
2090 prev_tx_ctx
= np
->put_tx_ctx
;
2091 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2092 np
->put_tx_ctx
->dma
= pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
2094 np
->put_tx_ctx
->dma_len
= bcnt
;
2095 put_tx
->buf
= cpu_to_le32(np
->put_tx_ctx
->dma
);
2096 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2098 tx_flags
= np
->tx_flags
;
2101 if (unlikely(put_tx
++ == np
->last_tx
.orig
))
2102 put_tx
= np
->first_tx
.orig
;
2103 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2104 np
->put_tx_ctx
= np
->first_tx_ctx
;
2107 /* setup the fragments */
2108 for (i
= 0; i
< fragments
; i
++) {
2109 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2110 u32 size
= frag
->size
;
2115 prev_tx_ctx
= np
->put_tx_ctx
;
2116 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2117 np
->put_tx_ctx
->dma
= pci_map_page(np
->pci_dev
, frag
->page
, frag
->page_offset
+offset
, bcnt
,
2119 np
->put_tx_ctx
->dma_len
= bcnt
;
2120 put_tx
->buf
= cpu_to_le32(np
->put_tx_ctx
->dma
);
2121 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2125 if (unlikely(put_tx
++ == np
->last_tx
.orig
))
2126 put_tx
= np
->first_tx
.orig
;
2127 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2128 np
->put_tx_ctx
= np
->first_tx_ctx
;
2132 /* set last fragment flag */
2133 prev_tx
->flaglen
|= cpu_to_le32(tx_flags_extra
);
2135 /* save skb in this slot's context area */
2136 prev_tx_ctx
->skb
= skb
;
2138 if (skb_is_gso(skb
))
2139 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
2141 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
2142 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
2144 spin_lock_irqsave(&np
->lock
, flags
);
2147 start_tx
->flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
2148 np
->put_tx
.orig
= put_tx
;
2150 spin_unlock_irqrestore(&np
->lock
, flags
);
2152 dprintk(KERN_DEBUG
"%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
2153 dev
->name
, entries
, tx_flags_extra
);
2156 for (j
=0; j
<64; j
++) {
2158 dprintk("\n%03x:", j
);
2159 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2164 dev
->trans_start
= jiffies
;
2165 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2166 return NETDEV_TX_OK
;
2169 static int nv_start_xmit_optimized(struct sk_buff
*skb
, struct net_device
*dev
)
2171 struct fe_priv
*np
= netdev_priv(dev
);
2174 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
2178 u32 size
= skb
->len
-skb
->data_len
;
2179 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2181 struct ring_desc_ex
* put_tx
;
2182 struct ring_desc_ex
* start_tx
;
2183 struct ring_desc_ex
* prev_tx
;
2184 struct nv_skb_map
* prev_tx_ctx
;
2185 struct nv_skb_map
* start_tx_ctx
;
2186 unsigned long flags
;
2188 /* add fragments to entries count */
2189 for (i
= 0; i
< fragments
; i
++) {
2190 entries
+= (skb_shinfo(skb
)->frags
[i
].size
>> NV_TX2_TSO_MAX_SHIFT
) +
2191 ((skb_shinfo(skb
)->frags
[i
].size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
2194 empty_slots
= nv_get_empty_tx_slots(np
);
2195 if (unlikely(empty_slots
<= entries
)) {
2196 spin_lock_irqsave(&np
->lock
, flags
);
2197 netif_stop_queue(dev
);
2199 spin_unlock_irqrestore(&np
->lock
, flags
);
2200 return NETDEV_TX_BUSY
;
2203 start_tx
= put_tx
= np
->put_tx
.ex
;
2204 start_tx_ctx
= np
->put_tx_ctx
;
2206 /* setup the header buffer */
2209 prev_tx_ctx
= np
->put_tx_ctx
;
2210 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2211 np
->put_tx_ctx
->dma
= pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
2213 np
->put_tx_ctx
->dma_len
= bcnt
;
2214 put_tx
->bufhigh
= cpu_to_le32(dma_high(np
->put_tx_ctx
->dma
));
2215 put_tx
->buflow
= cpu_to_le32(dma_low(np
->put_tx_ctx
->dma
));
2216 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2218 tx_flags
= NV_TX2_VALID
;
2221 if (unlikely(put_tx
++ == np
->last_tx
.ex
))
2222 put_tx
= np
->first_tx
.ex
;
2223 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2224 np
->put_tx_ctx
= np
->first_tx_ctx
;
2227 /* setup the fragments */
2228 for (i
= 0; i
< fragments
; i
++) {
2229 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2230 u32 size
= frag
->size
;
2235 prev_tx_ctx
= np
->put_tx_ctx
;
2236 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
2237 np
->put_tx_ctx
->dma
= pci_map_page(np
->pci_dev
, frag
->page
, frag
->page_offset
+offset
, bcnt
,
2239 np
->put_tx_ctx
->dma_len
= bcnt
;
2240 put_tx
->bufhigh
= cpu_to_le32(dma_high(np
->put_tx_ctx
->dma
));
2241 put_tx
->buflow
= cpu_to_le32(dma_low(np
->put_tx_ctx
->dma
));
2242 put_tx
->flaglen
= cpu_to_le32((bcnt
-1) | tx_flags
);
2246 if (unlikely(put_tx
++ == np
->last_tx
.ex
))
2247 put_tx
= np
->first_tx
.ex
;
2248 if (unlikely(np
->put_tx_ctx
++ == np
->last_tx_ctx
))
2249 np
->put_tx_ctx
= np
->first_tx_ctx
;
2253 /* set last fragment flag */
2254 prev_tx
->flaglen
|= cpu_to_le32(NV_TX2_LASTPACKET
);
2256 /* save skb in this slot's context area */
2257 prev_tx_ctx
->skb
= skb
;
2259 if (skb_is_gso(skb
))
2260 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->gso_size
<< NV_TX2_TSO_SHIFT
);
2262 tx_flags_extra
= skb
->ip_summed
== CHECKSUM_PARTIAL
?
2263 NV_TX2_CHECKSUM_L3
| NV_TX2_CHECKSUM_L4
: 0;
2266 if (likely(!np
->vlangrp
)) {
2267 start_tx
->txvlan
= 0;
2269 if (vlan_tx_tag_present(skb
))
2270 start_tx
->txvlan
= cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT
| vlan_tx_tag_get(skb
));
2272 start_tx
->txvlan
= 0;
2275 spin_lock_irqsave(&np
->lock
, flags
);
2278 /* Limit the number of outstanding tx. Setup all fragments, but
2279 * do not set the VALID bit on the first descriptor. Save a pointer
2280 * to that descriptor and also for next skb_map element.
2283 if (np
->tx_pkts_in_progress
== NV_TX_LIMIT_COUNT
) {
2284 if (!np
->tx_change_owner
)
2285 np
->tx_change_owner
= start_tx_ctx
;
2287 /* remove VALID bit */
2288 tx_flags
&= ~NV_TX2_VALID
;
2289 start_tx_ctx
->first_tx_desc
= start_tx
;
2290 start_tx_ctx
->next_tx_ctx
= np
->put_tx_ctx
;
2291 np
->tx_end_flip
= np
->put_tx_ctx
;
2293 np
->tx_pkts_in_progress
++;
2298 start_tx
->flaglen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
2299 np
->put_tx
.ex
= put_tx
;
2301 spin_unlock_irqrestore(&np
->lock
, flags
);
2303 dprintk(KERN_DEBUG
"%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2304 dev
->name
, entries
, tx_flags_extra
);
2307 for (j
=0; j
<64; j
++) {
2309 dprintk("\n%03x:", j
);
2310 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2315 dev
->trans_start
= jiffies
;
2316 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2317 return NETDEV_TX_OK
;
2320 static inline void nv_tx_flip_ownership(struct net_device
*dev
)
2322 struct fe_priv
*np
= netdev_priv(dev
);
2324 np
->tx_pkts_in_progress
--;
2325 if (np
->tx_change_owner
) {
2326 np
->tx_change_owner
->first_tx_desc
->flaglen
|=
2327 cpu_to_le32(NV_TX2_VALID
);
2328 np
->tx_pkts_in_progress
++;
2330 np
->tx_change_owner
= np
->tx_change_owner
->next_tx_ctx
;
2331 if (np
->tx_change_owner
== np
->tx_end_flip
)
2332 np
->tx_change_owner
= NULL
;
2334 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2339 * nv_tx_done: check for completed packets, release the skbs.
2341 * Caller must own np->lock.
2343 static void nv_tx_done(struct net_device
*dev
)
2345 struct fe_priv
*np
= netdev_priv(dev
);
2347 struct ring_desc
* orig_get_tx
= np
->get_tx
.orig
;
2349 while ((np
->get_tx
.orig
!= np
->put_tx
.orig
) &&
2350 !((flags
= le32_to_cpu(np
->get_tx
.orig
->flaglen
)) & NV_TX_VALID
)) {
2352 dprintk(KERN_DEBUG
"%s: nv_tx_done: flags 0x%x.\n",
2355 pci_unmap_page(np
->pci_dev
, np
->get_tx_ctx
->dma
,
2356 np
->get_tx_ctx
->dma_len
,
2358 np
->get_tx_ctx
->dma
= 0;
2360 if (np
->desc_ver
== DESC_VER_1
) {
2361 if (flags
& NV_TX_LASTPACKET
) {
2362 if (flags
& NV_TX_ERROR
) {
2363 if (flags
& NV_TX_UNDERFLOW
)
2364 dev
->stats
.tx_fifo_errors
++;
2365 if (flags
& NV_TX_CARRIERLOST
)
2366 dev
->stats
.tx_carrier_errors
++;
2367 if ((flags
& NV_TX_RETRYERROR
) && !(flags
& NV_TX_RETRYCOUNT_MASK
))
2368 nv_legacybackoff_reseed(dev
);
2369 dev
->stats
.tx_errors
++;
2371 dev
->stats
.tx_packets
++;
2372 dev
->stats
.tx_bytes
+= np
->get_tx_ctx
->skb
->len
;
2374 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2375 np
->get_tx_ctx
->skb
= NULL
;
2378 if (flags
& NV_TX2_LASTPACKET
) {
2379 if (flags
& NV_TX2_ERROR
) {
2380 if (flags
& NV_TX2_UNDERFLOW
)
2381 dev
->stats
.tx_fifo_errors
++;
2382 if (flags
& NV_TX2_CARRIERLOST
)
2383 dev
->stats
.tx_carrier_errors
++;
2384 if ((flags
& NV_TX2_RETRYERROR
) && !(flags
& NV_TX2_RETRYCOUNT_MASK
))
2385 nv_legacybackoff_reseed(dev
);
2386 dev
->stats
.tx_errors
++;
2388 dev
->stats
.tx_packets
++;
2389 dev
->stats
.tx_bytes
+= np
->get_tx_ctx
->skb
->len
;
2391 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2392 np
->get_tx_ctx
->skb
= NULL
;
2395 if (unlikely(np
->get_tx
.orig
++ == np
->last_tx
.orig
))
2396 np
->get_tx
.orig
= np
->first_tx
.orig
;
2397 if (unlikely(np
->get_tx_ctx
++ == np
->last_tx_ctx
))
2398 np
->get_tx_ctx
= np
->first_tx_ctx
;
2400 if (unlikely((np
->tx_stop
== 1) && (np
->get_tx
.orig
!= orig_get_tx
))) {
2402 netif_wake_queue(dev
);
2406 static void nv_tx_done_optimized(struct net_device
*dev
, int limit
)
2408 struct fe_priv
*np
= netdev_priv(dev
);
2410 struct ring_desc_ex
* orig_get_tx
= np
->get_tx
.ex
;
2412 while ((np
->get_tx
.ex
!= np
->put_tx
.ex
) &&
2413 !((flags
= le32_to_cpu(np
->get_tx
.ex
->flaglen
)) & NV_TX_VALID
) &&
2416 dprintk(KERN_DEBUG
"%s: nv_tx_done_optimized: flags 0x%x.\n",
2419 pci_unmap_page(np
->pci_dev
, np
->get_tx_ctx
->dma
,
2420 np
->get_tx_ctx
->dma_len
,
2422 np
->get_tx_ctx
->dma
= 0;
2424 if (flags
& NV_TX2_LASTPACKET
) {
2425 if (!(flags
& NV_TX2_ERROR
))
2426 dev
->stats
.tx_packets
++;
2428 if ((flags
& NV_TX2_RETRYERROR
) && !(flags
& NV_TX2_RETRYCOUNT_MASK
)) {
2429 if (np
->driver_data
& DEV_HAS_GEAR_MODE
)
2430 nv_gear_backoff_reseed(dev
);
2432 nv_legacybackoff_reseed(dev
);
2436 dev_kfree_skb_any(np
->get_tx_ctx
->skb
);
2437 np
->get_tx_ctx
->skb
= NULL
;
2440 nv_tx_flip_ownership(dev
);
2443 if (unlikely(np
->get_tx
.ex
++ == np
->last_tx
.ex
))
2444 np
->get_tx
.ex
= np
->first_tx
.ex
;
2445 if (unlikely(np
->get_tx_ctx
++ == np
->last_tx_ctx
))
2446 np
->get_tx_ctx
= np
->first_tx_ctx
;
2448 if (unlikely((np
->tx_stop
== 1) && (np
->get_tx
.ex
!= orig_get_tx
))) {
2450 netif_wake_queue(dev
);
2455 * nv_tx_timeout: dev->tx_timeout function
2456 * Called with netif_tx_lock held.
2458 static void nv_tx_timeout(struct net_device
*dev
)
2460 struct fe_priv
*np
= netdev_priv(dev
);
2461 u8 __iomem
*base
= get_hwbase(dev
);
2464 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
2465 status
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
2467 status
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
2469 printk(KERN_INFO
"%s: Got tx_timeout. irq: %08x\n", dev
->name
, status
);
2474 printk(KERN_INFO
"%s: Ring at %lx\n",
2475 dev
->name
, (unsigned long)np
->ring_addr
);
2476 printk(KERN_INFO
"%s: Dumping tx registers\n", dev
->name
);
2477 for (i
=0;i
<=np
->register_size
;i
+= 32) {
2478 printk(KERN_INFO
"%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2480 readl(base
+ i
+ 0), readl(base
+ i
+ 4),
2481 readl(base
+ i
+ 8), readl(base
+ i
+ 12),
2482 readl(base
+ i
+ 16), readl(base
+ i
+ 20),
2483 readl(base
+ i
+ 24), readl(base
+ i
+ 28));
2485 printk(KERN_INFO
"%s: Dumping tx ring\n", dev
->name
);
2486 for (i
=0;i
<np
->tx_ring_size
;i
+= 4) {
2487 if (!nv_optimized(np
)) {
2488 printk(KERN_INFO
"%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2490 le32_to_cpu(np
->tx_ring
.orig
[i
].buf
),
2491 le32_to_cpu(np
->tx_ring
.orig
[i
].flaglen
),
2492 le32_to_cpu(np
->tx_ring
.orig
[i
+1].buf
),
2493 le32_to_cpu(np
->tx_ring
.orig
[i
+1].flaglen
),
2494 le32_to_cpu(np
->tx_ring
.orig
[i
+2].buf
),
2495 le32_to_cpu(np
->tx_ring
.orig
[i
+2].flaglen
),
2496 le32_to_cpu(np
->tx_ring
.orig
[i
+3].buf
),
2497 le32_to_cpu(np
->tx_ring
.orig
[i
+3].flaglen
));
2499 printk(KERN_INFO
"%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2501 le32_to_cpu(np
->tx_ring
.ex
[i
].bufhigh
),
2502 le32_to_cpu(np
->tx_ring
.ex
[i
].buflow
),
2503 le32_to_cpu(np
->tx_ring
.ex
[i
].flaglen
),
2504 le32_to_cpu(np
->tx_ring
.ex
[i
+1].bufhigh
),
2505 le32_to_cpu(np
->tx_ring
.ex
[i
+1].buflow
),
2506 le32_to_cpu(np
->tx_ring
.ex
[i
+1].flaglen
),
2507 le32_to_cpu(np
->tx_ring
.ex
[i
+2].bufhigh
),
2508 le32_to_cpu(np
->tx_ring
.ex
[i
+2].buflow
),
2509 le32_to_cpu(np
->tx_ring
.ex
[i
+2].flaglen
),
2510 le32_to_cpu(np
->tx_ring
.ex
[i
+3].bufhigh
),
2511 le32_to_cpu(np
->tx_ring
.ex
[i
+3].buflow
),
2512 le32_to_cpu(np
->tx_ring
.ex
[i
+3].flaglen
));
2517 spin_lock_irq(&np
->lock
);
2519 /* 1) stop tx engine */
2522 /* 2) check that the packets were not sent already: */
2523 if (!nv_optimized(np
))
2526 nv_tx_done_optimized(dev
, np
->tx_ring_size
);
2528 /* 3) if there are dead entries: clear everything */
2529 if (np
->get_tx_ctx
!= np
->put_tx_ctx
) {
2530 printk(KERN_DEBUG
"%s: tx_timeout: dead entries!\n", dev
->name
);
2533 setup_hw_rings(dev
, NV_SETUP_TX_RING
);
2536 netif_wake_queue(dev
);
2538 /* 4) restart tx engine */
2540 spin_unlock_irq(&np
->lock
);
2544 * Called when the nic notices a mismatch between the actual data len on the
2545 * wire and the len indicated in the 802 header
2547 static int nv_getlen(struct net_device
*dev
, void *packet
, int datalen
)
2549 int hdrlen
; /* length of the 802 header */
2550 int protolen
; /* length as stored in the proto field */
2552 /* 1) calculate len according to header */
2553 if ( ((struct vlan_ethhdr
*)packet
)->h_vlan_proto
== htons(ETH_P_8021Q
)) {
2554 protolen
= ntohs( ((struct vlan_ethhdr
*)packet
)->h_vlan_encapsulated_proto
);
2557 protolen
= ntohs( ((struct ethhdr
*)packet
)->h_proto
);
2560 dprintk(KERN_DEBUG
"%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2561 dev
->name
, datalen
, protolen
, hdrlen
);
2562 if (protolen
> ETH_DATA_LEN
)
2563 return datalen
; /* Value in proto field not a len, no checks possible */
2566 /* consistency checks: */
2567 if (datalen
> ETH_ZLEN
) {
2568 if (datalen
>= protolen
) {
2569 /* more data on wire than in 802 header, trim of
2572 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
2573 dev
->name
, protolen
);
2576 /* less data on wire than mentioned in header.
2577 * Discard the packet.
2579 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding long packet.\n",
2584 /* short packet. Accept only if 802 values are also short */
2585 if (protolen
> ETH_ZLEN
) {
2586 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding short packet.\n",
2590 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
2591 dev
->name
, datalen
);
2596 static int nv_rx_process(struct net_device
*dev
, int limit
)
2598 struct fe_priv
*np
= netdev_priv(dev
);
2601 struct sk_buff
*skb
;
2604 while((np
->get_rx
.orig
!= np
->put_rx
.orig
) &&
2605 !((flags
= le32_to_cpu(np
->get_rx
.orig
->flaglen
)) & NV_RX_AVAIL
) &&
2606 (rx_work
< limit
)) {
2608 dprintk(KERN_DEBUG
"%s: nv_rx_process: flags 0x%x.\n",
2612 * the packet is for us - immediately tear down the pci mapping.
2613 * TODO: check if a prefetch of the first cacheline improves
2616 pci_unmap_single(np
->pci_dev
, np
->get_rx_ctx
->dma
,
2617 np
->get_rx_ctx
->dma_len
,
2618 PCI_DMA_FROMDEVICE
);
2619 skb
= np
->get_rx_ctx
->skb
;
2620 np
->get_rx_ctx
->skb
= NULL
;
2624 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",flags
);
2625 for (j
=0; j
<64; j
++) {
2627 dprintk("\n%03x:", j
);
2628 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2632 /* look at what we actually got: */
2633 if (np
->desc_ver
== DESC_VER_1
) {
2634 if (likely(flags
& NV_RX_DESCRIPTORVALID
)) {
2635 len
= flags
& LEN_MASK_V1
;
2636 if (unlikely(flags
& NV_RX_ERROR
)) {
2637 if ((flags
& NV_RX_ERROR_MASK
) == NV_RX_ERROR4
) {
2638 len
= nv_getlen(dev
, skb
->data
, len
);
2640 dev
->stats
.rx_errors
++;
2645 /* framing errors are soft errors */
2646 else if ((flags
& NV_RX_ERROR_MASK
) == NV_RX_FRAMINGERR
) {
2647 if (flags
& NV_RX_SUBSTRACT1
) {
2651 /* the rest are hard errors */
2653 if (flags
& NV_RX_MISSEDFRAME
)
2654 dev
->stats
.rx_missed_errors
++;
2655 if (flags
& NV_RX_CRCERR
)
2656 dev
->stats
.rx_crc_errors
++;
2657 if (flags
& NV_RX_OVERFLOW
)
2658 dev
->stats
.rx_over_errors
++;
2659 dev
->stats
.rx_errors
++;
2669 if (likely(flags
& NV_RX2_DESCRIPTORVALID
)) {
2670 len
= flags
& LEN_MASK_V2
;
2671 if (unlikely(flags
& NV_RX2_ERROR
)) {
2672 if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_ERROR4
) {
2673 len
= nv_getlen(dev
, skb
->data
, len
);
2675 dev
->stats
.rx_errors
++;
2680 /* framing errors are soft errors */
2681 else if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_FRAMINGERR
) {
2682 if (flags
& NV_RX2_SUBSTRACT1
) {
2686 /* the rest are hard errors */
2688 if (flags
& NV_RX2_CRCERR
)
2689 dev
->stats
.rx_crc_errors
++;
2690 if (flags
& NV_RX2_OVERFLOW
)
2691 dev
->stats
.rx_over_errors
++;
2692 dev
->stats
.rx_errors
++;
2697 if (((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_TCP
) || /*ip and tcp */
2698 ((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_UDP
)) /*ip and udp */
2699 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2705 /* got a valid packet - forward it to the network core */
2707 skb
->protocol
= eth_type_trans(skb
, dev
);
2708 dprintk(KERN_DEBUG
"%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2709 dev
->name
, len
, skb
->protocol
);
2710 #ifdef CONFIG_FORCEDETH_NAPI
2711 netif_receive_skb(skb
);
2715 dev
->last_rx
= jiffies
;
2716 dev
->stats
.rx_packets
++;
2717 dev
->stats
.rx_bytes
+= len
;
2719 if (unlikely(np
->get_rx
.orig
++ == np
->last_rx
.orig
))
2720 np
->get_rx
.orig
= np
->first_rx
.orig
;
2721 if (unlikely(np
->get_rx_ctx
++ == np
->last_rx_ctx
))
2722 np
->get_rx_ctx
= np
->first_rx_ctx
;
2730 static int nv_rx_process_optimized(struct net_device
*dev
, int limit
)
2732 struct fe_priv
*np
= netdev_priv(dev
);
2736 struct sk_buff
*skb
;
2739 while((np
->get_rx
.ex
!= np
->put_rx
.ex
) &&
2740 !((flags
= le32_to_cpu(np
->get_rx
.ex
->flaglen
)) & NV_RX2_AVAIL
) &&
2741 (rx_work
< limit
)) {
2743 dprintk(KERN_DEBUG
"%s: nv_rx_process_optimized: flags 0x%x.\n",
2747 * the packet is for us - immediately tear down the pci mapping.
2748 * TODO: check if a prefetch of the first cacheline improves
2751 pci_unmap_single(np
->pci_dev
, np
->get_rx_ctx
->dma
,
2752 np
->get_rx_ctx
->dma_len
,
2753 PCI_DMA_FROMDEVICE
);
2754 skb
= np
->get_rx_ctx
->skb
;
2755 np
->get_rx_ctx
->skb
= NULL
;
2759 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",flags
);
2760 for (j
=0; j
<64; j
++) {
2762 dprintk("\n%03x:", j
);
2763 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
2767 /* look at what we actually got: */
2768 if (likely(flags
& NV_RX2_DESCRIPTORVALID
)) {
2769 len
= flags
& LEN_MASK_V2
;
2770 if (unlikely(flags
& NV_RX2_ERROR
)) {
2771 if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_ERROR4
) {
2772 len
= nv_getlen(dev
, skb
->data
, len
);
2778 /* framing errors are soft errors */
2779 else if ((flags
& NV_RX2_ERROR_MASK
) == NV_RX2_FRAMINGERR
) {
2780 if (flags
& NV_RX2_SUBSTRACT1
) {
2784 /* the rest are hard errors */
2791 if (((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_TCP
) || /*ip and tcp */
2792 ((flags
& NV_RX2_CHECKSUMMASK
) == NV_RX2_CHECKSUM_IP_UDP
)) /*ip and udp */
2793 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2795 /* got a valid packet - forward it to the network core */
2797 skb
->protocol
= eth_type_trans(skb
, dev
);
2798 prefetch(skb
->data
);
2800 dprintk(KERN_DEBUG
"%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2801 dev
->name
, len
, skb
->protocol
);
2803 if (likely(!np
->vlangrp
)) {
2804 #ifdef CONFIG_FORCEDETH_NAPI
2805 netif_receive_skb(skb
);
2810 vlanflags
= le32_to_cpu(np
->get_rx
.ex
->buflow
);
2811 if (vlanflags
& NV_RX3_VLAN_TAG_PRESENT
) {
2812 #ifdef CONFIG_FORCEDETH_NAPI
2813 vlan_hwaccel_receive_skb(skb
, np
->vlangrp
,
2814 vlanflags
& NV_RX3_VLAN_TAG_MASK
);
2816 vlan_hwaccel_rx(skb
, np
->vlangrp
,
2817 vlanflags
& NV_RX3_VLAN_TAG_MASK
);
2820 #ifdef CONFIG_FORCEDETH_NAPI
2821 netif_receive_skb(skb
);
2828 dev
->last_rx
= jiffies
;
2829 dev
->stats
.rx_packets
++;
2830 dev
->stats
.rx_bytes
+= len
;
2835 if (unlikely(np
->get_rx
.ex
++ == np
->last_rx
.ex
))
2836 np
->get_rx
.ex
= np
->first_rx
.ex
;
2837 if (unlikely(np
->get_rx_ctx
++ == np
->last_rx_ctx
))
2838 np
->get_rx_ctx
= np
->first_rx_ctx
;
2846 static void set_bufsize(struct net_device
*dev
)
2848 struct fe_priv
*np
= netdev_priv(dev
);
2850 if (dev
->mtu
<= ETH_DATA_LEN
)
2851 np
->rx_buf_sz
= ETH_DATA_LEN
+ NV_RX_HEADERS
;
2853 np
->rx_buf_sz
= dev
->mtu
+ NV_RX_HEADERS
;
2857 * nv_change_mtu: dev->change_mtu function
2858 * Called with dev_base_lock held for read.
2860 static int nv_change_mtu(struct net_device
*dev
, int new_mtu
)
2862 struct fe_priv
*np
= netdev_priv(dev
);
2865 if (new_mtu
< 64 || new_mtu
> np
->pkt_limit
)
2871 /* return early if the buffer sizes will not change */
2872 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
2874 if (old_mtu
== new_mtu
)
2877 /* synchronized against open : rtnl_lock() held by caller */
2878 if (netif_running(dev
)) {
2879 u8 __iomem
*base
= get_hwbase(dev
);
2881 * It seems that the nic preloads valid ring entries into an
2882 * internal buffer. The procedure for flushing everything is
2883 * guessed, there is probably a simpler approach.
2884 * Changing the MTU is a rare event, it shouldn't matter.
2886 nv_disable_irq(dev
);
2887 netif_tx_lock_bh(dev
);
2888 netif_addr_lock(dev
);
2889 spin_lock(&np
->lock
);
2893 /* drain rx queue */
2895 /* reinit driver view of the rx queue */
2897 if (nv_init_ring(dev
)) {
2898 if (!np
->in_shutdown
)
2899 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2901 /* reinit nic view of the rx queue */
2902 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
2903 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
2904 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
2905 base
+ NvRegRingSizes
);
2907 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2910 /* restart rx engine */
2912 spin_unlock(&np
->lock
);
2913 netif_addr_unlock(dev
);
2914 netif_tx_unlock_bh(dev
);
2920 static void nv_copy_mac_to_hw(struct net_device
*dev
)
2922 u8 __iomem
*base
= get_hwbase(dev
);
2925 mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
2926 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
2927 mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
2929 writel(mac
[0], base
+ NvRegMacAddrA
);
2930 writel(mac
[1], base
+ NvRegMacAddrB
);
2934 * nv_set_mac_address: dev->set_mac_address function
2935 * Called with rtnl_lock() held.
2937 static int nv_set_mac_address(struct net_device
*dev
, void *addr
)
2939 struct fe_priv
*np
= netdev_priv(dev
);
2940 struct sockaddr
*macaddr
= (struct sockaddr
*)addr
;
2942 if (!is_valid_ether_addr(macaddr
->sa_data
))
2943 return -EADDRNOTAVAIL
;
2945 /* synchronized against open : rtnl_lock() held by caller */
2946 memcpy(dev
->dev_addr
, macaddr
->sa_data
, ETH_ALEN
);
2948 if (netif_running(dev
)) {
2949 netif_tx_lock_bh(dev
);
2950 netif_addr_lock(dev
);
2951 spin_lock_irq(&np
->lock
);
2953 /* stop rx engine */
2956 /* set mac address */
2957 nv_copy_mac_to_hw(dev
);
2959 /* restart rx engine */
2961 spin_unlock_irq(&np
->lock
);
2962 netif_addr_unlock(dev
);
2963 netif_tx_unlock_bh(dev
);
2965 nv_copy_mac_to_hw(dev
);
2971 * nv_set_multicast: dev->set_multicast function
2972 * Called with netif_tx_lock held.
2974 static void nv_set_multicast(struct net_device
*dev
)
2976 struct fe_priv
*np
= netdev_priv(dev
);
2977 u8 __iomem
*base
= get_hwbase(dev
);
2980 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & NVREG_PFF_PAUSE_RX
;
2982 memset(addr
, 0, sizeof(addr
));
2983 memset(mask
, 0, sizeof(mask
));
2985 if (dev
->flags
& IFF_PROMISC
) {
2986 pff
|= NVREG_PFF_PROMISC
;
2988 pff
|= NVREG_PFF_MYADDR
;
2990 if (dev
->flags
& IFF_ALLMULTI
|| dev
->mc_list
) {
2994 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0xffffffff;
2995 if (dev
->flags
& IFF_ALLMULTI
) {
2996 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0;
2998 struct dev_mc_list
*walk
;
3000 walk
= dev
->mc_list
;
3001 while (walk
!= NULL
) {
3003 a
= le32_to_cpu(*(__le32
*) walk
->dmi_addr
);
3004 b
= le16_to_cpu(*(__le16
*) (&walk
->dmi_addr
[4]));
3012 addr
[0] = alwaysOn
[0];
3013 addr
[1] = alwaysOn
[1];
3014 mask
[0] = alwaysOn
[0] | alwaysOff
[0];
3015 mask
[1] = alwaysOn
[1] | alwaysOff
[1];
3017 mask
[0] = NVREG_MCASTMASKA_NONE
;
3018 mask
[1] = NVREG_MCASTMASKB_NONE
;
3021 addr
[0] |= NVREG_MCASTADDRA_FORCE
;
3022 pff
|= NVREG_PFF_ALWAYS
;
3023 spin_lock_irq(&np
->lock
);
3025 writel(addr
[0], base
+ NvRegMulticastAddrA
);
3026 writel(addr
[1], base
+ NvRegMulticastAddrB
);
3027 writel(mask
[0], base
+ NvRegMulticastMaskA
);
3028 writel(mask
[1], base
+ NvRegMulticastMaskB
);
3029 writel(pff
, base
+ NvRegPacketFilterFlags
);
3030 dprintk(KERN_INFO
"%s: reconfiguration for multicast lists.\n",
3033 spin_unlock_irq(&np
->lock
);
3036 static void nv_update_pause(struct net_device
*dev
, u32 pause_flags
)
3038 struct fe_priv
*np
= netdev_priv(dev
);
3039 u8 __iomem
*base
= get_hwbase(dev
);
3041 np
->pause_flags
&= ~(NV_PAUSEFRAME_TX_ENABLE
| NV_PAUSEFRAME_RX_ENABLE
);
3043 if (np
->pause_flags
& NV_PAUSEFRAME_RX_CAPABLE
) {
3044 u32 pff
= readl(base
+ NvRegPacketFilterFlags
) & ~NVREG_PFF_PAUSE_RX
;
3045 if (pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) {
3046 writel(pff
|NVREG_PFF_PAUSE_RX
, base
+ NvRegPacketFilterFlags
);
3047 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3049 writel(pff
, base
+ NvRegPacketFilterFlags
);
3052 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
) {
3053 u32 regmisc
= readl(base
+ NvRegMisc1
) & ~NVREG_MISC1_PAUSE_TX
;
3054 if (pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) {
3055 u32 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V1
;
3056 if (np
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V2
)
3057 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V2
;
3058 if (np
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V3
)
3059 pause_enable
= NVREG_TX_PAUSEFRAME_ENABLE_V3
;
3060 writel(pause_enable
, base
+ NvRegTxPauseFrame
);
3061 writel(regmisc
|NVREG_MISC1_PAUSE_TX
, base
+ NvRegMisc1
);
3062 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3064 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
3065 writel(regmisc
, base
+ NvRegMisc1
);
3071 * nv_update_linkspeed: Setup the MAC according to the link partner
3072 * @dev: Network device to be configured
3074 * The function queries the PHY and checks if there is a link partner.
3075 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3076 * set to 10 MBit HD.
3078 * The function returns 0 if there is no link partner and 1 if there is
3079 * a good link partner.
3081 static int nv_update_linkspeed(struct net_device
*dev
)
3083 struct fe_priv
*np
= netdev_priv(dev
);
3084 u8 __iomem
*base
= get_hwbase(dev
);
3087 int adv_lpa
, adv_pause
, lpa_pause
;
3088 int newls
= np
->linkspeed
;
3089 int newdup
= np
->duplex
;
3092 u32 control_1000
, status_1000
, phyreg
, pause_flags
, txreg
;
3096 /* BMSR_LSTATUS is latched, read it twice:
3097 * we want the current value.
3099 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3100 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
3102 if (!(mii_status
& BMSR_LSTATUS
)) {
3103 dprintk(KERN_DEBUG
"%s: no link detected by phy - falling back to 10HD.\n",
3105 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3111 if (np
->autoneg
== 0) {
3112 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
3113 dev
->name
, np
->fixed_mode
);
3114 if (np
->fixed_mode
& LPA_100FULL
) {
3115 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3117 } else if (np
->fixed_mode
& LPA_100HALF
) {
3118 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3120 } else if (np
->fixed_mode
& LPA_10FULL
) {
3121 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3124 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3130 /* check auto negotiation is complete */
3131 if (!(mii_status
& BMSR_ANEGCOMPLETE
)) {
3132 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3133 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3136 dprintk(KERN_DEBUG
"%s: autoneg not completed - falling back to 10HD.\n", dev
->name
);
3140 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
3141 lpa
= mii_rw(dev
, np
->phyaddr
, MII_LPA
, MII_READ
);
3142 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
3143 dev
->name
, adv
, lpa
);
3146 if (np
->gigabit
== PHY_GIGABIT
) {
3147 control_1000
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
3148 status_1000
= mii_rw(dev
, np
->phyaddr
, MII_STAT1000
, MII_READ
);
3150 if ((control_1000
& ADVERTISE_1000FULL
) &&
3151 (status_1000
& LPA_1000FULL
)) {
3152 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: GBit ethernet detected.\n",
3154 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_1000
;
3160 /* FIXME: handle parallel detection properly */
3161 adv_lpa
= lpa
& adv
;
3162 if (adv_lpa
& LPA_100FULL
) {
3163 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3165 } else if (adv_lpa
& LPA_100HALF
) {
3166 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
3168 } else if (adv_lpa
& LPA_10FULL
) {
3169 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3171 } else if (adv_lpa
& LPA_10HALF
) {
3172 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3175 dprintk(KERN_DEBUG
"%s: bad ability %04x - falling back to 10HD.\n", dev
->name
, adv_lpa
);
3176 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3181 if (np
->duplex
== newdup
&& np
->linkspeed
== newls
)
3184 dprintk(KERN_INFO
"%s: changing link setting from %d/%d to %d/%d.\n",
3185 dev
->name
, np
->linkspeed
, np
->duplex
, newls
, newdup
);
3187 np
->duplex
= newdup
;
3188 np
->linkspeed
= newls
;
3190 /* The transmitter and receiver must be restarted for safe update */
3191 if (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_START
) {
3192 txrxFlags
|= NV_RESTART_TX
;
3195 if (readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) {
3196 txrxFlags
|= NV_RESTART_RX
;
3200 if (np
->gigabit
== PHY_GIGABIT
) {
3201 phyreg
= readl(base
+ NvRegSlotTime
);
3202 phyreg
&= ~(0x3FF00);
3203 if (((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
) ||
3204 ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
))
3205 phyreg
|= NVREG_SLOTTIME_10_100_FULL
;
3206 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
3207 phyreg
|= NVREG_SLOTTIME_1000_FULL
;
3208 writel(phyreg
, base
+ NvRegSlotTime
);
3211 phyreg
= readl(base
+ NvRegPhyInterface
);
3212 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
3213 if (np
->duplex
== 0)
3215 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
3217 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
3219 writel(phyreg
, base
+ NvRegPhyInterface
);
3221 phy_exp
= mii_rw(dev
, np
->phyaddr
, MII_EXPANSION
, MII_READ
) & EXPANSION_NWAY
; /* autoneg capable */
3222 if (phyreg
& PHY_RGMII
) {
3223 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
) {
3224 txreg
= NVREG_TX_DEFERRAL_RGMII_1000
;
3226 if (!phy_exp
&& !np
->duplex
&& (np
->driver_data
& DEV_HAS_COLLISION_FIX
)) {
3227 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_10
)
3228 txreg
= NVREG_TX_DEFERRAL_RGMII_STRETCH_10
;
3230 txreg
= NVREG_TX_DEFERRAL_RGMII_STRETCH_100
;
3232 txreg
= NVREG_TX_DEFERRAL_RGMII_10_100
;
3236 if (!phy_exp
&& !np
->duplex
&& (np
->driver_data
& DEV_HAS_COLLISION_FIX
))
3237 txreg
= NVREG_TX_DEFERRAL_MII_STRETCH
;
3239 txreg
= NVREG_TX_DEFERRAL_DEFAULT
;
3241 writel(txreg
, base
+ NvRegTxDeferral
);
3243 if (np
->desc_ver
== DESC_VER_1
) {
3244 txreg
= NVREG_TX_WM_DESC1_DEFAULT
;
3246 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
3247 txreg
= NVREG_TX_WM_DESC2_3_1000
;
3249 txreg
= NVREG_TX_WM_DESC2_3_DEFAULT
;
3251 writel(txreg
, base
+ NvRegTxWatermark
);
3253 writel(NVREG_MISC1_FORCE
| ( np
->duplex
? 0 : NVREG_MISC1_HD
),
3256 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
3260 /* setup pause frame */
3261 if (np
->duplex
!= 0) {
3262 if (np
->autoneg
&& np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) {
3263 adv_pause
= adv
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
3264 lpa_pause
= lpa
& (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
);
3266 switch (adv_pause
) {
3267 case ADVERTISE_PAUSE_CAP
:
3268 if (lpa_pause
& LPA_PAUSE_CAP
) {
3269 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3270 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3271 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3274 case ADVERTISE_PAUSE_ASYM
:
3275 if (lpa_pause
== (LPA_PAUSE_CAP
| LPA_PAUSE_ASYM
))
3277 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3280 case ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
:
3281 if (lpa_pause
& LPA_PAUSE_CAP
)
3283 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3284 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
3285 pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
3287 if (lpa_pause
== LPA_PAUSE_ASYM
)
3289 pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
3294 pause_flags
= np
->pause_flags
;
3297 nv_update_pause(dev
, pause_flags
);
3299 if (txrxFlags
& NV_RESTART_TX
)
3301 if (txrxFlags
& NV_RESTART_RX
)
3307 static void nv_linkchange(struct net_device
*dev
)
3309 if (nv_update_linkspeed(dev
)) {
3310 if (!netif_carrier_ok(dev
)) {
3311 netif_carrier_on(dev
);
3312 printk(KERN_INFO
"%s: link up.\n", dev
->name
);
3316 if (netif_carrier_ok(dev
)) {
3317 netif_carrier_off(dev
);
3318 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
3324 static void nv_link_irq(struct net_device
*dev
)
3326 u8 __iomem
*base
= get_hwbase(dev
);
3329 miistat
= readl(base
+ NvRegMIIStatus
);
3330 writel(NVREG_MIISTAT_LINKCHANGE
, base
+ NvRegMIIStatus
);
3331 dprintk(KERN_INFO
"%s: link change irq, status 0x%x.\n", dev
->name
, miistat
);
3333 if (miistat
& (NVREG_MIISTAT_LINKCHANGE
))
3335 dprintk(KERN_DEBUG
"%s: link change notification done.\n", dev
->name
);
3338 static void nv_msi_workaround(struct fe_priv
*np
)
3341 /* Need to toggle the msi irq mask within the ethernet device,
3342 * otherwise, future interrupts will not be detected.
3344 if (np
->msi_flags
& NV_MSI_ENABLED
) {
3345 u8 __iomem
*base
= np
->base
;
3347 writel(0, base
+ NvRegMSIIrqMask
);
3348 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
3352 static irqreturn_t
nv_nic_irq(int foo
, void *data
)
3354 struct net_device
*dev
= (struct net_device
*) data
;
3355 struct fe_priv
*np
= netdev_priv(dev
);
3356 u8 __iomem
*base
= get_hwbase(dev
);
3360 dprintk(KERN_DEBUG
"%s: nv_nic_irq\n", dev
->name
);
3363 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3364 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
3365 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
3367 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
3368 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
3370 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3371 if (!(events
& np
->irqmask
))
3374 nv_msi_workaround(np
);
3376 spin_lock(&np
->lock
);
3378 spin_unlock(&np
->lock
);
3380 #ifdef CONFIG_FORCEDETH_NAPI
3381 if (events
& NVREG_IRQ_RX_ALL
) {
3382 netif_rx_schedule(dev
, &np
->napi
);
3384 /* Disable furthur receive irq's */
3385 spin_lock(&np
->lock
);
3386 np
->irqmask
&= ~NVREG_IRQ_RX_ALL
;
3388 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
3389 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3391 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3392 spin_unlock(&np
->lock
);
3395 if (nv_rx_process(dev
, RX_WORK_PER_LOOP
)) {
3396 if (unlikely(nv_alloc_rx(dev
))) {
3397 spin_lock(&np
->lock
);
3398 if (!np
->in_shutdown
)
3399 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3400 spin_unlock(&np
->lock
);
3404 if (unlikely(events
& NVREG_IRQ_LINK
)) {
3405 spin_lock(&np
->lock
);
3407 spin_unlock(&np
->lock
);
3409 if (unlikely(np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
))) {
3410 spin_lock(&np
->lock
);
3412 spin_unlock(&np
->lock
);
3413 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3415 if (unlikely(events
& (NVREG_IRQ_TX_ERR
))) {
3416 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
3419 if (unlikely(events
& (NVREG_IRQ_UNKNOWN
))) {
3420 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
3423 if (unlikely(events
& NVREG_IRQ_RECOVER_ERROR
)) {
3424 spin_lock(&np
->lock
);
3425 /* disable interrupts on the nic */
3426 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3427 writel(0, base
+ NvRegIrqMask
);
3429 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3432 if (!np
->in_shutdown
) {
3433 np
->nic_poll_irq
= np
->irqmask
;
3434 np
->recover_error
= 1;
3435 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3437 spin_unlock(&np
->lock
);
3440 if (unlikely(i
> max_interrupt_work
)) {
3441 spin_lock(&np
->lock
);
3442 /* disable interrupts on the nic */
3443 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3444 writel(0, base
+ NvRegIrqMask
);
3446 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3449 if (!np
->in_shutdown
) {
3450 np
->nic_poll_irq
= np
->irqmask
;
3451 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3453 spin_unlock(&np
->lock
);
3454 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq.\n", dev
->name
, i
);
3459 dprintk(KERN_DEBUG
"%s: nv_nic_irq completed\n", dev
->name
);
3461 return IRQ_RETVAL(i
);
3465 * All _optimized functions are used to help increase performance
3466 * (reduce CPU and increase throughput). They use descripter version 3,
3467 * compiler directives, and reduce memory accesses.
3469 static irqreturn_t
nv_nic_irq_optimized(int foo
, void *data
)
3471 struct net_device
*dev
= (struct net_device
*) data
;
3472 struct fe_priv
*np
= netdev_priv(dev
);
3473 u8 __iomem
*base
= get_hwbase(dev
);
3477 dprintk(KERN_DEBUG
"%s: nv_nic_irq_optimized\n", dev
->name
);
3480 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3481 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
3482 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
3484 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
3485 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
3487 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3488 if (!(events
& np
->irqmask
))
3491 nv_msi_workaround(np
);
3493 spin_lock(&np
->lock
);
3494 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3495 spin_unlock(&np
->lock
);
3497 #ifdef CONFIG_FORCEDETH_NAPI
3498 if (events
& NVREG_IRQ_RX_ALL
) {
3499 netif_rx_schedule(dev
, &np
->napi
);
3501 /* Disable furthur receive irq's */
3502 spin_lock(&np
->lock
);
3503 np
->irqmask
&= ~NVREG_IRQ_RX_ALL
;
3505 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
3506 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3508 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3509 spin_unlock(&np
->lock
);
3512 if (nv_rx_process_optimized(dev
, RX_WORK_PER_LOOP
)) {
3513 if (unlikely(nv_alloc_rx_optimized(dev
))) {
3514 spin_lock(&np
->lock
);
3515 if (!np
->in_shutdown
)
3516 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3517 spin_unlock(&np
->lock
);
3521 if (unlikely(events
& NVREG_IRQ_LINK
)) {
3522 spin_lock(&np
->lock
);
3524 spin_unlock(&np
->lock
);
3526 if (unlikely(np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
))) {
3527 spin_lock(&np
->lock
);
3529 spin_unlock(&np
->lock
);
3530 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3532 if (unlikely(events
& (NVREG_IRQ_TX_ERR
))) {
3533 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
3536 if (unlikely(events
& (NVREG_IRQ_UNKNOWN
))) {
3537 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
3540 if (unlikely(events
& NVREG_IRQ_RECOVER_ERROR
)) {
3541 spin_lock(&np
->lock
);
3542 /* disable interrupts on the nic */
3543 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3544 writel(0, base
+ NvRegIrqMask
);
3546 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3549 if (!np
->in_shutdown
) {
3550 np
->nic_poll_irq
= np
->irqmask
;
3551 np
->recover_error
= 1;
3552 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3554 spin_unlock(&np
->lock
);
3558 if (unlikely(i
> max_interrupt_work
)) {
3559 spin_lock(&np
->lock
);
3560 /* disable interrupts on the nic */
3561 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
3562 writel(0, base
+ NvRegIrqMask
);
3564 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3567 if (!np
->in_shutdown
) {
3568 np
->nic_poll_irq
= np
->irqmask
;
3569 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3571 spin_unlock(&np
->lock
);
3572 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq.\n", dev
->name
, i
);
3577 dprintk(KERN_DEBUG
"%s: nv_nic_irq_optimized completed\n", dev
->name
);
3579 return IRQ_RETVAL(i
);
3582 static irqreturn_t
nv_nic_irq_tx(int foo
, void *data
)
3584 struct net_device
*dev
= (struct net_device
*) data
;
3585 struct fe_priv
*np
= netdev_priv(dev
);
3586 u8 __iomem
*base
= get_hwbase(dev
);
3589 unsigned long flags
;
3591 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx\n", dev
->name
);
3594 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_TX_ALL
;
3595 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegMSIXIrqStatus
);
3596 dprintk(KERN_DEBUG
"%s: tx irq: %08x\n", dev
->name
, events
);
3597 if (!(events
& np
->irqmask
))
3600 spin_lock_irqsave(&np
->lock
, flags
);
3601 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3602 spin_unlock_irqrestore(&np
->lock
, flags
);
3604 if (unlikely(events
& (NVREG_IRQ_TX_ERR
))) {
3605 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
3608 if (unlikely(i
> max_interrupt_work
)) {
3609 spin_lock_irqsave(&np
->lock
, flags
);
3610 /* disable interrupts on the nic */
3611 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegIrqMask
);
3614 if (!np
->in_shutdown
) {
3615 np
->nic_poll_irq
|= NVREG_IRQ_TX_ALL
;
3616 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3618 spin_unlock_irqrestore(&np
->lock
, flags
);
3619 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev
->name
, i
);
3624 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx completed\n", dev
->name
);
3626 return IRQ_RETVAL(i
);
3629 #ifdef CONFIG_FORCEDETH_NAPI
3630 static int nv_napi_poll(struct napi_struct
*napi
, int budget
)
3632 struct fe_priv
*np
= container_of(napi
, struct fe_priv
, napi
);
3633 struct net_device
*dev
= np
->dev
;
3634 u8 __iomem
*base
= get_hwbase(dev
);
3635 unsigned long flags
;
3638 if (!nv_optimized(np
)) {
3639 pkts
= nv_rx_process(dev
, budget
);
3640 retcode
= nv_alloc_rx(dev
);
3642 pkts
= nv_rx_process_optimized(dev
, budget
);
3643 retcode
= nv_alloc_rx_optimized(dev
);
3647 spin_lock_irqsave(&np
->lock
, flags
);
3648 if (!np
->in_shutdown
)
3649 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3650 spin_unlock_irqrestore(&np
->lock
, flags
);
3653 if (pkts
< budget
) {
3654 /* re-enable receive interrupts */
3655 spin_lock_irqsave(&np
->lock
, flags
);
3657 __netif_rx_complete(dev
, napi
);
3659 np
->irqmask
|= NVREG_IRQ_RX_ALL
;
3660 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
3661 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3663 writel(np
->irqmask
, base
+ NvRegIrqMask
);
3665 spin_unlock_irqrestore(&np
->lock
, flags
);
3671 #ifdef CONFIG_FORCEDETH_NAPI
3672 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
)
3674 struct net_device
*dev
= (struct net_device
*) data
;
3675 struct fe_priv
*np
= netdev_priv(dev
);
3676 u8 __iomem
*base
= get_hwbase(dev
);
3679 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
3680 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegMSIXIrqStatus
);
3683 netif_rx_schedule(dev
, &np
->napi
);
3684 /* disable receive interrupts on the nic */
3685 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3691 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
)
3693 struct net_device
*dev
= (struct net_device
*) data
;
3694 struct fe_priv
*np
= netdev_priv(dev
);
3695 u8 __iomem
*base
= get_hwbase(dev
);
3698 unsigned long flags
;
3700 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx\n", dev
->name
);
3703 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
3704 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegMSIXIrqStatus
);
3705 dprintk(KERN_DEBUG
"%s: rx irq: %08x\n", dev
->name
, events
);
3706 if (!(events
& np
->irqmask
))
3709 if (nv_rx_process_optimized(dev
, RX_WORK_PER_LOOP
)) {
3710 if (unlikely(nv_alloc_rx_optimized(dev
))) {
3711 spin_lock_irqsave(&np
->lock
, flags
);
3712 if (!np
->in_shutdown
)
3713 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
3714 spin_unlock_irqrestore(&np
->lock
, flags
);
3718 if (unlikely(i
> max_interrupt_work
)) {
3719 spin_lock_irqsave(&np
->lock
, flags
);
3720 /* disable interrupts on the nic */
3721 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
3724 if (!np
->in_shutdown
) {
3725 np
->nic_poll_irq
|= NVREG_IRQ_RX_ALL
;
3726 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3728 spin_unlock_irqrestore(&np
->lock
, flags
);
3729 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev
->name
, i
);
3733 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx completed\n", dev
->name
);
3735 return IRQ_RETVAL(i
);
3739 static irqreturn_t
nv_nic_irq_other(int foo
, void *data
)
3741 struct net_device
*dev
= (struct net_device
*) data
;
3742 struct fe_priv
*np
= netdev_priv(dev
);
3743 u8 __iomem
*base
= get_hwbase(dev
);
3746 unsigned long flags
;
3748 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other\n", dev
->name
);
3751 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_OTHER
;
3752 writel(NVREG_IRQ_OTHER
, base
+ NvRegMSIXIrqStatus
);
3753 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3754 if (!(events
& np
->irqmask
))
3757 /* check tx in case we reached max loop limit in tx isr */
3758 spin_lock_irqsave(&np
->lock
, flags
);
3759 nv_tx_done_optimized(dev
, TX_WORK_PER_LOOP
);
3760 spin_unlock_irqrestore(&np
->lock
, flags
);
3762 if (events
& NVREG_IRQ_LINK
) {
3763 spin_lock_irqsave(&np
->lock
, flags
);
3765 spin_unlock_irqrestore(&np
->lock
, flags
);
3767 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
3768 spin_lock_irqsave(&np
->lock
, flags
);
3770 spin_unlock_irqrestore(&np
->lock
, flags
);
3771 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3773 if (events
& NVREG_IRQ_RECOVER_ERROR
) {
3774 spin_lock_irq(&np
->lock
);
3775 /* disable interrupts on the nic */
3776 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
3779 if (!np
->in_shutdown
) {
3780 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
3781 np
->recover_error
= 1;
3782 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3784 spin_unlock_irq(&np
->lock
);
3787 if (events
& (NVREG_IRQ_UNKNOWN
)) {
3788 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
3791 if (unlikely(i
> max_interrupt_work
)) {
3792 spin_lock_irqsave(&np
->lock
, flags
);
3793 /* disable interrupts on the nic */
3794 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
3797 if (!np
->in_shutdown
) {
3798 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
3799 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
3801 spin_unlock_irqrestore(&np
->lock
, flags
);
3802 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_other.\n", dev
->name
, i
);
3807 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other completed\n", dev
->name
);
3809 return IRQ_RETVAL(i
);
3812 static irqreturn_t
nv_nic_irq_test(int foo
, void *data
)
3814 struct net_device
*dev
= (struct net_device
*) data
;
3815 struct fe_priv
*np
= netdev_priv(dev
);
3816 u8 __iomem
*base
= get_hwbase(dev
);
3819 dprintk(KERN_DEBUG
"%s: nv_nic_irq_test\n", dev
->name
);
3821 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
3822 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
3823 writel(NVREG_IRQ_TIMER
, base
+ NvRegIrqStatus
);
3825 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
3826 writel(NVREG_IRQ_TIMER
, base
+ NvRegMSIXIrqStatus
);
3829 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
3830 if (!(events
& NVREG_IRQ_TIMER
))
3831 return IRQ_RETVAL(0);
3833 nv_msi_workaround(np
);
3835 spin_lock(&np
->lock
);
3837 spin_unlock(&np
->lock
);
3839 dprintk(KERN_DEBUG
"%s: nv_nic_irq_test completed\n", dev
->name
);
3841 return IRQ_RETVAL(1);
3844 static void set_msix_vector_map(struct net_device
*dev
, u32 vector
, u32 irqmask
)
3846 u8 __iomem
*base
= get_hwbase(dev
);
3850 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3851 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3852 * the remaining 8 interrupts.
3854 for (i
= 0; i
< 8; i
++) {
3855 if ((irqmask
>> i
) & 0x1) {
3856 msixmap
|= vector
<< (i
<< 2);
3859 writel(readl(base
+ NvRegMSIXMap0
) | msixmap
, base
+ NvRegMSIXMap0
);
3862 for (i
= 0; i
< 8; i
++) {
3863 if ((irqmask
>> (i
+ 8)) & 0x1) {
3864 msixmap
|= vector
<< (i
<< 2);
3867 writel(readl(base
+ NvRegMSIXMap1
) | msixmap
, base
+ NvRegMSIXMap1
);
3870 static int nv_request_irq(struct net_device
*dev
, int intr_test
)
3872 struct fe_priv
*np
= get_nvpriv(dev
);
3873 u8 __iomem
*base
= get_hwbase(dev
);
3876 irqreturn_t (*handler
)(int foo
, void *data
);
3879 handler
= nv_nic_irq_test
;
3881 if (nv_optimized(np
))
3882 handler
= nv_nic_irq_optimized
;
3884 handler
= nv_nic_irq
;
3887 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) {
3888 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
3889 np
->msi_x_entry
[i
].entry
= i
;
3891 if ((ret
= pci_enable_msix(np
->pci_dev
, np
->msi_x_entry
, (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
))) == 0) {
3892 np
->msi_flags
|= NV_MSI_X_ENABLED
;
3893 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
&& !intr_test
) {
3894 /* Request irq for rx handling */
3895 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, &nv_nic_irq_rx
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3896 printk(KERN_INFO
"forcedeth: request_irq failed for rx %d\n", ret
);
3897 pci_disable_msix(np
->pci_dev
);
3898 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3901 /* Request irq for tx handling */
3902 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, &nv_nic_irq_tx
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3903 printk(KERN_INFO
"forcedeth: request_irq failed for tx %d\n", ret
);
3904 pci_disable_msix(np
->pci_dev
);
3905 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3908 /* Request irq for link and timer handling */
3909 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
, &nv_nic_irq_other
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3910 printk(KERN_INFO
"forcedeth: request_irq failed for link %d\n", ret
);
3911 pci_disable_msix(np
->pci_dev
);
3912 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3915 /* map interrupts to their respective vector */
3916 writel(0, base
+ NvRegMSIXMap0
);
3917 writel(0, base
+ NvRegMSIXMap1
);
3918 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_RX
, NVREG_IRQ_RX_ALL
);
3919 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_TX
, NVREG_IRQ_TX_ALL
);
3920 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_OTHER
, NVREG_IRQ_OTHER
);
3922 /* Request irq for all interrupts */
3923 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3924 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
3925 pci_disable_msix(np
->pci_dev
);
3926 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3930 /* map interrupts to vector 0 */
3931 writel(0, base
+ NvRegMSIXMap0
);
3932 writel(0, base
+ NvRegMSIXMap1
);
3936 if (ret
!= 0 && np
->msi_flags
& NV_MSI_CAPABLE
) {
3937 if ((ret
= pci_enable_msi(np
->pci_dev
)) == 0) {
3938 np
->msi_flags
|= NV_MSI_ENABLED
;
3939 dev
->irq
= np
->pci_dev
->irq
;
3940 if (request_irq(np
->pci_dev
->irq
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0) {
3941 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
3942 pci_disable_msi(np
->pci_dev
);
3943 np
->msi_flags
&= ~NV_MSI_ENABLED
;
3944 dev
->irq
= np
->pci_dev
->irq
;
3948 /* map interrupts to vector 0 */
3949 writel(0, base
+ NvRegMSIMap0
);
3950 writel(0, base
+ NvRegMSIMap1
);
3951 /* enable msi vector 0 */
3952 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
3956 if (request_irq(np
->pci_dev
->irq
, handler
, IRQF_SHARED
, dev
->name
, dev
) != 0)
3963 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, dev
);
3965 free_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, dev
);
3970 static void nv_free_irq(struct net_device
*dev
)
3972 struct fe_priv
*np
= get_nvpriv(dev
);
3975 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
3976 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
3977 free_irq(np
->msi_x_entry
[i
].vector
, dev
);
3979 pci_disable_msix(np
->pci_dev
);
3980 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
3982 free_irq(np
->pci_dev
->irq
, dev
);
3983 if (np
->msi_flags
& NV_MSI_ENABLED
) {
3984 pci_disable_msi(np
->pci_dev
);
3985 np
->msi_flags
&= ~NV_MSI_ENABLED
;
3990 static void nv_do_nic_poll(unsigned long data
)
3992 struct net_device
*dev
= (struct net_device
*) data
;
3993 struct fe_priv
*np
= netdev_priv(dev
);
3994 u8 __iomem
*base
= get_hwbase(dev
);
3998 * First disable irq(s) and then
3999 * reenable interrupts on the nic, we have to do this before calling
4000 * nv_nic_irq because that may decide to do otherwise
4003 if (!using_multi_irqs(dev
)) {
4004 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
4005 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
4007 disable_irq_lockdep(np
->pci_dev
->irq
);
4010 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
4011 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
4012 mask
|= NVREG_IRQ_RX_ALL
;
4014 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
4015 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
4016 mask
|= NVREG_IRQ_TX_ALL
;
4018 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
4019 disable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
4020 mask
|= NVREG_IRQ_OTHER
;
4023 np
->nic_poll_irq
= 0;
4025 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4027 if (np
->recover_error
) {
4028 np
->recover_error
= 0;
4029 printk(KERN_INFO
"forcedeth: MAC in recoverable error state\n");
4030 if (netif_running(dev
)) {
4031 netif_tx_lock_bh(dev
);
4032 netif_addr_lock(dev
);
4033 spin_lock(&np
->lock
);
4037 /* drain rx queue */
4039 /* reinit driver view of the rx queue */
4041 if (nv_init_ring(dev
)) {
4042 if (!np
->in_shutdown
)
4043 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4045 /* reinit nic view of the rx queue */
4046 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4047 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4048 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4049 base
+ NvRegRingSizes
);
4051 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4054 /* restart rx engine */
4056 spin_unlock(&np
->lock
);
4057 netif_addr_unlock(dev
);
4058 netif_tx_unlock_bh(dev
);
4063 writel(mask
, base
+ NvRegIrqMask
);
4066 if (!using_multi_irqs(dev
)) {
4067 if (nv_optimized(np
))
4068 nv_nic_irq_optimized(0, dev
);
4071 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
4072 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
);
4074 enable_irq_lockdep(np
->pci_dev
->irq
);
4076 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
4077 nv_nic_irq_rx(0, dev
);
4078 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
4080 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
4081 nv_nic_irq_tx(0, dev
);
4082 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
4084 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
4085 nv_nic_irq_other(0, dev
);
4086 enable_irq_lockdep(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
4091 #ifdef CONFIG_NET_POLL_CONTROLLER
4092 static void nv_poll_controller(struct net_device
*dev
)
4094 nv_do_nic_poll((unsigned long) dev
);
4098 static void nv_do_stats_poll(unsigned long data
)
4100 struct net_device
*dev
= (struct net_device
*) data
;
4101 struct fe_priv
*np
= netdev_priv(dev
);
4103 nv_get_hw_stats(dev
);
4105 if (!np
->in_shutdown
)
4106 mod_timer(&np
->stats_poll
,
4107 round_jiffies(jiffies
+ STATS_INTERVAL
));
4110 static void nv_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
4112 struct fe_priv
*np
= netdev_priv(dev
);
4113 strcpy(info
->driver
, DRV_NAME
);
4114 strcpy(info
->version
, FORCEDETH_VERSION
);
4115 strcpy(info
->bus_info
, pci_name(np
->pci_dev
));
4118 static void nv_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
4120 struct fe_priv
*np
= netdev_priv(dev
);
4121 wolinfo
->supported
= WAKE_MAGIC
;
4123 spin_lock_irq(&np
->lock
);
4125 wolinfo
->wolopts
= WAKE_MAGIC
;
4126 spin_unlock_irq(&np
->lock
);
4129 static int nv_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
4131 struct fe_priv
*np
= netdev_priv(dev
);
4132 u8 __iomem
*base
= get_hwbase(dev
);
4135 if (wolinfo
->wolopts
== 0) {
4137 } else if (wolinfo
->wolopts
& WAKE_MAGIC
) {
4139 flags
= NVREG_WAKEUPFLAGS_ENABLE
;
4141 if (netif_running(dev
)) {
4142 spin_lock_irq(&np
->lock
);
4143 writel(flags
, base
+ NvRegWakeUpFlags
);
4144 spin_unlock_irq(&np
->lock
);
4149 static int nv_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
4151 struct fe_priv
*np
= netdev_priv(dev
);
4154 spin_lock_irq(&np
->lock
);
4155 ecmd
->port
= PORT_MII
;
4156 if (!netif_running(dev
)) {
4157 /* We do not track link speed / duplex setting if the
4158 * interface is disabled. Force a link check */
4159 if (nv_update_linkspeed(dev
)) {
4160 if (!netif_carrier_ok(dev
))
4161 netif_carrier_on(dev
);
4163 if (netif_carrier_ok(dev
))
4164 netif_carrier_off(dev
);
4168 if (netif_carrier_ok(dev
)) {
4169 switch(np
->linkspeed
& (NVREG_LINKSPEED_MASK
)) {
4170 case NVREG_LINKSPEED_10
:
4171 ecmd
->speed
= SPEED_10
;
4173 case NVREG_LINKSPEED_100
:
4174 ecmd
->speed
= SPEED_100
;
4176 case NVREG_LINKSPEED_1000
:
4177 ecmd
->speed
= SPEED_1000
;
4180 ecmd
->duplex
= DUPLEX_HALF
;
4182 ecmd
->duplex
= DUPLEX_FULL
;
4188 ecmd
->autoneg
= np
->autoneg
;
4190 ecmd
->advertising
= ADVERTISED_MII
;
4192 ecmd
->advertising
|= ADVERTISED_Autoneg
;
4193 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4194 if (adv
& ADVERTISE_10HALF
)
4195 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
4196 if (adv
& ADVERTISE_10FULL
)
4197 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
4198 if (adv
& ADVERTISE_100HALF
)
4199 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
4200 if (adv
& ADVERTISE_100FULL
)
4201 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
4202 if (np
->gigabit
== PHY_GIGABIT
) {
4203 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4204 if (adv
& ADVERTISE_1000FULL
)
4205 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
4208 ecmd
->supported
= (SUPPORTED_Autoneg
|
4209 SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
4210 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
4212 if (np
->gigabit
== PHY_GIGABIT
)
4213 ecmd
->supported
|= SUPPORTED_1000baseT_Full
;
4215 ecmd
->phy_address
= np
->phyaddr
;
4216 ecmd
->transceiver
= XCVR_EXTERNAL
;
4218 /* ignore maxtxpkt, maxrxpkt for now */
4219 spin_unlock_irq(&np
->lock
);
4223 static int nv_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
4225 struct fe_priv
*np
= netdev_priv(dev
);
4227 if (ecmd
->port
!= PORT_MII
)
4229 if (ecmd
->transceiver
!= XCVR_EXTERNAL
)
4231 if (ecmd
->phy_address
!= np
->phyaddr
) {
4232 /* TODO: support switching between multiple phys. Should be
4233 * trivial, but not enabled due to lack of test hardware. */
4236 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
4239 mask
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
4240 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
4241 if (np
->gigabit
== PHY_GIGABIT
)
4242 mask
|= ADVERTISED_1000baseT_Full
;
4244 if ((ecmd
->advertising
& mask
) == 0)
4247 } else if (ecmd
->autoneg
== AUTONEG_DISABLE
) {
4248 /* Note: autonegotiation disable, speed 1000 intentionally
4249 * forbidden - noone should need that. */
4251 if (ecmd
->speed
!= SPEED_10
&& ecmd
->speed
!= SPEED_100
)
4253 if (ecmd
->duplex
!= DUPLEX_HALF
&& ecmd
->duplex
!= DUPLEX_FULL
)
4259 netif_carrier_off(dev
);
4260 if (netif_running(dev
)) {
4261 unsigned long flags
;
4263 nv_disable_irq(dev
);
4264 netif_tx_lock_bh(dev
);
4265 netif_addr_lock(dev
);
4266 /* with plain spinlock lockdep complains */
4267 spin_lock_irqsave(&np
->lock
, flags
);
4270 * this can take some time, and interrupts are disabled
4271 * due to spin_lock_irqsave, but let's hope no daemon
4272 * is going to change the settings very often...
4274 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4275 * + some minor delays, which is up to a second approximately
4278 spin_unlock_irqrestore(&np
->lock
, flags
);
4279 netif_addr_unlock(dev
);
4280 netif_tx_unlock_bh(dev
);
4283 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
4288 /* advertise only what has been requested */
4289 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4290 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4291 if (ecmd
->advertising
& ADVERTISED_10baseT_Half
)
4292 adv
|= ADVERTISE_10HALF
;
4293 if (ecmd
->advertising
& ADVERTISED_10baseT_Full
)
4294 adv
|= ADVERTISE_10FULL
;
4295 if (ecmd
->advertising
& ADVERTISED_100baseT_Half
)
4296 adv
|= ADVERTISE_100HALF
;
4297 if (ecmd
->advertising
& ADVERTISED_100baseT_Full
)
4298 adv
|= ADVERTISE_100FULL
;
4299 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisments but disable tx pause */
4300 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4301 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
4302 adv
|= ADVERTISE_PAUSE_ASYM
;
4303 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4305 if (np
->gigabit
== PHY_GIGABIT
) {
4306 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4307 adv
&= ~ADVERTISE_1000FULL
;
4308 if (ecmd
->advertising
& ADVERTISED_1000baseT_Full
)
4309 adv
|= ADVERTISE_1000FULL
;
4310 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
4313 if (netif_running(dev
))
4314 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4315 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4316 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
4317 bmcr
|= BMCR_ANENABLE
;
4318 /* reset the phy in order for settings to stick,
4319 * and cause autoneg to start */
4320 if (phy_reset(dev
, bmcr
)) {
4321 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4325 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4326 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4333 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4334 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4335 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_HALF
)
4336 adv
|= ADVERTISE_10HALF
;
4337 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_FULL
)
4338 adv
|= ADVERTISE_10FULL
;
4339 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_HALF
)
4340 adv
|= ADVERTISE_100HALF
;
4341 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_FULL
)
4342 adv
|= ADVERTISE_100FULL
;
4343 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
4344 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) {/* for rx we set both advertisments but disable tx pause */
4345 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4346 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
4348 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
) {
4349 adv
|= ADVERTISE_PAUSE_ASYM
;
4350 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
4352 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4353 np
->fixed_mode
= adv
;
4355 if (np
->gigabit
== PHY_GIGABIT
) {
4356 adv
= mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, MII_READ
);
4357 adv
&= ~ADVERTISE_1000FULL
;
4358 mii_rw(dev
, np
->phyaddr
, MII_CTRL1000
, adv
);
4361 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4362 bmcr
&= ~(BMCR_ANENABLE
|BMCR_SPEED100
|BMCR_SPEED1000
|BMCR_FULLDPLX
);
4363 if (np
->fixed_mode
& (ADVERTISE_10FULL
|ADVERTISE_100FULL
))
4364 bmcr
|= BMCR_FULLDPLX
;
4365 if (np
->fixed_mode
& (ADVERTISE_100HALF
|ADVERTISE_100FULL
))
4366 bmcr
|= BMCR_SPEED100
;
4367 if (np
->phy_oui
== PHY_OUI_MARVELL
) {
4368 /* reset the phy in order for forced mode settings to stick */
4369 if (phy_reset(dev
, bmcr
)) {
4370 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4374 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4375 if (netif_running(dev
)) {
4376 /* Wait a bit and then reconfigure the nic. */
4383 if (netif_running(dev
)) {
4391 #define FORCEDETH_REGS_VER 1
4393 static int nv_get_regs_len(struct net_device
*dev
)
4395 struct fe_priv
*np
= netdev_priv(dev
);
4396 return np
->register_size
;
4399 static void nv_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
, void *buf
)
4401 struct fe_priv
*np
= netdev_priv(dev
);
4402 u8 __iomem
*base
= get_hwbase(dev
);
4406 regs
->version
= FORCEDETH_REGS_VER
;
4407 spin_lock_irq(&np
->lock
);
4408 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
4409 rbuf
[i
] = readl(base
+ i
*sizeof(u32
));
4410 spin_unlock_irq(&np
->lock
);
4413 static int nv_nway_reset(struct net_device
*dev
)
4415 struct fe_priv
*np
= netdev_priv(dev
);
4421 netif_carrier_off(dev
);
4422 if (netif_running(dev
)) {
4423 nv_disable_irq(dev
);
4424 netif_tx_lock_bh(dev
);
4425 netif_addr_lock(dev
);
4426 spin_lock(&np
->lock
);
4429 spin_unlock(&np
->lock
);
4430 netif_addr_unlock(dev
);
4431 netif_tx_unlock_bh(dev
);
4432 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4435 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4436 if (np
->phy_model
== PHY_MODEL_MARVELL_E3016
) {
4437 bmcr
|= BMCR_ANENABLE
;
4438 /* reset the phy in order for settings to stick*/
4439 if (phy_reset(dev
, bmcr
)) {
4440 printk(KERN_INFO
"%s: phy reset failed\n", dev
->name
);
4444 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4445 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4448 if (netif_running(dev
)) {
4460 static int nv_set_tso(struct net_device
*dev
, u32 value
)
4462 struct fe_priv
*np
= netdev_priv(dev
);
4464 if ((np
->driver_data
& DEV_HAS_CHECKSUM
))
4465 return ethtool_op_set_tso(dev
, value
);
4470 static void nv_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
4472 struct fe_priv
*np
= netdev_priv(dev
);
4474 ring
->rx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
4475 ring
->rx_mini_max_pending
= 0;
4476 ring
->rx_jumbo_max_pending
= 0;
4477 ring
->tx_max_pending
= (np
->desc_ver
== DESC_VER_1
) ? RING_MAX_DESC_VER_1
: RING_MAX_DESC_VER_2_3
;
4479 ring
->rx_pending
= np
->rx_ring_size
;
4480 ring
->rx_mini_pending
= 0;
4481 ring
->rx_jumbo_pending
= 0;
4482 ring
->tx_pending
= np
->tx_ring_size
;
4485 static int nv_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
* ring
)
4487 struct fe_priv
*np
= netdev_priv(dev
);
4488 u8 __iomem
*base
= get_hwbase(dev
);
4489 u8
*rxtx_ring
, *rx_skbuff
, *tx_skbuff
;
4490 dma_addr_t ring_addr
;
4492 if (ring
->rx_pending
< RX_RING_MIN
||
4493 ring
->tx_pending
< TX_RING_MIN
||
4494 ring
->rx_mini_pending
!= 0 ||
4495 ring
->rx_jumbo_pending
!= 0 ||
4496 (np
->desc_ver
== DESC_VER_1
&&
4497 (ring
->rx_pending
> RING_MAX_DESC_VER_1
||
4498 ring
->tx_pending
> RING_MAX_DESC_VER_1
)) ||
4499 (np
->desc_ver
!= DESC_VER_1
&&
4500 (ring
->rx_pending
> RING_MAX_DESC_VER_2_3
||
4501 ring
->tx_pending
> RING_MAX_DESC_VER_2_3
))) {
4505 /* allocate new rings */
4506 if (!nv_optimized(np
)) {
4507 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
4508 sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
4511 rxtx_ring
= pci_alloc_consistent(np
->pci_dev
,
4512 sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
4515 rx_skbuff
= kmalloc(sizeof(struct nv_skb_map
) * ring
->rx_pending
, GFP_KERNEL
);
4516 tx_skbuff
= kmalloc(sizeof(struct nv_skb_map
) * ring
->tx_pending
, GFP_KERNEL
);
4517 if (!rxtx_ring
|| !rx_skbuff
|| !tx_skbuff
) {
4518 /* fall back to old rings */
4519 if (!nv_optimized(np
)) {
4521 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (ring
->rx_pending
+ ring
->tx_pending
),
4522 rxtx_ring
, ring_addr
);
4525 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (ring
->rx_pending
+ ring
->tx_pending
),
4526 rxtx_ring
, ring_addr
);
4535 if (netif_running(dev
)) {
4536 nv_disable_irq(dev
);
4537 netif_tx_lock_bh(dev
);
4538 netif_addr_lock(dev
);
4539 spin_lock(&np
->lock
);
4549 /* set new values */
4550 np
->rx_ring_size
= ring
->rx_pending
;
4551 np
->tx_ring_size
= ring
->tx_pending
;
4553 if (!nv_optimized(np
)) {
4554 np
->rx_ring
.orig
= (struct ring_desc
*)rxtx_ring
;
4555 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
4557 np
->rx_ring
.ex
= (struct ring_desc_ex
*)rxtx_ring
;
4558 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
4560 np
->rx_skb
= (struct nv_skb_map
*)rx_skbuff
;
4561 np
->tx_skb
= (struct nv_skb_map
*)tx_skbuff
;
4562 np
->ring_addr
= ring_addr
;
4564 memset(np
->rx_skb
, 0, sizeof(struct nv_skb_map
) * np
->rx_ring_size
);
4565 memset(np
->tx_skb
, 0, sizeof(struct nv_skb_map
) * np
->tx_ring_size
);
4567 if (netif_running(dev
)) {
4568 /* reinit driver view of the queues */
4570 if (nv_init_ring(dev
)) {
4571 if (!np
->in_shutdown
)
4572 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
4575 /* reinit nic view of the queues */
4576 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4577 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4578 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4579 base
+ NvRegRingSizes
);
4581 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4584 /* restart engines */
4586 spin_unlock(&np
->lock
);
4587 netif_addr_unlock(dev
);
4588 netif_tx_unlock_bh(dev
);
4596 static void nv_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
4598 struct fe_priv
*np
= netdev_priv(dev
);
4600 pause
->autoneg
= (np
->pause_flags
& NV_PAUSEFRAME_AUTONEG
) != 0;
4601 pause
->rx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_RX_ENABLE
) != 0;
4602 pause
->tx_pause
= (np
->pause_flags
& NV_PAUSEFRAME_TX_ENABLE
) != 0;
4605 static int nv_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
* pause
)
4607 struct fe_priv
*np
= netdev_priv(dev
);
4610 if ((!np
->autoneg
&& np
->duplex
== 0) ||
4611 (np
->autoneg
&& !pause
->autoneg
&& np
->duplex
== 0)) {
4612 printk(KERN_INFO
"%s: can not set pause settings when forced link is in half duplex.\n",
4616 if (pause
->tx_pause
&& !(np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)) {
4617 printk(KERN_INFO
"%s: hardware does not support tx pause frames.\n", dev
->name
);
4621 netif_carrier_off(dev
);
4622 if (netif_running(dev
)) {
4623 nv_disable_irq(dev
);
4624 netif_tx_lock_bh(dev
);
4625 netif_addr_lock(dev
);
4626 spin_lock(&np
->lock
);
4629 spin_unlock(&np
->lock
);
4630 netif_addr_unlock(dev
);
4631 netif_tx_unlock_bh(dev
);
4634 np
->pause_flags
&= ~(NV_PAUSEFRAME_RX_REQ
|NV_PAUSEFRAME_TX_REQ
);
4635 if (pause
->rx_pause
)
4636 np
->pause_flags
|= NV_PAUSEFRAME_RX_REQ
;
4637 if (pause
->tx_pause
)
4638 np
->pause_flags
|= NV_PAUSEFRAME_TX_REQ
;
4640 if (np
->autoneg
&& pause
->autoneg
) {
4641 np
->pause_flags
|= NV_PAUSEFRAME_AUTONEG
;
4643 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
4644 adv
&= ~(ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
4645 if (np
->pause_flags
& NV_PAUSEFRAME_RX_REQ
) /* for rx we set both advertisments but disable tx pause */
4646 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4647 if (np
->pause_flags
& NV_PAUSEFRAME_TX_REQ
)
4648 adv
|= ADVERTISE_PAUSE_ASYM
;
4649 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
4651 if (netif_running(dev
))
4652 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
4653 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
4654 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
4655 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
4657 np
->pause_flags
&= ~(NV_PAUSEFRAME_AUTONEG
|NV_PAUSEFRAME_RX_ENABLE
|NV_PAUSEFRAME_TX_ENABLE
);
4658 if (pause
->rx_pause
)
4659 np
->pause_flags
|= NV_PAUSEFRAME_RX_ENABLE
;
4660 if (pause
->tx_pause
)
4661 np
->pause_flags
|= NV_PAUSEFRAME_TX_ENABLE
;
4663 if (!netif_running(dev
))
4664 nv_update_linkspeed(dev
);
4666 nv_update_pause(dev
, np
->pause_flags
);
4669 if (netif_running(dev
)) {
4676 static u32
nv_get_rx_csum(struct net_device
*dev
)
4678 struct fe_priv
*np
= netdev_priv(dev
);
4679 return (np
->rx_csum
) != 0;
4682 static int nv_set_rx_csum(struct net_device
*dev
, u32 data
)
4684 struct fe_priv
*np
= netdev_priv(dev
);
4685 u8 __iomem
*base
= get_hwbase(dev
);
4688 if (np
->driver_data
& DEV_HAS_CHECKSUM
) {
4691 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
4694 /* vlan is dependent on rx checksum offload */
4695 if (!(np
->vlanctl_bits
& NVREG_VLANCONTROL_ENABLE
))
4696 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_RXCHECK
;
4698 if (netif_running(dev
)) {
4699 spin_lock_irq(&np
->lock
);
4700 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
4701 spin_unlock_irq(&np
->lock
);
4710 static int nv_set_tx_csum(struct net_device
*dev
, u32 data
)
4712 struct fe_priv
*np
= netdev_priv(dev
);
4714 if (np
->driver_data
& DEV_HAS_CHECKSUM
)
4715 return ethtool_op_set_tx_hw_csum(dev
, data
);
4720 static int nv_set_sg(struct net_device
*dev
, u32 data
)
4722 struct fe_priv
*np
= netdev_priv(dev
);
4724 if (np
->driver_data
& DEV_HAS_CHECKSUM
)
4725 return ethtool_op_set_sg(dev
, data
);
4730 static int nv_get_sset_count(struct net_device
*dev
, int sset
)
4732 struct fe_priv
*np
= netdev_priv(dev
);
4736 if (np
->driver_data
& DEV_HAS_TEST_EXTENDED
)
4737 return NV_TEST_COUNT_EXTENDED
;
4739 return NV_TEST_COUNT_BASE
;
4741 if (np
->driver_data
& DEV_HAS_STATISTICS_V1
)
4742 return NV_DEV_STATISTICS_V1_COUNT
;
4743 else if (np
->driver_data
& DEV_HAS_STATISTICS_V2
)
4744 return NV_DEV_STATISTICS_V2_COUNT
;
4752 static void nv_get_ethtool_stats(struct net_device
*dev
, struct ethtool_stats
*estats
, u64
*buffer
)
4754 struct fe_priv
*np
= netdev_priv(dev
);
4757 nv_do_stats_poll((unsigned long)dev
);
4759 memcpy(buffer
, &np
->estats
, nv_get_sset_count(dev
, ETH_SS_STATS
)*sizeof(u64
));
4762 static int nv_link_test(struct net_device
*dev
)
4764 struct fe_priv
*np
= netdev_priv(dev
);
4767 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4768 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
4770 /* check phy link status */
4771 if (!(mii_status
& BMSR_LSTATUS
))
4777 static int nv_register_test(struct net_device
*dev
)
4779 u8 __iomem
*base
= get_hwbase(dev
);
4781 u32 orig_read
, new_read
;
4784 orig_read
= readl(base
+ nv_registers_test
[i
].reg
);
4786 /* xor with mask to toggle bits */
4787 orig_read
^= nv_registers_test
[i
].mask
;
4789 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
4791 new_read
= readl(base
+ nv_registers_test
[i
].reg
);
4793 if ((new_read
& nv_registers_test
[i
].mask
) != (orig_read
& nv_registers_test
[i
].mask
))
4796 /* restore original value */
4797 orig_read
^= nv_registers_test
[i
].mask
;
4798 writel(orig_read
, base
+ nv_registers_test
[i
].reg
);
4800 } while (nv_registers_test
[++i
].reg
!= 0);
4805 static int nv_interrupt_test(struct net_device
*dev
)
4807 struct fe_priv
*np
= netdev_priv(dev
);
4808 u8 __iomem
*base
= get_hwbase(dev
);
4811 u32 save_msi_flags
, save_poll_interval
= 0;
4813 if (netif_running(dev
)) {
4814 /* free current irq */
4816 save_poll_interval
= readl(base
+NvRegPollingInterval
);
4819 /* flag to test interrupt handler */
4822 /* setup test irq */
4823 save_msi_flags
= np
->msi_flags
;
4824 np
->msi_flags
&= ~NV_MSI_X_VECTORS_MASK
;
4825 np
->msi_flags
|= 0x001; /* setup 1 vector */
4826 if (nv_request_irq(dev
, 1))
4829 /* setup timer interrupt */
4830 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
4831 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
4833 nv_enable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
4835 /* wait for at least one interrupt */
4838 spin_lock_irq(&np
->lock
);
4840 /* flag should be set within ISR */
4841 testcnt
= np
->intr_test
;
4845 nv_disable_hw_interrupts(dev
, NVREG_IRQ_TIMER
);
4846 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
4847 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
4849 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
4851 spin_unlock_irq(&np
->lock
);
4855 np
->msi_flags
= save_msi_flags
;
4857 if (netif_running(dev
)) {
4858 writel(save_poll_interval
, base
+ NvRegPollingInterval
);
4859 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
4860 /* restore original irq */
4861 if (nv_request_irq(dev
, 0))
4868 static int nv_loopback_test(struct net_device
*dev
)
4870 struct fe_priv
*np
= netdev_priv(dev
);
4871 u8 __iomem
*base
= get_hwbase(dev
);
4872 struct sk_buff
*tx_skb
, *rx_skb
;
4873 dma_addr_t test_dma_addr
;
4874 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
4876 int len
, i
, pkt_len
;
4878 u32 filter_flags
= 0;
4879 u32 misc1_flags
= 0;
4882 if (netif_running(dev
)) {
4883 nv_disable_irq(dev
);
4884 filter_flags
= readl(base
+ NvRegPacketFilterFlags
);
4885 misc1_flags
= readl(base
+ NvRegMisc1
);
4890 /* reinit driver view of the rx queue */
4894 /* setup hardware for loopback */
4895 writel(NVREG_MISC1_FORCE
, base
+ NvRegMisc1
);
4896 writel(NVREG_PFF_ALWAYS
| NVREG_PFF_LOOPBACK
, base
+ NvRegPacketFilterFlags
);
4898 /* reinit nic view of the rx queue */
4899 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
4900 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
4901 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
4902 base
+ NvRegRingSizes
);
4905 /* restart rx engine */
4908 /* setup packet for tx */
4909 pkt_len
= ETH_DATA_LEN
;
4910 tx_skb
= dev_alloc_skb(pkt_len
);
4912 printk(KERN_ERR
"dev_alloc_skb() failed during loopback test"
4913 " of %s\n", dev
->name
);
4917 test_dma_addr
= pci_map_single(np
->pci_dev
, tx_skb
->data
,
4918 skb_tailroom(tx_skb
),
4919 PCI_DMA_FROMDEVICE
);
4920 pkt_data
= skb_put(tx_skb
, pkt_len
);
4921 for (i
= 0; i
< pkt_len
; i
++)
4922 pkt_data
[i
] = (u8
)(i
& 0xff);
4924 if (!nv_optimized(np
)) {
4925 np
->tx_ring
.orig
[0].buf
= cpu_to_le32(test_dma_addr
);
4926 np
->tx_ring
.orig
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
4928 np
->tx_ring
.ex
[0].bufhigh
= cpu_to_le32(dma_high(test_dma_addr
));
4929 np
->tx_ring
.ex
[0].buflow
= cpu_to_le32(dma_low(test_dma_addr
));
4930 np
->tx_ring
.ex
[0].flaglen
= cpu_to_le32((pkt_len
-1) | np
->tx_flags
| tx_flags_extra
);
4932 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
4933 pci_push(get_hwbase(dev
));
4937 /* check for rx of the packet */
4938 if (!nv_optimized(np
)) {
4939 flags
= le32_to_cpu(np
->rx_ring
.orig
[0].flaglen
);
4940 len
= nv_descr_getlength(&np
->rx_ring
.orig
[0], np
->desc_ver
);
4943 flags
= le32_to_cpu(np
->rx_ring
.ex
[0].flaglen
);
4944 len
= nv_descr_getlength_ex(&np
->rx_ring
.ex
[0], np
->desc_ver
);
4947 if (flags
& NV_RX_AVAIL
) {
4949 } else if (np
->desc_ver
== DESC_VER_1
) {
4950 if (flags
& NV_RX_ERROR
)
4953 if (flags
& NV_RX2_ERROR
) {
4959 if (len
!= pkt_len
) {
4961 dprintk(KERN_DEBUG
"%s: loopback len mismatch %d vs %d\n",
4962 dev
->name
, len
, pkt_len
);
4964 rx_skb
= np
->rx_skb
[0].skb
;
4965 for (i
= 0; i
< pkt_len
; i
++) {
4966 if (rx_skb
->data
[i
] != (u8
)(i
& 0xff)) {
4968 dprintk(KERN_DEBUG
"%s: loopback pattern check failed on byte %d\n",
4975 dprintk(KERN_DEBUG
"%s: loopback - did not receive test packet\n", dev
->name
);
4978 pci_unmap_page(np
->pci_dev
, test_dma_addr
,
4979 (skb_end_pointer(tx_skb
) - tx_skb
->data
),
4981 dev_kfree_skb_any(tx_skb
);
4986 /* drain rx queue */
4989 if (netif_running(dev
)) {
4990 writel(misc1_flags
, base
+ NvRegMisc1
);
4991 writel(filter_flags
, base
+ NvRegPacketFilterFlags
);
4998 static void nv_self_test(struct net_device
*dev
, struct ethtool_test
*test
, u64
*buffer
)
5000 struct fe_priv
*np
= netdev_priv(dev
);
5001 u8 __iomem
*base
= get_hwbase(dev
);
5003 memset(buffer
, 0, nv_get_sset_count(dev
, ETH_SS_TEST
)*sizeof(u64
));
5005 if (!nv_link_test(dev
)) {
5006 test
->flags
|= ETH_TEST_FL_FAILED
;
5010 if (test
->flags
& ETH_TEST_FL_OFFLINE
) {
5011 if (netif_running(dev
)) {
5012 netif_stop_queue(dev
);
5013 #ifdef CONFIG_FORCEDETH_NAPI
5014 napi_disable(&np
->napi
);
5016 netif_tx_lock_bh(dev
);
5017 netif_addr_lock(dev
);
5018 spin_lock_irq(&np
->lock
);
5019 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5020 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
5021 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5023 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
5028 /* drain rx queue */
5030 spin_unlock_irq(&np
->lock
);
5031 netif_addr_unlock(dev
);
5032 netif_tx_unlock_bh(dev
);
5035 if (!nv_register_test(dev
)) {
5036 test
->flags
|= ETH_TEST_FL_FAILED
;
5040 result
= nv_interrupt_test(dev
);
5042 test
->flags
|= ETH_TEST_FL_FAILED
;
5050 if (!nv_loopback_test(dev
)) {
5051 test
->flags
|= ETH_TEST_FL_FAILED
;
5055 if (netif_running(dev
)) {
5056 /* reinit driver view of the rx queue */
5058 if (nv_init_ring(dev
)) {
5059 if (!np
->in_shutdown
)
5060 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
5062 /* reinit nic view of the rx queue */
5063 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5064 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5065 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5066 base
+ NvRegRingSizes
);
5068 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
5070 /* restart rx engine */
5072 netif_start_queue(dev
);
5073 #ifdef CONFIG_FORCEDETH_NAPI
5074 napi_enable(&np
->napi
);
5076 nv_enable_hw_interrupts(dev
, np
->irqmask
);
5081 static void nv_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buffer
)
5083 switch (stringset
) {
5085 memcpy(buffer
, &nv_estats_str
, nv_get_sset_count(dev
, ETH_SS_STATS
)*sizeof(struct nv_ethtool_str
));
5088 memcpy(buffer
, &nv_etests_str
, nv_get_sset_count(dev
, ETH_SS_TEST
)*sizeof(struct nv_ethtool_str
));
5093 static const struct ethtool_ops ops
= {
5094 .get_drvinfo
= nv_get_drvinfo
,
5095 .get_link
= ethtool_op_get_link
,
5096 .get_wol
= nv_get_wol
,
5097 .set_wol
= nv_set_wol
,
5098 .get_settings
= nv_get_settings
,
5099 .set_settings
= nv_set_settings
,
5100 .get_regs_len
= nv_get_regs_len
,
5101 .get_regs
= nv_get_regs
,
5102 .nway_reset
= nv_nway_reset
,
5103 .set_tso
= nv_set_tso
,
5104 .get_ringparam
= nv_get_ringparam
,
5105 .set_ringparam
= nv_set_ringparam
,
5106 .get_pauseparam
= nv_get_pauseparam
,
5107 .set_pauseparam
= nv_set_pauseparam
,
5108 .get_rx_csum
= nv_get_rx_csum
,
5109 .set_rx_csum
= nv_set_rx_csum
,
5110 .set_tx_csum
= nv_set_tx_csum
,
5111 .set_sg
= nv_set_sg
,
5112 .get_strings
= nv_get_strings
,
5113 .get_ethtool_stats
= nv_get_ethtool_stats
,
5114 .get_sset_count
= nv_get_sset_count
,
5115 .self_test
= nv_self_test
,
5118 static void nv_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
5120 struct fe_priv
*np
= get_nvpriv(dev
);
5122 spin_lock_irq(&np
->lock
);
5124 /* save vlan group */
5128 /* enable vlan on MAC */
5129 np
->txrxctl_bits
|= NVREG_TXRXCTL_VLANSTRIP
| NVREG_TXRXCTL_VLANINS
;
5131 /* disable vlan on MAC */
5132 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANSTRIP
;
5133 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANINS
;
5136 writel(np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
5138 spin_unlock_irq(&np
->lock
);
5141 /* The mgmt unit and driver use a semaphore to access the phy during init */
5142 static int nv_mgmt_acquire_sema(struct net_device
*dev
)
5144 u8 __iomem
*base
= get_hwbase(dev
);
5146 u32 tx_ctrl
, mgmt_sema
;
5148 for (i
= 0; i
< 10; i
++) {
5149 mgmt_sema
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_SEMA_MASK
;
5150 if (mgmt_sema
== NVREG_XMITCTL_MGMT_SEMA_FREE
)
5155 if (mgmt_sema
!= NVREG_XMITCTL_MGMT_SEMA_FREE
)
5158 for (i
= 0; i
< 2; i
++) {
5159 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5160 tx_ctrl
|= NVREG_XMITCTL_HOST_SEMA_ACQ
;
5161 writel(tx_ctrl
, base
+ NvRegTransmitterControl
);
5163 /* verify that semaphore was acquired */
5164 tx_ctrl
= readl(base
+ NvRegTransmitterControl
);
5165 if (((tx_ctrl
& NVREG_XMITCTL_HOST_SEMA_MASK
) == NVREG_XMITCTL_HOST_SEMA_ACQ
) &&
5166 ((tx_ctrl
& NVREG_XMITCTL_MGMT_SEMA_MASK
) == NVREG_XMITCTL_MGMT_SEMA_FREE
))
5175 static int nv_open(struct net_device
*dev
)
5177 struct fe_priv
*np
= netdev_priv(dev
);
5178 u8 __iomem
*base
= get_hwbase(dev
);
5183 dprintk(KERN_DEBUG
"nv_open: begin\n");
5185 /* erase previous misconfiguration */
5186 if (np
->driver_data
& DEV_HAS_POWER_CNTRL
)
5188 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
5189 writel(0, base
+ NvRegMulticastAddrB
);
5190 writel(NVREG_MCASTMASKA_NONE
, base
+ NvRegMulticastMaskA
);
5191 writel(NVREG_MCASTMASKB_NONE
, base
+ NvRegMulticastMaskB
);
5192 writel(0, base
+ NvRegPacketFilterFlags
);
5194 writel(0, base
+ NvRegTransmitterControl
);
5195 writel(0, base
+ NvRegReceiverControl
);
5197 writel(0, base
+ NvRegAdapterControl
);
5199 if (np
->pause_flags
& NV_PAUSEFRAME_TX_CAPABLE
)
5200 writel(NVREG_TX_PAUSEFRAME_DISABLE
, base
+ NvRegTxPauseFrame
);
5202 /* initialize descriptor rings */
5204 oom
= nv_init_ring(dev
);
5206 writel(0, base
+ NvRegLinkSpeed
);
5207 writel(readl(base
+ NvRegTransmitPoll
) & NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
5209 writel(0, base
+ NvRegUnknownSetupReg6
);
5211 np
->in_shutdown
= 0;
5214 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
5215 writel( ((np
->rx_ring_size
-1) << NVREG_RINGSZ_RXSHIFT
) + ((np
->tx_ring_size
-1) << NVREG_RINGSZ_TXSHIFT
),
5216 base
+ NvRegRingSizes
);
5218 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
5219 if (np
->desc_ver
== DESC_VER_1
)
5220 writel(NVREG_TX_WM_DESC1_DEFAULT
, base
+ NvRegTxWatermark
);
5222 writel(NVREG_TX_WM_DESC2_3_DEFAULT
, base
+ NvRegTxWatermark
);
5223 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
5224 writel(np
->vlanctl_bits
, base
+ NvRegVlanControl
);
5226 writel(NVREG_TXRXCTL_BIT1
|np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
5227 reg_delay(dev
, NvRegUnknownSetupReg5
, NVREG_UNKSETUP5_BIT31
, NVREG_UNKSETUP5_BIT31
,
5228 NV_SETUP5_DELAY
, NV_SETUP5_DELAYMAX
,
5229 KERN_INFO
"open: SetupReg5, Bit 31 remained off\n");
5231 writel(0, base
+ NvRegMIIMask
);
5232 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5233 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5235 writel(NVREG_MISC1_FORCE
| NVREG_MISC1_HD
, base
+ NvRegMisc1
);
5236 writel(readl(base
+ NvRegTransmitterStatus
), base
+ NvRegTransmitterStatus
);
5237 writel(NVREG_PFF_ALWAYS
, base
+ NvRegPacketFilterFlags
);
5238 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
5240 writel(readl(base
+ NvRegReceiverStatus
), base
+ NvRegReceiverStatus
);
5242 get_random_bytes(&low
, sizeof(low
));
5243 low
&= NVREG_SLOTTIME_MASK
;
5244 if (np
->desc_ver
== DESC_VER_1
) {
5245 writel(low
|NVREG_SLOTTIME_DEFAULT
, base
+ NvRegSlotTime
);
5247 if (!(np
->driver_data
& DEV_HAS_GEAR_MODE
)) {
5248 /* setup legacy backoff */
5249 writel(NVREG_SLOTTIME_LEGBF_ENABLED
|NVREG_SLOTTIME_10_100_FULL
|low
, base
+ NvRegSlotTime
);
5251 writel(NVREG_SLOTTIME_10_100_FULL
, base
+ NvRegSlotTime
);
5252 nv_gear_backoff_reseed(dev
);
5255 writel(NVREG_TX_DEFERRAL_DEFAULT
, base
+ NvRegTxDeferral
);
5256 writel(NVREG_RX_DEFERRAL_DEFAULT
, base
+ NvRegRxDeferral
);
5257 if (poll_interval
== -1) {
5258 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
)
5259 writel(NVREG_POLL_DEFAULT_THROUGHPUT
, base
+ NvRegPollingInterval
);
5261 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
5264 writel(poll_interval
& 0xFFFF, base
+ NvRegPollingInterval
);
5265 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
5266 writel((np
->phyaddr
<< NVREG_ADAPTCTL_PHYSHIFT
)|NVREG_ADAPTCTL_PHYVALID
|NVREG_ADAPTCTL_RUNNING
,
5267 base
+ NvRegAdapterControl
);
5268 writel(NVREG_MIISPEED_BIT8
|NVREG_MIIDELAY
, base
+ NvRegMIISpeed
);
5269 writel(NVREG_MII_LINKCHANGE
, base
+ NvRegMIIMask
);
5271 writel(NVREG_WAKEUPFLAGS_ENABLE
, base
+ NvRegWakeUpFlags
);
5273 i
= readl(base
+ NvRegPowerState
);
5274 if ( (i
& NVREG_POWERSTATE_POWEREDUP
) == 0)
5275 writel(NVREG_POWERSTATE_POWEREDUP
|i
, base
+ NvRegPowerState
);
5279 writel(readl(base
+ NvRegPowerState
) | NVREG_POWERSTATE_VALID
, base
+ NvRegPowerState
);
5281 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5283 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5284 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
5287 if (nv_request_irq(dev
, 0)) {
5291 /* ask for interrupts */
5292 nv_enable_hw_interrupts(dev
, np
->irqmask
);
5294 spin_lock_irq(&np
->lock
);
5295 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
5296 writel(0, base
+ NvRegMulticastAddrB
);
5297 writel(NVREG_MCASTMASKA_NONE
, base
+ NvRegMulticastMaskA
);
5298 writel(NVREG_MCASTMASKB_NONE
, base
+ NvRegMulticastMaskB
);
5299 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
5300 /* One manual link speed update: Interrupts are enabled, future link
5301 * speed changes cause interrupts and are handled by nv_link_irq().
5305 miistat
= readl(base
+ NvRegMIIStatus
);
5306 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5307 dprintk(KERN_INFO
"startup: got 0x%08x.\n", miistat
);
5309 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5312 ret
= nv_update_linkspeed(dev
);
5314 netif_start_queue(dev
);
5315 #ifdef CONFIG_FORCEDETH_NAPI
5316 napi_enable(&np
->napi
);
5320 netif_carrier_on(dev
);
5322 printk(KERN_INFO
"%s: no link during initialization.\n", dev
->name
);
5323 netif_carrier_off(dev
);
5326 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
5328 /* start statistics timer */
5329 if (np
->driver_data
& (DEV_HAS_STATISTICS_V1
|DEV_HAS_STATISTICS_V2
))
5330 mod_timer(&np
->stats_poll
,
5331 round_jiffies(jiffies
+ STATS_INTERVAL
));
5333 spin_unlock_irq(&np
->lock
);
5341 static int nv_close(struct net_device
*dev
)
5343 struct fe_priv
*np
= netdev_priv(dev
);
5346 spin_lock_irq(&np
->lock
);
5347 np
->in_shutdown
= 1;
5348 spin_unlock_irq(&np
->lock
);
5349 #ifdef CONFIG_FORCEDETH_NAPI
5350 napi_disable(&np
->napi
);
5352 synchronize_irq(np
->pci_dev
->irq
);
5354 del_timer_sync(&np
->oom_kick
);
5355 del_timer_sync(&np
->nic_poll
);
5356 del_timer_sync(&np
->stats_poll
);
5358 netif_stop_queue(dev
);
5359 spin_lock_irq(&np
->lock
);
5363 /* disable interrupts on the nic or we will lock up */
5364 base
= get_hwbase(dev
);
5365 nv_disable_hw_interrupts(dev
, np
->irqmask
);
5367 dprintk(KERN_INFO
"%s: Irqmask is zero again\n", dev
->name
);
5369 spin_unlock_irq(&np
->lock
);
5375 if (np
->wolenabled
) {
5376 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
5380 /* FIXME: power down nic */
5385 static int __devinit
nv_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
5387 struct net_device
*dev
;
5392 u32 powerstate
, txreg
;
5393 u32 phystate_orig
= 0, phystate
;
5394 int phyinitialized
= 0;
5395 DECLARE_MAC_BUF(mac
);
5396 static int printed_version
;
5398 if (!printed_version
++)
5399 printk(KERN_INFO
"%s: Reverse Engineered nForce ethernet"
5400 " driver. Version %s.\n", DRV_NAME
, FORCEDETH_VERSION
);
5402 dev
= alloc_etherdev(sizeof(struct fe_priv
));
5407 np
= netdev_priv(dev
);
5409 np
->pci_dev
= pci_dev
;
5410 spin_lock_init(&np
->lock
);
5411 SET_NETDEV_DEV(dev
, &pci_dev
->dev
);
5413 init_timer(&np
->oom_kick
);
5414 np
->oom_kick
.data
= (unsigned long) dev
;
5415 np
->oom_kick
.function
= &nv_do_rx_refill
; /* timer handler */
5416 init_timer(&np
->nic_poll
);
5417 np
->nic_poll
.data
= (unsigned long) dev
;
5418 np
->nic_poll
.function
= &nv_do_nic_poll
; /* timer handler */
5419 init_timer(&np
->stats_poll
);
5420 np
->stats_poll
.data
= (unsigned long) dev
;
5421 np
->stats_poll
.function
= &nv_do_stats_poll
; /* timer handler */
5423 err
= pci_enable_device(pci_dev
);
5427 pci_set_master(pci_dev
);
5429 err
= pci_request_regions(pci_dev
, DRV_NAME
);
5433 if (id
->driver_data
& (DEV_HAS_VLAN
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V2
))
5434 np
->register_size
= NV_PCI_REGSZ_VER3
;
5435 else if (id
->driver_data
& DEV_HAS_STATISTICS_V1
)
5436 np
->register_size
= NV_PCI_REGSZ_VER2
;
5438 np
->register_size
= NV_PCI_REGSZ_VER1
;
5442 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
5443 dprintk(KERN_DEBUG
"%s: resource %d start %p len %ld flags 0x%08lx.\n",
5444 pci_name(pci_dev
), i
, (void*)pci_resource_start(pci_dev
, i
),
5445 pci_resource_len(pci_dev
, i
),
5446 pci_resource_flags(pci_dev
, i
));
5447 if (pci_resource_flags(pci_dev
, i
) & IORESOURCE_MEM
&&
5448 pci_resource_len(pci_dev
, i
) >= np
->register_size
) {
5449 addr
= pci_resource_start(pci_dev
, i
);
5453 if (i
== DEVICE_COUNT_RESOURCE
) {
5454 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5455 "Couldn't find register window\n");
5459 /* copy of driver data */
5460 np
->driver_data
= id
->driver_data
;
5461 /* copy of device id */
5462 np
->device_id
= id
->device
;
5464 /* handle different descriptor versions */
5465 if (id
->driver_data
& DEV_HAS_HIGH_DMA
) {
5466 /* packet format 3: supports 40-bit addressing */
5467 np
->desc_ver
= DESC_VER_3
;
5468 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_3
;
5470 if (pci_set_dma_mask(pci_dev
, DMA_39BIT_MASK
))
5471 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5472 "64-bit DMA failed, using 32-bit addressing\n");
5474 dev
->features
|= NETIF_F_HIGHDMA
;
5475 if (pci_set_consistent_dma_mask(pci_dev
, DMA_39BIT_MASK
)) {
5476 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5477 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5480 } else if (id
->driver_data
& DEV_HAS_LARGEDESC
) {
5481 /* packet format 2: supports jumbo frames */
5482 np
->desc_ver
= DESC_VER_2
;
5483 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_2
;
5485 /* original packet format */
5486 np
->desc_ver
= DESC_VER_1
;
5487 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_1
;
5490 np
->pkt_limit
= NV_PKTLIMIT_1
;
5491 if (id
->driver_data
& DEV_HAS_LARGEDESC
)
5492 np
->pkt_limit
= NV_PKTLIMIT_2
;
5494 if (id
->driver_data
& DEV_HAS_CHECKSUM
) {
5496 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
5497 dev
->features
|= NETIF_F_HW_CSUM
| NETIF_F_SG
;
5498 dev
->features
|= NETIF_F_TSO
;
5501 np
->vlanctl_bits
= 0;
5502 if (id
->driver_data
& DEV_HAS_VLAN
) {
5503 np
->vlanctl_bits
= NVREG_VLANCONTROL_ENABLE
;
5504 dev
->features
|= NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
;
5505 dev
->vlan_rx_register
= nv_vlan_rx_register
;
5509 if ((id
->driver_data
& DEV_HAS_MSI
) && msi
) {
5510 np
->msi_flags
|= NV_MSI_CAPABLE
;
5512 if ((id
->driver_data
& DEV_HAS_MSI_X
) && msix
) {
5513 np
->msi_flags
|= NV_MSI_X_CAPABLE
;
5516 np
->pause_flags
= NV_PAUSEFRAME_RX_CAPABLE
| NV_PAUSEFRAME_RX_REQ
| NV_PAUSEFRAME_AUTONEG
;
5517 if ((id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V1
) ||
5518 (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V2
) ||
5519 (id
->driver_data
& DEV_HAS_PAUSEFRAME_TX_V3
)) {
5520 np
->pause_flags
|= NV_PAUSEFRAME_TX_CAPABLE
| NV_PAUSEFRAME_TX_REQ
;
5525 np
->base
= ioremap(addr
, np
->register_size
);
5528 dev
->base_addr
= (unsigned long)np
->base
;
5530 dev
->irq
= pci_dev
->irq
;
5532 np
->rx_ring_size
= RX_RING_DEFAULT
;
5533 np
->tx_ring_size
= TX_RING_DEFAULT
;
5535 if (!nv_optimized(np
)) {
5536 np
->rx_ring
.orig
= pci_alloc_consistent(pci_dev
,
5537 sizeof(struct ring_desc
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
5539 if (!np
->rx_ring
.orig
)
5541 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[np
->rx_ring_size
];
5543 np
->rx_ring
.ex
= pci_alloc_consistent(pci_dev
,
5544 sizeof(struct ring_desc_ex
) * (np
->rx_ring_size
+ np
->tx_ring_size
),
5546 if (!np
->rx_ring
.ex
)
5548 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[np
->rx_ring_size
];
5550 np
->rx_skb
= kcalloc(np
->rx_ring_size
, sizeof(struct nv_skb_map
), GFP_KERNEL
);
5551 np
->tx_skb
= kcalloc(np
->tx_ring_size
, sizeof(struct nv_skb_map
), GFP_KERNEL
);
5552 if (!np
->rx_skb
|| !np
->tx_skb
)
5555 dev
->open
= nv_open
;
5556 dev
->stop
= nv_close
;
5558 if (!nv_optimized(np
))
5559 dev
->hard_start_xmit
= nv_start_xmit
;
5561 dev
->hard_start_xmit
= nv_start_xmit_optimized
;
5562 dev
->get_stats
= nv_get_stats
;
5563 dev
->change_mtu
= nv_change_mtu
;
5564 dev
->set_mac_address
= nv_set_mac_address
;
5565 dev
->set_multicast_list
= nv_set_multicast
;
5566 #ifdef CONFIG_NET_POLL_CONTROLLER
5567 dev
->poll_controller
= nv_poll_controller
;
5569 #ifdef CONFIG_FORCEDETH_NAPI
5570 netif_napi_add(dev
, &np
->napi
, nv_napi_poll
, RX_WORK_PER_LOOP
);
5572 SET_ETHTOOL_OPS(dev
, &ops
);
5573 dev
->tx_timeout
= nv_tx_timeout
;
5574 dev
->watchdog_timeo
= NV_WATCHDOG_TIMEO
;
5576 pci_set_drvdata(pci_dev
, dev
);
5578 /* read the mac address */
5579 base
= get_hwbase(dev
);
5580 np
->orig_mac
[0] = readl(base
+ NvRegMacAddrA
);
5581 np
->orig_mac
[1] = readl(base
+ NvRegMacAddrB
);
5583 /* check the workaround bit for correct mac address order */
5584 txreg
= readl(base
+ NvRegTransmitPoll
);
5585 if (id
->driver_data
& DEV_HAS_CORRECT_MACADDR
) {
5586 /* mac address is already in correct order */
5587 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
5588 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
5589 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
5590 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
5591 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
5592 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
5593 } else if (txreg
& NVREG_TRANSMITPOLL_MAC_ADDR_REV
) {
5594 /* mac address is already in correct order */
5595 dev
->dev_addr
[0] = (np
->orig_mac
[0] >> 0) & 0xff;
5596 dev
->dev_addr
[1] = (np
->orig_mac
[0] >> 8) & 0xff;
5597 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 16) & 0xff;
5598 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 24) & 0xff;
5599 dev
->dev_addr
[4] = (np
->orig_mac
[1] >> 0) & 0xff;
5600 dev
->dev_addr
[5] = (np
->orig_mac
[1] >> 8) & 0xff;
5602 * Set orig mac address back to the reversed version.
5603 * This flag will be cleared during low power transition.
5604 * Therefore, we should always put back the reversed address.
5606 np
->orig_mac
[0] = (dev
->dev_addr
[5] << 0) + (dev
->dev_addr
[4] << 8) +
5607 (dev
->dev_addr
[3] << 16) + (dev
->dev_addr
[2] << 24);
5608 np
->orig_mac
[1] = (dev
->dev_addr
[1] << 0) + (dev
->dev_addr
[0] << 8);
5610 /* need to reverse mac address to correct order */
5611 dev
->dev_addr
[0] = (np
->orig_mac
[1] >> 8) & 0xff;
5612 dev
->dev_addr
[1] = (np
->orig_mac
[1] >> 0) & 0xff;
5613 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 24) & 0xff;
5614 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 16) & 0xff;
5615 dev
->dev_addr
[4] = (np
->orig_mac
[0] >> 8) & 0xff;
5616 dev
->dev_addr
[5] = (np
->orig_mac
[0] >> 0) & 0xff;
5617 writel(txreg
|NVREG_TRANSMITPOLL_MAC_ADDR_REV
, base
+ NvRegTransmitPoll
);
5619 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
5621 if (!is_valid_ether_addr(dev
->perm_addr
)) {
5623 * Bad mac address. At least one bios sets the mac address
5624 * to 01:23:45:67:89:ab
5626 dev_printk(KERN_ERR
, &pci_dev
->dev
,
5627 "Invalid Mac address detected: %s\n",
5628 print_mac(mac
, dev
->dev_addr
));
5629 dev_printk(KERN_ERR
, &pci_dev
->dev
,
5630 "Please complain to your hardware vendor. Switching to a random MAC.\n");
5631 dev
->dev_addr
[0] = 0x00;
5632 dev
->dev_addr
[1] = 0x00;
5633 dev
->dev_addr
[2] = 0x6c;
5634 get_random_bytes(&dev
->dev_addr
[3], 3);
5637 dprintk(KERN_DEBUG
"%s: MAC Address %s\n",
5638 pci_name(pci_dev
), print_mac(mac
, dev
->dev_addr
));
5640 /* set mac address */
5641 nv_copy_mac_to_hw(dev
);
5643 /* Workaround current PCI init glitch: wakeup bits aren't
5644 * being set from PCI PM capability.
5646 device_init_wakeup(&pci_dev
->dev
, 1);
5649 writel(0, base
+ NvRegWakeUpFlags
);
5652 if (id
->driver_data
& DEV_HAS_POWER_CNTRL
) {
5654 /* take phy and nic out of low power mode */
5655 powerstate
= readl(base
+ NvRegPowerState2
);
5656 powerstate
&= ~NVREG_POWERSTATE2_POWERUP_MASK
;
5657 if ((id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_12
||
5658 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_13
) &&
5659 pci_dev
->revision
>= 0xA3)
5660 powerstate
|= NVREG_POWERSTATE2_POWERUP_REV_A3
;
5661 writel(powerstate
, base
+ NvRegPowerState2
);
5664 if (np
->desc_ver
== DESC_VER_1
) {
5665 np
->tx_flags
= NV_TX_VALID
;
5667 np
->tx_flags
= NV_TX2_VALID
;
5669 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
) {
5670 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
5671 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
5672 np
->msi_flags
|= 0x0003;
5674 np
->irqmask
= NVREG_IRQMASK_CPU
;
5675 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
5676 np
->msi_flags
|= 0x0001;
5679 if (id
->driver_data
& DEV_NEED_TIMERIRQ
)
5680 np
->irqmask
|= NVREG_IRQ_TIMER
;
5681 if (id
->driver_data
& DEV_NEED_LINKTIMER
) {
5682 dprintk(KERN_INFO
"%s: link timer on.\n", pci_name(pci_dev
));
5683 np
->need_linktimer
= 1;
5684 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
5686 dprintk(KERN_INFO
"%s: link timer off.\n", pci_name(pci_dev
));
5687 np
->need_linktimer
= 0;
5690 /* Limit the number of tx's outstanding for hw bug */
5691 if (id
->driver_data
& DEV_NEED_TX_LIMIT
) {
5693 if ((id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_32
||
5694 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_33
||
5695 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_34
||
5696 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_35
||
5697 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_36
||
5698 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_37
||
5699 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_38
||
5700 id
->device
== PCI_DEVICE_ID_NVIDIA_NVENET_39
) &&
5701 pci_dev
->revision
>= 0xA2)
5705 /* clear phy state and temporarily halt phy interrupts */
5706 writel(0, base
+ NvRegMIIMask
);
5707 phystate
= readl(base
+ NvRegAdapterControl
);
5708 if (phystate
& NVREG_ADAPTCTL_RUNNING
) {
5710 phystate
&= ~NVREG_ADAPTCTL_RUNNING
;
5711 writel(phystate
, base
+ NvRegAdapterControl
);
5713 writel(NVREG_MIISTAT_MASK_ALL
, base
+ NvRegMIIStatus
);
5715 if (id
->driver_data
& DEV_HAS_MGMT_UNIT
) {
5716 /* management unit running on the mac? */
5717 if (readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_PHY_INIT
) {
5718 np
->mac_in_use
= readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_MGMT_ST
;
5719 dprintk(KERN_INFO
"%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev
), np
->mac_in_use
);
5720 if (nv_mgmt_acquire_sema(dev
)) {
5721 /* management unit setup the phy already? */
5722 if ((readl(base
+ NvRegTransmitterControl
) & NVREG_XMITCTL_SYNC_MASK
) ==
5723 NVREG_XMITCTL_SYNC_PHY_INIT
) {
5724 /* phy is inited by mgmt unit */
5726 dprintk(KERN_INFO
"%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev
));
5728 /* we need to init the phy */
5734 /* find a suitable phy */
5735 for (i
= 1; i
<= 32; i
++) {
5737 int phyaddr
= i
& 0x1F;
5739 spin_lock_irq(&np
->lock
);
5740 id1
= mii_rw(dev
, phyaddr
, MII_PHYSID1
, MII_READ
);
5741 spin_unlock_irq(&np
->lock
);
5742 if (id1
< 0 || id1
== 0xffff)
5744 spin_lock_irq(&np
->lock
);
5745 id2
= mii_rw(dev
, phyaddr
, MII_PHYSID2
, MII_READ
);
5746 spin_unlock_irq(&np
->lock
);
5747 if (id2
< 0 || id2
== 0xffff)
5750 np
->phy_model
= id2
& PHYID2_MODEL_MASK
;
5751 id1
= (id1
& PHYID1_OUI_MASK
) << PHYID1_OUI_SHFT
;
5752 id2
= (id2
& PHYID2_OUI_MASK
) >> PHYID2_OUI_SHFT
;
5753 dprintk(KERN_DEBUG
"%s: open: Found PHY %04x:%04x at address %d.\n",
5754 pci_name(pci_dev
), id1
, id2
, phyaddr
);
5755 np
->phyaddr
= phyaddr
;
5756 np
->phy_oui
= id1
| id2
;
5758 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5759 if (np
->phy_oui
== PHY_OUI_REALTEK2
)
5760 np
->phy_oui
= PHY_OUI_REALTEK
;
5761 /* Setup phy revision for Realtek */
5762 if (np
->phy_oui
== PHY_OUI_REALTEK
&& np
->phy_model
== PHY_MODEL_REALTEK_8211
)
5763 np
->phy_rev
= mii_rw(dev
, phyaddr
, MII_RESV1
, MII_READ
) & PHY_REV_MASK
;
5768 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5769 "open: Could not find a valid PHY.\n");
5773 if (!phyinitialized
) {
5777 /* see if it is a gigabit phy */
5778 u32 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
5779 if (mii_status
& PHY_GIGABIT
) {
5780 np
->gigabit
= PHY_GIGABIT
;
5784 /* set default link speed settings */
5785 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
5789 err
= register_netdev(dev
);
5791 dev_printk(KERN_INFO
, &pci_dev
->dev
,
5792 "unable to register netdev: %d\n", err
);
5796 dev_printk(KERN_INFO
, &pci_dev
->dev
, "ifname %s, PHY OUI 0x%x @ %d, "
5797 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5808 dev_printk(KERN_INFO
, &pci_dev
->dev
, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5809 dev
->features
& NETIF_F_HIGHDMA
? "highdma " : "",
5810 dev
->features
& (NETIF_F_HW_CSUM
| NETIF_F_SG
) ?
5812 dev
->features
& (NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
) ?
5814 id
->driver_data
& DEV_HAS_POWER_CNTRL
? "pwrctl " : "",
5815 id
->driver_data
& DEV_HAS_MGMT_UNIT
? "mgmt " : "",
5816 id
->driver_data
& DEV_NEED_TIMERIRQ
? "timirq " : "",
5817 np
->gigabit
== PHY_GIGABIT
? "gbit " : "",
5818 np
->need_linktimer
? "lnktim " : "",
5819 np
->msi_flags
& NV_MSI_CAPABLE
? "msi " : "",
5820 np
->msi_flags
& NV_MSI_X_CAPABLE
? "msi-x " : "",
5827 writel(phystate
|NVREG_ADAPTCTL_RUNNING
, base
+ NvRegAdapterControl
);
5828 pci_set_drvdata(pci_dev
, NULL
);
5832 iounmap(get_hwbase(dev
));
5834 pci_release_regions(pci_dev
);
5836 pci_disable_device(pci_dev
);
5843 static void nv_restore_phy(struct net_device
*dev
)
5845 struct fe_priv
*np
= netdev_priv(dev
);
5846 u16 phy_reserved
, mii_control
;
5848 if (np
->phy_oui
== PHY_OUI_REALTEK
&&
5849 np
->phy_model
== PHY_MODEL_REALTEK_8201
&&
5850 phy_cross
== NV_CROSSOVER_DETECTION_DISABLED
) {
5851 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT3
);
5852 phy_reserved
= mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, MII_READ
);
5853 phy_reserved
&= ~PHY_REALTEK_INIT_MSK1
;
5854 phy_reserved
|= PHY_REALTEK_INIT8
;
5855 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG2
, phy_reserved
);
5856 mii_rw(dev
, np
->phyaddr
, PHY_REALTEK_INIT_REG1
, PHY_REALTEK_INIT1
);
5858 /* restart auto negotiation */
5859 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
5860 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
5861 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
);
5865 static void __devexit
nv_remove(struct pci_dev
*pci_dev
)
5867 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
5868 struct fe_priv
*np
= netdev_priv(dev
);
5869 u8 __iomem
*base
= get_hwbase(dev
);
5871 unregister_netdev(dev
);
5873 /* special op: write back the misordered MAC address - otherwise
5874 * the next nv_probe would see a wrong address.
5876 writel(np
->orig_mac
[0], base
+ NvRegMacAddrA
);
5877 writel(np
->orig_mac
[1], base
+ NvRegMacAddrB
);
5878 writel(readl(base
+ NvRegTransmitPoll
) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV
,
5879 base
+ NvRegTransmitPoll
);
5881 /* restore any phy related changes */
5882 nv_restore_phy(dev
);
5884 /* free all structures */
5886 iounmap(get_hwbase(dev
));
5887 pci_release_regions(pci_dev
);
5888 pci_disable_device(pci_dev
);
5890 pci_set_drvdata(pci_dev
, NULL
);
5894 static int nv_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5896 struct net_device
*dev
= pci_get_drvdata(pdev
);
5897 struct fe_priv
*np
= netdev_priv(dev
);
5898 u8 __iomem
*base
= get_hwbase(dev
);
5901 if (netif_running(dev
)) {
5905 netif_device_detach(dev
);
5907 /* save non-pci configuration space */
5908 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
5909 np
->saved_config_space
[i
] = readl(base
+ i
*sizeof(u32
));
5911 pci_save_state(pdev
);
5912 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), np
->wolenabled
);
5913 pci_disable_device(pdev
);
5914 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
5918 static int nv_resume(struct pci_dev
*pdev
)
5920 struct net_device
*dev
= pci_get_drvdata(pdev
);
5921 struct fe_priv
*np
= netdev_priv(dev
);
5922 u8 __iomem
*base
= get_hwbase(dev
);
5925 pci_set_power_state(pdev
, PCI_D0
);
5926 pci_restore_state(pdev
);
5927 /* ack any pending wake events, disable PME */
5928 pci_enable_wake(pdev
, PCI_D0
, 0);
5930 /* restore non-pci configuration space */
5931 for (i
= 0;i
<= np
->register_size
/sizeof(u32
); i
++)
5932 writel(np
->saved_config_space
[i
], base
+i
*sizeof(u32
));
5934 netif_device_attach(dev
);
5935 if (netif_running(dev
)) {
5937 nv_set_multicast(dev
);
5942 static void nv_shutdown(struct pci_dev
*pdev
)
5944 struct net_device
*dev
= pci_get_drvdata(pdev
);
5945 struct fe_priv
*np
= netdev_priv(dev
);
5947 if (netif_running(dev
))
5950 pci_enable_wake(pdev
, PCI_D3hot
, np
->wolenabled
);
5951 pci_enable_wake(pdev
, PCI_D3cold
, np
->wolenabled
);
5952 pci_disable_device(pdev
);
5953 pci_set_power_state(pdev
, PCI_D3hot
);
5956 #define nv_suspend NULL
5957 #define nv_shutdown NULL
5958 #define nv_resume NULL
5959 #endif /* CONFIG_PM */
5961 static struct pci_device_id pci_tbl
[] = {
5962 { /* nForce Ethernet Controller */
5963 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_1
),
5964 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
5966 { /* nForce2 Ethernet Controller */
5967 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_2
),
5968 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
5970 { /* nForce3 Ethernet Controller */
5971 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_3
),
5972 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
5974 { /* nForce3 Ethernet Controller */
5975 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_4
),
5976 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
5978 { /* nForce3 Ethernet Controller */
5979 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_5
),
5980 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
5982 { /* nForce3 Ethernet Controller */
5983 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_6
),
5984 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
5986 { /* nForce3 Ethernet Controller */
5987 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_7
),
5988 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
5990 { /* CK804 Ethernet Controller */
5991 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_8
),
5992 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
5994 { /* CK804 Ethernet Controller */
5995 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_9
),
5996 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
5998 { /* MCP04 Ethernet Controller */
5999 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_10
),
6000 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6002 { /* MCP04 Ethernet Controller */
6003 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_11
),
6004 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_STATISTICS_V1
|DEV_NEED_TX_LIMIT
,
6006 { /* MCP51 Ethernet Controller */
6007 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_12
),
6008 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V1
,
6010 { /* MCP51 Ethernet Controller */
6011 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_13
),
6012 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_STATISTICS_V1
,
6014 { /* MCP55 Ethernet Controller */
6015 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_14
),
6016 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_NEED_TX_LIMIT
,
6018 { /* MCP55 Ethernet Controller */
6019 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_15
),
6020 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_NEED_TX_LIMIT
,
6022 { /* MCP61 Ethernet Controller */
6023 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_16
),
6024 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
6026 { /* MCP61 Ethernet Controller */
6027 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_17
),
6028 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
6030 { /* MCP61 Ethernet Controller */
6031 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_18
),
6032 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
6034 { /* MCP61 Ethernet Controller */
6035 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_19
),
6036 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
,
6038 { /* MCP65 Ethernet Controller */
6039 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_20
),
6040 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6042 { /* MCP65 Ethernet Controller */
6043 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_21
),
6044 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6046 { /* MCP65 Ethernet Controller */
6047 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_22
),
6048 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6050 { /* MCP65 Ethernet Controller */
6051 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_23
),
6052 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6054 { /* MCP67 Ethernet Controller */
6055 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_24
),
6056 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
6058 { /* MCP67 Ethernet Controller */
6059 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_25
),
6060 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
6062 { /* MCP67 Ethernet Controller */
6063 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_26
),
6064 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
6066 { /* MCP67 Ethernet Controller */
6067 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_27
),
6068 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_GEAR_MODE
,
6070 { /* MCP73 Ethernet Controller */
6071 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_28
),
6072 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
6074 { /* MCP73 Ethernet Controller */
6075 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_29
),
6076 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
6078 { /* MCP73 Ethernet Controller */
6079 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_30
),
6080 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
6082 { /* MCP73 Ethernet Controller */
6083 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_31
),
6084 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
|DEV_HAS_POWER_CNTRL
|DEV_HAS_MSI
|DEV_HAS_PAUSEFRAME_TX_V1
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_HAS_GEAR_MODE
,
6086 { /* MCP77 Ethernet Controller */
6087 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_32
),
6088 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6090 { /* MCP77 Ethernet Controller */
6091 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_33
),
6092 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6094 { /* MCP77 Ethernet Controller */
6095 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_34
),
6096 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6098 { /* MCP77 Ethernet Controller */
6099 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_35
),
6100 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V2
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6102 { /* MCP79 Ethernet Controller */
6103 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_36
),
6104 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6106 { /* MCP79 Ethernet Controller */
6107 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_37
),
6108 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6110 { /* MCP79 Ethernet Controller */
6111 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_38
),
6112 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6114 { /* MCP79 Ethernet Controller */
6115 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_39
),
6116 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_MSI
|DEV_HAS_POWER_CNTRL
|DEV_HAS_PAUSEFRAME_TX_V3
|DEV_HAS_STATISTICS_V2
|DEV_HAS_TEST_EXTENDED
|DEV_HAS_MGMT_UNIT
|DEV_HAS_CORRECT_MACADDR
|DEV_HAS_COLLISION_FIX
|DEV_NEED_TX_LIMIT
|DEV_HAS_GEAR_MODE
,
6121 static struct pci_driver driver
= {
6123 .id_table
= pci_tbl
,
6125 .remove
= __devexit_p(nv_remove
),
6126 .suspend
= nv_suspend
,
6127 .resume
= nv_resume
,
6128 .shutdown
= nv_shutdown
,
6131 static int __init
init_nic(void)
6133 return pci_register_driver(&driver
);
6136 static void __exit
exit_nic(void)
6138 pci_unregister_driver(&driver
);
6141 module_param(max_interrupt_work
, int, 0);
6142 MODULE_PARM_DESC(max_interrupt_work
, "forcedeth maximum events handled per interrupt");
6143 module_param(optimization_mode
, int, 0);
6144 MODULE_PARM_DESC(optimization_mode
, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
6145 module_param(poll_interval
, int, 0);
6146 MODULE_PARM_DESC(poll_interval
, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6147 module_param(msi
, int, 0);
6148 MODULE_PARM_DESC(msi
, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6149 module_param(msix
, int, 0);
6150 MODULE_PARM_DESC(msix
, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6151 module_param(dma_64bit
, int, 0);
6152 MODULE_PARM_DESC(dma_64bit
, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6153 module_param(phy_cross
, int, 0);
6154 MODULE_PARM_DESC(phy_cross
, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6156 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6157 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6158 MODULE_LICENSE("GPL");
6160 MODULE_DEVICE_TABLE(pci
, pci_tbl
);
6162 module_init(init_nic
);
6163 module_exit(exit_nic
);