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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
[deliverable/linux.git] / drivers / net / forcedeth.c
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Changelog:
33 * 0.01: 05 Oct 2003: First release that compiles without warnings.
34 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
35 * Check all PCI BARs for the register window.
36 * udelay added to mii_rw.
37 * 0.03: 06 Oct 2003: Initialize dev->irq.
38 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
39 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
40 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
41 * irq mask updated
42 * 0.07: 14 Oct 2003: Further irq mask updates.
43 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
44 * added into irq handler, NULL check for drain_ring.
45 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
46 * requested interrupt sources.
47 * 0.10: 20 Oct 2003: First cleanup for release.
48 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
49 * MAC Address init fix, set_multicast cleanup.
50 * 0.12: 23 Oct 2003: Cleanups for release.
51 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
52 * Set link speed correctly. start rx before starting
53 * tx (nv_start_rx sets the link speed).
54 * 0.14: 25 Oct 2003: Nic dependant irq mask.
55 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
56 * open.
57 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
58 * increased to 1628 bytes.
59 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
60 * the tx length.
61 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
62 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
63 * addresses, really stop rx if already running
64 * in nv_start_rx, clean up a bit.
65 * 0.20: 07 Dec 2003: alloc fixes
66 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
67 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
68 * on close.
69 * 0.23: 26 Jan 2004: various small cleanups
70 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
71 * 0.25: 09 Mar 2004: wol support
72 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
73 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
74 * added CK804/MCP04 device IDs, code fixes
75 * for registers, link status and other minor fixes.
76 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
77 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
78 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
79 * into nv_close, otherwise reenabling for wol can
80 * cause DMA to kfree'd memory.
81 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
82 * capabilities.
83 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
84 * 0.33: 16 May 2005: Support for MCP51 added.
85 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
86 * 0.35: 26 Jun 2005: Support for MCP55 added.
87 * 0.36: 28 Jun 2005: Add jumbo frame support.
88 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
89 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
90 * per-packet flags.
91 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
92 * 0.40: 19 Jul 2005: Add support for mac address change.
93 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
94 * of nv_remove
95 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
96 * in the second (and later) nv_open call
97 * 0.43: 10 Aug 2005: Add support for tx checksum.
98 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
99 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
100 * 0.46: 20 Oct 2005: Add irq optimization modes.
101 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
102 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
103 * 0.49: 10 Dec 2005: Fix tso for large buffers.
104 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
105 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
106 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
107 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
108 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
109 * 0.55: 22 Mar 2006: Add flow control (pause frame).
110 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
111 * 0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
112 * 0.58: 30 Oct 2006: Added support for sideband management unit.
113 * 0.59: 30 Oct 2006: Added support for recoverable error.
114 * 0.60: 20 Jan 2007: Code optimizations for rings, rx & tx data paths, and stats.
115 *
116 * Known bugs:
117 * We suspect that on some hardware no TX done interrupts are generated.
118 * This means recovery from netif_stop_queue only happens if the hw timer
119 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
120 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
121 * If your hardware reliably generates tx done interrupts, then you can remove
122 * DEV_NEED_TIMERIRQ from the driver_data flags.
123 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
124 * superfluous timer interrupts from the nic.
125 */
126 #ifdef CONFIG_FORCEDETH_NAPI
127 #define DRIVERNAPI "-NAPI"
128 #else
129 #define DRIVERNAPI
130 #endif
131 #define FORCEDETH_VERSION "0.61"
132 #define DRV_NAME "forcedeth"
133
134 #include <linux/module.h>
135 #include <linux/types.h>
136 #include <linux/pci.h>
137 #include <linux/interrupt.h>
138 #include <linux/netdevice.h>
139 #include <linux/etherdevice.h>
140 #include <linux/delay.h>
141 #include <linux/spinlock.h>
142 #include <linux/ethtool.h>
143 #include <linux/timer.h>
144 #include <linux/skbuff.h>
145 #include <linux/mii.h>
146 #include <linux/random.h>
147 #include <linux/init.h>
148 #include <linux/if_vlan.h>
149 #include <linux/dma-mapping.h>
150
151 #include <asm/irq.h>
152 #include <asm/io.h>
153 #include <asm/uaccess.h>
154 #include <asm/system.h>
155
156 #if 0
157 #define dprintk printk
158 #else
159 #define dprintk(x...) do { } while (0)
160 #endif
161
162 #define TX_WORK_PER_LOOP 64
163 #define RX_WORK_PER_LOOP 64
164
165 /*
166 * Hardware access:
167 */
168
169 #define DEV_NEED_TIMERIRQ 0x00001 /* set the timer irq flag in the irq mask */
170 #define DEV_NEED_LINKTIMER 0x00002 /* poll link settings. Relies on the timer irq */
171 #define DEV_HAS_LARGEDESC 0x00004 /* device supports jumbo frames and needs packet format 2 */
172 #define DEV_HAS_HIGH_DMA 0x00008 /* device supports 64bit dma */
173 #define DEV_HAS_CHECKSUM 0x00010 /* device supports tx and rx checksum offloads */
174 #define DEV_HAS_VLAN 0x00020 /* device supports vlan tagging and striping */
175 #define DEV_HAS_MSI 0x00040 /* device supports MSI */
176 #define DEV_HAS_MSI_X 0x00080 /* device supports MSI-X */
177 #define DEV_HAS_POWER_CNTRL 0x00100 /* device supports power savings */
178 #define DEV_HAS_STATISTICS_V1 0x00200 /* device supports hw statistics version 1 */
179 #define DEV_HAS_STATISTICS_V2 0x00400 /* device supports hw statistics version 2 */
180 #define DEV_HAS_TEST_EXTENDED 0x00800 /* device supports extended diagnostic test */
181 #define DEV_HAS_MGMT_UNIT 0x01000 /* device supports management unit */
182 #define DEV_HAS_CORRECT_MACADDR 0x02000 /* device supports correct mac address order */
183 #define DEV_HAS_COLLISION_FIX 0x04000 /* device supports tx collision fix */
184 #define DEV_HAS_PAUSEFRAME_TX_V1 0x08000 /* device supports tx pause frames version 1 */
185 #define DEV_HAS_PAUSEFRAME_TX_V2 0x10000 /* device supports tx pause frames version 2 */
186 #define DEV_HAS_PAUSEFRAME_TX_V3 0x20000 /* device supports tx pause frames version 3 */
187 #define DEV_NEED_TX_LIMIT 0x40000 /* device needs to limit tx */
188
189 enum {
190 NvRegIrqStatus = 0x000,
191 #define NVREG_IRQSTAT_MIIEVENT 0x040
192 #define NVREG_IRQSTAT_MASK 0x81ff
193 NvRegIrqMask = 0x004,
194 #define NVREG_IRQ_RX_ERROR 0x0001
195 #define NVREG_IRQ_RX 0x0002
196 #define NVREG_IRQ_RX_NOBUF 0x0004
197 #define NVREG_IRQ_TX_ERR 0x0008
198 #define NVREG_IRQ_TX_OK 0x0010
199 #define NVREG_IRQ_TIMER 0x0020
200 #define NVREG_IRQ_LINK 0x0040
201 #define NVREG_IRQ_RX_FORCED 0x0080
202 #define NVREG_IRQ_TX_FORCED 0x0100
203 #define NVREG_IRQ_RECOVER_ERROR 0x8000
204 #define NVREG_IRQMASK_THROUGHPUT 0x00df
205 #define NVREG_IRQMASK_CPU 0x0060
206 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
207 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
208 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
209
210 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
211 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
212 NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
213
214 NvRegUnknownSetupReg6 = 0x008,
215 #define NVREG_UNKSETUP6_VAL 3
216
217 /*
218 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
219 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
220 */
221 NvRegPollingInterval = 0x00c,
222 #define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */
223 #define NVREG_POLL_DEFAULT_CPU 13
224 NvRegMSIMap0 = 0x020,
225 NvRegMSIMap1 = 0x024,
226 NvRegMSIIrqMask = 0x030,
227 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
228 NvRegMisc1 = 0x080,
229 #define NVREG_MISC1_PAUSE_TX 0x01
230 #define NVREG_MISC1_HD 0x02
231 #define NVREG_MISC1_FORCE 0x3b0f3c
232
233 NvRegMacReset = 0x34,
234 #define NVREG_MAC_RESET_ASSERT 0x0F3
235 NvRegTransmitterControl = 0x084,
236 #define NVREG_XMITCTL_START 0x01
237 #define NVREG_XMITCTL_MGMT_ST 0x40000000
238 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
239 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
240 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
241 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
242 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
243 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
244 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
245 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
246 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
247 NvRegTransmitterStatus = 0x088,
248 #define NVREG_XMITSTAT_BUSY 0x01
249
250 NvRegPacketFilterFlags = 0x8c,
251 #define NVREG_PFF_PAUSE_RX 0x08
252 #define NVREG_PFF_ALWAYS 0x7F0000
253 #define NVREG_PFF_PROMISC 0x80
254 #define NVREG_PFF_MYADDR 0x20
255 #define NVREG_PFF_LOOPBACK 0x10
256
257 NvRegOffloadConfig = 0x90,
258 #define NVREG_OFFLOAD_HOMEPHY 0x601
259 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
260 NvRegReceiverControl = 0x094,
261 #define NVREG_RCVCTL_START 0x01
262 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
263 NvRegReceiverStatus = 0x98,
264 #define NVREG_RCVSTAT_BUSY 0x01
265
266 NvRegRandomSeed = 0x9c,
267 #define NVREG_RNDSEED_MASK 0x00ff
268 #define NVREG_RNDSEED_FORCE 0x7f00
269 #define NVREG_RNDSEED_FORCE2 0x2d00
270 #define NVREG_RNDSEED_FORCE3 0x7400
271
272 NvRegTxDeferral = 0xA0,
273 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
274 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
275 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
276 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
277 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
278 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
279 NvRegRxDeferral = 0xA4,
280 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
281 NvRegMacAddrA = 0xA8,
282 NvRegMacAddrB = 0xAC,
283 NvRegMulticastAddrA = 0xB0,
284 #define NVREG_MCASTADDRA_FORCE 0x01
285 NvRegMulticastAddrB = 0xB4,
286 NvRegMulticastMaskA = 0xB8,
287 #define NVREG_MCASTMASKA_NONE 0xffffffff
288 NvRegMulticastMaskB = 0xBC,
289 #define NVREG_MCASTMASKB_NONE 0xffff
290
291 NvRegPhyInterface = 0xC0,
292 #define PHY_RGMII 0x10000000
293
294 NvRegTxRingPhysAddr = 0x100,
295 NvRegRxRingPhysAddr = 0x104,
296 NvRegRingSizes = 0x108,
297 #define NVREG_RINGSZ_TXSHIFT 0
298 #define NVREG_RINGSZ_RXSHIFT 16
299 NvRegTransmitPoll = 0x10c,
300 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
301 NvRegLinkSpeed = 0x110,
302 #define NVREG_LINKSPEED_FORCE 0x10000
303 #define NVREG_LINKSPEED_10 1000
304 #define NVREG_LINKSPEED_100 100
305 #define NVREG_LINKSPEED_1000 50
306 #define NVREG_LINKSPEED_MASK (0xFFF)
307 NvRegUnknownSetupReg5 = 0x130,
308 #define NVREG_UNKSETUP5_BIT31 (1<<31)
309 NvRegTxWatermark = 0x13c,
310 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
311 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
312 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
313 NvRegTxRxControl = 0x144,
314 #define NVREG_TXRXCTL_KICK 0x0001
315 #define NVREG_TXRXCTL_BIT1 0x0002
316 #define NVREG_TXRXCTL_BIT2 0x0004
317 #define NVREG_TXRXCTL_IDLE 0x0008
318 #define NVREG_TXRXCTL_RESET 0x0010
319 #define NVREG_TXRXCTL_RXCHECK 0x0400
320 #define NVREG_TXRXCTL_DESC_1 0
321 #define NVREG_TXRXCTL_DESC_2 0x002100
322 #define NVREG_TXRXCTL_DESC_3 0xc02200
323 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
324 #define NVREG_TXRXCTL_VLANINS 0x00080
325 NvRegTxRingPhysAddrHigh = 0x148,
326 NvRegRxRingPhysAddrHigh = 0x14C,
327 NvRegTxPauseFrame = 0x170,
328 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
329 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
330 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
331 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
332 NvRegMIIStatus = 0x180,
333 #define NVREG_MIISTAT_ERROR 0x0001
334 #define NVREG_MIISTAT_LINKCHANGE 0x0008
335 #define NVREG_MIISTAT_MASK_RW 0x0007
336 #define NVREG_MIISTAT_MASK_ALL 0x000f
337 NvRegMIIMask = 0x184,
338 #define NVREG_MII_LINKCHANGE 0x0008
339
340 NvRegAdapterControl = 0x188,
341 #define NVREG_ADAPTCTL_START 0x02
342 #define NVREG_ADAPTCTL_LINKUP 0x04
343 #define NVREG_ADAPTCTL_PHYVALID 0x40000
344 #define NVREG_ADAPTCTL_RUNNING 0x100000
345 #define NVREG_ADAPTCTL_PHYSHIFT 24
346 NvRegMIISpeed = 0x18c,
347 #define NVREG_MIISPEED_BIT8 (1<<8)
348 #define NVREG_MIIDELAY 5
349 NvRegMIIControl = 0x190,
350 #define NVREG_MIICTL_INUSE 0x08000
351 #define NVREG_MIICTL_WRITE 0x00400
352 #define NVREG_MIICTL_ADDRSHIFT 5
353 NvRegMIIData = 0x194,
354 NvRegWakeUpFlags = 0x200,
355 #define NVREG_WAKEUPFLAGS_VAL 0x7770
356 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
357 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
358 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
359 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
360 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
361 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
362 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
363 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
364 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
365 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
366
367 NvRegPatternCRC = 0x204,
368 NvRegPatternMask = 0x208,
369 NvRegPowerCap = 0x268,
370 #define NVREG_POWERCAP_D3SUPP (1<<30)
371 #define NVREG_POWERCAP_D2SUPP (1<<26)
372 #define NVREG_POWERCAP_D1SUPP (1<<25)
373 NvRegPowerState = 0x26c,
374 #define NVREG_POWERSTATE_POWEREDUP 0x8000
375 #define NVREG_POWERSTATE_VALID 0x0100
376 #define NVREG_POWERSTATE_MASK 0x0003
377 #define NVREG_POWERSTATE_D0 0x0000
378 #define NVREG_POWERSTATE_D1 0x0001
379 #define NVREG_POWERSTATE_D2 0x0002
380 #define NVREG_POWERSTATE_D3 0x0003
381 NvRegTxCnt = 0x280,
382 NvRegTxZeroReXmt = 0x284,
383 NvRegTxOneReXmt = 0x288,
384 NvRegTxManyReXmt = 0x28c,
385 NvRegTxLateCol = 0x290,
386 NvRegTxUnderflow = 0x294,
387 NvRegTxLossCarrier = 0x298,
388 NvRegTxExcessDef = 0x29c,
389 NvRegTxRetryErr = 0x2a0,
390 NvRegRxFrameErr = 0x2a4,
391 NvRegRxExtraByte = 0x2a8,
392 NvRegRxLateCol = 0x2ac,
393 NvRegRxRunt = 0x2b0,
394 NvRegRxFrameTooLong = 0x2b4,
395 NvRegRxOverflow = 0x2b8,
396 NvRegRxFCSErr = 0x2bc,
397 NvRegRxFrameAlignErr = 0x2c0,
398 NvRegRxLenErr = 0x2c4,
399 NvRegRxUnicast = 0x2c8,
400 NvRegRxMulticast = 0x2cc,
401 NvRegRxBroadcast = 0x2d0,
402 NvRegTxDef = 0x2d4,
403 NvRegTxFrame = 0x2d8,
404 NvRegRxCnt = 0x2dc,
405 NvRegTxPause = 0x2e0,
406 NvRegRxPause = 0x2e4,
407 NvRegRxDropFrame = 0x2e8,
408 NvRegVlanControl = 0x300,
409 #define NVREG_VLANCONTROL_ENABLE 0x2000
410 NvRegMSIXMap0 = 0x3e0,
411 NvRegMSIXMap1 = 0x3e4,
412 NvRegMSIXIrqStatus = 0x3f0,
413
414 NvRegPowerState2 = 0x600,
415 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
416 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
417 };
418
419 /* Big endian: should work, but is untested */
420 struct ring_desc {
421 __le32 buf;
422 __le32 flaglen;
423 };
424
425 struct ring_desc_ex {
426 __le32 bufhigh;
427 __le32 buflow;
428 __le32 txvlan;
429 __le32 flaglen;
430 };
431
432 union ring_type {
433 struct ring_desc* orig;
434 struct ring_desc_ex* ex;
435 };
436
437 #define FLAG_MASK_V1 0xffff0000
438 #define FLAG_MASK_V2 0xffffc000
439 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
440 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
441
442 #define NV_TX_LASTPACKET (1<<16)
443 #define NV_TX_RETRYERROR (1<<19)
444 #define NV_TX_FORCED_INTERRUPT (1<<24)
445 #define NV_TX_DEFERRED (1<<26)
446 #define NV_TX_CARRIERLOST (1<<27)
447 #define NV_TX_LATECOLLISION (1<<28)
448 #define NV_TX_UNDERFLOW (1<<29)
449 #define NV_TX_ERROR (1<<30)
450 #define NV_TX_VALID (1<<31)
451
452 #define NV_TX2_LASTPACKET (1<<29)
453 #define NV_TX2_RETRYERROR (1<<18)
454 #define NV_TX2_FORCED_INTERRUPT (1<<30)
455 #define NV_TX2_DEFERRED (1<<25)
456 #define NV_TX2_CARRIERLOST (1<<26)
457 #define NV_TX2_LATECOLLISION (1<<27)
458 #define NV_TX2_UNDERFLOW (1<<28)
459 /* error and valid are the same for both */
460 #define NV_TX2_ERROR (1<<30)
461 #define NV_TX2_VALID (1<<31)
462 #define NV_TX2_TSO (1<<28)
463 #define NV_TX2_TSO_SHIFT 14
464 #define NV_TX2_TSO_MAX_SHIFT 14
465 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
466 #define NV_TX2_CHECKSUM_L3 (1<<27)
467 #define NV_TX2_CHECKSUM_L4 (1<<26)
468
469 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
470
471 #define NV_RX_DESCRIPTORVALID (1<<16)
472 #define NV_RX_MISSEDFRAME (1<<17)
473 #define NV_RX_SUBSTRACT1 (1<<18)
474 #define NV_RX_ERROR1 (1<<23)
475 #define NV_RX_ERROR2 (1<<24)
476 #define NV_RX_ERROR3 (1<<25)
477 #define NV_RX_ERROR4 (1<<26)
478 #define NV_RX_CRCERR (1<<27)
479 #define NV_RX_OVERFLOW (1<<28)
480 #define NV_RX_FRAMINGERR (1<<29)
481 #define NV_RX_ERROR (1<<30)
482 #define NV_RX_AVAIL (1<<31)
483
484 #define NV_RX2_CHECKSUMMASK (0x1C000000)
485 #define NV_RX2_CHECKSUM_IP (0x10000000)
486 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
487 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
488 #define NV_RX2_DESCRIPTORVALID (1<<29)
489 #define NV_RX2_SUBSTRACT1 (1<<25)
490 #define NV_RX2_ERROR1 (1<<18)
491 #define NV_RX2_ERROR2 (1<<19)
492 #define NV_RX2_ERROR3 (1<<20)
493 #define NV_RX2_ERROR4 (1<<21)
494 #define NV_RX2_CRCERR (1<<22)
495 #define NV_RX2_OVERFLOW (1<<23)
496 #define NV_RX2_FRAMINGERR (1<<24)
497 /* error and avail are the same for both */
498 #define NV_RX2_ERROR (1<<30)
499 #define NV_RX2_AVAIL (1<<31)
500
501 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
502 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
503
504 /* Miscelaneous hardware related defines: */
505 #define NV_PCI_REGSZ_VER1 0x270
506 #define NV_PCI_REGSZ_VER2 0x2d4
507 #define NV_PCI_REGSZ_VER3 0x604
508
509 /* various timeout delays: all in usec */
510 #define NV_TXRX_RESET_DELAY 4
511 #define NV_TXSTOP_DELAY1 10
512 #define NV_TXSTOP_DELAY1MAX 500000
513 #define NV_TXSTOP_DELAY2 100
514 #define NV_RXSTOP_DELAY1 10
515 #define NV_RXSTOP_DELAY1MAX 500000
516 #define NV_RXSTOP_DELAY2 100
517 #define NV_SETUP5_DELAY 5
518 #define NV_SETUP5_DELAYMAX 50000
519 #define NV_POWERUP_DELAY 5
520 #define NV_POWERUP_DELAYMAX 5000
521 #define NV_MIIBUSY_DELAY 50
522 #define NV_MIIPHY_DELAY 10
523 #define NV_MIIPHY_DELAYMAX 10000
524 #define NV_MAC_RESET_DELAY 64
525
526 #define NV_WAKEUPPATTERNS 5
527 #define NV_WAKEUPMASKENTRIES 4
528
529 /* General driver defaults */
530 #define NV_WATCHDOG_TIMEO (5*HZ)
531
532 #define RX_RING_DEFAULT 128
533 #define TX_RING_DEFAULT 256
534 #define RX_RING_MIN 128
535 #define TX_RING_MIN 64
536 #define RING_MAX_DESC_VER_1 1024
537 #define RING_MAX_DESC_VER_2_3 16384
538
539 /* rx/tx mac addr + type + vlan + align + slack*/
540 #define NV_RX_HEADERS (64)
541 /* even more slack. */
542 #define NV_RX_ALLOC_PAD (64)
543
544 /* maximum mtu size */
545 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
546 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
547
548 #define OOM_REFILL (1+HZ/20)
549 #define POLL_WAIT (1+HZ/100)
550 #define LINK_TIMEOUT (3*HZ)
551 #define STATS_INTERVAL (10*HZ)
552
553 /*
554 * desc_ver values:
555 * The nic supports three different descriptor types:
556 * - DESC_VER_1: Original
557 * - DESC_VER_2: support for jumbo frames.
558 * - DESC_VER_3: 64-bit format.
559 */
560 #define DESC_VER_1 1
561 #define DESC_VER_2 2
562 #define DESC_VER_3 3
563
564 /* PHY defines */
565 #define PHY_OUI_MARVELL 0x5043
566 #define PHY_OUI_CICADA 0x03f1
567 #define PHY_OUI_VITESSE 0x01c1
568 #define PHY_OUI_REALTEK 0x0732
569 #define PHYID1_OUI_MASK 0x03ff
570 #define PHYID1_OUI_SHFT 6
571 #define PHYID2_OUI_MASK 0xfc00
572 #define PHYID2_OUI_SHFT 10
573 #define PHYID2_MODEL_MASK 0x03f0
574 #define PHY_MODEL_MARVELL_E3016 0x220
575 #define PHY_MARVELL_E3016_INITMASK 0x0300
576 #define PHY_CICADA_INIT1 0x0f000
577 #define PHY_CICADA_INIT2 0x0e00
578 #define PHY_CICADA_INIT3 0x01000
579 #define PHY_CICADA_INIT4 0x0200
580 #define PHY_CICADA_INIT5 0x0004
581 #define PHY_CICADA_INIT6 0x02000
582 #define PHY_VITESSE_INIT_REG1 0x1f
583 #define PHY_VITESSE_INIT_REG2 0x10
584 #define PHY_VITESSE_INIT_REG3 0x11
585 #define PHY_VITESSE_INIT_REG4 0x12
586 #define PHY_VITESSE_INIT_MSK1 0xc
587 #define PHY_VITESSE_INIT_MSK2 0x0180
588 #define PHY_VITESSE_INIT1 0x52b5
589 #define PHY_VITESSE_INIT2 0xaf8a
590 #define PHY_VITESSE_INIT3 0x8
591 #define PHY_VITESSE_INIT4 0x8f8a
592 #define PHY_VITESSE_INIT5 0xaf86
593 #define PHY_VITESSE_INIT6 0x8f86
594 #define PHY_VITESSE_INIT7 0xaf82
595 #define PHY_VITESSE_INIT8 0x0100
596 #define PHY_VITESSE_INIT9 0x8f82
597 #define PHY_VITESSE_INIT10 0x0
598 #define PHY_REALTEK_INIT_REG1 0x1f
599 #define PHY_REALTEK_INIT_REG2 0x19
600 #define PHY_REALTEK_INIT_REG3 0x13
601 #define PHY_REALTEK_INIT1 0x0000
602 #define PHY_REALTEK_INIT2 0x8e00
603 #define PHY_REALTEK_INIT3 0x0001
604 #define PHY_REALTEK_INIT4 0xad17
605
606 #define PHY_GIGABIT 0x0100
607
608 #define PHY_TIMEOUT 0x1
609 #define PHY_ERROR 0x2
610
611 #define PHY_100 0x1
612 #define PHY_1000 0x2
613 #define PHY_HALF 0x100
614
615 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
616 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
617 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
618 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
619 #define NV_PAUSEFRAME_RX_REQ 0x0010
620 #define NV_PAUSEFRAME_TX_REQ 0x0020
621 #define NV_PAUSEFRAME_AUTONEG 0x0040
622
623 /* MSI/MSI-X defines */
624 #define NV_MSI_X_MAX_VECTORS 8
625 #define NV_MSI_X_VECTORS_MASK 0x000f
626 #define NV_MSI_CAPABLE 0x0010
627 #define NV_MSI_X_CAPABLE 0x0020
628 #define NV_MSI_ENABLED 0x0040
629 #define NV_MSI_X_ENABLED 0x0080
630
631 #define NV_MSI_X_VECTOR_ALL 0x0
632 #define NV_MSI_X_VECTOR_RX 0x0
633 #define NV_MSI_X_VECTOR_TX 0x1
634 #define NV_MSI_X_VECTOR_OTHER 0x2
635
636 #define NV_RESTART_TX 0x1
637 #define NV_RESTART_RX 0x2
638
639 #define NV_TX_LIMIT_COUNT 16
640
641 /* statistics */
642 struct nv_ethtool_str {
643 char name[ETH_GSTRING_LEN];
644 };
645
646 static const struct nv_ethtool_str nv_estats_str[] = {
647 { "tx_bytes" },
648 { "tx_zero_rexmt" },
649 { "tx_one_rexmt" },
650 { "tx_many_rexmt" },
651 { "tx_late_collision" },
652 { "tx_fifo_errors" },
653 { "tx_carrier_errors" },
654 { "tx_excess_deferral" },
655 { "tx_retry_error" },
656 { "rx_frame_error" },
657 { "rx_extra_byte" },
658 { "rx_late_collision" },
659 { "rx_runt" },
660 { "rx_frame_too_long" },
661 { "rx_over_errors" },
662 { "rx_crc_errors" },
663 { "rx_frame_align_error" },
664 { "rx_length_error" },
665 { "rx_unicast" },
666 { "rx_multicast" },
667 { "rx_broadcast" },
668 { "rx_packets" },
669 { "rx_errors_total" },
670 { "tx_errors_total" },
671
672 /* version 2 stats */
673 { "tx_deferral" },
674 { "tx_packets" },
675 { "rx_bytes" },
676 { "tx_pause" },
677 { "rx_pause" },
678 { "rx_drop_frame" }
679 };
680
681 struct nv_ethtool_stats {
682 u64 tx_bytes;
683 u64 tx_zero_rexmt;
684 u64 tx_one_rexmt;
685 u64 tx_many_rexmt;
686 u64 tx_late_collision;
687 u64 tx_fifo_errors;
688 u64 tx_carrier_errors;
689 u64 tx_excess_deferral;
690 u64 tx_retry_error;
691 u64 rx_frame_error;
692 u64 rx_extra_byte;
693 u64 rx_late_collision;
694 u64 rx_runt;
695 u64 rx_frame_too_long;
696 u64 rx_over_errors;
697 u64 rx_crc_errors;
698 u64 rx_frame_align_error;
699 u64 rx_length_error;
700 u64 rx_unicast;
701 u64 rx_multicast;
702 u64 rx_broadcast;
703 u64 rx_packets;
704 u64 rx_errors_total;
705 u64 tx_errors_total;
706
707 /* version 2 stats */
708 u64 tx_deferral;
709 u64 tx_packets;
710 u64 rx_bytes;
711 u64 tx_pause;
712 u64 rx_pause;
713 u64 rx_drop_frame;
714 };
715
716 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
717 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
718
719 /* diagnostics */
720 #define NV_TEST_COUNT_BASE 3
721 #define NV_TEST_COUNT_EXTENDED 4
722
723 static const struct nv_ethtool_str nv_etests_str[] = {
724 { "link (online/offline)" },
725 { "register (offline) " },
726 { "interrupt (offline) " },
727 { "loopback (offline) " }
728 };
729
730 struct register_test {
731 __u32 reg;
732 __u32 mask;
733 };
734
735 static const struct register_test nv_registers_test[] = {
736 { NvRegUnknownSetupReg6, 0x01 },
737 { NvRegMisc1, 0x03c },
738 { NvRegOffloadConfig, 0x03ff },
739 { NvRegMulticastAddrA, 0xffffffff },
740 { NvRegTxWatermark, 0x0ff },
741 { NvRegWakeUpFlags, 0x07777 },
742 { 0,0 }
743 };
744
745 struct nv_skb_map {
746 struct sk_buff *skb;
747 dma_addr_t dma;
748 unsigned int dma_len;
749 struct ring_desc_ex *first_tx_desc;
750 struct nv_skb_map *next_tx_ctx;
751 };
752
753 /*
754 * SMP locking:
755 * All hardware access under dev->priv->lock, except the performance
756 * critical parts:
757 * - rx is (pseudo-) lockless: it relies on the single-threading provided
758 * by the arch code for interrupts.
759 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
760 * needs dev->priv->lock :-(
761 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
762 */
763
764 /* in dev: base, irq */
765 struct fe_priv {
766 spinlock_t lock;
767
768 struct net_device *dev;
769 struct napi_struct napi;
770
771 /* General data:
772 * Locking: spin_lock(&np->lock); */
773 struct nv_ethtool_stats estats;
774 int in_shutdown;
775 u32 linkspeed;
776 int duplex;
777 int autoneg;
778 int fixed_mode;
779 int phyaddr;
780 int wolenabled;
781 unsigned int phy_oui;
782 unsigned int phy_model;
783 u16 gigabit;
784 int intr_test;
785 int recover_error;
786
787 /* General data: RO fields */
788 dma_addr_t ring_addr;
789 struct pci_dev *pci_dev;
790 u32 orig_mac[2];
791 u32 irqmask;
792 u32 desc_ver;
793 u32 txrxctl_bits;
794 u32 vlanctl_bits;
795 u32 driver_data;
796 u32 register_size;
797 int rx_csum;
798 u32 mac_in_use;
799
800 void __iomem *base;
801
802 /* rx specific fields.
803 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
804 */
805 union ring_type get_rx, put_rx, first_rx, last_rx;
806 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
807 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
808 struct nv_skb_map *rx_skb;
809
810 union ring_type rx_ring;
811 unsigned int rx_buf_sz;
812 unsigned int pkt_limit;
813 struct timer_list oom_kick;
814 struct timer_list nic_poll;
815 struct timer_list stats_poll;
816 u32 nic_poll_irq;
817 int rx_ring_size;
818
819 /* media detection workaround.
820 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
821 */
822 int need_linktimer;
823 unsigned long link_timeout;
824 /*
825 * tx specific fields.
826 */
827 union ring_type get_tx, put_tx, first_tx, last_tx;
828 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
829 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
830 struct nv_skb_map *tx_skb;
831
832 union ring_type tx_ring;
833 u32 tx_flags;
834 int tx_ring_size;
835 int tx_limit;
836 u32 tx_pkts_in_progress;
837 struct nv_skb_map *tx_change_owner;
838 struct nv_skb_map *tx_end_flip;
839 int tx_stop;
840
841 /* vlan fields */
842 struct vlan_group *vlangrp;
843
844 /* msi/msi-x fields */
845 u32 msi_flags;
846 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
847
848 /* flow control */
849 u32 pause_flags;
850 };
851
852 /*
853 * Maximum number of loops until we assume that a bit in the irq mask
854 * is stuck. Overridable with module param.
855 */
856 static int max_interrupt_work = 5;
857
858 /*
859 * Optimization can be either throuput mode or cpu mode
860 *
861 * Throughput Mode: Every tx and rx packet will generate an interrupt.
862 * CPU Mode: Interrupts are controlled by a timer.
863 */
864 enum {
865 NV_OPTIMIZATION_MODE_THROUGHPUT,
866 NV_OPTIMIZATION_MODE_CPU
867 };
868 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
869
870 /*
871 * Poll interval for timer irq
872 *
873 * This interval determines how frequent an interrupt is generated.
874 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
875 * Min = 0, and Max = 65535
876 */
877 static int poll_interval = -1;
878
879 /*
880 * MSI interrupts
881 */
882 enum {
883 NV_MSI_INT_DISABLED,
884 NV_MSI_INT_ENABLED
885 };
886 static int msi = NV_MSI_INT_ENABLED;
887
888 /*
889 * MSIX interrupts
890 */
891 enum {
892 NV_MSIX_INT_DISABLED,
893 NV_MSIX_INT_ENABLED
894 };
895 static int msix = NV_MSIX_INT_DISABLED;
896
897 /*
898 * DMA 64bit
899 */
900 enum {
901 NV_DMA_64BIT_DISABLED,
902 NV_DMA_64BIT_ENABLED
903 };
904 static int dma_64bit = NV_DMA_64BIT_ENABLED;
905
906 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
907 {
908 return netdev_priv(dev);
909 }
910
911 static inline u8 __iomem *get_hwbase(struct net_device *dev)
912 {
913 return ((struct fe_priv *)netdev_priv(dev))->base;
914 }
915
916 static inline void pci_push(u8 __iomem *base)
917 {
918 /* force out pending posted writes */
919 readl(base);
920 }
921
922 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
923 {
924 return le32_to_cpu(prd->flaglen)
925 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
926 }
927
928 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
929 {
930 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
931 }
932
933 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
934 int delay, int delaymax, const char *msg)
935 {
936 u8 __iomem *base = get_hwbase(dev);
937
938 pci_push(base);
939 do {
940 udelay(delay);
941 delaymax -= delay;
942 if (delaymax < 0) {
943 if (msg)
944 printk(msg);
945 return 1;
946 }
947 } while ((readl(base + offset) & mask) != target);
948 return 0;
949 }
950
951 #define NV_SETUP_RX_RING 0x01
952 #define NV_SETUP_TX_RING 0x02
953
954 static inline u32 dma_low(dma_addr_t addr)
955 {
956 return addr;
957 }
958
959 static inline u32 dma_high(dma_addr_t addr)
960 {
961 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
962 }
963
964 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
965 {
966 struct fe_priv *np = get_nvpriv(dev);
967 u8 __iomem *base = get_hwbase(dev);
968
969 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
970 if (rxtx_flags & NV_SETUP_RX_RING) {
971 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
972 }
973 if (rxtx_flags & NV_SETUP_TX_RING) {
974 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
975 }
976 } else {
977 if (rxtx_flags & NV_SETUP_RX_RING) {
978 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
979 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
980 }
981 if (rxtx_flags & NV_SETUP_TX_RING) {
982 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
983 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
984 }
985 }
986 }
987
988 static void free_rings(struct net_device *dev)
989 {
990 struct fe_priv *np = get_nvpriv(dev);
991
992 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
993 if (np->rx_ring.orig)
994 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
995 np->rx_ring.orig, np->ring_addr);
996 } else {
997 if (np->rx_ring.ex)
998 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
999 np->rx_ring.ex, np->ring_addr);
1000 }
1001 if (np->rx_skb)
1002 kfree(np->rx_skb);
1003 if (np->tx_skb)
1004 kfree(np->tx_skb);
1005 }
1006
1007 static int using_multi_irqs(struct net_device *dev)
1008 {
1009 struct fe_priv *np = get_nvpriv(dev);
1010
1011 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1012 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1013 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1014 return 0;
1015 else
1016 return 1;
1017 }
1018
1019 static void nv_enable_irq(struct net_device *dev)
1020 {
1021 struct fe_priv *np = get_nvpriv(dev);
1022
1023 if (!using_multi_irqs(dev)) {
1024 if (np->msi_flags & NV_MSI_X_ENABLED)
1025 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1026 else
1027 enable_irq(np->pci_dev->irq);
1028 } else {
1029 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1030 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1031 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1032 }
1033 }
1034
1035 static void nv_disable_irq(struct net_device *dev)
1036 {
1037 struct fe_priv *np = get_nvpriv(dev);
1038
1039 if (!using_multi_irqs(dev)) {
1040 if (np->msi_flags & NV_MSI_X_ENABLED)
1041 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1042 else
1043 disable_irq(np->pci_dev->irq);
1044 } else {
1045 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1046 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1047 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1048 }
1049 }
1050
1051 /* In MSIX mode, a write to irqmask behaves as XOR */
1052 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1053 {
1054 u8 __iomem *base = get_hwbase(dev);
1055
1056 writel(mask, base + NvRegIrqMask);
1057 }
1058
1059 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1060 {
1061 struct fe_priv *np = get_nvpriv(dev);
1062 u8 __iomem *base = get_hwbase(dev);
1063
1064 if (np->msi_flags & NV_MSI_X_ENABLED) {
1065 writel(mask, base + NvRegIrqMask);
1066 } else {
1067 if (np->msi_flags & NV_MSI_ENABLED)
1068 writel(0, base + NvRegMSIIrqMask);
1069 writel(0, base + NvRegIrqMask);
1070 }
1071 }
1072
1073 #define MII_READ (-1)
1074 /* mii_rw: read/write a register on the PHY.
1075 *
1076 * Caller must guarantee serialization
1077 */
1078 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1079 {
1080 u8 __iomem *base = get_hwbase(dev);
1081 u32 reg;
1082 int retval;
1083
1084 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1085
1086 reg = readl(base + NvRegMIIControl);
1087 if (reg & NVREG_MIICTL_INUSE) {
1088 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1089 udelay(NV_MIIBUSY_DELAY);
1090 }
1091
1092 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1093 if (value != MII_READ) {
1094 writel(value, base + NvRegMIIData);
1095 reg |= NVREG_MIICTL_WRITE;
1096 }
1097 writel(reg, base + NvRegMIIControl);
1098
1099 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1100 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1101 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1102 dev->name, miireg, addr);
1103 retval = -1;
1104 } else if (value != MII_READ) {
1105 /* it was a write operation - fewer failures are detectable */
1106 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1107 dev->name, value, miireg, addr);
1108 retval = 0;
1109 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1110 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1111 dev->name, miireg, addr);
1112 retval = -1;
1113 } else {
1114 retval = readl(base + NvRegMIIData);
1115 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1116 dev->name, miireg, addr, retval);
1117 }
1118
1119 return retval;
1120 }
1121
1122 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1123 {
1124 struct fe_priv *np = netdev_priv(dev);
1125 u32 miicontrol;
1126 unsigned int tries = 0;
1127
1128 miicontrol = BMCR_RESET | bmcr_setup;
1129 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1130 return -1;
1131 }
1132
1133 /* wait for 500ms */
1134 msleep(500);
1135
1136 /* must wait till reset is deasserted */
1137 while (miicontrol & BMCR_RESET) {
1138 msleep(10);
1139 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1140 /* FIXME: 100 tries seem excessive */
1141 if (tries++ > 100)
1142 return -1;
1143 }
1144 return 0;
1145 }
1146
1147 static int phy_init(struct net_device *dev)
1148 {
1149 struct fe_priv *np = get_nvpriv(dev);
1150 u8 __iomem *base = get_hwbase(dev);
1151 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1152
1153 /* phy errata for E3016 phy */
1154 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1155 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1156 reg &= ~PHY_MARVELL_E3016_INITMASK;
1157 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1158 printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1159 return PHY_ERROR;
1160 }
1161 }
1162 if (np->phy_oui == PHY_OUI_REALTEK) {
1163 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1164 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1165 return PHY_ERROR;
1166 }
1167 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1168 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1169 return PHY_ERROR;
1170 }
1171 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1172 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1173 return PHY_ERROR;
1174 }
1175 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1176 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1177 return PHY_ERROR;
1178 }
1179 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1180 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1181 return PHY_ERROR;
1182 }
1183 }
1184
1185 /* set advertise register */
1186 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1187 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1188 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1189 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1190 return PHY_ERROR;
1191 }
1192
1193 /* get phy interface type */
1194 phyinterface = readl(base + NvRegPhyInterface);
1195
1196 /* see if gigabit phy */
1197 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1198 if (mii_status & PHY_GIGABIT) {
1199 np->gigabit = PHY_GIGABIT;
1200 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1201 mii_control_1000 &= ~ADVERTISE_1000HALF;
1202 if (phyinterface & PHY_RGMII)
1203 mii_control_1000 |= ADVERTISE_1000FULL;
1204 else
1205 mii_control_1000 &= ~ADVERTISE_1000FULL;
1206
1207 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1208 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1209 return PHY_ERROR;
1210 }
1211 }
1212 else
1213 np->gigabit = 0;
1214
1215 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1216 mii_control |= BMCR_ANENABLE;
1217
1218 /* reset the phy
1219 * (certain phys need bmcr to be setup with reset)
1220 */
1221 if (phy_reset(dev, mii_control)) {
1222 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1223 return PHY_ERROR;
1224 }
1225
1226 /* phy vendor specific configuration */
1227 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1228 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1229 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1230 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1231 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1232 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1233 return PHY_ERROR;
1234 }
1235 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1236 phy_reserved |= PHY_CICADA_INIT5;
1237 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1238 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1239 return PHY_ERROR;
1240 }
1241 }
1242 if (np->phy_oui == PHY_OUI_CICADA) {
1243 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1244 phy_reserved |= PHY_CICADA_INIT6;
1245 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1246 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1247 return PHY_ERROR;
1248 }
1249 }
1250 if (np->phy_oui == PHY_OUI_VITESSE) {
1251 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1252 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1253 return PHY_ERROR;
1254 }
1255 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1256 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1257 return PHY_ERROR;
1258 }
1259 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1260 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1261 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1262 return PHY_ERROR;
1263 }
1264 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1265 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1266 phy_reserved |= PHY_VITESSE_INIT3;
1267 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1268 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1269 return PHY_ERROR;
1270 }
1271 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1272 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1273 return PHY_ERROR;
1274 }
1275 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1276 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1277 return PHY_ERROR;
1278 }
1279 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1280 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1281 phy_reserved |= PHY_VITESSE_INIT3;
1282 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1283 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1284 return PHY_ERROR;
1285 }
1286 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1287 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1288 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1289 return PHY_ERROR;
1290 }
1291 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1292 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1293 return PHY_ERROR;
1294 }
1295 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1296 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1297 return PHY_ERROR;
1298 }
1299 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1300 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1301 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1302 return PHY_ERROR;
1303 }
1304 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1305 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1306 phy_reserved |= PHY_VITESSE_INIT8;
1307 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1308 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1309 return PHY_ERROR;
1310 }
1311 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1312 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1313 return PHY_ERROR;
1314 }
1315 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1316 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1317 return PHY_ERROR;
1318 }
1319 }
1320 if (np->phy_oui == PHY_OUI_REALTEK) {
1321 /* reset could have cleared these out, set them back */
1322 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1323 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1324 return PHY_ERROR;
1325 }
1326 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1327 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1328 return PHY_ERROR;
1329 }
1330 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1331 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1332 return PHY_ERROR;
1333 }
1334 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1335 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1336 return PHY_ERROR;
1337 }
1338 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1339 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1340 return PHY_ERROR;
1341 }
1342 }
1343
1344 /* some phys clear out pause advertisment on reset, set it back */
1345 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1346
1347 /* restart auto negotiation */
1348 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1349 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1350 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1351 return PHY_ERROR;
1352 }
1353
1354 return 0;
1355 }
1356
1357 static void nv_start_rx(struct net_device *dev)
1358 {
1359 struct fe_priv *np = netdev_priv(dev);
1360 u8 __iomem *base = get_hwbase(dev);
1361 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1362
1363 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1364 /* Already running? Stop it. */
1365 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1366 rx_ctrl &= ~NVREG_RCVCTL_START;
1367 writel(rx_ctrl, base + NvRegReceiverControl);
1368 pci_push(base);
1369 }
1370 writel(np->linkspeed, base + NvRegLinkSpeed);
1371 pci_push(base);
1372 rx_ctrl |= NVREG_RCVCTL_START;
1373 if (np->mac_in_use)
1374 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1375 writel(rx_ctrl, base + NvRegReceiverControl);
1376 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1377 dev->name, np->duplex, np->linkspeed);
1378 pci_push(base);
1379 }
1380
1381 static void nv_stop_rx(struct net_device *dev)
1382 {
1383 struct fe_priv *np = netdev_priv(dev);
1384 u8 __iomem *base = get_hwbase(dev);
1385 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1386
1387 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1388 if (!np->mac_in_use)
1389 rx_ctrl &= ~NVREG_RCVCTL_START;
1390 else
1391 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1392 writel(rx_ctrl, base + NvRegReceiverControl);
1393 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1394 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1395 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1396
1397 udelay(NV_RXSTOP_DELAY2);
1398 if (!np->mac_in_use)
1399 writel(0, base + NvRegLinkSpeed);
1400 }
1401
1402 static void nv_start_tx(struct net_device *dev)
1403 {
1404 struct fe_priv *np = netdev_priv(dev);
1405 u8 __iomem *base = get_hwbase(dev);
1406 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1407
1408 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1409 tx_ctrl |= NVREG_XMITCTL_START;
1410 if (np->mac_in_use)
1411 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1412 writel(tx_ctrl, base + NvRegTransmitterControl);
1413 pci_push(base);
1414 }
1415
1416 static void nv_stop_tx(struct net_device *dev)
1417 {
1418 struct fe_priv *np = netdev_priv(dev);
1419 u8 __iomem *base = get_hwbase(dev);
1420 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1421
1422 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1423 if (!np->mac_in_use)
1424 tx_ctrl &= ~NVREG_XMITCTL_START;
1425 else
1426 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1427 writel(tx_ctrl, base + NvRegTransmitterControl);
1428 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1429 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1430 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1431
1432 udelay(NV_TXSTOP_DELAY2);
1433 if (!np->mac_in_use)
1434 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1435 base + NvRegTransmitPoll);
1436 }
1437
1438 static void nv_txrx_reset(struct net_device *dev)
1439 {
1440 struct fe_priv *np = netdev_priv(dev);
1441 u8 __iomem *base = get_hwbase(dev);
1442
1443 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1444 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1445 pci_push(base);
1446 udelay(NV_TXRX_RESET_DELAY);
1447 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1448 pci_push(base);
1449 }
1450
1451 static void nv_mac_reset(struct net_device *dev)
1452 {
1453 struct fe_priv *np = netdev_priv(dev);
1454 u8 __iomem *base = get_hwbase(dev);
1455 u32 temp1, temp2, temp3;
1456
1457 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1458
1459 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1460 pci_push(base);
1461
1462 /* save registers since they will be cleared on reset */
1463 temp1 = readl(base + NvRegMacAddrA);
1464 temp2 = readl(base + NvRegMacAddrB);
1465 temp3 = readl(base + NvRegTransmitPoll);
1466
1467 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1468 pci_push(base);
1469 udelay(NV_MAC_RESET_DELAY);
1470 writel(0, base + NvRegMacReset);
1471 pci_push(base);
1472 udelay(NV_MAC_RESET_DELAY);
1473
1474 /* restore saved registers */
1475 writel(temp1, base + NvRegMacAddrA);
1476 writel(temp2, base + NvRegMacAddrB);
1477 writel(temp3, base + NvRegTransmitPoll);
1478
1479 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1480 pci_push(base);
1481 }
1482
1483 static void nv_get_hw_stats(struct net_device *dev)
1484 {
1485 struct fe_priv *np = netdev_priv(dev);
1486 u8 __iomem *base = get_hwbase(dev);
1487
1488 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1489 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1490 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1491 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1492 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1493 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1494 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1495 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1496 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1497 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1498 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1499 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1500 np->estats.rx_runt += readl(base + NvRegRxRunt);
1501 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1502 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1503 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1504 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1505 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1506 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1507 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1508 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1509 np->estats.rx_packets =
1510 np->estats.rx_unicast +
1511 np->estats.rx_multicast +
1512 np->estats.rx_broadcast;
1513 np->estats.rx_errors_total =
1514 np->estats.rx_crc_errors +
1515 np->estats.rx_over_errors +
1516 np->estats.rx_frame_error +
1517 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1518 np->estats.rx_late_collision +
1519 np->estats.rx_runt +
1520 np->estats.rx_frame_too_long;
1521 np->estats.tx_errors_total =
1522 np->estats.tx_late_collision +
1523 np->estats.tx_fifo_errors +
1524 np->estats.tx_carrier_errors +
1525 np->estats.tx_excess_deferral +
1526 np->estats.tx_retry_error;
1527
1528 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1529 np->estats.tx_deferral += readl(base + NvRegTxDef);
1530 np->estats.tx_packets += readl(base + NvRegTxFrame);
1531 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1532 np->estats.tx_pause += readl(base + NvRegTxPause);
1533 np->estats.rx_pause += readl(base + NvRegRxPause);
1534 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1535 }
1536 }
1537
1538 /*
1539 * nv_get_stats: dev->get_stats function
1540 * Get latest stats value from the nic.
1541 * Called with read_lock(&dev_base_lock) held for read -
1542 * only synchronized against unregister_netdevice.
1543 */
1544 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1545 {
1546 struct fe_priv *np = netdev_priv(dev);
1547
1548 /* If the nic supports hw counters then retrieve latest values */
1549 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1550 nv_get_hw_stats(dev);
1551
1552 /* copy to net_device stats */
1553 dev->stats.tx_bytes = np->estats.tx_bytes;
1554 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1555 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1556 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1557 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1558 dev->stats.rx_errors = np->estats.rx_errors_total;
1559 dev->stats.tx_errors = np->estats.tx_errors_total;
1560 }
1561
1562 return &dev->stats;
1563 }
1564
1565 /*
1566 * nv_alloc_rx: fill rx ring entries.
1567 * Return 1 if the allocations for the skbs failed and the
1568 * rx engine is without Available descriptors
1569 */
1570 static int nv_alloc_rx(struct net_device *dev)
1571 {
1572 struct fe_priv *np = netdev_priv(dev);
1573 struct ring_desc* less_rx;
1574
1575 less_rx = np->get_rx.orig;
1576 if (less_rx-- == np->first_rx.orig)
1577 less_rx = np->last_rx.orig;
1578
1579 while (np->put_rx.orig != less_rx) {
1580 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1581 if (skb) {
1582 np->put_rx_ctx->skb = skb;
1583 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1584 skb->data,
1585 skb_tailroom(skb),
1586 PCI_DMA_FROMDEVICE);
1587 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1588 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1589 wmb();
1590 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1591 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1592 np->put_rx.orig = np->first_rx.orig;
1593 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1594 np->put_rx_ctx = np->first_rx_ctx;
1595 } else {
1596 return 1;
1597 }
1598 }
1599 return 0;
1600 }
1601
1602 static int nv_alloc_rx_optimized(struct net_device *dev)
1603 {
1604 struct fe_priv *np = netdev_priv(dev);
1605 struct ring_desc_ex* less_rx;
1606
1607 less_rx = np->get_rx.ex;
1608 if (less_rx-- == np->first_rx.ex)
1609 less_rx = np->last_rx.ex;
1610
1611 while (np->put_rx.ex != less_rx) {
1612 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1613 if (skb) {
1614 np->put_rx_ctx->skb = skb;
1615 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1616 skb->data,
1617 skb_tailroom(skb),
1618 PCI_DMA_FROMDEVICE);
1619 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1620 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1621 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1622 wmb();
1623 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1624 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1625 np->put_rx.ex = np->first_rx.ex;
1626 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1627 np->put_rx_ctx = np->first_rx_ctx;
1628 } else {
1629 return 1;
1630 }
1631 }
1632 return 0;
1633 }
1634
1635 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1636 #ifdef CONFIG_FORCEDETH_NAPI
1637 static void nv_do_rx_refill(unsigned long data)
1638 {
1639 struct net_device *dev = (struct net_device *) data;
1640 struct fe_priv *np = netdev_priv(dev);
1641
1642 /* Just reschedule NAPI rx processing */
1643 netif_rx_schedule(dev, &np->napi);
1644 }
1645 #else
1646 static void nv_do_rx_refill(unsigned long data)
1647 {
1648 struct net_device *dev = (struct net_device *) data;
1649 struct fe_priv *np = netdev_priv(dev);
1650 int retcode;
1651
1652 if (!using_multi_irqs(dev)) {
1653 if (np->msi_flags & NV_MSI_X_ENABLED)
1654 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1655 else
1656 disable_irq(np->pci_dev->irq);
1657 } else {
1658 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1659 }
1660 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1661 retcode = nv_alloc_rx(dev);
1662 else
1663 retcode = nv_alloc_rx_optimized(dev);
1664 if (retcode) {
1665 spin_lock_irq(&np->lock);
1666 if (!np->in_shutdown)
1667 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1668 spin_unlock_irq(&np->lock);
1669 }
1670 if (!using_multi_irqs(dev)) {
1671 if (np->msi_flags & NV_MSI_X_ENABLED)
1672 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1673 else
1674 enable_irq(np->pci_dev->irq);
1675 } else {
1676 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1677 }
1678 }
1679 #endif
1680
1681 static void nv_init_rx(struct net_device *dev)
1682 {
1683 struct fe_priv *np = netdev_priv(dev);
1684 int i;
1685 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1686 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1687 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1688 else
1689 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1690 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1691 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1692
1693 for (i = 0; i < np->rx_ring_size; i++) {
1694 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1695 np->rx_ring.orig[i].flaglen = 0;
1696 np->rx_ring.orig[i].buf = 0;
1697 } else {
1698 np->rx_ring.ex[i].flaglen = 0;
1699 np->rx_ring.ex[i].txvlan = 0;
1700 np->rx_ring.ex[i].bufhigh = 0;
1701 np->rx_ring.ex[i].buflow = 0;
1702 }
1703 np->rx_skb[i].skb = NULL;
1704 np->rx_skb[i].dma = 0;
1705 }
1706 }
1707
1708 static void nv_init_tx(struct net_device *dev)
1709 {
1710 struct fe_priv *np = netdev_priv(dev);
1711 int i;
1712 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1713 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1714 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1715 else
1716 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1717 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1718 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1719 np->tx_pkts_in_progress = 0;
1720 np->tx_change_owner = NULL;
1721 np->tx_end_flip = NULL;
1722
1723 for (i = 0; i < np->tx_ring_size; i++) {
1724 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1725 np->tx_ring.orig[i].flaglen = 0;
1726 np->tx_ring.orig[i].buf = 0;
1727 } else {
1728 np->tx_ring.ex[i].flaglen = 0;
1729 np->tx_ring.ex[i].txvlan = 0;
1730 np->tx_ring.ex[i].bufhigh = 0;
1731 np->tx_ring.ex[i].buflow = 0;
1732 }
1733 np->tx_skb[i].skb = NULL;
1734 np->tx_skb[i].dma = 0;
1735 np->tx_skb[i].dma_len = 0;
1736 np->tx_skb[i].first_tx_desc = NULL;
1737 np->tx_skb[i].next_tx_ctx = NULL;
1738 }
1739 }
1740
1741 static int nv_init_ring(struct net_device *dev)
1742 {
1743 struct fe_priv *np = netdev_priv(dev);
1744
1745 nv_init_tx(dev);
1746 nv_init_rx(dev);
1747 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1748 return nv_alloc_rx(dev);
1749 else
1750 return nv_alloc_rx_optimized(dev);
1751 }
1752
1753 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1754 {
1755 struct fe_priv *np = netdev_priv(dev);
1756
1757 if (tx_skb->dma) {
1758 pci_unmap_page(np->pci_dev, tx_skb->dma,
1759 tx_skb->dma_len,
1760 PCI_DMA_TODEVICE);
1761 tx_skb->dma = 0;
1762 }
1763 if (tx_skb->skb) {
1764 dev_kfree_skb_any(tx_skb->skb);
1765 tx_skb->skb = NULL;
1766 return 1;
1767 } else {
1768 return 0;
1769 }
1770 }
1771
1772 static void nv_drain_tx(struct net_device *dev)
1773 {
1774 struct fe_priv *np = netdev_priv(dev);
1775 unsigned int i;
1776
1777 for (i = 0; i < np->tx_ring_size; i++) {
1778 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1779 np->tx_ring.orig[i].flaglen = 0;
1780 np->tx_ring.orig[i].buf = 0;
1781 } else {
1782 np->tx_ring.ex[i].flaglen = 0;
1783 np->tx_ring.ex[i].txvlan = 0;
1784 np->tx_ring.ex[i].bufhigh = 0;
1785 np->tx_ring.ex[i].buflow = 0;
1786 }
1787 if (nv_release_txskb(dev, &np->tx_skb[i]))
1788 dev->stats.tx_dropped++;
1789 np->tx_skb[i].dma = 0;
1790 np->tx_skb[i].dma_len = 0;
1791 np->tx_skb[i].first_tx_desc = NULL;
1792 np->tx_skb[i].next_tx_ctx = NULL;
1793 }
1794 np->tx_pkts_in_progress = 0;
1795 np->tx_change_owner = NULL;
1796 np->tx_end_flip = NULL;
1797 }
1798
1799 static void nv_drain_rx(struct net_device *dev)
1800 {
1801 struct fe_priv *np = netdev_priv(dev);
1802 int i;
1803
1804 for (i = 0; i < np->rx_ring_size; i++) {
1805 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1806 np->rx_ring.orig[i].flaglen = 0;
1807 np->rx_ring.orig[i].buf = 0;
1808 } else {
1809 np->rx_ring.ex[i].flaglen = 0;
1810 np->rx_ring.ex[i].txvlan = 0;
1811 np->rx_ring.ex[i].bufhigh = 0;
1812 np->rx_ring.ex[i].buflow = 0;
1813 }
1814 wmb();
1815 if (np->rx_skb[i].skb) {
1816 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1817 (skb_end_pointer(np->rx_skb[i].skb) -
1818 np->rx_skb[i].skb->data),
1819 PCI_DMA_FROMDEVICE);
1820 dev_kfree_skb(np->rx_skb[i].skb);
1821 np->rx_skb[i].skb = NULL;
1822 }
1823 }
1824 }
1825
1826 static void drain_ring(struct net_device *dev)
1827 {
1828 nv_drain_tx(dev);
1829 nv_drain_rx(dev);
1830 }
1831
1832 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1833 {
1834 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1835 }
1836
1837 /*
1838 * nv_start_xmit: dev->hard_start_xmit function
1839 * Called with netif_tx_lock held.
1840 */
1841 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1842 {
1843 struct fe_priv *np = netdev_priv(dev);
1844 u32 tx_flags = 0;
1845 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1846 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1847 unsigned int i;
1848 u32 offset = 0;
1849 u32 bcnt;
1850 u32 size = skb->len-skb->data_len;
1851 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1852 u32 empty_slots;
1853 struct ring_desc* put_tx;
1854 struct ring_desc* start_tx;
1855 struct ring_desc* prev_tx;
1856 struct nv_skb_map* prev_tx_ctx;
1857 unsigned long flags;
1858
1859 /* add fragments to entries count */
1860 for (i = 0; i < fragments; i++) {
1861 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1862 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1863 }
1864
1865 empty_slots = nv_get_empty_tx_slots(np);
1866 if (unlikely(empty_slots <= entries)) {
1867 spin_lock_irqsave(&np->lock, flags);
1868 netif_stop_queue(dev);
1869 np->tx_stop = 1;
1870 spin_unlock_irqrestore(&np->lock, flags);
1871 return NETDEV_TX_BUSY;
1872 }
1873
1874 start_tx = put_tx = np->put_tx.orig;
1875
1876 /* setup the header buffer */
1877 do {
1878 prev_tx = put_tx;
1879 prev_tx_ctx = np->put_tx_ctx;
1880 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1881 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1882 PCI_DMA_TODEVICE);
1883 np->put_tx_ctx->dma_len = bcnt;
1884 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1885 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1886
1887 tx_flags = np->tx_flags;
1888 offset += bcnt;
1889 size -= bcnt;
1890 if (unlikely(put_tx++ == np->last_tx.orig))
1891 put_tx = np->first_tx.orig;
1892 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1893 np->put_tx_ctx = np->first_tx_ctx;
1894 } while (size);
1895
1896 /* setup the fragments */
1897 for (i = 0; i < fragments; i++) {
1898 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1899 u32 size = frag->size;
1900 offset = 0;
1901
1902 do {
1903 prev_tx = put_tx;
1904 prev_tx_ctx = np->put_tx_ctx;
1905 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1906 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1907 PCI_DMA_TODEVICE);
1908 np->put_tx_ctx->dma_len = bcnt;
1909 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1910 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1911
1912 offset += bcnt;
1913 size -= bcnt;
1914 if (unlikely(put_tx++ == np->last_tx.orig))
1915 put_tx = np->first_tx.orig;
1916 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1917 np->put_tx_ctx = np->first_tx_ctx;
1918 } while (size);
1919 }
1920
1921 /* set last fragment flag */
1922 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
1923
1924 /* save skb in this slot's context area */
1925 prev_tx_ctx->skb = skb;
1926
1927 if (skb_is_gso(skb))
1928 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1929 else
1930 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1931 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1932
1933 spin_lock_irqsave(&np->lock, flags);
1934
1935 /* set tx flags */
1936 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1937 np->put_tx.orig = put_tx;
1938
1939 spin_unlock_irqrestore(&np->lock, flags);
1940
1941 dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1942 dev->name, entries, tx_flags_extra);
1943 {
1944 int j;
1945 for (j=0; j<64; j++) {
1946 if ((j%16) == 0)
1947 dprintk("\n%03x:", j);
1948 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1949 }
1950 dprintk("\n");
1951 }
1952
1953 dev->trans_start = jiffies;
1954 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1955 return NETDEV_TX_OK;
1956 }
1957
1958 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
1959 {
1960 struct fe_priv *np = netdev_priv(dev);
1961 u32 tx_flags = 0;
1962 u32 tx_flags_extra;
1963 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1964 unsigned int i;
1965 u32 offset = 0;
1966 u32 bcnt;
1967 u32 size = skb->len-skb->data_len;
1968 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1969 u32 empty_slots;
1970 struct ring_desc_ex* put_tx;
1971 struct ring_desc_ex* start_tx;
1972 struct ring_desc_ex* prev_tx;
1973 struct nv_skb_map* prev_tx_ctx;
1974 struct nv_skb_map* start_tx_ctx;
1975 unsigned long flags;
1976
1977 /* add fragments to entries count */
1978 for (i = 0; i < fragments; i++) {
1979 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1980 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1981 }
1982
1983 empty_slots = nv_get_empty_tx_slots(np);
1984 if (unlikely(empty_slots <= entries)) {
1985 spin_lock_irqsave(&np->lock, flags);
1986 netif_stop_queue(dev);
1987 np->tx_stop = 1;
1988 spin_unlock_irqrestore(&np->lock, flags);
1989 return NETDEV_TX_BUSY;
1990 }
1991
1992 start_tx = put_tx = np->put_tx.ex;
1993 start_tx_ctx = np->put_tx_ctx;
1994
1995 /* setup the header buffer */
1996 do {
1997 prev_tx = put_tx;
1998 prev_tx_ctx = np->put_tx_ctx;
1999 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2000 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2001 PCI_DMA_TODEVICE);
2002 np->put_tx_ctx->dma_len = bcnt;
2003 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2004 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2005 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2006
2007 tx_flags = NV_TX2_VALID;
2008 offset += bcnt;
2009 size -= bcnt;
2010 if (unlikely(put_tx++ == np->last_tx.ex))
2011 put_tx = np->first_tx.ex;
2012 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2013 np->put_tx_ctx = np->first_tx_ctx;
2014 } while (size);
2015
2016 /* setup the fragments */
2017 for (i = 0; i < fragments; i++) {
2018 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2019 u32 size = frag->size;
2020 offset = 0;
2021
2022 do {
2023 prev_tx = put_tx;
2024 prev_tx_ctx = np->put_tx_ctx;
2025 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2026 np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
2027 PCI_DMA_TODEVICE);
2028 np->put_tx_ctx->dma_len = bcnt;
2029 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2030 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2031 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2032
2033 offset += bcnt;
2034 size -= bcnt;
2035 if (unlikely(put_tx++ == np->last_tx.ex))
2036 put_tx = np->first_tx.ex;
2037 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2038 np->put_tx_ctx = np->first_tx_ctx;
2039 } while (size);
2040 }
2041
2042 /* set last fragment flag */
2043 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2044
2045 /* save skb in this slot's context area */
2046 prev_tx_ctx->skb = skb;
2047
2048 if (skb_is_gso(skb))
2049 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2050 else
2051 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2052 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2053
2054 /* vlan tag */
2055 if (likely(!np->vlangrp)) {
2056 start_tx->txvlan = 0;
2057 } else {
2058 if (vlan_tx_tag_present(skb))
2059 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
2060 else
2061 start_tx->txvlan = 0;
2062 }
2063
2064 spin_lock_irqsave(&np->lock, flags);
2065
2066 if (np->tx_limit) {
2067 /* Limit the number of outstanding tx. Setup all fragments, but
2068 * do not set the VALID bit on the first descriptor. Save a pointer
2069 * to that descriptor and also for next skb_map element.
2070 */
2071
2072 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2073 if (!np->tx_change_owner)
2074 np->tx_change_owner = start_tx_ctx;
2075
2076 /* remove VALID bit */
2077 tx_flags &= ~NV_TX2_VALID;
2078 start_tx_ctx->first_tx_desc = start_tx;
2079 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2080 np->tx_end_flip = np->put_tx_ctx;
2081 } else {
2082 np->tx_pkts_in_progress++;
2083 }
2084 }
2085
2086 /* set tx flags */
2087 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2088 np->put_tx.ex = put_tx;
2089
2090 spin_unlock_irqrestore(&np->lock, flags);
2091
2092 dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2093 dev->name, entries, tx_flags_extra);
2094 {
2095 int j;
2096 for (j=0; j<64; j++) {
2097 if ((j%16) == 0)
2098 dprintk("\n%03x:", j);
2099 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2100 }
2101 dprintk("\n");
2102 }
2103
2104 dev->trans_start = jiffies;
2105 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2106 return NETDEV_TX_OK;
2107 }
2108
2109 static inline void nv_tx_flip_ownership(struct net_device *dev)
2110 {
2111 struct fe_priv *np = netdev_priv(dev);
2112
2113 np->tx_pkts_in_progress--;
2114 if (np->tx_change_owner) {
2115 __le32 flaglen = le32_to_cpu(np->tx_change_owner->first_tx_desc->flaglen);
2116 flaglen |= NV_TX2_VALID;
2117 np->tx_change_owner->first_tx_desc->flaglen = cpu_to_le32(flaglen);
2118 np->tx_pkts_in_progress++;
2119
2120 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2121 if (np->tx_change_owner == np->tx_end_flip)
2122 np->tx_change_owner = NULL;
2123
2124 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2125 }
2126 }
2127
2128 /*
2129 * nv_tx_done: check for completed packets, release the skbs.
2130 *
2131 * Caller must own np->lock.
2132 */
2133 static void nv_tx_done(struct net_device *dev)
2134 {
2135 struct fe_priv *np = netdev_priv(dev);
2136 u32 flags;
2137 struct ring_desc* orig_get_tx = np->get_tx.orig;
2138
2139 while ((np->get_tx.orig != np->put_tx.orig) &&
2140 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
2141
2142 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2143 dev->name, flags);
2144
2145 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2146 np->get_tx_ctx->dma_len,
2147 PCI_DMA_TODEVICE);
2148 np->get_tx_ctx->dma = 0;
2149
2150 if (np->desc_ver == DESC_VER_1) {
2151 if (flags & NV_TX_LASTPACKET) {
2152 if (flags & NV_TX_ERROR) {
2153 if (flags & NV_TX_UNDERFLOW)
2154 dev->stats.tx_fifo_errors++;
2155 if (flags & NV_TX_CARRIERLOST)
2156 dev->stats.tx_carrier_errors++;
2157 dev->stats.tx_errors++;
2158 } else {
2159 dev->stats.tx_packets++;
2160 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2161 }
2162 dev_kfree_skb_any(np->get_tx_ctx->skb);
2163 np->get_tx_ctx->skb = NULL;
2164 }
2165 } else {
2166 if (flags & NV_TX2_LASTPACKET) {
2167 if (flags & NV_TX2_ERROR) {
2168 if (flags & NV_TX2_UNDERFLOW)
2169 dev->stats.tx_fifo_errors++;
2170 if (flags & NV_TX2_CARRIERLOST)
2171 dev->stats.tx_carrier_errors++;
2172 dev->stats.tx_errors++;
2173 } else {
2174 dev->stats.tx_packets++;
2175 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2176 }
2177 dev_kfree_skb_any(np->get_tx_ctx->skb);
2178 np->get_tx_ctx->skb = NULL;
2179 }
2180 }
2181 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2182 np->get_tx.orig = np->first_tx.orig;
2183 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2184 np->get_tx_ctx = np->first_tx_ctx;
2185 }
2186 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2187 np->tx_stop = 0;
2188 netif_wake_queue(dev);
2189 }
2190 }
2191
2192 static void nv_tx_done_optimized(struct net_device *dev, int limit)
2193 {
2194 struct fe_priv *np = netdev_priv(dev);
2195 u32 flags;
2196 struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2197
2198 while ((np->get_tx.ex != np->put_tx.ex) &&
2199 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2200 (limit-- > 0)) {
2201
2202 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2203 dev->name, flags);
2204
2205 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2206 np->get_tx_ctx->dma_len,
2207 PCI_DMA_TODEVICE);
2208 np->get_tx_ctx->dma = 0;
2209
2210 if (flags & NV_TX2_LASTPACKET) {
2211 if (!(flags & NV_TX2_ERROR))
2212 dev->stats.tx_packets++;
2213 dev_kfree_skb_any(np->get_tx_ctx->skb);
2214 np->get_tx_ctx->skb = NULL;
2215
2216 if (np->tx_limit) {
2217 nv_tx_flip_ownership(dev);
2218 }
2219 }
2220 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2221 np->get_tx.ex = np->first_tx.ex;
2222 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2223 np->get_tx_ctx = np->first_tx_ctx;
2224 }
2225 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2226 np->tx_stop = 0;
2227 netif_wake_queue(dev);
2228 }
2229 }
2230
2231 /*
2232 * nv_tx_timeout: dev->tx_timeout function
2233 * Called with netif_tx_lock held.
2234 */
2235 static void nv_tx_timeout(struct net_device *dev)
2236 {
2237 struct fe_priv *np = netdev_priv(dev);
2238 u8 __iomem *base = get_hwbase(dev);
2239 u32 status;
2240
2241 if (np->msi_flags & NV_MSI_X_ENABLED)
2242 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2243 else
2244 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2245
2246 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2247
2248 {
2249 int i;
2250
2251 printk(KERN_INFO "%s: Ring at %lx\n",
2252 dev->name, (unsigned long)np->ring_addr);
2253 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2254 for (i=0;i<=np->register_size;i+= 32) {
2255 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2256 i,
2257 readl(base + i + 0), readl(base + i + 4),
2258 readl(base + i + 8), readl(base + i + 12),
2259 readl(base + i + 16), readl(base + i + 20),
2260 readl(base + i + 24), readl(base + i + 28));
2261 }
2262 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2263 for (i=0;i<np->tx_ring_size;i+= 4) {
2264 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2265 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2266 i,
2267 le32_to_cpu(np->tx_ring.orig[i].buf),
2268 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2269 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2270 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2271 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2272 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2273 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2274 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2275 } else {
2276 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2277 i,
2278 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2279 le32_to_cpu(np->tx_ring.ex[i].buflow),
2280 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2281 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2282 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2283 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2284 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2285 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2286 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2287 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2288 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2289 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2290 }
2291 }
2292 }
2293
2294 spin_lock_irq(&np->lock);
2295
2296 /* 1) stop tx engine */
2297 nv_stop_tx(dev);
2298
2299 /* 2) check that the packets were not sent already: */
2300 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2301 nv_tx_done(dev);
2302 else
2303 nv_tx_done_optimized(dev, np->tx_ring_size);
2304
2305 /* 3) if there are dead entries: clear everything */
2306 if (np->get_tx_ctx != np->put_tx_ctx) {
2307 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2308 nv_drain_tx(dev);
2309 nv_init_tx(dev);
2310 setup_hw_rings(dev, NV_SETUP_TX_RING);
2311 }
2312
2313 netif_wake_queue(dev);
2314
2315 /* 4) restart tx engine */
2316 nv_start_tx(dev);
2317 spin_unlock_irq(&np->lock);
2318 }
2319
2320 /*
2321 * Called when the nic notices a mismatch between the actual data len on the
2322 * wire and the len indicated in the 802 header
2323 */
2324 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2325 {
2326 int hdrlen; /* length of the 802 header */
2327 int protolen; /* length as stored in the proto field */
2328
2329 /* 1) calculate len according to header */
2330 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2331 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2332 hdrlen = VLAN_HLEN;
2333 } else {
2334 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2335 hdrlen = ETH_HLEN;
2336 }
2337 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2338 dev->name, datalen, protolen, hdrlen);
2339 if (protolen > ETH_DATA_LEN)
2340 return datalen; /* Value in proto field not a len, no checks possible */
2341
2342 protolen += hdrlen;
2343 /* consistency checks: */
2344 if (datalen > ETH_ZLEN) {
2345 if (datalen >= protolen) {
2346 /* more data on wire than in 802 header, trim of
2347 * additional data.
2348 */
2349 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2350 dev->name, protolen);
2351 return protolen;
2352 } else {
2353 /* less data on wire than mentioned in header.
2354 * Discard the packet.
2355 */
2356 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2357 dev->name);
2358 return -1;
2359 }
2360 } else {
2361 /* short packet. Accept only if 802 values are also short */
2362 if (protolen > ETH_ZLEN) {
2363 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2364 dev->name);
2365 return -1;
2366 }
2367 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2368 dev->name, datalen);
2369 return datalen;
2370 }
2371 }
2372
2373 static int nv_rx_process(struct net_device *dev, int limit)
2374 {
2375 struct fe_priv *np = netdev_priv(dev);
2376 u32 flags;
2377 int rx_work = 0;
2378 struct sk_buff *skb;
2379 int len;
2380
2381 while((np->get_rx.orig != np->put_rx.orig) &&
2382 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2383 (rx_work < limit)) {
2384
2385 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2386 dev->name, flags);
2387
2388 /*
2389 * the packet is for us - immediately tear down the pci mapping.
2390 * TODO: check if a prefetch of the first cacheline improves
2391 * the performance.
2392 */
2393 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2394 np->get_rx_ctx->dma_len,
2395 PCI_DMA_FROMDEVICE);
2396 skb = np->get_rx_ctx->skb;
2397 np->get_rx_ctx->skb = NULL;
2398
2399 {
2400 int j;
2401 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2402 for (j=0; j<64; j++) {
2403 if ((j%16) == 0)
2404 dprintk("\n%03x:", j);
2405 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2406 }
2407 dprintk("\n");
2408 }
2409 /* look at what we actually got: */
2410 if (np->desc_ver == DESC_VER_1) {
2411 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2412 len = flags & LEN_MASK_V1;
2413 if (unlikely(flags & NV_RX_ERROR)) {
2414 if (flags & NV_RX_ERROR4) {
2415 len = nv_getlen(dev, skb->data, len);
2416 if (len < 0) {
2417 dev->stats.rx_errors++;
2418 dev_kfree_skb(skb);
2419 goto next_pkt;
2420 }
2421 }
2422 /* framing errors are soft errors */
2423 else if (flags & NV_RX_FRAMINGERR) {
2424 if (flags & NV_RX_SUBSTRACT1) {
2425 len--;
2426 }
2427 }
2428 /* the rest are hard errors */
2429 else {
2430 if (flags & NV_RX_MISSEDFRAME)
2431 dev->stats.rx_missed_errors++;
2432 if (flags & NV_RX_CRCERR)
2433 dev->stats.rx_crc_errors++;
2434 if (flags & NV_RX_OVERFLOW)
2435 dev->stats.rx_over_errors++;
2436 dev->stats.rx_errors++;
2437 dev_kfree_skb(skb);
2438 goto next_pkt;
2439 }
2440 }
2441 } else {
2442 dev_kfree_skb(skb);
2443 goto next_pkt;
2444 }
2445 } else {
2446 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2447 len = flags & LEN_MASK_V2;
2448 if (unlikely(flags & NV_RX2_ERROR)) {
2449 if (flags & NV_RX2_ERROR4) {
2450 len = nv_getlen(dev, skb->data, len);
2451 if (len < 0) {
2452 dev->stats.rx_errors++;
2453 dev_kfree_skb(skb);
2454 goto next_pkt;
2455 }
2456 }
2457 /* framing errors are soft errors */
2458 else if (flags & NV_RX2_FRAMINGERR) {
2459 if (flags & NV_RX2_SUBSTRACT1) {
2460 len--;
2461 }
2462 }
2463 /* the rest are hard errors */
2464 else {
2465 if (flags & NV_RX2_CRCERR)
2466 dev->stats.rx_crc_errors++;
2467 if (flags & NV_RX2_OVERFLOW)
2468 dev->stats.rx_over_errors++;
2469 dev->stats.rx_errors++;
2470 dev_kfree_skb(skb);
2471 goto next_pkt;
2472 }
2473 }
2474 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2475 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2476 skb->ip_summed = CHECKSUM_UNNECESSARY;
2477 } else {
2478 dev_kfree_skb(skb);
2479 goto next_pkt;
2480 }
2481 }
2482 /* got a valid packet - forward it to the network core */
2483 skb_put(skb, len);
2484 skb->protocol = eth_type_trans(skb, dev);
2485 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2486 dev->name, len, skb->protocol);
2487 #ifdef CONFIG_FORCEDETH_NAPI
2488 netif_receive_skb(skb);
2489 #else
2490 netif_rx(skb);
2491 #endif
2492 dev->last_rx = jiffies;
2493 dev->stats.rx_packets++;
2494 dev->stats.rx_bytes += len;
2495 next_pkt:
2496 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2497 np->get_rx.orig = np->first_rx.orig;
2498 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2499 np->get_rx_ctx = np->first_rx_ctx;
2500
2501 rx_work++;
2502 }
2503
2504 return rx_work;
2505 }
2506
2507 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2508 {
2509 struct fe_priv *np = netdev_priv(dev);
2510 u32 flags;
2511 u32 vlanflags = 0;
2512 int rx_work = 0;
2513 struct sk_buff *skb;
2514 int len;
2515
2516 while((np->get_rx.ex != np->put_rx.ex) &&
2517 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2518 (rx_work < limit)) {
2519
2520 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2521 dev->name, flags);
2522
2523 /*
2524 * the packet is for us - immediately tear down the pci mapping.
2525 * TODO: check if a prefetch of the first cacheline improves
2526 * the performance.
2527 */
2528 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2529 np->get_rx_ctx->dma_len,
2530 PCI_DMA_FROMDEVICE);
2531 skb = np->get_rx_ctx->skb;
2532 np->get_rx_ctx->skb = NULL;
2533
2534 {
2535 int j;
2536 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2537 for (j=0; j<64; j++) {
2538 if ((j%16) == 0)
2539 dprintk("\n%03x:", j);
2540 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2541 }
2542 dprintk("\n");
2543 }
2544 /* look at what we actually got: */
2545 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2546 len = flags & LEN_MASK_V2;
2547 if (unlikely(flags & NV_RX2_ERROR)) {
2548 if (flags & NV_RX2_ERROR4) {
2549 len = nv_getlen(dev, skb->data, len);
2550 if (len < 0) {
2551 dev_kfree_skb(skb);
2552 goto next_pkt;
2553 }
2554 }
2555 /* framing errors are soft errors */
2556 else if (flags & NV_RX2_FRAMINGERR) {
2557 if (flags & NV_RX2_SUBSTRACT1) {
2558 len--;
2559 }
2560 }
2561 /* the rest are hard errors */
2562 else {
2563 dev_kfree_skb(skb);
2564 goto next_pkt;
2565 }
2566 }
2567
2568 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2569 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2570 skb->ip_summed = CHECKSUM_UNNECESSARY;
2571
2572 /* got a valid packet - forward it to the network core */
2573 skb_put(skb, len);
2574 skb->protocol = eth_type_trans(skb, dev);
2575 prefetch(skb->data);
2576
2577 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2578 dev->name, len, skb->protocol);
2579
2580 if (likely(!np->vlangrp)) {
2581 #ifdef CONFIG_FORCEDETH_NAPI
2582 netif_receive_skb(skb);
2583 #else
2584 netif_rx(skb);
2585 #endif
2586 } else {
2587 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2588 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2589 #ifdef CONFIG_FORCEDETH_NAPI
2590 vlan_hwaccel_receive_skb(skb, np->vlangrp,
2591 vlanflags & NV_RX3_VLAN_TAG_MASK);
2592 #else
2593 vlan_hwaccel_rx(skb, np->vlangrp,
2594 vlanflags & NV_RX3_VLAN_TAG_MASK);
2595 #endif
2596 } else {
2597 #ifdef CONFIG_FORCEDETH_NAPI
2598 netif_receive_skb(skb);
2599 #else
2600 netif_rx(skb);
2601 #endif
2602 }
2603 }
2604
2605 dev->last_rx = jiffies;
2606 dev->stats.rx_packets++;
2607 dev->stats.rx_bytes += len;
2608 } else {
2609 dev_kfree_skb(skb);
2610 }
2611 next_pkt:
2612 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2613 np->get_rx.ex = np->first_rx.ex;
2614 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2615 np->get_rx_ctx = np->first_rx_ctx;
2616
2617 rx_work++;
2618 }
2619
2620 return rx_work;
2621 }
2622
2623 static void set_bufsize(struct net_device *dev)
2624 {
2625 struct fe_priv *np = netdev_priv(dev);
2626
2627 if (dev->mtu <= ETH_DATA_LEN)
2628 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2629 else
2630 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2631 }
2632
2633 /*
2634 * nv_change_mtu: dev->change_mtu function
2635 * Called with dev_base_lock held for read.
2636 */
2637 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2638 {
2639 struct fe_priv *np = netdev_priv(dev);
2640 int old_mtu;
2641
2642 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2643 return -EINVAL;
2644
2645 old_mtu = dev->mtu;
2646 dev->mtu = new_mtu;
2647
2648 /* return early if the buffer sizes will not change */
2649 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2650 return 0;
2651 if (old_mtu == new_mtu)
2652 return 0;
2653
2654 /* synchronized against open : rtnl_lock() held by caller */
2655 if (netif_running(dev)) {
2656 u8 __iomem *base = get_hwbase(dev);
2657 /*
2658 * It seems that the nic preloads valid ring entries into an
2659 * internal buffer. The procedure for flushing everything is
2660 * guessed, there is probably a simpler approach.
2661 * Changing the MTU is a rare event, it shouldn't matter.
2662 */
2663 nv_disable_irq(dev);
2664 netif_tx_lock_bh(dev);
2665 spin_lock(&np->lock);
2666 /* stop engines */
2667 nv_stop_rx(dev);
2668 nv_stop_tx(dev);
2669 nv_txrx_reset(dev);
2670 /* drain rx queue */
2671 nv_drain_rx(dev);
2672 nv_drain_tx(dev);
2673 /* reinit driver view of the rx queue */
2674 set_bufsize(dev);
2675 if (nv_init_ring(dev)) {
2676 if (!np->in_shutdown)
2677 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2678 }
2679 /* reinit nic view of the rx queue */
2680 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2681 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2682 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2683 base + NvRegRingSizes);
2684 pci_push(base);
2685 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2686 pci_push(base);
2687
2688 /* restart rx engine */
2689 nv_start_rx(dev);
2690 nv_start_tx(dev);
2691 spin_unlock(&np->lock);
2692 netif_tx_unlock_bh(dev);
2693 nv_enable_irq(dev);
2694 }
2695 return 0;
2696 }
2697
2698 static void nv_copy_mac_to_hw(struct net_device *dev)
2699 {
2700 u8 __iomem *base = get_hwbase(dev);
2701 u32 mac[2];
2702
2703 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2704 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2705 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2706
2707 writel(mac[0], base + NvRegMacAddrA);
2708 writel(mac[1], base + NvRegMacAddrB);
2709 }
2710
2711 /*
2712 * nv_set_mac_address: dev->set_mac_address function
2713 * Called with rtnl_lock() held.
2714 */
2715 static int nv_set_mac_address(struct net_device *dev, void *addr)
2716 {
2717 struct fe_priv *np = netdev_priv(dev);
2718 struct sockaddr *macaddr = (struct sockaddr*)addr;
2719
2720 if (!is_valid_ether_addr(macaddr->sa_data))
2721 return -EADDRNOTAVAIL;
2722
2723 /* synchronized against open : rtnl_lock() held by caller */
2724 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2725
2726 if (netif_running(dev)) {
2727 netif_tx_lock_bh(dev);
2728 spin_lock_irq(&np->lock);
2729
2730 /* stop rx engine */
2731 nv_stop_rx(dev);
2732
2733 /* set mac address */
2734 nv_copy_mac_to_hw(dev);
2735
2736 /* restart rx engine */
2737 nv_start_rx(dev);
2738 spin_unlock_irq(&np->lock);
2739 netif_tx_unlock_bh(dev);
2740 } else {
2741 nv_copy_mac_to_hw(dev);
2742 }
2743 return 0;
2744 }
2745
2746 /*
2747 * nv_set_multicast: dev->set_multicast function
2748 * Called with netif_tx_lock held.
2749 */
2750 static void nv_set_multicast(struct net_device *dev)
2751 {
2752 struct fe_priv *np = netdev_priv(dev);
2753 u8 __iomem *base = get_hwbase(dev);
2754 u32 addr[2];
2755 u32 mask[2];
2756 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2757
2758 memset(addr, 0, sizeof(addr));
2759 memset(mask, 0, sizeof(mask));
2760
2761 if (dev->flags & IFF_PROMISC) {
2762 pff |= NVREG_PFF_PROMISC;
2763 } else {
2764 pff |= NVREG_PFF_MYADDR;
2765
2766 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2767 u32 alwaysOff[2];
2768 u32 alwaysOn[2];
2769
2770 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2771 if (dev->flags & IFF_ALLMULTI) {
2772 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2773 } else {
2774 struct dev_mc_list *walk;
2775
2776 walk = dev->mc_list;
2777 while (walk != NULL) {
2778 u32 a, b;
2779 a = le32_to_cpu(*(__le32 *) walk->dmi_addr);
2780 b = le16_to_cpu(*(__le16 *) (&walk->dmi_addr[4]));
2781 alwaysOn[0] &= a;
2782 alwaysOff[0] &= ~a;
2783 alwaysOn[1] &= b;
2784 alwaysOff[1] &= ~b;
2785 walk = walk->next;
2786 }
2787 }
2788 addr[0] = alwaysOn[0];
2789 addr[1] = alwaysOn[1];
2790 mask[0] = alwaysOn[0] | alwaysOff[0];
2791 mask[1] = alwaysOn[1] | alwaysOff[1];
2792 } else {
2793 mask[0] = NVREG_MCASTMASKA_NONE;
2794 mask[1] = NVREG_MCASTMASKB_NONE;
2795 }
2796 }
2797 addr[0] |= NVREG_MCASTADDRA_FORCE;
2798 pff |= NVREG_PFF_ALWAYS;
2799 spin_lock_irq(&np->lock);
2800 nv_stop_rx(dev);
2801 writel(addr[0], base + NvRegMulticastAddrA);
2802 writel(addr[1], base + NvRegMulticastAddrB);
2803 writel(mask[0], base + NvRegMulticastMaskA);
2804 writel(mask[1], base + NvRegMulticastMaskB);
2805 writel(pff, base + NvRegPacketFilterFlags);
2806 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2807 dev->name);
2808 nv_start_rx(dev);
2809 spin_unlock_irq(&np->lock);
2810 }
2811
2812 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2813 {
2814 struct fe_priv *np = netdev_priv(dev);
2815 u8 __iomem *base = get_hwbase(dev);
2816
2817 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2818
2819 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2820 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2821 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2822 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2823 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2824 } else {
2825 writel(pff, base + NvRegPacketFilterFlags);
2826 }
2827 }
2828 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2829 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2830 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2831 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
2832 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
2833 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
2834 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)
2835 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
2836 writel(pause_enable, base + NvRegTxPauseFrame);
2837 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2838 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2839 } else {
2840 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
2841 writel(regmisc, base + NvRegMisc1);
2842 }
2843 }
2844 }
2845
2846 /**
2847 * nv_update_linkspeed: Setup the MAC according to the link partner
2848 * @dev: Network device to be configured
2849 *
2850 * The function queries the PHY and checks if there is a link partner.
2851 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2852 * set to 10 MBit HD.
2853 *
2854 * The function returns 0 if there is no link partner and 1 if there is
2855 * a good link partner.
2856 */
2857 static int nv_update_linkspeed(struct net_device *dev)
2858 {
2859 struct fe_priv *np = netdev_priv(dev);
2860 u8 __iomem *base = get_hwbase(dev);
2861 int adv = 0;
2862 int lpa = 0;
2863 int adv_lpa, adv_pause, lpa_pause;
2864 int newls = np->linkspeed;
2865 int newdup = np->duplex;
2866 int mii_status;
2867 int retval = 0;
2868 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2869 u32 txrxFlags = 0;
2870 u32 phy_exp;
2871
2872 /* BMSR_LSTATUS is latched, read it twice:
2873 * we want the current value.
2874 */
2875 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2876 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2877
2878 if (!(mii_status & BMSR_LSTATUS)) {
2879 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2880 dev->name);
2881 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2882 newdup = 0;
2883 retval = 0;
2884 goto set_speed;
2885 }
2886
2887 if (np->autoneg == 0) {
2888 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2889 dev->name, np->fixed_mode);
2890 if (np->fixed_mode & LPA_100FULL) {
2891 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2892 newdup = 1;
2893 } else if (np->fixed_mode & LPA_100HALF) {
2894 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2895 newdup = 0;
2896 } else if (np->fixed_mode & LPA_10FULL) {
2897 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2898 newdup = 1;
2899 } else {
2900 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2901 newdup = 0;
2902 }
2903 retval = 1;
2904 goto set_speed;
2905 }
2906 /* check auto negotiation is complete */
2907 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2908 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2909 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2910 newdup = 0;
2911 retval = 0;
2912 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2913 goto set_speed;
2914 }
2915
2916 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2917 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2918 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2919 dev->name, adv, lpa);
2920
2921 retval = 1;
2922 if (np->gigabit == PHY_GIGABIT) {
2923 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2924 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2925
2926 if ((control_1000 & ADVERTISE_1000FULL) &&
2927 (status_1000 & LPA_1000FULL)) {
2928 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2929 dev->name);
2930 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2931 newdup = 1;
2932 goto set_speed;
2933 }
2934 }
2935
2936 /* FIXME: handle parallel detection properly */
2937 adv_lpa = lpa & adv;
2938 if (adv_lpa & LPA_100FULL) {
2939 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2940 newdup = 1;
2941 } else if (adv_lpa & LPA_100HALF) {
2942 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2943 newdup = 0;
2944 } else if (adv_lpa & LPA_10FULL) {
2945 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2946 newdup = 1;
2947 } else if (adv_lpa & LPA_10HALF) {
2948 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2949 newdup = 0;
2950 } else {
2951 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2952 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2953 newdup = 0;
2954 }
2955
2956 set_speed:
2957 if (np->duplex == newdup && np->linkspeed == newls)
2958 return retval;
2959
2960 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2961 dev->name, np->linkspeed, np->duplex, newls, newdup);
2962
2963 np->duplex = newdup;
2964 np->linkspeed = newls;
2965
2966 /* The transmitter and receiver must be restarted for safe update */
2967 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
2968 txrxFlags |= NV_RESTART_TX;
2969 nv_stop_tx(dev);
2970 }
2971 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
2972 txrxFlags |= NV_RESTART_RX;
2973 nv_stop_rx(dev);
2974 }
2975
2976 if (np->gigabit == PHY_GIGABIT) {
2977 phyreg = readl(base + NvRegRandomSeed);
2978 phyreg &= ~(0x3FF00);
2979 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2980 phyreg |= NVREG_RNDSEED_FORCE3;
2981 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2982 phyreg |= NVREG_RNDSEED_FORCE2;
2983 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2984 phyreg |= NVREG_RNDSEED_FORCE;
2985 writel(phyreg, base + NvRegRandomSeed);
2986 }
2987
2988 phyreg = readl(base + NvRegPhyInterface);
2989 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2990 if (np->duplex == 0)
2991 phyreg |= PHY_HALF;
2992 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2993 phyreg |= PHY_100;
2994 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2995 phyreg |= PHY_1000;
2996 writel(phyreg, base + NvRegPhyInterface);
2997
2998 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
2999 if (phyreg & PHY_RGMII) {
3000 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3001 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3002 } else {
3003 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3004 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3005 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3006 else
3007 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3008 } else {
3009 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3010 }
3011 }
3012 } else {
3013 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3014 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3015 else
3016 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3017 }
3018 writel(txreg, base + NvRegTxDeferral);
3019
3020 if (np->desc_ver == DESC_VER_1) {
3021 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3022 } else {
3023 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3024 txreg = NVREG_TX_WM_DESC2_3_1000;
3025 else
3026 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3027 }
3028 writel(txreg, base + NvRegTxWatermark);
3029
3030 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
3031 base + NvRegMisc1);
3032 pci_push(base);
3033 writel(np->linkspeed, base + NvRegLinkSpeed);
3034 pci_push(base);
3035
3036 pause_flags = 0;
3037 /* setup pause frame */
3038 if (np->duplex != 0) {
3039 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3040 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
3041 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
3042
3043 switch (adv_pause) {
3044 case ADVERTISE_PAUSE_CAP:
3045 if (lpa_pause & LPA_PAUSE_CAP) {
3046 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3047 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3048 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3049 }
3050 break;
3051 case ADVERTISE_PAUSE_ASYM:
3052 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
3053 {
3054 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3055 }
3056 break;
3057 case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
3058 if (lpa_pause & LPA_PAUSE_CAP)
3059 {
3060 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3061 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3062 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3063 }
3064 if (lpa_pause == LPA_PAUSE_ASYM)
3065 {
3066 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3067 }
3068 break;
3069 }
3070 } else {
3071 pause_flags = np->pause_flags;
3072 }
3073 }
3074 nv_update_pause(dev, pause_flags);
3075
3076 if (txrxFlags & NV_RESTART_TX)
3077 nv_start_tx(dev);
3078 if (txrxFlags & NV_RESTART_RX)
3079 nv_start_rx(dev);
3080
3081 return retval;
3082 }
3083
3084 static void nv_linkchange(struct net_device *dev)
3085 {
3086 if (nv_update_linkspeed(dev)) {
3087 if (!netif_carrier_ok(dev)) {
3088 netif_carrier_on(dev);
3089 printk(KERN_INFO "%s: link up.\n", dev->name);
3090 nv_start_rx(dev);
3091 }
3092 } else {
3093 if (netif_carrier_ok(dev)) {
3094 netif_carrier_off(dev);
3095 printk(KERN_INFO "%s: link down.\n", dev->name);
3096 nv_stop_rx(dev);
3097 }
3098 }
3099 }
3100
3101 static void nv_link_irq(struct net_device *dev)
3102 {
3103 u8 __iomem *base = get_hwbase(dev);
3104 u32 miistat;
3105
3106 miistat = readl(base + NvRegMIIStatus);
3107 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3108 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
3109
3110 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3111 nv_linkchange(dev);
3112 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
3113 }
3114
3115 static irqreturn_t nv_nic_irq(int foo, void *data)
3116 {
3117 struct net_device *dev = (struct net_device *) data;
3118 struct fe_priv *np = netdev_priv(dev);
3119 u8 __iomem *base = get_hwbase(dev);
3120 u32 events;
3121 int i;
3122
3123 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
3124
3125 for (i=0; ; i++) {
3126 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3127 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3128 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3129 } else {
3130 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3131 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3132 }
3133 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3134 if (!(events & np->irqmask))
3135 break;
3136
3137 spin_lock(&np->lock);
3138 nv_tx_done(dev);
3139 spin_unlock(&np->lock);
3140
3141 #ifdef CONFIG_FORCEDETH_NAPI
3142 if (events & NVREG_IRQ_RX_ALL) {
3143 netif_rx_schedule(dev, &np->napi);
3144
3145 /* Disable furthur receive irq's */
3146 spin_lock(&np->lock);
3147 np->irqmask &= ~NVREG_IRQ_RX_ALL;
3148
3149 if (np->msi_flags & NV_MSI_X_ENABLED)
3150 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3151 else
3152 writel(np->irqmask, base + NvRegIrqMask);
3153 spin_unlock(&np->lock);
3154 }
3155 #else
3156 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3157 if (unlikely(nv_alloc_rx(dev))) {
3158 spin_lock(&np->lock);
3159 if (!np->in_shutdown)
3160 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3161 spin_unlock(&np->lock);
3162 }
3163 }
3164 #endif
3165 if (unlikely(events & NVREG_IRQ_LINK)) {
3166 spin_lock(&np->lock);
3167 nv_link_irq(dev);
3168 spin_unlock(&np->lock);
3169 }
3170 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3171 spin_lock(&np->lock);
3172 nv_linkchange(dev);
3173 spin_unlock(&np->lock);
3174 np->link_timeout = jiffies + LINK_TIMEOUT;
3175 }
3176 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3177 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3178 dev->name, events);
3179 }
3180 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3181 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3182 dev->name, events);
3183 }
3184 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3185 spin_lock(&np->lock);
3186 /* disable interrupts on the nic */
3187 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3188 writel(0, base + NvRegIrqMask);
3189 else
3190 writel(np->irqmask, base + NvRegIrqMask);
3191 pci_push(base);
3192
3193 if (!np->in_shutdown) {
3194 np->nic_poll_irq = np->irqmask;
3195 np->recover_error = 1;
3196 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3197 }
3198 spin_unlock(&np->lock);
3199 break;
3200 }
3201 if (unlikely(i > max_interrupt_work)) {
3202 spin_lock(&np->lock);
3203 /* disable interrupts on the nic */
3204 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3205 writel(0, base + NvRegIrqMask);
3206 else
3207 writel(np->irqmask, base + NvRegIrqMask);
3208 pci_push(base);
3209
3210 if (!np->in_shutdown) {
3211 np->nic_poll_irq = np->irqmask;
3212 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3213 }
3214 spin_unlock(&np->lock);
3215 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3216 break;
3217 }
3218
3219 }
3220 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3221
3222 return IRQ_RETVAL(i);
3223 }
3224
3225 /**
3226 * All _optimized functions are used to help increase performance
3227 * (reduce CPU and increase throughput). They use descripter version 3,
3228 * compiler directives, and reduce memory accesses.
3229 */
3230 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3231 {
3232 struct net_device *dev = (struct net_device *) data;
3233 struct fe_priv *np = netdev_priv(dev);
3234 u8 __iomem *base = get_hwbase(dev);
3235 u32 events;
3236 int i;
3237
3238 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3239
3240 for (i=0; ; i++) {
3241 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3242 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3243 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3244 } else {
3245 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3246 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3247 }
3248 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3249 if (!(events & np->irqmask))
3250 break;
3251
3252 spin_lock(&np->lock);
3253 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3254 spin_unlock(&np->lock);
3255
3256 #ifdef CONFIG_FORCEDETH_NAPI
3257 if (events & NVREG_IRQ_RX_ALL) {
3258 netif_rx_schedule(dev, &np->napi);
3259
3260 /* Disable furthur receive irq's */
3261 spin_lock(&np->lock);
3262 np->irqmask &= ~NVREG_IRQ_RX_ALL;
3263
3264 if (np->msi_flags & NV_MSI_X_ENABLED)
3265 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3266 else
3267 writel(np->irqmask, base + NvRegIrqMask);
3268 spin_unlock(&np->lock);
3269 }
3270 #else
3271 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3272 if (unlikely(nv_alloc_rx_optimized(dev))) {
3273 spin_lock(&np->lock);
3274 if (!np->in_shutdown)
3275 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3276 spin_unlock(&np->lock);
3277 }
3278 }
3279 #endif
3280 if (unlikely(events & NVREG_IRQ_LINK)) {
3281 spin_lock(&np->lock);
3282 nv_link_irq(dev);
3283 spin_unlock(&np->lock);
3284 }
3285 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3286 spin_lock(&np->lock);
3287 nv_linkchange(dev);
3288 spin_unlock(&np->lock);
3289 np->link_timeout = jiffies + LINK_TIMEOUT;
3290 }
3291 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3292 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3293 dev->name, events);
3294 }
3295 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3296 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3297 dev->name, events);
3298 }
3299 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3300 spin_lock(&np->lock);
3301 /* disable interrupts on the nic */
3302 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3303 writel(0, base + NvRegIrqMask);
3304 else
3305 writel(np->irqmask, base + NvRegIrqMask);
3306 pci_push(base);
3307
3308 if (!np->in_shutdown) {
3309 np->nic_poll_irq = np->irqmask;
3310 np->recover_error = 1;
3311 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3312 }
3313 spin_unlock(&np->lock);
3314 break;
3315 }
3316
3317 if (unlikely(i > max_interrupt_work)) {
3318 spin_lock(&np->lock);
3319 /* disable interrupts on the nic */
3320 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3321 writel(0, base + NvRegIrqMask);
3322 else
3323 writel(np->irqmask, base + NvRegIrqMask);
3324 pci_push(base);
3325
3326 if (!np->in_shutdown) {
3327 np->nic_poll_irq = np->irqmask;
3328 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3329 }
3330 spin_unlock(&np->lock);
3331 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3332 break;
3333 }
3334
3335 }
3336 dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3337
3338 return IRQ_RETVAL(i);
3339 }
3340
3341 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3342 {
3343 struct net_device *dev = (struct net_device *) data;
3344 struct fe_priv *np = netdev_priv(dev);
3345 u8 __iomem *base = get_hwbase(dev);
3346 u32 events;
3347 int i;
3348 unsigned long flags;
3349
3350 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3351
3352 for (i=0; ; i++) {
3353 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3354 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3355 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3356 if (!(events & np->irqmask))
3357 break;
3358
3359 spin_lock_irqsave(&np->lock, flags);
3360 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3361 spin_unlock_irqrestore(&np->lock, flags);
3362
3363 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3364 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3365 dev->name, events);
3366 }
3367 if (unlikely(i > max_interrupt_work)) {
3368 spin_lock_irqsave(&np->lock, flags);
3369 /* disable interrupts on the nic */
3370 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3371 pci_push(base);
3372
3373 if (!np->in_shutdown) {
3374 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3375 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3376 }
3377 spin_unlock_irqrestore(&np->lock, flags);
3378 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3379 break;
3380 }
3381
3382 }
3383 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3384
3385 return IRQ_RETVAL(i);
3386 }
3387
3388 #ifdef CONFIG_FORCEDETH_NAPI
3389 static int nv_napi_poll(struct napi_struct *napi, int budget)
3390 {
3391 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3392 struct net_device *dev = np->dev;
3393 u8 __iomem *base = get_hwbase(dev);
3394 unsigned long flags;
3395 int pkts, retcode;
3396
3397 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3398 pkts = nv_rx_process(dev, budget);
3399 retcode = nv_alloc_rx(dev);
3400 } else {
3401 pkts = nv_rx_process_optimized(dev, budget);
3402 retcode = nv_alloc_rx_optimized(dev);
3403 }
3404
3405 if (retcode) {
3406 spin_lock_irqsave(&np->lock, flags);
3407 if (!np->in_shutdown)
3408 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3409 spin_unlock_irqrestore(&np->lock, flags);
3410 }
3411
3412 if (pkts < budget) {
3413 /* re-enable receive interrupts */
3414 spin_lock_irqsave(&np->lock, flags);
3415
3416 __netif_rx_complete(dev, napi);
3417
3418 np->irqmask |= NVREG_IRQ_RX_ALL;
3419 if (np->msi_flags & NV_MSI_X_ENABLED)
3420 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3421 else
3422 writel(np->irqmask, base + NvRegIrqMask);
3423
3424 spin_unlock_irqrestore(&np->lock, flags);
3425 }
3426 return pkts;
3427 }
3428 #endif
3429
3430 #ifdef CONFIG_FORCEDETH_NAPI
3431 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3432 {
3433 struct net_device *dev = (struct net_device *) data;
3434 struct fe_priv *np = netdev_priv(dev);
3435 u8 __iomem *base = get_hwbase(dev);
3436 u32 events;
3437
3438 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3439 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3440
3441 if (events) {
3442 netif_rx_schedule(dev, &np->napi);
3443 /* disable receive interrupts on the nic */
3444 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3445 pci_push(base);
3446 }
3447 return IRQ_HANDLED;
3448 }
3449 #else
3450 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3451 {
3452 struct net_device *dev = (struct net_device *) data;
3453 struct fe_priv *np = netdev_priv(dev);
3454 u8 __iomem *base = get_hwbase(dev);
3455 u32 events;
3456 int i;
3457 unsigned long flags;
3458
3459 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3460
3461 for (i=0; ; i++) {
3462 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3463 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3464 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3465 if (!(events & np->irqmask))
3466 break;
3467
3468 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3469 if (unlikely(nv_alloc_rx_optimized(dev))) {
3470 spin_lock_irqsave(&np->lock, flags);
3471 if (!np->in_shutdown)
3472 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3473 spin_unlock_irqrestore(&np->lock, flags);
3474 }
3475 }
3476
3477 if (unlikely(i > max_interrupt_work)) {
3478 spin_lock_irqsave(&np->lock, flags);
3479 /* disable interrupts on the nic */
3480 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3481 pci_push(base);
3482
3483 if (!np->in_shutdown) {
3484 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3485 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3486 }
3487 spin_unlock_irqrestore(&np->lock, flags);
3488 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3489 break;
3490 }
3491 }
3492 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3493
3494 return IRQ_RETVAL(i);
3495 }
3496 #endif
3497
3498 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3499 {
3500 struct net_device *dev = (struct net_device *) data;
3501 struct fe_priv *np = netdev_priv(dev);
3502 u8 __iomem *base = get_hwbase(dev);
3503 u32 events;
3504 int i;
3505 unsigned long flags;
3506
3507 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3508
3509 for (i=0; ; i++) {
3510 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3511 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3512 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3513 if (!(events & np->irqmask))
3514 break;
3515
3516 /* check tx in case we reached max loop limit in tx isr */
3517 spin_lock_irqsave(&np->lock, flags);
3518 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3519 spin_unlock_irqrestore(&np->lock, flags);
3520
3521 if (events & NVREG_IRQ_LINK) {
3522 spin_lock_irqsave(&np->lock, flags);
3523 nv_link_irq(dev);
3524 spin_unlock_irqrestore(&np->lock, flags);
3525 }
3526 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3527 spin_lock_irqsave(&np->lock, flags);
3528 nv_linkchange(dev);
3529 spin_unlock_irqrestore(&np->lock, flags);
3530 np->link_timeout = jiffies + LINK_TIMEOUT;
3531 }
3532 if (events & NVREG_IRQ_RECOVER_ERROR) {
3533 spin_lock_irq(&np->lock);
3534 /* disable interrupts on the nic */
3535 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3536 pci_push(base);
3537
3538 if (!np->in_shutdown) {
3539 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3540 np->recover_error = 1;
3541 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3542 }
3543 spin_unlock_irq(&np->lock);
3544 break;
3545 }
3546 if (events & (NVREG_IRQ_UNKNOWN)) {
3547 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3548 dev->name, events);
3549 }
3550 if (unlikely(i > max_interrupt_work)) {
3551 spin_lock_irqsave(&np->lock, flags);
3552 /* disable interrupts on the nic */
3553 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3554 pci_push(base);
3555
3556 if (!np->in_shutdown) {
3557 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3558 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3559 }
3560 spin_unlock_irqrestore(&np->lock, flags);
3561 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3562 break;
3563 }
3564
3565 }
3566 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3567
3568 return IRQ_RETVAL(i);
3569 }
3570
3571 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3572 {
3573 struct net_device *dev = (struct net_device *) data;
3574 struct fe_priv *np = netdev_priv(dev);
3575 u8 __iomem *base = get_hwbase(dev);
3576 u32 events;
3577
3578 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3579
3580 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3581 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3582 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3583 } else {
3584 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3585 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3586 }
3587 pci_push(base);
3588 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3589 if (!(events & NVREG_IRQ_TIMER))
3590 return IRQ_RETVAL(0);
3591
3592 spin_lock(&np->lock);
3593 np->intr_test = 1;
3594 spin_unlock(&np->lock);
3595
3596 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3597
3598 return IRQ_RETVAL(1);
3599 }
3600
3601 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3602 {
3603 u8 __iomem *base = get_hwbase(dev);
3604 int i;
3605 u32 msixmap = 0;
3606
3607 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3608 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3609 * the remaining 8 interrupts.
3610 */
3611 for (i = 0; i < 8; i++) {
3612 if ((irqmask >> i) & 0x1) {
3613 msixmap |= vector << (i << 2);
3614 }
3615 }
3616 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3617
3618 msixmap = 0;
3619 for (i = 0; i < 8; i++) {
3620 if ((irqmask >> (i + 8)) & 0x1) {
3621 msixmap |= vector << (i << 2);
3622 }
3623 }
3624 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3625 }
3626
3627 static int nv_request_irq(struct net_device *dev, int intr_test)
3628 {
3629 struct fe_priv *np = get_nvpriv(dev);
3630 u8 __iomem *base = get_hwbase(dev);
3631 int ret = 1;
3632 int i;
3633 irqreturn_t (*handler)(int foo, void *data);
3634
3635 if (intr_test) {
3636 handler = nv_nic_irq_test;
3637 } else {
3638 if (np->desc_ver == DESC_VER_3)
3639 handler = nv_nic_irq_optimized;
3640 else
3641 handler = nv_nic_irq;
3642 }
3643
3644 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3645 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3646 np->msi_x_entry[i].entry = i;
3647 }
3648 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3649 np->msi_flags |= NV_MSI_X_ENABLED;
3650 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3651 /* Request irq for rx handling */
3652 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3653 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3654 pci_disable_msix(np->pci_dev);
3655 np->msi_flags &= ~NV_MSI_X_ENABLED;
3656 goto out_err;
3657 }
3658 /* Request irq for tx handling */
3659 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3660 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3661 pci_disable_msix(np->pci_dev);
3662 np->msi_flags &= ~NV_MSI_X_ENABLED;
3663 goto out_free_rx;
3664 }
3665 /* Request irq for link and timer handling */
3666 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3667 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3668 pci_disable_msix(np->pci_dev);
3669 np->msi_flags &= ~NV_MSI_X_ENABLED;
3670 goto out_free_tx;
3671 }
3672 /* map interrupts to their respective vector */
3673 writel(0, base + NvRegMSIXMap0);
3674 writel(0, base + NvRegMSIXMap1);
3675 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3676 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3677 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3678 } else {
3679 /* Request irq for all interrupts */
3680 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3681 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3682 pci_disable_msix(np->pci_dev);
3683 np->msi_flags &= ~NV_MSI_X_ENABLED;
3684 goto out_err;
3685 }
3686
3687 /* map interrupts to vector 0 */
3688 writel(0, base + NvRegMSIXMap0);
3689 writel(0, base + NvRegMSIXMap1);
3690 }
3691 }
3692 }
3693 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3694 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3695 np->msi_flags |= NV_MSI_ENABLED;
3696 dev->irq = np->pci_dev->irq;
3697 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3698 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3699 pci_disable_msi(np->pci_dev);
3700 np->msi_flags &= ~NV_MSI_ENABLED;
3701 dev->irq = np->pci_dev->irq;
3702 goto out_err;
3703 }
3704
3705 /* map interrupts to vector 0 */
3706 writel(0, base + NvRegMSIMap0);
3707 writel(0, base + NvRegMSIMap1);
3708 /* enable msi vector 0 */
3709 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3710 }
3711 }
3712 if (ret != 0) {
3713 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3714 goto out_err;
3715
3716 }
3717
3718 return 0;
3719 out_free_tx:
3720 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3721 out_free_rx:
3722 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3723 out_err:
3724 return 1;
3725 }
3726
3727 static void nv_free_irq(struct net_device *dev)
3728 {
3729 struct fe_priv *np = get_nvpriv(dev);
3730 int i;
3731
3732 if (np->msi_flags & NV_MSI_X_ENABLED) {
3733 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3734 free_irq(np->msi_x_entry[i].vector, dev);
3735 }
3736 pci_disable_msix(np->pci_dev);
3737 np->msi_flags &= ~NV_MSI_X_ENABLED;
3738 } else {
3739 free_irq(np->pci_dev->irq, dev);
3740 if (np->msi_flags & NV_MSI_ENABLED) {
3741 pci_disable_msi(np->pci_dev);
3742 np->msi_flags &= ~NV_MSI_ENABLED;
3743 }
3744 }
3745 }
3746
3747 static void nv_do_nic_poll(unsigned long data)
3748 {
3749 struct net_device *dev = (struct net_device *) data;
3750 struct fe_priv *np = netdev_priv(dev);
3751 u8 __iomem *base = get_hwbase(dev);
3752 u32 mask = 0;
3753
3754 /*
3755 * First disable irq(s) and then
3756 * reenable interrupts on the nic, we have to do this before calling
3757 * nv_nic_irq because that may decide to do otherwise
3758 */
3759
3760 if (!using_multi_irqs(dev)) {
3761 if (np->msi_flags & NV_MSI_X_ENABLED)
3762 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3763 else
3764 disable_irq_lockdep(np->pci_dev->irq);
3765 mask = np->irqmask;
3766 } else {
3767 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3768 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3769 mask |= NVREG_IRQ_RX_ALL;
3770 }
3771 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3772 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3773 mask |= NVREG_IRQ_TX_ALL;
3774 }
3775 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3776 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3777 mask |= NVREG_IRQ_OTHER;
3778 }
3779 }
3780 np->nic_poll_irq = 0;
3781
3782 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3783
3784 if (np->recover_error) {
3785 np->recover_error = 0;
3786 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3787 if (netif_running(dev)) {
3788 netif_tx_lock_bh(dev);
3789 spin_lock(&np->lock);
3790 /* stop engines */
3791 nv_stop_rx(dev);
3792 nv_stop_tx(dev);
3793 nv_txrx_reset(dev);
3794 /* drain rx queue */
3795 nv_drain_rx(dev);
3796 nv_drain_tx(dev);
3797 /* reinit driver view of the rx queue */
3798 set_bufsize(dev);
3799 if (nv_init_ring(dev)) {
3800 if (!np->in_shutdown)
3801 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3802 }
3803 /* reinit nic view of the rx queue */
3804 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3805 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3806 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3807 base + NvRegRingSizes);
3808 pci_push(base);
3809 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3810 pci_push(base);
3811
3812 /* restart rx engine */
3813 nv_start_rx(dev);
3814 nv_start_tx(dev);
3815 spin_unlock(&np->lock);
3816 netif_tx_unlock_bh(dev);
3817 }
3818 }
3819
3820
3821 writel(mask, base + NvRegIrqMask);
3822 pci_push(base);
3823
3824 if (!using_multi_irqs(dev)) {
3825 if (np->desc_ver == DESC_VER_3)
3826 nv_nic_irq_optimized(0, dev);
3827 else
3828 nv_nic_irq(0, dev);
3829 if (np->msi_flags & NV_MSI_X_ENABLED)
3830 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3831 else
3832 enable_irq_lockdep(np->pci_dev->irq);
3833 } else {
3834 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3835 nv_nic_irq_rx(0, dev);
3836 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3837 }
3838 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3839 nv_nic_irq_tx(0, dev);
3840 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3841 }
3842 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3843 nv_nic_irq_other(0, dev);
3844 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3845 }
3846 }
3847 }
3848
3849 #ifdef CONFIG_NET_POLL_CONTROLLER
3850 static void nv_poll_controller(struct net_device *dev)
3851 {
3852 nv_do_nic_poll((unsigned long) dev);
3853 }
3854 #endif
3855
3856 static void nv_do_stats_poll(unsigned long data)
3857 {
3858 struct net_device *dev = (struct net_device *) data;
3859 struct fe_priv *np = netdev_priv(dev);
3860
3861 nv_get_hw_stats(dev);
3862
3863 if (!np->in_shutdown)
3864 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3865 }
3866
3867 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3868 {
3869 struct fe_priv *np = netdev_priv(dev);
3870 strcpy(info->driver, DRV_NAME);
3871 strcpy(info->version, FORCEDETH_VERSION);
3872 strcpy(info->bus_info, pci_name(np->pci_dev));
3873 }
3874
3875 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3876 {
3877 struct fe_priv *np = netdev_priv(dev);
3878 wolinfo->supported = WAKE_MAGIC;
3879
3880 spin_lock_irq(&np->lock);
3881 if (np->wolenabled)
3882 wolinfo->wolopts = WAKE_MAGIC;
3883 spin_unlock_irq(&np->lock);
3884 }
3885
3886 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3887 {
3888 struct fe_priv *np = netdev_priv(dev);
3889 u8 __iomem *base = get_hwbase(dev);
3890 u32 flags = 0;
3891
3892 if (wolinfo->wolopts == 0) {
3893 np->wolenabled = 0;
3894 } else if (wolinfo->wolopts & WAKE_MAGIC) {
3895 np->wolenabled = 1;
3896 flags = NVREG_WAKEUPFLAGS_ENABLE;
3897 }
3898 if (netif_running(dev)) {
3899 spin_lock_irq(&np->lock);
3900 writel(flags, base + NvRegWakeUpFlags);
3901 spin_unlock_irq(&np->lock);
3902 }
3903 return 0;
3904 }
3905
3906 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3907 {
3908 struct fe_priv *np = netdev_priv(dev);
3909 int adv;
3910
3911 spin_lock_irq(&np->lock);
3912 ecmd->port = PORT_MII;
3913 if (!netif_running(dev)) {
3914 /* We do not track link speed / duplex setting if the
3915 * interface is disabled. Force a link check */
3916 if (nv_update_linkspeed(dev)) {
3917 if (!netif_carrier_ok(dev))
3918 netif_carrier_on(dev);
3919 } else {
3920 if (netif_carrier_ok(dev))
3921 netif_carrier_off(dev);
3922 }
3923 }
3924
3925 if (netif_carrier_ok(dev)) {
3926 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3927 case NVREG_LINKSPEED_10:
3928 ecmd->speed = SPEED_10;
3929 break;
3930 case NVREG_LINKSPEED_100:
3931 ecmd->speed = SPEED_100;
3932 break;
3933 case NVREG_LINKSPEED_1000:
3934 ecmd->speed = SPEED_1000;
3935 break;
3936 }
3937 ecmd->duplex = DUPLEX_HALF;
3938 if (np->duplex)
3939 ecmd->duplex = DUPLEX_FULL;
3940 } else {
3941 ecmd->speed = -1;
3942 ecmd->duplex = -1;
3943 }
3944
3945 ecmd->autoneg = np->autoneg;
3946
3947 ecmd->advertising = ADVERTISED_MII;
3948 if (np->autoneg) {
3949 ecmd->advertising |= ADVERTISED_Autoneg;
3950 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3951 if (adv & ADVERTISE_10HALF)
3952 ecmd->advertising |= ADVERTISED_10baseT_Half;
3953 if (adv & ADVERTISE_10FULL)
3954 ecmd->advertising |= ADVERTISED_10baseT_Full;
3955 if (adv & ADVERTISE_100HALF)
3956 ecmd->advertising |= ADVERTISED_100baseT_Half;
3957 if (adv & ADVERTISE_100FULL)
3958 ecmd->advertising |= ADVERTISED_100baseT_Full;
3959 if (np->gigabit == PHY_GIGABIT) {
3960 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3961 if (adv & ADVERTISE_1000FULL)
3962 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3963 }
3964 }
3965 ecmd->supported = (SUPPORTED_Autoneg |
3966 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3967 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3968 SUPPORTED_MII);
3969 if (np->gigabit == PHY_GIGABIT)
3970 ecmd->supported |= SUPPORTED_1000baseT_Full;
3971
3972 ecmd->phy_address = np->phyaddr;
3973 ecmd->transceiver = XCVR_EXTERNAL;
3974
3975 /* ignore maxtxpkt, maxrxpkt for now */
3976 spin_unlock_irq(&np->lock);
3977 return 0;
3978 }
3979
3980 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3981 {
3982 struct fe_priv *np = netdev_priv(dev);
3983
3984 if (ecmd->port != PORT_MII)
3985 return -EINVAL;
3986 if (ecmd->transceiver != XCVR_EXTERNAL)
3987 return -EINVAL;
3988 if (ecmd->phy_address != np->phyaddr) {
3989 /* TODO: support switching between multiple phys. Should be
3990 * trivial, but not enabled due to lack of test hardware. */
3991 return -EINVAL;
3992 }
3993 if (ecmd->autoneg == AUTONEG_ENABLE) {
3994 u32 mask;
3995
3996 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3997 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3998 if (np->gigabit == PHY_GIGABIT)
3999 mask |= ADVERTISED_1000baseT_Full;
4000
4001 if ((ecmd->advertising & mask) == 0)
4002 return -EINVAL;
4003
4004 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4005 /* Note: autonegotiation disable, speed 1000 intentionally
4006 * forbidden - noone should need that. */
4007
4008 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
4009 return -EINVAL;
4010 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4011 return -EINVAL;
4012 } else {
4013 return -EINVAL;
4014 }
4015
4016 netif_carrier_off(dev);
4017 if (netif_running(dev)) {
4018 nv_disable_irq(dev);
4019 netif_tx_lock_bh(dev);
4020 spin_lock(&np->lock);
4021 /* stop engines */
4022 nv_stop_rx(dev);
4023 nv_stop_tx(dev);
4024 spin_unlock(&np->lock);
4025 netif_tx_unlock_bh(dev);
4026 }
4027
4028 if (ecmd->autoneg == AUTONEG_ENABLE) {
4029 int adv, bmcr;
4030
4031 np->autoneg = 1;
4032
4033 /* advertise only what has been requested */
4034 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4035 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4036 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4037 adv |= ADVERTISE_10HALF;
4038 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4039 adv |= ADVERTISE_10FULL;
4040 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4041 adv |= ADVERTISE_100HALF;
4042 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4043 adv |= ADVERTISE_100FULL;
4044 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4045 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4046 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4047 adv |= ADVERTISE_PAUSE_ASYM;
4048 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4049
4050 if (np->gigabit == PHY_GIGABIT) {
4051 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4052 adv &= ~ADVERTISE_1000FULL;
4053 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4054 adv |= ADVERTISE_1000FULL;
4055 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4056 }
4057
4058 if (netif_running(dev))
4059 printk(KERN_INFO "%s: link down.\n", dev->name);
4060 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4061 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4062 bmcr |= BMCR_ANENABLE;
4063 /* reset the phy in order for settings to stick,
4064 * and cause autoneg to start */
4065 if (phy_reset(dev, bmcr)) {
4066 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4067 return -EINVAL;
4068 }
4069 } else {
4070 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4071 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4072 }
4073 } else {
4074 int adv, bmcr;
4075
4076 np->autoneg = 0;
4077
4078 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4079 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4080 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4081 adv |= ADVERTISE_10HALF;
4082 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4083 adv |= ADVERTISE_10FULL;
4084 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4085 adv |= ADVERTISE_100HALF;
4086 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4087 adv |= ADVERTISE_100FULL;
4088 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4089 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
4090 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4091 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4092 }
4093 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4094 adv |= ADVERTISE_PAUSE_ASYM;
4095 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4096 }
4097 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4098 np->fixed_mode = adv;
4099
4100 if (np->gigabit == PHY_GIGABIT) {
4101 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4102 adv &= ~ADVERTISE_1000FULL;
4103 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4104 }
4105
4106 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4107 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4108 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4109 bmcr |= BMCR_FULLDPLX;
4110 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4111 bmcr |= BMCR_SPEED100;
4112 if (np->phy_oui == PHY_OUI_MARVELL) {
4113 /* reset the phy in order for forced mode settings to stick */
4114 if (phy_reset(dev, bmcr)) {
4115 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4116 return -EINVAL;
4117 }
4118 } else {
4119 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4120 if (netif_running(dev)) {
4121 /* Wait a bit and then reconfigure the nic. */
4122 udelay(10);
4123 nv_linkchange(dev);
4124 }
4125 }
4126 }
4127
4128 if (netif_running(dev)) {
4129 nv_start_rx(dev);
4130 nv_start_tx(dev);
4131 nv_enable_irq(dev);
4132 }
4133
4134 return 0;
4135 }
4136
4137 #define FORCEDETH_REGS_VER 1
4138
4139 static int nv_get_regs_len(struct net_device *dev)
4140 {
4141 struct fe_priv *np = netdev_priv(dev);
4142 return np->register_size;
4143 }
4144
4145 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4146 {
4147 struct fe_priv *np = netdev_priv(dev);
4148 u8 __iomem *base = get_hwbase(dev);
4149 u32 *rbuf = buf;
4150 int i;
4151
4152 regs->version = FORCEDETH_REGS_VER;
4153 spin_lock_irq(&np->lock);
4154 for (i = 0;i <= np->register_size/sizeof(u32); i++)
4155 rbuf[i] = readl(base + i*sizeof(u32));
4156 spin_unlock_irq(&np->lock);
4157 }
4158
4159 static int nv_nway_reset(struct net_device *dev)
4160 {
4161 struct fe_priv *np = netdev_priv(dev);
4162 int ret;
4163
4164 if (np->autoneg) {
4165 int bmcr;
4166
4167 netif_carrier_off(dev);
4168 if (netif_running(dev)) {
4169 nv_disable_irq(dev);
4170 netif_tx_lock_bh(dev);
4171 spin_lock(&np->lock);
4172 /* stop engines */
4173 nv_stop_rx(dev);
4174 nv_stop_tx(dev);
4175 spin_unlock(&np->lock);
4176 netif_tx_unlock_bh(dev);
4177 printk(KERN_INFO "%s: link down.\n", dev->name);
4178 }
4179
4180 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4181 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4182 bmcr |= BMCR_ANENABLE;
4183 /* reset the phy in order for settings to stick*/
4184 if (phy_reset(dev, bmcr)) {
4185 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4186 return -EINVAL;
4187 }
4188 } else {
4189 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4190 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4191 }
4192
4193 if (netif_running(dev)) {
4194 nv_start_rx(dev);
4195 nv_start_tx(dev);
4196 nv_enable_irq(dev);
4197 }
4198 ret = 0;
4199 } else {
4200 ret = -EINVAL;
4201 }
4202
4203 return ret;
4204 }
4205
4206 static int nv_set_tso(struct net_device *dev, u32 value)
4207 {
4208 struct fe_priv *np = netdev_priv(dev);
4209
4210 if ((np->driver_data & DEV_HAS_CHECKSUM))
4211 return ethtool_op_set_tso(dev, value);
4212 else
4213 return -EOPNOTSUPP;
4214 }
4215
4216 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4217 {
4218 struct fe_priv *np = netdev_priv(dev);
4219
4220 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4221 ring->rx_mini_max_pending = 0;
4222 ring->rx_jumbo_max_pending = 0;
4223 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4224
4225 ring->rx_pending = np->rx_ring_size;
4226 ring->rx_mini_pending = 0;
4227 ring->rx_jumbo_pending = 0;
4228 ring->tx_pending = np->tx_ring_size;
4229 }
4230
4231 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4232 {
4233 struct fe_priv *np = netdev_priv(dev);
4234 u8 __iomem *base = get_hwbase(dev);
4235 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4236 dma_addr_t ring_addr;
4237
4238 if (ring->rx_pending < RX_RING_MIN ||
4239 ring->tx_pending < TX_RING_MIN ||
4240 ring->rx_mini_pending != 0 ||
4241 ring->rx_jumbo_pending != 0 ||
4242 (np->desc_ver == DESC_VER_1 &&
4243 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4244 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4245 (np->desc_ver != DESC_VER_1 &&
4246 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4247 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4248 return -EINVAL;
4249 }
4250
4251 /* allocate new rings */
4252 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4253 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4254 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4255 &ring_addr);
4256 } else {
4257 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4258 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4259 &ring_addr);
4260 }
4261 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4262 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4263 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4264 /* fall back to old rings */
4265 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4266 if (rxtx_ring)
4267 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4268 rxtx_ring, ring_addr);
4269 } else {
4270 if (rxtx_ring)
4271 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4272 rxtx_ring, ring_addr);
4273 }
4274 if (rx_skbuff)
4275 kfree(rx_skbuff);
4276 if (tx_skbuff)
4277 kfree(tx_skbuff);
4278 goto exit;
4279 }
4280
4281 if (netif_running(dev)) {
4282 nv_disable_irq(dev);
4283 netif_tx_lock_bh(dev);
4284 spin_lock(&np->lock);
4285 /* stop engines */
4286 nv_stop_rx(dev);
4287 nv_stop_tx(dev);
4288 nv_txrx_reset(dev);
4289 /* drain queues */
4290 nv_drain_rx(dev);
4291 nv_drain_tx(dev);
4292 /* delete queues */
4293 free_rings(dev);
4294 }
4295
4296 /* set new values */
4297 np->rx_ring_size = ring->rx_pending;
4298 np->tx_ring_size = ring->tx_pending;
4299 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4300 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4301 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4302 } else {
4303 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4304 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4305 }
4306 np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4307 np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4308 np->ring_addr = ring_addr;
4309
4310 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4311 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4312
4313 if (netif_running(dev)) {
4314 /* reinit driver view of the queues */
4315 set_bufsize(dev);
4316 if (nv_init_ring(dev)) {
4317 if (!np->in_shutdown)
4318 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4319 }
4320
4321 /* reinit nic view of the queues */
4322 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4323 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4324 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4325 base + NvRegRingSizes);
4326 pci_push(base);
4327 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4328 pci_push(base);
4329
4330 /* restart engines */
4331 nv_start_rx(dev);
4332 nv_start_tx(dev);
4333 spin_unlock(&np->lock);
4334 netif_tx_unlock_bh(dev);
4335 nv_enable_irq(dev);
4336 }
4337 return 0;
4338 exit:
4339 return -ENOMEM;
4340 }
4341
4342 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4343 {
4344 struct fe_priv *np = netdev_priv(dev);
4345
4346 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4347 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4348 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4349 }
4350
4351 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4352 {
4353 struct fe_priv *np = netdev_priv(dev);
4354 int adv, bmcr;
4355
4356 if ((!np->autoneg && np->duplex == 0) ||
4357 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4358 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4359 dev->name);
4360 return -EINVAL;
4361 }
4362 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4363 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4364 return -EINVAL;
4365 }
4366
4367 netif_carrier_off(dev);
4368 if (netif_running(dev)) {
4369 nv_disable_irq(dev);
4370 netif_tx_lock_bh(dev);
4371 spin_lock(&np->lock);
4372 /* stop engines */
4373 nv_stop_rx(dev);
4374 nv_stop_tx(dev);
4375 spin_unlock(&np->lock);
4376 netif_tx_unlock_bh(dev);
4377 }
4378
4379 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4380 if (pause->rx_pause)
4381 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4382 if (pause->tx_pause)
4383 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4384
4385 if (np->autoneg && pause->autoneg) {
4386 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4387
4388 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4389 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4390 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4391 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4392 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4393 adv |= ADVERTISE_PAUSE_ASYM;
4394 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4395
4396 if (netif_running(dev))
4397 printk(KERN_INFO "%s: link down.\n", dev->name);
4398 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4399 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4400 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4401 } else {
4402 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4403 if (pause->rx_pause)
4404 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4405 if (pause->tx_pause)
4406 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4407
4408 if (!netif_running(dev))
4409 nv_update_linkspeed(dev);
4410 else
4411 nv_update_pause(dev, np->pause_flags);
4412 }
4413
4414 if (netif_running(dev)) {
4415 nv_start_rx(dev);
4416 nv_start_tx(dev);
4417 nv_enable_irq(dev);
4418 }
4419 return 0;
4420 }
4421
4422 static u32 nv_get_rx_csum(struct net_device *dev)
4423 {
4424 struct fe_priv *np = netdev_priv(dev);
4425 return (np->rx_csum) != 0;
4426 }
4427
4428 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4429 {
4430 struct fe_priv *np = netdev_priv(dev);
4431 u8 __iomem *base = get_hwbase(dev);
4432 int retcode = 0;
4433
4434 if (np->driver_data & DEV_HAS_CHECKSUM) {
4435 if (data) {
4436 np->rx_csum = 1;
4437 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4438 } else {
4439 np->rx_csum = 0;
4440 /* vlan is dependent on rx checksum offload */
4441 if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4442 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4443 }
4444 if (netif_running(dev)) {
4445 spin_lock_irq(&np->lock);
4446 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4447 spin_unlock_irq(&np->lock);
4448 }
4449 } else {
4450 return -EINVAL;
4451 }
4452
4453 return retcode;
4454 }
4455
4456 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4457 {
4458 struct fe_priv *np = netdev_priv(dev);
4459
4460 if (np->driver_data & DEV_HAS_CHECKSUM)
4461 return ethtool_op_set_tx_hw_csum(dev, data);
4462 else
4463 return -EOPNOTSUPP;
4464 }
4465
4466 static int nv_set_sg(struct net_device *dev, u32 data)
4467 {
4468 struct fe_priv *np = netdev_priv(dev);
4469
4470 if (np->driver_data & DEV_HAS_CHECKSUM)
4471 return ethtool_op_set_sg(dev, data);
4472 else
4473 return -EOPNOTSUPP;
4474 }
4475
4476 static int nv_get_sset_count(struct net_device *dev, int sset)
4477 {
4478 struct fe_priv *np = netdev_priv(dev);
4479
4480 switch (sset) {
4481 case ETH_SS_TEST:
4482 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4483 return NV_TEST_COUNT_EXTENDED;
4484 else
4485 return NV_TEST_COUNT_BASE;
4486 case ETH_SS_STATS:
4487 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4488 return NV_DEV_STATISTICS_V1_COUNT;
4489 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4490 return NV_DEV_STATISTICS_V2_COUNT;
4491 else
4492 return 0;
4493 default:
4494 return -EOPNOTSUPP;
4495 }
4496 }
4497
4498 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4499 {
4500 struct fe_priv *np = netdev_priv(dev);
4501
4502 /* update stats */
4503 nv_do_stats_poll((unsigned long)dev);
4504
4505 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4506 }
4507
4508 static int nv_link_test(struct net_device *dev)
4509 {
4510 struct fe_priv *np = netdev_priv(dev);
4511 int mii_status;
4512
4513 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4514 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4515
4516 /* check phy link status */
4517 if (!(mii_status & BMSR_LSTATUS))
4518 return 0;
4519 else
4520 return 1;
4521 }
4522
4523 static int nv_register_test(struct net_device *dev)
4524 {
4525 u8 __iomem *base = get_hwbase(dev);
4526 int i = 0;
4527 u32 orig_read, new_read;
4528
4529 do {
4530 orig_read = readl(base + nv_registers_test[i].reg);
4531
4532 /* xor with mask to toggle bits */
4533 orig_read ^= nv_registers_test[i].mask;
4534
4535 writel(orig_read, base + nv_registers_test[i].reg);
4536
4537 new_read = readl(base + nv_registers_test[i].reg);
4538
4539 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4540 return 0;
4541
4542 /* restore original value */
4543 orig_read ^= nv_registers_test[i].mask;
4544 writel(orig_read, base + nv_registers_test[i].reg);
4545
4546 } while (nv_registers_test[++i].reg != 0);
4547
4548 return 1;
4549 }
4550
4551 static int nv_interrupt_test(struct net_device *dev)
4552 {
4553 struct fe_priv *np = netdev_priv(dev);
4554 u8 __iomem *base = get_hwbase(dev);
4555 int ret = 1;
4556 int testcnt;
4557 u32 save_msi_flags, save_poll_interval = 0;
4558
4559 if (netif_running(dev)) {
4560 /* free current irq */
4561 nv_free_irq(dev);
4562 save_poll_interval = readl(base+NvRegPollingInterval);
4563 }
4564
4565 /* flag to test interrupt handler */
4566 np->intr_test = 0;
4567
4568 /* setup test irq */
4569 save_msi_flags = np->msi_flags;
4570 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4571 np->msi_flags |= 0x001; /* setup 1 vector */
4572 if (nv_request_irq(dev, 1))
4573 return 0;
4574
4575 /* setup timer interrupt */
4576 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4577 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4578
4579 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4580
4581 /* wait for at least one interrupt */
4582 msleep(100);
4583
4584 spin_lock_irq(&np->lock);
4585
4586 /* flag should be set within ISR */
4587 testcnt = np->intr_test;
4588 if (!testcnt)
4589 ret = 2;
4590
4591 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4592 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4593 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4594 else
4595 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4596
4597 spin_unlock_irq(&np->lock);
4598
4599 nv_free_irq(dev);
4600
4601 np->msi_flags = save_msi_flags;
4602
4603 if (netif_running(dev)) {
4604 writel(save_poll_interval, base + NvRegPollingInterval);
4605 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4606 /* restore original irq */
4607 if (nv_request_irq(dev, 0))
4608 return 0;
4609 }
4610
4611 return ret;
4612 }
4613
4614 static int nv_loopback_test(struct net_device *dev)
4615 {
4616 struct fe_priv *np = netdev_priv(dev);
4617 u8 __iomem *base = get_hwbase(dev);
4618 struct sk_buff *tx_skb, *rx_skb;
4619 dma_addr_t test_dma_addr;
4620 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4621 u32 flags;
4622 int len, i, pkt_len;
4623 u8 *pkt_data;
4624 u32 filter_flags = 0;
4625 u32 misc1_flags = 0;
4626 int ret = 1;
4627
4628 if (netif_running(dev)) {
4629 nv_disable_irq(dev);
4630 filter_flags = readl(base + NvRegPacketFilterFlags);
4631 misc1_flags = readl(base + NvRegMisc1);
4632 } else {
4633 nv_txrx_reset(dev);
4634 }
4635
4636 /* reinit driver view of the rx queue */
4637 set_bufsize(dev);
4638 nv_init_ring(dev);
4639
4640 /* setup hardware for loopback */
4641 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4642 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4643
4644 /* reinit nic view of the rx queue */
4645 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4646 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4647 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4648 base + NvRegRingSizes);
4649 pci_push(base);
4650
4651 /* restart rx engine */
4652 nv_start_rx(dev);
4653 nv_start_tx(dev);
4654
4655 /* setup packet for tx */
4656 pkt_len = ETH_DATA_LEN;
4657 tx_skb = dev_alloc_skb(pkt_len);
4658 if (!tx_skb) {
4659 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4660 " of %s\n", dev->name);
4661 ret = 0;
4662 goto out;
4663 }
4664 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4665 skb_tailroom(tx_skb),
4666 PCI_DMA_FROMDEVICE);
4667 pkt_data = skb_put(tx_skb, pkt_len);
4668 for (i = 0; i < pkt_len; i++)
4669 pkt_data[i] = (u8)(i & 0xff);
4670
4671 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4672 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4673 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4674 } else {
4675 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4676 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4677 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4678 }
4679 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4680 pci_push(get_hwbase(dev));
4681
4682 msleep(500);
4683
4684 /* check for rx of the packet */
4685 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4686 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4687 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4688
4689 } else {
4690 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4691 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4692 }
4693
4694 if (flags & NV_RX_AVAIL) {
4695 ret = 0;
4696 } else if (np->desc_ver == DESC_VER_1) {
4697 if (flags & NV_RX_ERROR)
4698 ret = 0;
4699 } else {
4700 if (flags & NV_RX2_ERROR) {
4701 ret = 0;
4702 }
4703 }
4704
4705 if (ret) {
4706 if (len != pkt_len) {
4707 ret = 0;
4708 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4709 dev->name, len, pkt_len);
4710 } else {
4711 rx_skb = np->rx_skb[0].skb;
4712 for (i = 0; i < pkt_len; i++) {
4713 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4714 ret = 0;
4715 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4716 dev->name, i);
4717 break;
4718 }
4719 }
4720 }
4721 } else {
4722 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4723 }
4724
4725 pci_unmap_page(np->pci_dev, test_dma_addr,
4726 (skb_end_pointer(tx_skb) - tx_skb->data),
4727 PCI_DMA_TODEVICE);
4728 dev_kfree_skb_any(tx_skb);
4729 out:
4730 /* stop engines */
4731 nv_stop_rx(dev);
4732 nv_stop_tx(dev);
4733 nv_txrx_reset(dev);
4734 /* drain rx queue */
4735 nv_drain_rx(dev);
4736 nv_drain_tx(dev);
4737
4738 if (netif_running(dev)) {
4739 writel(misc1_flags, base + NvRegMisc1);
4740 writel(filter_flags, base + NvRegPacketFilterFlags);
4741 nv_enable_irq(dev);
4742 }
4743
4744 return ret;
4745 }
4746
4747 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4748 {
4749 struct fe_priv *np = netdev_priv(dev);
4750 u8 __iomem *base = get_hwbase(dev);
4751 int result;
4752 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4753
4754 if (!nv_link_test(dev)) {
4755 test->flags |= ETH_TEST_FL_FAILED;
4756 buffer[0] = 1;
4757 }
4758
4759 if (test->flags & ETH_TEST_FL_OFFLINE) {
4760 if (netif_running(dev)) {
4761 netif_stop_queue(dev);
4762 #ifdef CONFIG_FORCEDETH_NAPI
4763 napi_disable(&np->napi);
4764 #endif
4765 netif_tx_lock_bh(dev);
4766 spin_lock_irq(&np->lock);
4767 nv_disable_hw_interrupts(dev, np->irqmask);
4768 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4769 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4770 } else {
4771 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4772 }
4773 /* stop engines */
4774 nv_stop_rx(dev);
4775 nv_stop_tx(dev);
4776 nv_txrx_reset(dev);
4777 /* drain rx queue */
4778 nv_drain_rx(dev);
4779 nv_drain_tx(dev);
4780 spin_unlock_irq(&np->lock);
4781 netif_tx_unlock_bh(dev);
4782 }
4783
4784 if (!nv_register_test(dev)) {
4785 test->flags |= ETH_TEST_FL_FAILED;
4786 buffer[1] = 1;
4787 }
4788
4789 result = nv_interrupt_test(dev);
4790 if (result != 1) {
4791 test->flags |= ETH_TEST_FL_FAILED;
4792 buffer[2] = 1;
4793 }
4794 if (result == 0) {
4795 /* bail out */
4796 return;
4797 }
4798
4799 if (!nv_loopback_test(dev)) {
4800 test->flags |= ETH_TEST_FL_FAILED;
4801 buffer[3] = 1;
4802 }
4803
4804 if (netif_running(dev)) {
4805 /* reinit driver view of the rx queue */
4806 set_bufsize(dev);
4807 if (nv_init_ring(dev)) {
4808 if (!np->in_shutdown)
4809 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4810 }
4811 /* reinit nic view of the rx queue */
4812 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4813 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4814 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4815 base + NvRegRingSizes);
4816 pci_push(base);
4817 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4818 pci_push(base);
4819 /* restart rx engine */
4820 nv_start_rx(dev);
4821 nv_start_tx(dev);
4822 netif_start_queue(dev);
4823 #ifdef CONFIG_FORCEDETH_NAPI
4824 napi_enable(&np->napi);
4825 #endif
4826 nv_enable_hw_interrupts(dev, np->irqmask);
4827 }
4828 }
4829 }
4830
4831 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4832 {
4833 switch (stringset) {
4834 case ETH_SS_STATS:
4835 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4836 break;
4837 case ETH_SS_TEST:
4838 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4839 break;
4840 }
4841 }
4842
4843 static const struct ethtool_ops ops = {
4844 .get_drvinfo = nv_get_drvinfo,
4845 .get_link = ethtool_op_get_link,
4846 .get_wol = nv_get_wol,
4847 .set_wol = nv_set_wol,
4848 .get_settings = nv_get_settings,
4849 .set_settings = nv_set_settings,
4850 .get_regs_len = nv_get_regs_len,
4851 .get_regs = nv_get_regs,
4852 .nway_reset = nv_nway_reset,
4853 .set_tso = nv_set_tso,
4854 .get_ringparam = nv_get_ringparam,
4855 .set_ringparam = nv_set_ringparam,
4856 .get_pauseparam = nv_get_pauseparam,
4857 .set_pauseparam = nv_set_pauseparam,
4858 .get_rx_csum = nv_get_rx_csum,
4859 .set_rx_csum = nv_set_rx_csum,
4860 .set_tx_csum = nv_set_tx_csum,
4861 .set_sg = nv_set_sg,
4862 .get_strings = nv_get_strings,
4863 .get_ethtool_stats = nv_get_ethtool_stats,
4864 .get_sset_count = nv_get_sset_count,
4865 .self_test = nv_self_test,
4866 };
4867
4868 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4869 {
4870 struct fe_priv *np = get_nvpriv(dev);
4871
4872 spin_lock_irq(&np->lock);
4873
4874 /* save vlan group */
4875 np->vlangrp = grp;
4876
4877 if (grp) {
4878 /* enable vlan on MAC */
4879 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4880 } else {
4881 /* disable vlan on MAC */
4882 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4883 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4884 }
4885
4886 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4887
4888 spin_unlock_irq(&np->lock);
4889 }
4890
4891 /* The mgmt unit and driver use a semaphore to access the phy during init */
4892 static int nv_mgmt_acquire_sema(struct net_device *dev)
4893 {
4894 u8 __iomem *base = get_hwbase(dev);
4895 int i;
4896 u32 tx_ctrl, mgmt_sema;
4897
4898 for (i = 0; i < 10; i++) {
4899 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4900 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4901 break;
4902 msleep(500);
4903 }
4904
4905 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4906 return 0;
4907
4908 for (i = 0; i < 2; i++) {
4909 tx_ctrl = readl(base + NvRegTransmitterControl);
4910 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4911 writel(tx_ctrl, base + NvRegTransmitterControl);
4912
4913 /* verify that semaphore was acquired */
4914 tx_ctrl = readl(base + NvRegTransmitterControl);
4915 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4916 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4917 return 1;
4918 else
4919 udelay(50);
4920 }
4921
4922 return 0;
4923 }
4924
4925 static int nv_open(struct net_device *dev)
4926 {
4927 struct fe_priv *np = netdev_priv(dev);
4928 u8 __iomem *base = get_hwbase(dev);
4929 int ret = 1;
4930 int oom, i;
4931
4932 dprintk(KERN_DEBUG "nv_open: begin\n");
4933
4934 /* erase previous misconfiguration */
4935 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4936 nv_mac_reset(dev);
4937 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4938 writel(0, base + NvRegMulticastAddrB);
4939 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
4940 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
4941 writel(0, base + NvRegPacketFilterFlags);
4942
4943 writel(0, base + NvRegTransmitterControl);
4944 writel(0, base + NvRegReceiverControl);
4945
4946 writel(0, base + NvRegAdapterControl);
4947
4948 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4949 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
4950
4951 /* initialize descriptor rings */
4952 set_bufsize(dev);
4953 oom = nv_init_ring(dev);
4954
4955 writel(0, base + NvRegLinkSpeed);
4956 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4957 nv_txrx_reset(dev);
4958 writel(0, base + NvRegUnknownSetupReg6);
4959
4960 np->in_shutdown = 0;
4961
4962 /* give hw rings */
4963 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4964 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4965 base + NvRegRingSizes);
4966
4967 writel(np->linkspeed, base + NvRegLinkSpeed);
4968 if (np->desc_ver == DESC_VER_1)
4969 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4970 else
4971 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4972 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4973 writel(np->vlanctl_bits, base + NvRegVlanControl);
4974 pci_push(base);
4975 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4976 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4977 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4978 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4979
4980 writel(0, base + NvRegMIIMask);
4981 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4982 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
4983
4984 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4985 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4986 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4987 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4988
4989 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4990 get_random_bytes(&i, sizeof(i));
4991 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4992 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4993 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4994 if (poll_interval == -1) {
4995 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4996 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4997 else
4998 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4999 }
5000 else
5001 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5002 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5003 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5004 base + NvRegAdapterControl);
5005 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5006 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5007 if (np->wolenabled)
5008 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5009
5010 i = readl(base + NvRegPowerState);
5011 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
5012 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5013
5014 pci_push(base);
5015 udelay(10);
5016 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5017
5018 nv_disable_hw_interrupts(dev, np->irqmask);
5019 pci_push(base);
5020 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5021 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5022 pci_push(base);
5023
5024 if (nv_request_irq(dev, 0)) {
5025 goto out_drain;
5026 }
5027
5028 /* ask for interrupts */
5029 nv_enable_hw_interrupts(dev, np->irqmask);
5030
5031 spin_lock_irq(&np->lock);
5032 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5033 writel(0, base + NvRegMulticastAddrB);
5034 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5035 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5036 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5037 /* One manual link speed update: Interrupts are enabled, future link
5038 * speed changes cause interrupts and are handled by nv_link_irq().
5039 */
5040 {
5041 u32 miistat;
5042 miistat = readl(base + NvRegMIIStatus);
5043 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5044 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
5045 }
5046 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5047 * to init hw */
5048 np->linkspeed = 0;
5049 ret = nv_update_linkspeed(dev);
5050 nv_start_rx(dev);
5051 nv_start_tx(dev);
5052 netif_start_queue(dev);
5053 #ifdef CONFIG_FORCEDETH_NAPI
5054 napi_enable(&np->napi);
5055 #endif
5056
5057 if (ret) {
5058 netif_carrier_on(dev);
5059 } else {
5060 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
5061 netif_carrier_off(dev);
5062 }
5063 if (oom)
5064 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5065
5066 /* start statistics timer */
5067 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
5068 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
5069
5070 spin_unlock_irq(&np->lock);
5071
5072 return 0;
5073 out_drain:
5074 drain_ring(dev);
5075 return ret;
5076 }
5077
5078 static int nv_close(struct net_device *dev)
5079 {
5080 struct fe_priv *np = netdev_priv(dev);
5081 u8 __iomem *base;
5082
5083 spin_lock_irq(&np->lock);
5084 np->in_shutdown = 1;
5085 spin_unlock_irq(&np->lock);
5086 #ifdef CONFIG_FORCEDETH_NAPI
5087 napi_disable(&np->napi);
5088 #endif
5089 synchronize_irq(np->pci_dev->irq);
5090
5091 del_timer_sync(&np->oom_kick);
5092 del_timer_sync(&np->nic_poll);
5093 del_timer_sync(&np->stats_poll);
5094
5095 netif_stop_queue(dev);
5096 spin_lock_irq(&np->lock);
5097 nv_stop_tx(dev);
5098 nv_stop_rx(dev);
5099 nv_txrx_reset(dev);
5100
5101 /* disable interrupts on the nic or we will lock up */
5102 base = get_hwbase(dev);
5103 nv_disable_hw_interrupts(dev, np->irqmask);
5104 pci_push(base);
5105 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
5106
5107 spin_unlock_irq(&np->lock);
5108
5109 nv_free_irq(dev);
5110
5111 drain_ring(dev);
5112
5113 if (np->wolenabled) {
5114 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5115 nv_start_rx(dev);
5116 }
5117
5118 /* FIXME: power down nic */
5119
5120 return 0;
5121 }
5122
5123 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5124 {
5125 struct net_device *dev;
5126 struct fe_priv *np;
5127 unsigned long addr;
5128 u8 __iomem *base;
5129 int err, i;
5130 u32 powerstate, txreg;
5131 u32 phystate_orig = 0, phystate;
5132 int phyinitialized = 0;
5133 DECLARE_MAC_BUF(mac);
5134 static int printed_version;
5135
5136 if (!printed_version++)
5137 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5138 " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5139
5140 dev = alloc_etherdev(sizeof(struct fe_priv));
5141 err = -ENOMEM;
5142 if (!dev)
5143 goto out;
5144
5145 np = netdev_priv(dev);
5146 np->dev = dev;
5147 np->pci_dev = pci_dev;
5148 spin_lock_init(&np->lock);
5149 SET_NETDEV_DEV(dev, &pci_dev->dev);
5150
5151 init_timer(&np->oom_kick);
5152 np->oom_kick.data = (unsigned long) dev;
5153 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
5154 init_timer(&np->nic_poll);
5155 np->nic_poll.data = (unsigned long) dev;
5156 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
5157 init_timer(&np->stats_poll);
5158 np->stats_poll.data = (unsigned long) dev;
5159 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
5160
5161 err = pci_enable_device(pci_dev);
5162 if (err)
5163 goto out_free;
5164
5165 pci_set_master(pci_dev);
5166
5167 err = pci_request_regions(pci_dev, DRV_NAME);
5168 if (err < 0)
5169 goto out_disable;
5170
5171 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
5172 np->register_size = NV_PCI_REGSZ_VER3;
5173 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5174 np->register_size = NV_PCI_REGSZ_VER2;
5175 else
5176 np->register_size = NV_PCI_REGSZ_VER1;
5177
5178 err = -EINVAL;
5179 addr = 0;
5180 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5181 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5182 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5183 pci_resource_len(pci_dev, i),
5184 pci_resource_flags(pci_dev, i));
5185 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5186 pci_resource_len(pci_dev, i) >= np->register_size) {
5187 addr = pci_resource_start(pci_dev, i);
5188 break;
5189 }
5190 }
5191 if (i == DEVICE_COUNT_RESOURCE) {
5192 dev_printk(KERN_INFO, &pci_dev->dev,
5193 "Couldn't find register window\n");
5194 goto out_relreg;
5195 }
5196
5197 /* copy of driver data */
5198 np->driver_data = id->driver_data;
5199
5200 /* handle different descriptor versions */
5201 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5202 /* packet format 3: supports 40-bit addressing */
5203 np->desc_ver = DESC_VER_3;
5204 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5205 if (dma_64bit) {
5206 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5207 dev_printk(KERN_INFO, &pci_dev->dev,
5208 "64-bit DMA failed, using 32-bit addressing\n");
5209 else
5210 dev->features |= NETIF_F_HIGHDMA;
5211 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
5212 dev_printk(KERN_INFO, &pci_dev->dev,
5213 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5214 }
5215 }
5216 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5217 /* packet format 2: supports jumbo frames */
5218 np->desc_ver = DESC_VER_2;
5219 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5220 } else {
5221 /* original packet format */
5222 np->desc_ver = DESC_VER_1;
5223 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5224 }
5225
5226 np->pkt_limit = NV_PKTLIMIT_1;
5227 if (id->driver_data & DEV_HAS_LARGEDESC)
5228 np->pkt_limit = NV_PKTLIMIT_2;
5229
5230 if (id->driver_data & DEV_HAS_CHECKSUM) {
5231 np->rx_csum = 1;
5232 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5233 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5234 dev->features |= NETIF_F_TSO;
5235 }
5236
5237 np->vlanctl_bits = 0;
5238 if (id->driver_data & DEV_HAS_VLAN) {
5239 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5240 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5241 dev->vlan_rx_register = nv_vlan_rx_register;
5242 }
5243
5244 np->msi_flags = 0;
5245 if ((id->driver_data & DEV_HAS_MSI) && msi) {
5246 np->msi_flags |= NV_MSI_CAPABLE;
5247 }
5248 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5249 np->msi_flags |= NV_MSI_X_CAPABLE;
5250 }
5251
5252 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5253 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5254 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5255 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5256 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5257 }
5258
5259
5260 err = -ENOMEM;
5261 np->base = ioremap(addr, np->register_size);
5262 if (!np->base)
5263 goto out_relreg;
5264 dev->base_addr = (unsigned long)np->base;
5265
5266 dev->irq = pci_dev->irq;
5267
5268 np->rx_ring_size = RX_RING_DEFAULT;
5269 np->tx_ring_size = TX_RING_DEFAULT;
5270
5271 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
5272 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5273 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5274 &np->ring_addr);
5275 if (!np->rx_ring.orig)
5276 goto out_unmap;
5277 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5278 } else {
5279 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5280 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5281 &np->ring_addr);
5282 if (!np->rx_ring.ex)
5283 goto out_unmap;
5284 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5285 }
5286 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5287 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5288 if (!np->rx_skb || !np->tx_skb)
5289 goto out_freering;
5290
5291 dev->open = nv_open;
5292 dev->stop = nv_close;
5293 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
5294 dev->hard_start_xmit = nv_start_xmit;
5295 else
5296 dev->hard_start_xmit = nv_start_xmit_optimized;
5297 dev->get_stats = nv_get_stats;
5298 dev->change_mtu = nv_change_mtu;
5299 dev->set_mac_address = nv_set_mac_address;
5300 dev->set_multicast_list = nv_set_multicast;
5301 #ifdef CONFIG_NET_POLL_CONTROLLER
5302 dev->poll_controller = nv_poll_controller;
5303 #endif
5304 #ifdef CONFIG_FORCEDETH_NAPI
5305 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5306 #endif
5307 SET_ETHTOOL_OPS(dev, &ops);
5308 dev->tx_timeout = nv_tx_timeout;
5309 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5310
5311 pci_set_drvdata(pci_dev, dev);
5312
5313 /* read the mac address */
5314 base = get_hwbase(dev);
5315 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5316 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5317
5318 /* check the workaround bit for correct mac address order */
5319 txreg = readl(base + NvRegTransmitPoll);
5320 if ((txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) ||
5321 (id->driver_data & DEV_HAS_CORRECT_MACADDR)) {
5322 /* mac address is already in correct order */
5323 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5324 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5325 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5326 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5327 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5328 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5329 } else {
5330 /* need to reverse mac address to correct order */
5331 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5332 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5333 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5334 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5335 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5336 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5337 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5338 }
5339 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5340
5341 if (!is_valid_ether_addr(dev->perm_addr)) {
5342 /*
5343 * Bad mac address. At least one bios sets the mac address
5344 * to 01:23:45:67:89:ab
5345 */
5346 dev_printk(KERN_ERR, &pci_dev->dev,
5347 "Invalid Mac address detected: %s\n",
5348 print_mac(mac, dev->dev_addr));
5349 dev_printk(KERN_ERR, &pci_dev->dev,
5350 "Please complain to your hardware vendor. Switching to a random MAC.\n");
5351 dev->dev_addr[0] = 0x00;
5352 dev->dev_addr[1] = 0x00;
5353 dev->dev_addr[2] = 0x6c;
5354 get_random_bytes(&dev->dev_addr[3], 3);
5355 }
5356
5357 dprintk(KERN_DEBUG "%s: MAC Address %s\n",
5358 pci_name(pci_dev), print_mac(mac, dev->dev_addr));
5359
5360 /* set mac address */
5361 nv_copy_mac_to_hw(dev);
5362
5363 /* disable WOL */
5364 writel(0, base + NvRegWakeUpFlags);
5365 np->wolenabled = 0;
5366
5367 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5368
5369 /* take phy and nic out of low power mode */
5370 powerstate = readl(base + NvRegPowerState2);
5371 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5372 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5373 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5374 pci_dev->revision >= 0xA3)
5375 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5376 writel(powerstate, base + NvRegPowerState2);
5377 }
5378
5379 if (np->desc_ver == DESC_VER_1) {
5380 np->tx_flags = NV_TX_VALID;
5381 } else {
5382 np->tx_flags = NV_TX2_VALID;
5383 }
5384 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5385 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5386 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5387 np->msi_flags |= 0x0003;
5388 } else {
5389 np->irqmask = NVREG_IRQMASK_CPU;
5390 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5391 np->msi_flags |= 0x0001;
5392 }
5393
5394 if (id->driver_data & DEV_NEED_TIMERIRQ)
5395 np->irqmask |= NVREG_IRQ_TIMER;
5396 if (id->driver_data & DEV_NEED_LINKTIMER) {
5397 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5398 np->need_linktimer = 1;
5399 np->link_timeout = jiffies + LINK_TIMEOUT;
5400 } else {
5401 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5402 np->need_linktimer = 0;
5403 }
5404
5405 /* Limit the number of tx's outstanding for hw bug */
5406 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5407 np->tx_limit = 1;
5408 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_32 ||
5409 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_33 ||
5410 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_34 ||
5411 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_35 ||
5412 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_36 ||
5413 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_37 ||
5414 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_38 ||
5415 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_39) &&
5416 pci_dev->revision >= 0xA2)
5417 np->tx_limit = 0;
5418 }
5419
5420 /* clear phy state and temporarily halt phy interrupts */
5421 writel(0, base + NvRegMIIMask);
5422 phystate = readl(base + NvRegAdapterControl);
5423 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5424 phystate_orig = 1;
5425 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5426 writel(phystate, base + NvRegAdapterControl);
5427 }
5428 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5429
5430 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5431 /* management unit running on the mac? */
5432 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5433 np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5434 dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5435 if (nv_mgmt_acquire_sema(dev)) {
5436 /* management unit setup the phy already? */
5437 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5438 NVREG_XMITCTL_SYNC_PHY_INIT) {
5439 /* phy is inited by mgmt unit */
5440 phyinitialized = 1;
5441 dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5442 } else {
5443 /* we need to init the phy */
5444 }
5445 }
5446 }
5447 }
5448
5449 /* find a suitable phy */
5450 for (i = 1; i <= 32; i++) {
5451 int id1, id2;
5452 int phyaddr = i & 0x1F;
5453
5454 spin_lock_irq(&np->lock);
5455 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5456 spin_unlock_irq(&np->lock);
5457 if (id1 < 0 || id1 == 0xffff)
5458 continue;
5459 spin_lock_irq(&np->lock);
5460 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5461 spin_unlock_irq(&np->lock);
5462 if (id2 < 0 || id2 == 0xffff)
5463 continue;
5464
5465 np->phy_model = id2 & PHYID2_MODEL_MASK;
5466 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5467 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5468 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5469 pci_name(pci_dev), id1, id2, phyaddr);
5470 np->phyaddr = phyaddr;
5471 np->phy_oui = id1 | id2;
5472 break;
5473 }
5474 if (i == 33) {
5475 dev_printk(KERN_INFO, &pci_dev->dev,
5476 "open: Could not find a valid PHY.\n");
5477 goto out_error;
5478 }
5479
5480 if (!phyinitialized) {
5481 /* reset it */
5482 phy_init(dev);
5483 } else {
5484 /* see if it is a gigabit phy */
5485 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5486 if (mii_status & PHY_GIGABIT) {
5487 np->gigabit = PHY_GIGABIT;
5488 }
5489 }
5490
5491 /* set default link speed settings */
5492 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5493 np->duplex = 0;
5494 np->autoneg = 1;
5495
5496 err = register_netdev(dev);
5497 if (err) {
5498 dev_printk(KERN_INFO, &pci_dev->dev,
5499 "unable to register netdev: %d\n", err);
5500 goto out_error;
5501 }
5502
5503 dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5504 "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5505 dev->name,
5506 np->phy_oui,
5507 np->phyaddr,
5508 dev->dev_addr[0],
5509 dev->dev_addr[1],
5510 dev->dev_addr[2],
5511 dev->dev_addr[3],
5512 dev->dev_addr[4],
5513 dev->dev_addr[5]);
5514
5515 dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5516 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5517 dev->features & (NETIF_F_HW_CSUM | NETIF_F_SG) ?
5518 "csum " : "",
5519 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5520 "vlan " : "",
5521 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5522 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5523 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5524 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5525 np->need_linktimer ? "lnktim " : "",
5526 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5527 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5528 np->desc_ver);
5529
5530 return 0;
5531
5532 out_error:
5533 if (phystate_orig)
5534 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5535 pci_set_drvdata(pci_dev, NULL);
5536 out_freering:
5537 free_rings(dev);
5538 out_unmap:
5539 iounmap(get_hwbase(dev));
5540 out_relreg:
5541 pci_release_regions(pci_dev);
5542 out_disable:
5543 pci_disable_device(pci_dev);
5544 out_free:
5545 free_netdev(dev);
5546 out:
5547 return err;
5548 }
5549
5550 static void __devexit nv_remove(struct pci_dev *pci_dev)
5551 {
5552 struct net_device *dev = pci_get_drvdata(pci_dev);
5553 struct fe_priv *np = netdev_priv(dev);
5554 u8 __iomem *base = get_hwbase(dev);
5555
5556 unregister_netdev(dev);
5557
5558 /* special op: write back the misordered MAC address - otherwise
5559 * the next nv_probe would see a wrong address.
5560 */
5561 writel(np->orig_mac[0], base + NvRegMacAddrA);
5562 writel(np->orig_mac[1], base + NvRegMacAddrB);
5563 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5564 base + NvRegTransmitPoll);
5565
5566 /* free all structures */
5567 free_rings(dev);
5568 iounmap(get_hwbase(dev));
5569 pci_release_regions(pci_dev);
5570 pci_disable_device(pci_dev);
5571 free_netdev(dev);
5572 pci_set_drvdata(pci_dev, NULL);
5573 }
5574
5575 #ifdef CONFIG_PM
5576 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5577 {
5578 struct net_device *dev = pci_get_drvdata(pdev);
5579 struct fe_priv *np = netdev_priv(dev);
5580
5581 if (!netif_running(dev))
5582 goto out;
5583
5584 netif_device_detach(dev);
5585
5586 // Gross.
5587 nv_close(dev);
5588
5589 pci_save_state(pdev);
5590 pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5591 pci_set_power_state(pdev, pci_choose_state(pdev, state));
5592 out:
5593 return 0;
5594 }
5595
5596 static int nv_resume(struct pci_dev *pdev)
5597 {
5598 struct net_device *dev = pci_get_drvdata(pdev);
5599 int rc = 0;
5600
5601 if (!netif_running(dev))
5602 goto out;
5603
5604 netif_device_attach(dev);
5605
5606 pci_set_power_state(pdev, PCI_D0);
5607 pci_restore_state(pdev);
5608 pci_enable_wake(pdev, PCI_D0, 0);
5609
5610 rc = nv_open(dev);
5611 out:
5612 return rc;
5613 }
5614 #else
5615 #define nv_suspend NULL
5616 #define nv_resume NULL
5617 #endif /* CONFIG_PM */
5618
5619 static struct pci_device_id pci_tbl[] = {
5620 { /* nForce Ethernet Controller */
5621 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
5622 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5623 },
5624 { /* nForce2 Ethernet Controller */
5625 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
5626 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5627 },
5628 { /* nForce3 Ethernet Controller */
5629 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
5630 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5631 },
5632 { /* nForce3 Ethernet Controller */
5633 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
5634 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5635 },
5636 { /* nForce3 Ethernet Controller */
5637 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
5638 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5639 },
5640 { /* nForce3 Ethernet Controller */
5641 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
5642 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5643 },
5644 { /* nForce3 Ethernet Controller */
5645 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
5646 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5647 },
5648 { /* CK804 Ethernet Controller */
5649 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
5650 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5651 },
5652 { /* CK804 Ethernet Controller */
5653 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
5654 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5655 },
5656 { /* MCP04 Ethernet Controller */
5657 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
5658 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5659 },
5660 { /* MCP04 Ethernet Controller */
5661 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
5662 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5663 },
5664 { /* MCP51 Ethernet Controller */
5665 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
5666 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5667 },
5668 { /* MCP51 Ethernet Controller */
5669 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
5670 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5671 },
5672 { /* MCP55 Ethernet Controller */
5673 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
5674 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
5675 },
5676 { /* MCP55 Ethernet Controller */
5677 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
5678 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT,
5679 },
5680 { /* MCP61 Ethernet Controller */
5681 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
5682 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5683 },
5684 { /* MCP61 Ethernet Controller */
5685 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
5686 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5687 },
5688 { /* MCP61 Ethernet Controller */
5689 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
5690 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5691 },
5692 { /* MCP61 Ethernet Controller */
5693 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
5694 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5695 },
5696 { /* MCP65 Ethernet Controller */
5697 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5698 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_NEED_TX_LIMIT,
5699 },
5700 { /* MCP65 Ethernet Controller */
5701 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5702 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
5703 },
5704 { /* MCP65 Ethernet Controller */
5705 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5706 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
5707 },
5708 { /* MCP65 Ethernet Controller */
5709 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5710 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT,
5711 },
5712 { /* MCP67 Ethernet Controller */
5713 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5714 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5715 },
5716 { /* MCP67 Ethernet Controller */
5717 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5718 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5719 },
5720 { /* MCP67 Ethernet Controller */
5721 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5722 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5723 },
5724 { /* MCP67 Ethernet Controller */
5725 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5726 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5727 },
5728 { /* MCP73 Ethernet Controller */
5729 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
5730 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
5731 },
5732 { /* MCP73 Ethernet Controller */
5733 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
5734 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
5735 },
5736 { /* MCP73 Ethernet Controller */
5737 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
5738 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
5739 },
5740 { /* MCP73 Ethernet Controller */
5741 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
5742 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX,
5743 },
5744 { /* MCP77 Ethernet Controller */
5745 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
5746 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5747 },
5748 { /* MCP77 Ethernet Controller */
5749 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
5750 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5751 },
5752 { /* MCP77 Ethernet Controller */
5753 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
5754 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5755 },
5756 { /* MCP77 Ethernet Controller */
5757 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
5758 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5759 },
5760 { /* MCP79 Ethernet Controller */
5761 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
5762 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5763 },
5764 { /* MCP79 Ethernet Controller */
5765 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
5766 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5767 },
5768 { /* MCP79 Ethernet Controller */
5769 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
5770 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5771 },
5772 { /* MCP79 Ethernet Controller */
5773 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
5774 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT,
5775 },
5776 {0,},
5777 };
5778
5779 static struct pci_driver driver = {
5780 .name = DRV_NAME,
5781 .id_table = pci_tbl,
5782 .probe = nv_probe,
5783 .remove = __devexit_p(nv_remove),
5784 .suspend = nv_suspend,
5785 .resume = nv_resume,
5786 };
5787
5788 static int __init init_nic(void)
5789 {
5790 return pci_register_driver(&driver);
5791 }
5792
5793 static void __exit exit_nic(void)
5794 {
5795 pci_unregister_driver(&driver);
5796 }
5797
5798 module_param(max_interrupt_work, int, 0);
5799 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5800 module_param(optimization_mode, int, 0);
5801 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
5802 module_param(poll_interval, int, 0);
5803 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5804 module_param(msi, int, 0);
5805 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5806 module_param(msix, int, 0);
5807 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5808 module_param(dma_64bit, int, 0);
5809 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5810
5811 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5812 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5813 MODULE_LICENSE("GPL");
5814
5815 MODULE_DEVICE_TABLE(pci, pci_tbl);
5816
5817 module_init(init_nic);
5818 module_exit(exit_nic);
Linux kernel - Deliverables
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