2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4,5 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
92 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
93 * 0.40: 19 Jul 2005: Add support for mac address change.
94 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
96 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
97 * in the second (and later) nv_open call
98 * 0.43: 10 Aug 2005: Add support for tx checksum.
99 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
101 * 0.46: 20 Oct 2005: Add irq optimization modes.
102 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
103 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
104 * 0.49: 10 Dec 2005: Fix tso for large buffers.
105 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
106 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
107 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
110 * We suspect that on some hardware no TX done interrupts are generated.
111 * This means recovery from netif_stop_queue only happens if the hw timer
112 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
113 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
114 * If your hardware reliably generates tx done interrupts, then you can remove
115 * DEV_NEED_TIMERIRQ from the driver_data flags.
116 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
117 * superfluous timer interrupts from the nic.
119 #define FORCEDETH_VERSION "0.52"
120 #define DRV_NAME "forcedeth"
122 #include <linux/module.h>
123 #include <linux/types.h>
124 #include <linux/pci.h>
125 #include <linux/interrupt.h>
126 #include <linux/netdevice.h>
127 #include <linux/etherdevice.h>
128 #include <linux/delay.h>
129 #include <linux/spinlock.h>
130 #include <linux/ethtool.h>
131 #include <linux/timer.h>
132 #include <linux/skbuff.h>
133 #include <linux/mii.h>
134 #include <linux/random.h>
135 #include <linux/init.h>
136 #include <linux/if_vlan.h>
140 #include <asm/uaccess.h>
141 #include <asm/system.h>
144 #define dprintk printk
146 #define dprintk(x...) do { } while (0)
154 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
155 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
156 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
157 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
158 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
159 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
160 #define DEV_HAS_MSI 0x0040 /* device supports MSI */
161 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
164 NvRegIrqStatus
= 0x000,
165 #define NVREG_IRQSTAT_MIIEVENT 0x040
166 #define NVREG_IRQSTAT_MASK 0x1ff
167 NvRegIrqMask
= 0x004,
168 #define NVREG_IRQ_RX_ERROR 0x0001
169 #define NVREG_IRQ_RX 0x0002
170 #define NVREG_IRQ_RX_NOBUF 0x0004
171 #define NVREG_IRQ_TX_ERR 0x0008
172 #define NVREG_IRQ_TX_OK 0x0010
173 #define NVREG_IRQ_TIMER 0x0020
174 #define NVREG_IRQ_LINK 0x0040
175 #define NVREG_IRQ_RX_FORCED 0x0080
176 #define NVREG_IRQ_TX_FORCED 0x0100
177 #define NVREG_IRQMASK_THROUGHPUT 0x00df
178 #define NVREG_IRQMASK_CPU 0x0040
179 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
180 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
181 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
183 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
184 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
185 NVREG_IRQ_TX_FORCED))
187 NvRegUnknownSetupReg6
= 0x008,
188 #define NVREG_UNKSETUP6_VAL 3
191 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
192 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
194 NvRegPollingInterval
= 0x00c,
195 #define NVREG_POLL_DEFAULT_THROUGHPUT 970
196 #define NVREG_POLL_DEFAULT_CPU 13
197 NvRegMSIMap0
= 0x020,
198 NvRegMSIMap1
= 0x024,
199 NvRegMSIIrqMask
= 0x030,
200 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
202 #define NVREG_MISC1_HD 0x02
203 #define NVREG_MISC1_FORCE 0x3b0f3c
205 NvRegTransmitterControl
= 0x084,
206 #define NVREG_XMITCTL_START 0x01
207 NvRegTransmitterStatus
= 0x088,
208 #define NVREG_XMITSTAT_BUSY 0x01
210 NvRegPacketFilterFlags
= 0x8c,
211 #define NVREG_PFF_ALWAYS 0x7F0008
212 #define NVREG_PFF_PROMISC 0x80
213 #define NVREG_PFF_MYADDR 0x20
215 NvRegOffloadConfig
= 0x90,
216 #define NVREG_OFFLOAD_HOMEPHY 0x601
217 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
218 NvRegReceiverControl
= 0x094,
219 #define NVREG_RCVCTL_START 0x01
220 NvRegReceiverStatus
= 0x98,
221 #define NVREG_RCVSTAT_BUSY 0x01
223 NvRegRandomSeed
= 0x9c,
224 #define NVREG_RNDSEED_MASK 0x00ff
225 #define NVREG_RNDSEED_FORCE 0x7f00
226 #define NVREG_RNDSEED_FORCE2 0x2d00
227 #define NVREG_RNDSEED_FORCE3 0x7400
229 NvRegUnknownSetupReg1
= 0xA0,
230 #define NVREG_UNKSETUP1_VAL 0x16070f
231 NvRegUnknownSetupReg2
= 0xA4,
232 #define NVREG_UNKSETUP2_VAL 0x16
233 NvRegMacAddrA
= 0xA8,
234 NvRegMacAddrB
= 0xAC,
235 NvRegMulticastAddrA
= 0xB0,
236 #define NVREG_MCASTADDRA_FORCE 0x01
237 NvRegMulticastAddrB
= 0xB4,
238 NvRegMulticastMaskA
= 0xB8,
239 NvRegMulticastMaskB
= 0xBC,
241 NvRegPhyInterface
= 0xC0,
242 #define PHY_RGMII 0x10000000
244 NvRegTxRingPhysAddr
= 0x100,
245 NvRegRxRingPhysAddr
= 0x104,
246 NvRegRingSizes
= 0x108,
247 #define NVREG_RINGSZ_TXSHIFT 0
248 #define NVREG_RINGSZ_RXSHIFT 16
249 NvRegUnknownTransmitterReg
= 0x10c,
250 NvRegLinkSpeed
= 0x110,
251 #define NVREG_LINKSPEED_FORCE 0x10000
252 #define NVREG_LINKSPEED_10 1000
253 #define NVREG_LINKSPEED_100 100
254 #define NVREG_LINKSPEED_1000 50
255 #define NVREG_LINKSPEED_MASK (0xFFF)
256 NvRegUnknownSetupReg5
= 0x130,
257 #define NVREG_UNKSETUP5_BIT31 (1<<31)
258 NvRegUnknownSetupReg3
= 0x13c,
259 #define NVREG_UNKSETUP3_VAL1 0x200010
260 NvRegTxRxControl
= 0x144,
261 #define NVREG_TXRXCTL_KICK 0x0001
262 #define NVREG_TXRXCTL_BIT1 0x0002
263 #define NVREG_TXRXCTL_BIT2 0x0004
264 #define NVREG_TXRXCTL_IDLE 0x0008
265 #define NVREG_TXRXCTL_RESET 0x0010
266 #define NVREG_TXRXCTL_RXCHECK 0x0400
267 #define NVREG_TXRXCTL_DESC_1 0
268 #define NVREG_TXRXCTL_DESC_2 0x02100
269 #define NVREG_TXRXCTL_DESC_3 0x02200
270 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
271 #define NVREG_TXRXCTL_VLANINS 0x00080
272 NvRegTxRingPhysAddrHigh
= 0x148,
273 NvRegRxRingPhysAddrHigh
= 0x14C,
274 NvRegMIIStatus
= 0x180,
275 #define NVREG_MIISTAT_ERROR 0x0001
276 #define NVREG_MIISTAT_LINKCHANGE 0x0008
277 #define NVREG_MIISTAT_MASK 0x000f
278 #define NVREG_MIISTAT_MASK2 0x000f
279 NvRegUnknownSetupReg4
= 0x184,
280 #define NVREG_UNKSETUP4_VAL 8
282 NvRegAdapterControl
= 0x188,
283 #define NVREG_ADAPTCTL_START 0x02
284 #define NVREG_ADAPTCTL_LINKUP 0x04
285 #define NVREG_ADAPTCTL_PHYVALID 0x40000
286 #define NVREG_ADAPTCTL_RUNNING 0x100000
287 #define NVREG_ADAPTCTL_PHYSHIFT 24
288 NvRegMIISpeed
= 0x18c,
289 #define NVREG_MIISPEED_BIT8 (1<<8)
290 #define NVREG_MIIDELAY 5
291 NvRegMIIControl
= 0x190,
292 #define NVREG_MIICTL_INUSE 0x08000
293 #define NVREG_MIICTL_WRITE 0x00400
294 #define NVREG_MIICTL_ADDRSHIFT 5
295 NvRegMIIData
= 0x194,
296 NvRegWakeUpFlags
= 0x200,
297 #define NVREG_WAKEUPFLAGS_VAL 0x7770
298 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
299 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
300 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
301 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
302 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
303 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
304 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
305 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
306 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
307 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
309 NvRegPatternCRC
= 0x204,
310 NvRegPatternMask
= 0x208,
311 NvRegPowerCap
= 0x268,
312 #define NVREG_POWERCAP_D3SUPP (1<<30)
313 #define NVREG_POWERCAP_D2SUPP (1<<26)
314 #define NVREG_POWERCAP_D1SUPP (1<<25)
315 NvRegPowerState
= 0x26c,
316 #define NVREG_POWERSTATE_POWEREDUP 0x8000
317 #define NVREG_POWERSTATE_VALID 0x0100
318 #define NVREG_POWERSTATE_MASK 0x0003
319 #define NVREG_POWERSTATE_D0 0x0000
320 #define NVREG_POWERSTATE_D1 0x0001
321 #define NVREG_POWERSTATE_D2 0x0002
322 #define NVREG_POWERSTATE_D3 0x0003
323 NvRegVlanControl
= 0x300,
324 #define NVREG_VLANCONTROL_ENABLE 0x2000
325 NvRegMSIXMap0
= 0x3e0,
326 NvRegMSIXMap1
= 0x3e4,
327 NvRegMSIXIrqStatus
= 0x3f0,
330 /* Big endian: should work, but is untested */
336 struct ring_desc_ex
{
337 u32 PacketBufferHigh
;
343 typedef union _ring_type
{
344 struct ring_desc
* orig
;
345 struct ring_desc_ex
* ex
;
348 #define FLAG_MASK_V1 0xffff0000
349 #define FLAG_MASK_V2 0xffffc000
350 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
351 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
353 #define NV_TX_LASTPACKET (1<<16)
354 #define NV_TX_RETRYERROR (1<<19)
355 #define NV_TX_FORCED_INTERRUPT (1<<24)
356 #define NV_TX_DEFERRED (1<<26)
357 #define NV_TX_CARRIERLOST (1<<27)
358 #define NV_TX_LATECOLLISION (1<<28)
359 #define NV_TX_UNDERFLOW (1<<29)
360 #define NV_TX_ERROR (1<<30)
361 #define NV_TX_VALID (1<<31)
363 #define NV_TX2_LASTPACKET (1<<29)
364 #define NV_TX2_RETRYERROR (1<<18)
365 #define NV_TX2_FORCED_INTERRUPT (1<<30)
366 #define NV_TX2_DEFERRED (1<<25)
367 #define NV_TX2_CARRIERLOST (1<<26)
368 #define NV_TX2_LATECOLLISION (1<<27)
369 #define NV_TX2_UNDERFLOW (1<<28)
370 /* error and valid are the same for both */
371 #define NV_TX2_ERROR (1<<30)
372 #define NV_TX2_VALID (1<<31)
373 #define NV_TX2_TSO (1<<28)
374 #define NV_TX2_TSO_SHIFT 14
375 #define NV_TX2_TSO_MAX_SHIFT 14
376 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
377 #define NV_TX2_CHECKSUM_L3 (1<<27)
378 #define NV_TX2_CHECKSUM_L4 (1<<26)
380 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
382 #define NV_RX_DESCRIPTORVALID (1<<16)
383 #define NV_RX_MISSEDFRAME (1<<17)
384 #define NV_RX_SUBSTRACT1 (1<<18)
385 #define NV_RX_ERROR1 (1<<23)
386 #define NV_RX_ERROR2 (1<<24)
387 #define NV_RX_ERROR3 (1<<25)
388 #define NV_RX_ERROR4 (1<<26)
389 #define NV_RX_CRCERR (1<<27)
390 #define NV_RX_OVERFLOW (1<<28)
391 #define NV_RX_FRAMINGERR (1<<29)
392 #define NV_RX_ERROR (1<<30)
393 #define NV_RX_AVAIL (1<<31)
395 #define NV_RX2_CHECKSUMMASK (0x1C000000)
396 #define NV_RX2_CHECKSUMOK1 (0x10000000)
397 #define NV_RX2_CHECKSUMOK2 (0x14000000)
398 #define NV_RX2_CHECKSUMOK3 (0x18000000)
399 #define NV_RX2_DESCRIPTORVALID (1<<29)
400 #define NV_RX2_SUBSTRACT1 (1<<25)
401 #define NV_RX2_ERROR1 (1<<18)
402 #define NV_RX2_ERROR2 (1<<19)
403 #define NV_RX2_ERROR3 (1<<20)
404 #define NV_RX2_ERROR4 (1<<21)
405 #define NV_RX2_CRCERR (1<<22)
406 #define NV_RX2_OVERFLOW (1<<23)
407 #define NV_RX2_FRAMINGERR (1<<24)
408 /* error and avail are the same for both */
409 #define NV_RX2_ERROR (1<<30)
410 #define NV_RX2_AVAIL (1<<31)
412 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
413 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
415 /* Miscelaneous hardware related defines: */
416 #define NV_PCI_REGSZ 0x270
418 /* various timeout delays: all in usec */
419 #define NV_TXRX_RESET_DELAY 4
420 #define NV_TXSTOP_DELAY1 10
421 #define NV_TXSTOP_DELAY1MAX 500000
422 #define NV_TXSTOP_DELAY2 100
423 #define NV_RXSTOP_DELAY1 10
424 #define NV_RXSTOP_DELAY1MAX 500000
425 #define NV_RXSTOP_DELAY2 100
426 #define NV_SETUP5_DELAY 5
427 #define NV_SETUP5_DELAYMAX 50000
428 #define NV_POWERUP_DELAY 5
429 #define NV_POWERUP_DELAYMAX 5000
430 #define NV_MIIBUSY_DELAY 50
431 #define NV_MIIPHY_DELAY 10
432 #define NV_MIIPHY_DELAYMAX 10000
434 #define NV_WAKEUPPATTERNS 5
435 #define NV_WAKEUPMASKENTRIES 4
437 /* General driver defaults */
438 #define NV_WATCHDOG_TIMEO (5*HZ)
443 * If your nic mysteriously hangs then try to reduce the limits
444 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
445 * last valid ring entry. But this would be impossible to
446 * implement - probably a disassembly error.
448 #define TX_LIMIT_STOP 255
449 #define TX_LIMIT_START 254
451 /* rx/tx mac addr + type + vlan + align + slack*/
452 #define NV_RX_HEADERS (64)
453 /* even more slack. */
454 #define NV_RX_ALLOC_PAD (64)
456 /* maximum mtu size */
457 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
458 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
460 #define OOM_REFILL (1+HZ/20)
461 #define POLL_WAIT (1+HZ/100)
462 #define LINK_TIMEOUT (3*HZ)
466 * The nic supports three different descriptor types:
467 * - DESC_VER_1: Original
468 * - DESC_VER_2: support for jumbo frames.
469 * - DESC_VER_3: 64-bit format.
476 #define PHY_OUI_MARVELL 0x5043
477 #define PHY_OUI_CICADA 0x03f1
478 #define PHYID1_OUI_MASK 0x03ff
479 #define PHYID1_OUI_SHFT 6
480 #define PHYID2_OUI_MASK 0xfc00
481 #define PHYID2_OUI_SHFT 10
482 #define PHY_INIT1 0x0f000
483 #define PHY_INIT2 0x0e00
484 #define PHY_INIT3 0x01000
485 #define PHY_INIT4 0x0200
486 #define PHY_INIT5 0x0004
487 #define PHY_INIT6 0x02000
488 #define PHY_GIGABIT 0x0100
490 #define PHY_TIMEOUT 0x1
491 #define PHY_ERROR 0x2
495 #define PHY_HALF 0x100
497 /* FIXME: MII defines that should be added to <linux/mii.h> */
498 #define MII_1000BT_CR 0x09
499 #define MII_1000BT_SR 0x0a
500 #define ADVERTISE_1000FULL 0x0200
501 #define ADVERTISE_1000HALF 0x0100
502 #define LPA_1000FULL 0x0800
503 #define LPA_1000HALF 0x0400
505 /* MSI/MSI-X defines */
506 #define NV_MSI_X_MAX_VECTORS 8
507 #define NV_MSI_X_VECTORS_MASK 0x000f
508 #define NV_MSI_CAPABLE 0x0010
509 #define NV_MSI_X_CAPABLE 0x0020
510 #define NV_MSI_ENABLED 0x0040
511 #define NV_MSI_X_ENABLED 0x0080
513 #define NV_MSI_X_VECTOR_ALL 0x0
514 #define NV_MSI_X_VECTOR_RX 0x0
515 #define NV_MSI_X_VECTOR_TX 0x1
516 #define NV_MSI_X_VECTOR_OTHER 0x2
520 * All hardware access under dev->priv->lock, except the performance
522 * - rx is (pseudo-) lockless: it relies on the single-threading provided
523 * by the arch code for interrupts.
524 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
525 * needs dev->priv->lock :-(
526 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
529 /* in dev: base, irq */
534 * Locking: spin_lock(&np->lock); */
535 struct net_device_stats stats
;
543 unsigned int phy_oui
;
546 /* General data: RO fields */
547 dma_addr_t ring_addr
;
548 struct pci_dev
*pci_dev
;
557 /* rx specific fields.
558 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
561 unsigned int cur_rx
, refill_rx
;
562 struct sk_buff
*rx_skbuff
[RX_RING
];
563 dma_addr_t rx_dma
[RX_RING
];
564 unsigned int rx_buf_sz
;
565 unsigned int pkt_limit
;
566 struct timer_list oom_kick
;
567 struct timer_list nic_poll
;
570 /* media detection workaround.
571 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
574 unsigned long link_timeout
;
576 * tx specific fields.
579 unsigned int next_tx
, nic_tx
;
580 struct sk_buff
*tx_skbuff
[TX_RING
];
581 dma_addr_t tx_dma
[TX_RING
];
582 unsigned int tx_dma_len
[TX_RING
];
586 struct vlan_group
*vlangrp
;
588 /* msi/msi-x fields */
590 struct msix_entry msi_x_entry
[NV_MSI_X_MAX_VECTORS
];
594 * Maximum number of loops until we assume that a bit in the irq mask
595 * is stuck. Overridable with module param.
597 static int max_interrupt_work
= 5;
600 * Optimization can be either throuput mode or cpu mode
602 * Throughput Mode: Every tx and rx packet will generate an interrupt.
603 * CPU Mode: Interrupts are controlled by a timer.
605 #define NV_OPTIMIZATION_MODE_THROUGHPUT 0
606 #define NV_OPTIMIZATION_MODE_CPU 1
607 static int optimization_mode
= NV_OPTIMIZATION_MODE_THROUGHPUT
;
610 * Poll interval for timer irq
612 * This interval determines how frequent an interrupt is generated.
613 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
614 * Min = 0, and Max = 65535
616 static int poll_interval
= -1;
619 * Disable MSI interrupts
621 static int disable_msi
= 0;
624 * Disable MSIX interrupts
626 static int disable_msix
= 0;
628 static inline struct fe_priv
*get_nvpriv(struct net_device
*dev
)
630 return netdev_priv(dev
);
633 static inline u8 __iomem
*get_hwbase(struct net_device
*dev
)
635 return ((struct fe_priv
*)netdev_priv(dev
))->base
;
638 static inline void pci_push(u8 __iomem
*base
)
640 /* force out pending posted writes */
644 static inline u32
nv_descr_getlength(struct ring_desc
*prd
, u32 v
)
646 return le32_to_cpu(prd
->FlagLen
)
647 & ((v
== DESC_VER_1
) ? LEN_MASK_V1
: LEN_MASK_V2
);
650 static inline u32
nv_descr_getlength_ex(struct ring_desc_ex
*prd
, u32 v
)
652 return le32_to_cpu(prd
->FlagLen
) & LEN_MASK_V2
;
655 static int reg_delay(struct net_device
*dev
, int offset
, u32 mask
, u32 target
,
656 int delay
, int delaymax
, const char *msg
)
658 u8 __iomem
*base
= get_hwbase(dev
);
669 } while ((readl(base
+ offset
) & mask
) != target
);
673 #define NV_SETUP_RX_RING 0x01
674 #define NV_SETUP_TX_RING 0x02
676 static void setup_hw_rings(struct net_device
*dev
, int rxtx_flags
)
678 struct fe_priv
*np
= get_nvpriv(dev
);
679 u8 __iomem
*base
= get_hwbase(dev
);
681 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
682 if (rxtx_flags
& NV_SETUP_RX_RING
) {
683 writel((u32
) cpu_to_le64(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
685 if (rxtx_flags
& NV_SETUP_TX_RING
) {
686 writel((u32
) cpu_to_le64(np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc
)), base
+ NvRegTxRingPhysAddr
);
689 if (rxtx_flags
& NV_SETUP_RX_RING
) {
690 writel((u32
) cpu_to_le64(np
->ring_addr
), base
+ NvRegRxRingPhysAddr
);
691 writel((u32
) (cpu_to_le64(np
->ring_addr
) >> 32), base
+ NvRegRxRingPhysAddrHigh
);
693 if (rxtx_flags
& NV_SETUP_TX_RING
) {
694 writel((u32
) cpu_to_le64(np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc_ex
)), base
+ NvRegTxRingPhysAddr
);
695 writel((u32
) (cpu_to_le64(np
->ring_addr
+ RX_RING
*sizeof(struct ring_desc_ex
)) >> 32), base
+ NvRegTxRingPhysAddrHigh
);
700 #define MII_READ (-1)
701 /* mii_rw: read/write a register on the PHY.
703 * Caller must guarantee serialization
705 static int mii_rw(struct net_device
*dev
, int addr
, int miireg
, int value
)
707 u8 __iomem
*base
= get_hwbase(dev
);
711 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
713 reg
= readl(base
+ NvRegMIIControl
);
714 if (reg
& NVREG_MIICTL_INUSE
) {
715 writel(NVREG_MIICTL_INUSE
, base
+ NvRegMIIControl
);
716 udelay(NV_MIIBUSY_DELAY
);
719 reg
= (addr
<< NVREG_MIICTL_ADDRSHIFT
) | miireg
;
720 if (value
!= MII_READ
) {
721 writel(value
, base
+ NvRegMIIData
);
722 reg
|= NVREG_MIICTL_WRITE
;
724 writel(reg
, base
+ NvRegMIIControl
);
726 if (reg_delay(dev
, NvRegMIIControl
, NVREG_MIICTL_INUSE
, 0,
727 NV_MIIPHY_DELAY
, NV_MIIPHY_DELAYMAX
, NULL
)) {
728 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d timed out.\n",
729 dev
->name
, miireg
, addr
);
731 } else if (value
!= MII_READ
) {
732 /* it was a write operation - fewer failures are detectable */
733 dprintk(KERN_DEBUG
"%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
734 dev
->name
, value
, miireg
, addr
);
736 } else if (readl(base
+ NvRegMIIStatus
) & NVREG_MIISTAT_ERROR
) {
737 dprintk(KERN_DEBUG
"%s: mii_rw of reg %d at PHY %d failed.\n",
738 dev
->name
, miireg
, addr
);
741 retval
= readl(base
+ NvRegMIIData
);
742 dprintk(KERN_DEBUG
"%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
743 dev
->name
, miireg
, addr
, retval
);
749 static int phy_reset(struct net_device
*dev
)
751 struct fe_priv
*np
= netdev_priv(dev
);
753 unsigned int tries
= 0;
755 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
756 miicontrol
|= BMCR_RESET
;
757 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, miicontrol
)) {
764 /* must wait till reset is deasserted */
765 while (miicontrol
& BMCR_RESET
) {
767 miicontrol
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
768 /* FIXME: 100 tries seem excessive */
775 static int phy_init(struct net_device
*dev
)
777 struct fe_priv
*np
= get_nvpriv(dev
);
778 u8 __iomem
*base
= get_hwbase(dev
);
779 u32 phyinterface
, phy_reserved
, mii_status
, mii_control
, mii_control_1000
,reg
;
781 /* set advertise register */
782 reg
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
783 reg
|= (ADVERTISE_10HALF
|ADVERTISE_10FULL
|ADVERTISE_100HALF
|ADVERTISE_100FULL
|0x800|0x400);
784 if (mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, reg
)) {
785 printk(KERN_INFO
"%s: phy write to advertise failed.\n", pci_name(np
->pci_dev
));
789 /* get phy interface type */
790 phyinterface
= readl(base
+ NvRegPhyInterface
);
792 /* see if gigabit phy */
793 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
794 if (mii_status
& PHY_GIGABIT
) {
795 np
->gigabit
= PHY_GIGABIT
;
796 mii_control_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
797 mii_control_1000
&= ~ADVERTISE_1000HALF
;
798 if (phyinterface
& PHY_RGMII
)
799 mii_control_1000
|= ADVERTISE_1000FULL
;
801 mii_control_1000
&= ~ADVERTISE_1000FULL
;
803 if (mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, mii_control_1000
)) {
804 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
812 if (phy_reset(dev
)) {
813 printk(KERN_INFO
"%s: phy reset failed\n", pci_name(np
->pci_dev
));
817 /* phy vendor specific configuration */
818 if ((np
->phy_oui
== PHY_OUI_CICADA
) && (phyinterface
& PHY_RGMII
) ) {
819 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_RESV1
, MII_READ
);
820 phy_reserved
&= ~(PHY_INIT1
| PHY_INIT2
);
821 phy_reserved
|= (PHY_INIT3
| PHY_INIT4
);
822 if (mii_rw(dev
, np
->phyaddr
, MII_RESV1
, phy_reserved
)) {
823 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
826 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, MII_READ
);
827 phy_reserved
|= PHY_INIT5
;
828 if (mii_rw(dev
, np
->phyaddr
, MII_NCONFIG
, phy_reserved
)) {
829 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
833 if (np
->phy_oui
== PHY_OUI_CICADA
) {
834 phy_reserved
= mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, MII_READ
);
835 phy_reserved
|= PHY_INIT6
;
836 if (mii_rw(dev
, np
->phyaddr
, MII_SREVISION
, phy_reserved
)) {
837 printk(KERN_INFO
"%s: phy init failed.\n", pci_name(np
->pci_dev
));
842 /* restart auto negotiation */
843 mii_control
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
844 mii_control
|= (BMCR_ANRESTART
| BMCR_ANENABLE
);
845 if (mii_rw(dev
, np
->phyaddr
, MII_BMCR
, mii_control
)) {
852 static void nv_start_rx(struct net_device
*dev
)
854 struct fe_priv
*np
= netdev_priv(dev
);
855 u8 __iomem
*base
= get_hwbase(dev
);
857 dprintk(KERN_DEBUG
"%s: nv_start_rx\n", dev
->name
);
858 /* Already running? Stop it. */
859 if (readl(base
+ NvRegReceiverControl
) & NVREG_RCVCTL_START
) {
860 writel(0, base
+ NvRegReceiverControl
);
863 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
865 writel(NVREG_RCVCTL_START
, base
+ NvRegReceiverControl
);
866 dprintk(KERN_DEBUG
"%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
867 dev
->name
, np
->duplex
, np
->linkspeed
);
871 static void nv_stop_rx(struct net_device
*dev
)
873 u8 __iomem
*base
= get_hwbase(dev
);
875 dprintk(KERN_DEBUG
"%s: nv_stop_rx\n", dev
->name
);
876 writel(0, base
+ NvRegReceiverControl
);
877 reg_delay(dev
, NvRegReceiverStatus
, NVREG_RCVSTAT_BUSY
, 0,
878 NV_RXSTOP_DELAY1
, NV_RXSTOP_DELAY1MAX
,
879 KERN_INFO
"nv_stop_rx: ReceiverStatus remained busy");
881 udelay(NV_RXSTOP_DELAY2
);
882 writel(0, base
+ NvRegLinkSpeed
);
885 static void nv_start_tx(struct net_device
*dev
)
887 u8 __iomem
*base
= get_hwbase(dev
);
889 dprintk(KERN_DEBUG
"%s: nv_start_tx\n", dev
->name
);
890 writel(NVREG_XMITCTL_START
, base
+ NvRegTransmitterControl
);
894 static void nv_stop_tx(struct net_device
*dev
)
896 u8 __iomem
*base
= get_hwbase(dev
);
898 dprintk(KERN_DEBUG
"%s: nv_stop_tx\n", dev
->name
);
899 writel(0, base
+ NvRegTransmitterControl
);
900 reg_delay(dev
, NvRegTransmitterStatus
, NVREG_XMITSTAT_BUSY
, 0,
901 NV_TXSTOP_DELAY1
, NV_TXSTOP_DELAY1MAX
,
902 KERN_INFO
"nv_stop_tx: TransmitterStatus remained busy");
904 udelay(NV_TXSTOP_DELAY2
);
905 writel(0, base
+ NvRegUnknownTransmitterReg
);
908 static void nv_txrx_reset(struct net_device
*dev
)
910 struct fe_priv
*np
= netdev_priv(dev
);
911 u8 __iomem
*base
= get_hwbase(dev
);
913 dprintk(KERN_DEBUG
"%s: nv_txrx_reset\n", dev
->name
);
914 writel(NVREG_TXRXCTL_BIT2
| NVREG_TXRXCTL_RESET
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
916 udelay(NV_TXRX_RESET_DELAY
);
917 writel(NVREG_TXRXCTL_BIT2
| np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
922 * nv_get_stats: dev->get_stats function
923 * Get latest stats value from the nic.
924 * Called with read_lock(&dev_base_lock) held for read -
925 * only synchronized against unregister_netdevice.
927 static struct net_device_stats
*nv_get_stats(struct net_device
*dev
)
929 struct fe_priv
*np
= netdev_priv(dev
);
931 /* It seems that the nic always generates interrupts and doesn't
932 * accumulate errors internally. Thus the current values in np->stats
933 * are already up to date.
939 * nv_alloc_rx: fill rx ring entries.
940 * Return 1 if the allocations for the skbs failed and the
941 * rx engine is without Available descriptors
943 static int nv_alloc_rx(struct net_device
*dev
)
945 struct fe_priv
*np
= netdev_priv(dev
);
946 unsigned int refill_rx
= np
->refill_rx
;
949 while (np
->cur_rx
!= refill_rx
) {
952 nr
= refill_rx
% RX_RING
;
953 if (np
->rx_skbuff
[nr
] == NULL
) {
955 skb
= dev_alloc_skb(np
->rx_buf_sz
+ NV_RX_ALLOC_PAD
);
960 np
->rx_skbuff
[nr
] = skb
;
962 skb
= np
->rx_skbuff
[nr
];
964 np
->rx_dma
[nr
] = pci_map_single(np
->pci_dev
, skb
->data
,
965 skb
->end
-skb
->data
, PCI_DMA_FROMDEVICE
);
966 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
967 np
->rx_ring
.orig
[nr
].PacketBuffer
= cpu_to_le32(np
->rx_dma
[nr
]);
969 np
->rx_ring
.orig
[nr
].FlagLen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX_AVAIL
);
971 np
->rx_ring
.ex
[nr
].PacketBufferHigh
= cpu_to_le64(np
->rx_dma
[nr
]) >> 32;
972 np
->rx_ring
.ex
[nr
].PacketBufferLow
= cpu_to_le64(np
->rx_dma
[nr
]) & 0x0FFFFFFFF;
974 np
->rx_ring
.ex
[nr
].FlagLen
= cpu_to_le32(np
->rx_buf_sz
| NV_RX2_AVAIL
);
976 dprintk(KERN_DEBUG
"%s: nv_alloc_rx: Packet %d marked as Available\n",
977 dev
->name
, refill_rx
);
980 np
->refill_rx
= refill_rx
;
981 if (np
->cur_rx
- refill_rx
== RX_RING
)
986 static void nv_do_rx_refill(unsigned long data
)
988 struct net_device
*dev
= (struct net_device
*) data
;
989 struct fe_priv
*np
= netdev_priv(dev
);
992 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
993 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
994 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1))) {
995 disable_irq(dev
->irq
);
997 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
999 if (nv_alloc_rx(dev
)) {
1000 spin_lock(&np
->lock
);
1001 if (!np
->in_shutdown
)
1002 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1003 spin_unlock(&np
->lock
);
1005 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
1006 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
1007 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1))) {
1008 enable_irq(dev
->irq
);
1010 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1014 static void nv_init_rx(struct net_device
*dev
)
1016 struct fe_priv
*np
= netdev_priv(dev
);
1019 np
->cur_rx
= RX_RING
;
1021 for (i
= 0; i
< RX_RING
; i
++)
1022 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1023 np
->rx_ring
.orig
[i
].FlagLen
= 0;
1025 np
->rx_ring
.ex
[i
].FlagLen
= 0;
1028 static void nv_init_tx(struct net_device
*dev
)
1030 struct fe_priv
*np
= netdev_priv(dev
);
1033 np
->next_tx
= np
->nic_tx
= 0;
1034 for (i
= 0; i
< TX_RING
; i
++) {
1035 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1036 np
->tx_ring
.orig
[i
].FlagLen
= 0;
1038 np
->tx_ring
.ex
[i
].FlagLen
= 0;
1039 np
->tx_skbuff
[i
] = NULL
;
1044 static int nv_init_ring(struct net_device
*dev
)
1048 return nv_alloc_rx(dev
);
1051 static int nv_release_txskb(struct net_device
*dev
, unsigned int skbnr
)
1053 struct fe_priv
*np
= netdev_priv(dev
);
1055 dprintk(KERN_INFO
"%s: nv_release_txskb for skbnr %d\n",
1058 if (np
->tx_dma
[skbnr
]) {
1059 pci_unmap_page(np
->pci_dev
, np
->tx_dma
[skbnr
],
1060 np
->tx_dma_len
[skbnr
],
1062 np
->tx_dma
[skbnr
] = 0;
1065 if (np
->tx_skbuff
[skbnr
]) {
1066 dev_kfree_skb_any(np
->tx_skbuff
[skbnr
]);
1067 np
->tx_skbuff
[skbnr
] = NULL
;
1074 static void nv_drain_tx(struct net_device
*dev
)
1076 struct fe_priv
*np
= netdev_priv(dev
);
1079 for (i
= 0; i
< TX_RING
; i
++) {
1080 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1081 np
->tx_ring
.orig
[i
].FlagLen
= 0;
1083 np
->tx_ring
.ex
[i
].FlagLen
= 0;
1084 if (nv_release_txskb(dev
, i
))
1085 np
->stats
.tx_dropped
++;
1089 static void nv_drain_rx(struct net_device
*dev
)
1091 struct fe_priv
*np
= netdev_priv(dev
);
1093 for (i
= 0; i
< RX_RING
; i
++) {
1094 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1095 np
->rx_ring
.orig
[i
].FlagLen
= 0;
1097 np
->rx_ring
.ex
[i
].FlagLen
= 0;
1099 if (np
->rx_skbuff
[i
]) {
1100 pci_unmap_single(np
->pci_dev
, np
->rx_dma
[i
],
1101 np
->rx_skbuff
[i
]->end
-np
->rx_skbuff
[i
]->data
,
1102 PCI_DMA_FROMDEVICE
);
1103 dev_kfree_skb(np
->rx_skbuff
[i
]);
1104 np
->rx_skbuff
[i
] = NULL
;
1109 static void drain_ring(struct net_device
*dev
)
1116 * nv_start_xmit: dev->hard_start_xmit function
1117 * Called with dev->xmit_lock held.
1119 static int nv_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1121 struct fe_priv
*np
= netdev_priv(dev
);
1123 u32 tx_flags_extra
= (np
->desc_ver
== DESC_VER_1
? NV_TX_LASTPACKET
: NV_TX2_LASTPACKET
);
1124 unsigned int fragments
= skb_shinfo(skb
)->nr_frags
;
1125 unsigned int nr
= (np
->next_tx
- 1) % TX_RING
;
1126 unsigned int start_nr
= np
->next_tx
% TX_RING
;
1130 u32 size
= skb
->len
-skb
->data_len
;
1131 u32 entries
= (size
>> NV_TX2_TSO_MAX_SHIFT
) + ((size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
1132 u32 tx_flags_vlan
= 0;
1134 /* add fragments to entries count */
1135 for (i
= 0; i
< fragments
; i
++) {
1136 entries
+= (skb_shinfo(skb
)->frags
[i
].size
>> NV_TX2_TSO_MAX_SHIFT
) +
1137 ((skb_shinfo(skb
)->frags
[i
].size
& (NV_TX2_TSO_MAX_SIZE
-1)) ? 1 : 0);
1140 spin_lock_irq(&np
->lock
);
1142 if ((np
->next_tx
- np
->nic_tx
+ entries
- 1) > TX_LIMIT_STOP
) {
1143 spin_unlock_irq(&np
->lock
);
1144 netif_stop_queue(dev
);
1145 return NETDEV_TX_BUSY
;
1148 /* setup the header buffer */
1150 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
1151 nr
= (nr
+ 1) % TX_RING
;
1153 np
->tx_dma
[nr
] = pci_map_single(np
->pci_dev
, skb
->data
+ offset
, bcnt
,
1155 np
->tx_dma_len
[nr
] = bcnt
;
1157 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1158 np
->tx_ring
.orig
[nr
].PacketBuffer
= cpu_to_le32(np
->tx_dma
[nr
]);
1159 np
->tx_ring
.orig
[nr
].FlagLen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1161 np
->tx_ring
.ex
[nr
].PacketBufferHigh
= cpu_to_le64(np
->tx_dma
[nr
]) >> 32;
1162 np
->tx_ring
.ex
[nr
].PacketBufferLow
= cpu_to_le64(np
->tx_dma
[nr
]) & 0x0FFFFFFFF;
1163 np
->tx_ring
.ex
[nr
].FlagLen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1165 tx_flags
= np
->tx_flags
;
1170 /* setup the fragments */
1171 for (i
= 0; i
< fragments
; i
++) {
1172 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1173 u32 size
= frag
->size
;
1177 bcnt
= (size
> NV_TX2_TSO_MAX_SIZE
) ? NV_TX2_TSO_MAX_SIZE
: size
;
1178 nr
= (nr
+ 1) % TX_RING
;
1180 np
->tx_dma
[nr
] = pci_map_page(np
->pci_dev
, frag
->page
, frag
->page_offset
+offset
, bcnt
,
1182 np
->tx_dma_len
[nr
] = bcnt
;
1184 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1185 np
->tx_ring
.orig
[nr
].PacketBuffer
= cpu_to_le32(np
->tx_dma
[nr
]);
1186 np
->tx_ring
.orig
[nr
].FlagLen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1188 np
->tx_ring
.ex
[nr
].PacketBufferHigh
= cpu_to_le64(np
->tx_dma
[nr
]) >> 32;
1189 np
->tx_ring
.ex
[nr
].PacketBufferLow
= cpu_to_le64(np
->tx_dma
[nr
]) & 0x0FFFFFFFF;
1190 np
->tx_ring
.ex
[nr
].FlagLen
= cpu_to_le32((bcnt
-1) | tx_flags
);
1197 /* set last fragment flag */
1198 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1199 np
->tx_ring
.orig
[nr
].FlagLen
|= cpu_to_le32(tx_flags_extra
);
1201 np
->tx_ring
.ex
[nr
].FlagLen
|= cpu_to_le32(tx_flags_extra
);
1204 np
->tx_skbuff
[nr
] = skb
;
1207 if (skb_shinfo(skb
)->tso_size
)
1208 tx_flags_extra
= NV_TX2_TSO
| (skb_shinfo(skb
)->tso_size
<< NV_TX2_TSO_SHIFT
);
1211 tx_flags_extra
= (skb
->ip_summed
== CHECKSUM_HW
? (NV_TX2_CHECKSUM_L3
|NV_TX2_CHECKSUM_L4
) : 0);
1214 if (np
->vlangrp
&& vlan_tx_tag_present(skb
)) {
1215 tx_flags_vlan
= NV_TX3_VLAN_TAG_PRESENT
| vlan_tx_tag_get(skb
);
1219 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1220 np
->tx_ring
.orig
[start_nr
].FlagLen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
1222 np
->tx_ring
.ex
[start_nr
].TxVlan
= cpu_to_le32(tx_flags_vlan
);
1223 np
->tx_ring
.ex
[start_nr
].FlagLen
|= cpu_to_le32(tx_flags
| tx_flags_extra
);
1226 dprintk(KERN_DEBUG
"%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1227 dev
->name
, np
->next_tx
, entries
, tx_flags_extra
);
1230 for (j
=0; j
<64; j
++) {
1232 dprintk("\n%03x:", j
);
1233 dprintk(" %02x", ((unsigned char*)skb
->data
)[j
]);
1238 np
->next_tx
+= entries
;
1240 dev
->trans_start
= jiffies
;
1241 spin_unlock_irq(&np
->lock
);
1242 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
1243 pci_push(get_hwbase(dev
));
1244 return NETDEV_TX_OK
;
1248 * nv_tx_done: check for completed packets, release the skbs.
1250 * Caller must own np->lock.
1252 static void nv_tx_done(struct net_device
*dev
)
1254 struct fe_priv
*np
= netdev_priv(dev
);
1257 struct sk_buff
*skb
;
1259 while (np
->nic_tx
!= np
->next_tx
) {
1260 i
= np
->nic_tx
% TX_RING
;
1262 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
1263 Flags
= le32_to_cpu(np
->tx_ring
.orig
[i
].FlagLen
);
1265 Flags
= le32_to_cpu(np
->tx_ring
.ex
[i
].FlagLen
);
1267 dprintk(KERN_DEBUG
"%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1268 dev
->name
, np
->nic_tx
, Flags
);
1269 if (Flags
& NV_TX_VALID
)
1271 if (np
->desc_ver
== DESC_VER_1
) {
1272 if (Flags
& NV_TX_LASTPACKET
) {
1273 skb
= np
->tx_skbuff
[i
];
1274 if (Flags
& (NV_TX_RETRYERROR
|NV_TX_CARRIERLOST
|NV_TX_LATECOLLISION
|
1275 NV_TX_UNDERFLOW
|NV_TX_ERROR
)) {
1276 if (Flags
& NV_TX_UNDERFLOW
)
1277 np
->stats
.tx_fifo_errors
++;
1278 if (Flags
& NV_TX_CARRIERLOST
)
1279 np
->stats
.tx_carrier_errors
++;
1280 np
->stats
.tx_errors
++;
1282 np
->stats
.tx_packets
++;
1283 np
->stats
.tx_bytes
+= skb
->len
;
1287 if (Flags
& NV_TX2_LASTPACKET
) {
1288 skb
= np
->tx_skbuff
[i
];
1289 if (Flags
& (NV_TX2_RETRYERROR
|NV_TX2_CARRIERLOST
|NV_TX2_LATECOLLISION
|
1290 NV_TX2_UNDERFLOW
|NV_TX2_ERROR
)) {
1291 if (Flags
& NV_TX2_UNDERFLOW
)
1292 np
->stats
.tx_fifo_errors
++;
1293 if (Flags
& NV_TX2_CARRIERLOST
)
1294 np
->stats
.tx_carrier_errors
++;
1295 np
->stats
.tx_errors
++;
1297 np
->stats
.tx_packets
++;
1298 np
->stats
.tx_bytes
+= skb
->len
;
1302 nv_release_txskb(dev
, i
);
1305 if (np
->next_tx
- np
->nic_tx
< TX_LIMIT_START
)
1306 netif_wake_queue(dev
);
1310 * nv_tx_timeout: dev->tx_timeout function
1311 * Called with dev->xmit_lock held.
1313 static void nv_tx_timeout(struct net_device
*dev
)
1315 struct fe_priv
*np
= netdev_priv(dev
);
1316 u8 __iomem
*base
= get_hwbase(dev
);
1319 if (np
->msi_flags
& NV_MSI_X_ENABLED
)
1320 status
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
1322 status
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
1324 printk(KERN_INFO
"%s: Got tx_timeout. irq: %08x\n", dev
->name
, status
);
1329 printk(KERN_INFO
"%s: Ring at %lx: next %d nic %d\n",
1330 dev
->name
, (unsigned long)np
->ring_addr
,
1331 np
->next_tx
, np
->nic_tx
);
1332 printk(KERN_INFO
"%s: Dumping tx registers\n", dev
->name
);
1333 for (i
=0;i
<0x400;i
+= 32) {
1334 printk(KERN_INFO
"%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1336 readl(base
+ i
+ 0), readl(base
+ i
+ 4),
1337 readl(base
+ i
+ 8), readl(base
+ i
+ 12),
1338 readl(base
+ i
+ 16), readl(base
+ i
+ 20),
1339 readl(base
+ i
+ 24), readl(base
+ i
+ 28));
1341 printk(KERN_INFO
"%s: Dumping tx ring\n", dev
->name
);
1342 for (i
=0;i
<TX_RING
;i
+= 4) {
1343 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1344 printk(KERN_INFO
"%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1346 le32_to_cpu(np
->tx_ring
.orig
[i
].PacketBuffer
),
1347 le32_to_cpu(np
->tx_ring
.orig
[i
].FlagLen
),
1348 le32_to_cpu(np
->tx_ring
.orig
[i
+1].PacketBuffer
),
1349 le32_to_cpu(np
->tx_ring
.orig
[i
+1].FlagLen
),
1350 le32_to_cpu(np
->tx_ring
.orig
[i
+2].PacketBuffer
),
1351 le32_to_cpu(np
->tx_ring
.orig
[i
+2].FlagLen
),
1352 le32_to_cpu(np
->tx_ring
.orig
[i
+3].PacketBuffer
),
1353 le32_to_cpu(np
->tx_ring
.orig
[i
+3].FlagLen
));
1355 printk(KERN_INFO
"%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1357 le32_to_cpu(np
->tx_ring
.ex
[i
].PacketBufferHigh
),
1358 le32_to_cpu(np
->tx_ring
.ex
[i
].PacketBufferLow
),
1359 le32_to_cpu(np
->tx_ring
.ex
[i
].FlagLen
),
1360 le32_to_cpu(np
->tx_ring
.ex
[i
+1].PacketBufferHigh
),
1361 le32_to_cpu(np
->tx_ring
.ex
[i
+1].PacketBufferLow
),
1362 le32_to_cpu(np
->tx_ring
.ex
[i
+1].FlagLen
),
1363 le32_to_cpu(np
->tx_ring
.ex
[i
+2].PacketBufferHigh
),
1364 le32_to_cpu(np
->tx_ring
.ex
[i
+2].PacketBufferLow
),
1365 le32_to_cpu(np
->tx_ring
.ex
[i
+2].FlagLen
),
1366 le32_to_cpu(np
->tx_ring
.ex
[i
+3].PacketBufferHigh
),
1367 le32_to_cpu(np
->tx_ring
.ex
[i
+3].PacketBufferLow
),
1368 le32_to_cpu(np
->tx_ring
.ex
[i
+3].FlagLen
));
1373 spin_lock_irq(&np
->lock
);
1375 /* 1) stop tx engine */
1378 /* 2) check that the packets were not sent already: */
1381 /* 3) if there are dead entries: clear everything */
1382 if (np
->next_tx
!= np
->nic_tx
) {
1383 printk(KERN_DEBUG
"%s: tx_timeout: dead entries!\n", dev
->name
);
1385 np
->next_tx
= np
->nic_tx
= 0;
1386 setup_hw_rings(dev
, NV_SETUP_TX_RING
);
1387 netif_wake_queue(dev
);
1390 /* 4) restart tx engine */
1392 spin_unlock_irq(&np
->lock
);
1396 * Called when the nic notices a mismatch between the actual data len on the
1397 * wire and the len indicated in the 802 header
1399 static int nv_getlen(struct net_device
*dev
, void *packet
, int datalen
)
1401 int hdrlen
; /* length of the 802 header */
1402 int protolen
; /* length as stored in the proto field */
1404 /* 1) calculate len according to header */
1405 if ( ((struct vlan_ethhdr
*)packet
)->h_vlan_proto
== __constant_htons(ETH_P_8021Q
)) {
1406 protolen
= ntohs( ((struct vlan_ethhdr
*)packet
)->h_vlan_encapsulated_proto
);
1409 protolen
= ntohs( ((struct ethhdr
*)packet
)->h_proto
);
1412 dprintk(KERN_DEBUG
"%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1413 dev
->name
, datalen
, protolen
, hdrlen
);
1414 if (protolen
> ETH_DATA_LEN
)
1415 return datalen
; /* Value in proto field not a len, no checks possible */
1418 /* consistency checks: */
1419 if (datalen
> ETH_ZLEN
) {
1420 if (datalen
>= protolen
) {
1421 /* more data on wire than in 802 header, trim of
1424 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
1425 dev
->name
, protolen
);
1428 /* less data on wire than mentioned in header.
1429 * Discard the packet.
1431 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding long packet.\n",
1436 /* short packet. Accept only if 802 values are also short */
1437 if (protolen
> ETH_ZLEN
) {
1438 dprintk(KERN_DEBUG
"%s: nv_getlen: discarding short packet.\n",
1442 dprintk(KERN_DEBUG
"%s: nv_getlen: accepting %d bytes.\n",
1443 dev
->name
, datalen
);
1448 static void nv_rx_process(struct net_device
*dev
)
1450 struct fe_priv
*np
= netdev_priv(dev
);
1456 struct sk_buff
*skb
;
1459 if (np
->cur_rx
- np
->refill_rx
>= RX_RING
)
1460 break; /* we scanned the whole ring - do not continue */
1462 i
= np
->cur_rx
% RX_RING
;
1463 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
1464 Flags
= le32_to_cpu(np
->rx_ring
.orig
[i
].FlagLen
);
1465 len
= nv_descr_getlength(&np
->rx_ring
.orig
[i
], np
->desc_ver
);
1467 Flags
= le32_to_cpu(np
->rx_ring
.ex
[i
].FlagLen
);
1468 len
= nv_descr_getlength_ex(&np
->rx_ring
.ex
[i
], np
->desc_ver
);
1469 vlanflags
= le32_to_cpu(np
->rx_ring
.ex
[i
].PacketBufferLow
);
1472 dprintk(KERN_DEBUG
"%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1473 dev
->name
, np
->cur_rx
, Flags
);
1475 if (Flags
& NV_RX_AVAIL
)
1476 break; /* still owned by hardware, */
1479 * the packet is for us - immediately tear down the pci mapping.
1480 * TODO: check if a prefetch of the first cacheline improves
1483 pci_unmap_single(np
->pci_dev
, np
->rx_dma
[i
],
1484 np
->rx_skbuff
[i
]->end
-np
->rx_skbuff
[i
]->data
,
1485 PCI_DMA_FROMDEVICE
);
1489 dprintk(KERN_DEBUG
"Dumping packet (flags 0x%x).",Flags
);
1490 for (j
=0; j
<64; j
++) {
1492 dprintk("\n%03x:", j
);
1493 dprintk(" %02x", ((unsigned char*)np
->rx_skbuff
[i
]->data
)[j
]);
1497 /* look at what we actually got: */
1498 if (np
->desc_ver
== DESC_VER_1
) {
1499 if (!(Flags
& NV_RX_DESCRIPTORVALID
))
1502 if (Flags
& NV_RX_ERROR
) {
1503 if (Flags
& NV_RX_MISSEDFRAME
) {
1504 np
->stats
.rx_missed_errors
++;
1505 np
->stats
.rx_errors
++;
1508 if (Flags
& (NV_RX_ERROR1
|NV_RX_ERROR2
|NV_RX_ERROR3
)) {
1509 np
->stats
.rx_errors
++;
1512 if (Flags
& NV_RX_CRCERR
) {
1513 np
->stats
.rx_crc_errors
++;
1514 np
->stats
.rx_errors
++;
1517 if (Flags
& NV_RX_OVERFLOW
) {
1518 np
->stats
.rx_over_errors
++;
1519 np
->stats
.rx_errors
++;
1522 if (Flags
& NV_RX_ERROR4
) {
1523 len
= nv_getlen(dev
, np
->rx_skbuff
[i
]->data
, len
);
1525 np
->stats
.rx_errors
++;
1529 /* framing errors are soft errors. */
1530 if (Flags
& NV_RX_FRAMINGERR
) {
1531 if (Flags
& NV_RX_SUBSTRACT1
) {
1537 if (!(Flags
& NV_RX2_DESCRIPTORVALID
))
1540 if (Flags
& NV_RX2_ERROR
) {
1541 if (Flags
& (NV_RX2_ERROR1
|NV_RX2_ERROR2
|NV_RX2_ERROR3
)) {
1542 np
->stats
.rx_errors
++;
1545 if (Flags
& NV_RX2_CRCERR
) {
1546 np
->stats
.rx_crc_errors
++;
1547 np
->stats
.rx_errors
++;
1550 if (Flags
& NV_RX2_OVERFLOW
) {
1551 np
->stats
.rx_over_errors
++;
1552 np
->stats
.rx_errors
++;
1555 if (Flags
& NV_RX2_ERROR4
) {
1556 len
= nv_getlen(dev
, np
->rx_skbuff
[i
]->data
, len
);
1558 np
->stats
.rx_errors
++;
1562 /* framing errors are soft errors */
1563 if (Flags
& NV_RX2_FRAMINGERR
) {
1564 if (Flags
& NV_RX2_SUBSTRACT1
) {
1569 Flags
&= NV_RX2_CHECKSUMMASK
;
1570 if (Flags
== NV_RX2_CHECKSUMOK1
||
1571 Flags
== NV_RX2_CHECKSUMOK2
||
1572 Flags
== NV_RX2_CHECKSUMOK3
) {
1573 dprintk(KERN_DEBUG
"%s: hw checksum hit!.\n", dev
->name
);
1574 np
->rx_skbuff
[i
]->ip_summed
= CHECKSUM_UNNECESSARY
;
1576 dprintk(KERN_DEBUG
"%s: hwchecksum miss!.\n", dev
->name
);
1579 /* got a valid packet - forward it to the network core */
1580 skb
= np
->rx_skbuff
[i
];
1581 np
->rx_skbuff
[i
] = NULL
;
1584 skb
->protocol
= eth_type_trans(skb
, dev
);
1585 dprintk(KERN_DEBUG
"%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1586 dev
->name
, np
->cur_rx
, len
, skb
->protocol
);
1587 if (np
->vlangrp
&& (vlanflags
& NV_RX3_VLAN_TAG_PRESENT
)) {
1588 vlan_hwaccel_rx(skb
, np
->vlangrp
, vlanflags
& NV_RX3_VLAN_TAG_MASK
);
1592 dev
->last_rx
= jiffies
;
1593 np
->stats
.rx_packets
++;
1594 np
->stats
.rx_bytes
+= len
;
1600 static void set_bufsize(struct net_device
*dev
)
1602 struct fe_priv
*np
= netdev_priv(dev
);
1604 if (dev
->mtu
<= ETH_DATA_LEN
)
1605 np
->rx_buf_sz
= ETH_DATA_LEN
+ NV_RX_HEADERS
;
1607 np
->rx_buf_sz
= dev
->mtu
+ NV_RX_HEADERS
;
1611 * nv_change_mtu: dev->change_mtu function
1612 * Called with dev_base_lock held for read.
1614 static int nv_change_mtu(struct net_device
*dev
, int new_mtu
)
1616 struct fe_priv
*np
= netdev_priv(dev
);
1619 if (new_mtu
< 64 || new_mtu
> np
->pkt_limit
)
1625 /* return early if the buffer sizes will not change */
1626 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
1628 if (old_mtu
== new_mtu
)
1631 /* synchronized against open : rtnl_lock() held by caller */
1632 if (netif_running(dev
)) {
1633 u8 __iomem
*base
= get_hwbase(dev
);
1635 * It seems that the nic preloads valid ring entries into an
1636 * internal buffer. The procedure for flushing everything is
1637 * guessed, there is probably a simpler approach.
1638 * Changing the MTU is a rare event, it shouldn't matter.
1640 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
1641 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
1642 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1))) {
1643 disable_irq(dev
->irq
);
1645 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1646 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1647 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1649 spin_lock_bh(&dev
->xmit_lock
);
1650 spin_lock(&np
->lock
);
1655 /* drain rx queue */
1658 /* reinit driver view of the rx queue */
1661 /* alloc new rx buffers */
1663 if (nv_alloc_rx(dev
)) {
1664 if (!np
->in_shutdown
)
1665 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
1667 /* reinit nic view of the rx queue */
1668 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
1669 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
1670 writel( ((RX_RING
-1) << NVREG_RINGSZ_RXSHIFT
) + ((TX_RING
-1) << NVREG_RINGSZ_TXSHIFT
),
1671 base
+ NvRegRingSizes
);
1673 writel(NVREG_TXRXCTL_KICK
|np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
1676 /* restart rx engine */
1679 spin_unlock(&np
->lock
);
1680 spin_unlock_bh(&dev
->xmit_lock
);
1681 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
1682 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
1683 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1))) {
1684 enable_irq(dev
->irq
);
1686 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
1687 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
1688 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
1694 static void nv_copy_mac_to_hw(struct net_device
*dev
)
1696 u8 __iomem
*base
= get_hwbase(dev
);
1699 mac
[0] = (dev
->dev_addr
[0] << 0) + (dev
->dev_addr
[1] << 8) +
1700 (dev
->dev_addr
[2] << 16) + (dev
->dev_addr
[3] << 24);
1701 mac
[1] = (dev
->dev_addr
[4] << 0) + (dev
->dev_addr
[5] << 8);
1703 writel(mac
[0], base
+ NvRegMacAddrA
);
1704 writel(mac
[1], base
+ NvRegMacAddrB
);
1708 * nv_set_mac_address: dev->set_mac_address function
1709 * Called with rtnl_lock() held.
1711 static int nv_set_mac_address(struct net_device
*dev
, void *addr
)
1713 struct fe_priv
*np
= netdev_priv(dev
);
1714 struct sockaddr
*macaddr
= (struct sockaddr
*)addr
;
1716 if(!is_valid_ether_addr(macaddr
->sa_data
))
1717 return -EADDRNOTAVAIL
;
1719 /* synchronized against open : rtnl_lock() held by caller */
1720 memcpy(dev
->dev_addr
, macaddr
->sa_data
, ETH_ALEN
);
1722 if (netif_running(dev
)) {
1723 spin_lock_bh(&dev
->xmit_lock
);
1724 spin_lock_irq(&np
->lock
);
1726 /* stop rx engine */
1729 /* set mac address */
1730 nv_copy_mac_to_hw(dev
);
1732 /* restart rx engine */
1734 spin_unlock_irq(&np
->lock
);
1735 spin_unlock_bh(&dev
->xmit_lock
);
1737 nv_copy_mac_to_hw(dev
);
1743 * nv_set_multicast: dev->set_multicast function
1744 * Called with dev->xmit_lock held.
1746 static void nv_set_multicast(struct net_device
*dev
)
1748 struct fe_priv
*np
= netdev_priv(dev
);
1749 u8 __iomem
*base
= get_hwbase(dev
);
1754 memset(addr
, 0, sizeof(addr
));
1755 memset(mask
, 0, sizeof(mask
));
1757 if (dev
->flags
& IFF_PROMISC
) {
1758 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n", dev
->name
);
1759 pff
= NVREG_PFF_PROMISC
;
1761 pff
= NVREG_PFF_MYADDR
;
1763 if (dev
->flags
& IFF_ALLMULTI
|| dev
->mc_list
) {
1767 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0xffffffff;
1768 if (dev
->flags
& IFF_ALLMULTI
) {
1769 alwaysOn
[0] = alwaysOn
[1] = alwaysOff
[0] = alwaysOff
[1] = 0;
1771 struct dev_mc_list
*walk
;
1773 walk
= dev
->mc_list
;
1774 while (walk
!= NULL
) {
1776 a
= le32_to_cpu(*(u32
*) walk
->dmi_addr
);
1777 b
= le16_to_cpu(*(u16
*) (&walk
->dmi_addr
[4]));
1785 addr
[0] = alwaysOn
[0];
1786 addr
[1] = alwaysOn
[1];
1787 mask
[0] = alwaysOn
[0] | alwaysOff
[0];
1788 mask
[1] = alwaysOn
[1] | alwaysOff
[1];
1791 addr
[0] |= NVREG_MCASTADDRA_FORCE
;
1792 pff
|= NVREG_PFF_ALWAYS
;
1793 spin_lock_irq(&np
->lock
);
1795 writel(addr
[0], base
+ NvRegMulticastAddrA
);
1796 writel(addr
[1], base
+ NvRegMulticastAddrB
);
1797 writel(mask
[0], base
+ NvRegMulticastMaskA
);
1798 writel(mask
[1], base
+ NvRegMulticastMaskB
);
1799 writel(pff
, base
+ NvRegPacketFilterFlags
);
1800 dprintk(KERN_INFO
"%s: reconfiguration for multicast lists.\n",
1803 spin_unlock_irq(&np
->lock
);
1807 * nv_update_linkspeed: Setup the MAC according to the link partner
1808 * @dev: Network device to be configured
1810 * The function queries the PHY and checks if there is a link partner.
1811 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
1812 * set to 10 MBit HD.
1814 * The function returns 0 if there is no link partner and 1 if there is
1815 * a good link partner.
1817 static int nv_update_linkspeed(struct net_device
*dev
)
1819 struct fe_priv
*np
= netdev_priv(dev
);
1820 u8 __iomem
*base
= get_hwbase(dev
);
1822 int newls
= np
->linkspeed
;
1823 int newdup
= np
->duplex
;
1826 u32 control_1000
, status_1000
, phyreg
;
1828 /* BMSR_LSTATUS is latched, read it twice:
1829 * we want the current value.
1831 mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1832 mii_status
= mii_rw(dev
, np
->phyaddr
, MII_BMSR
, MII_READ
);
1834 if (!(mii_status
& BMSR_LSTATUS
)) {
1835 dprintk(KERN_DEBUG
"%s: no link detected by phy - falling back to 10HD.\n",
1837 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1843 if (np
->autoneg
== 0) {
1844 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1845 dev
->name
, np
->fixed_mode
);
1846 if (np
->fixed_mode
& LPA_100FULL
) {
1847 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1849 } else if (np
->fixed_mode
& LPA_100HALF
) {
1850 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1852 } else if (np
->fixed_mode
& LPA_10FULL
) {
1853 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1856 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1862 /* check auto negotiation is complete */
1863 if (!(mii_status
& BMSR_ANEGCOMPLETE
)) {
1864 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1865 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1868 dprintk(KERN_DEBUG
"%s: autoneg not completed - falling back to 10HD.\n", dev
->name
);
1873 if (np
->gigabit
== PHY_GIGABIT
) {
1874 control_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
1875 status_1000
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_SR
, MII_READ
);
1877 if ((control_1000
& ADVERTISE_1000FULL
) &&
1878 (status_1000
& LPA_1000FULL
)) {
1879 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: GBit ethernet detected.\n",
1881 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_1000
;
1887 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
1888 lpa
= mii_rw(dev
, np
->phyaddr
, MII_LPA
, MII_READ
);
1889 dprintk(KERN_DEBUG
"%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1890 dev
->name
, adv
, lpa
);
1892 /* FIXME: handle parallel detection properly */
1894 if (lpa
& LPA_100FULL
) {
1895 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1897 } else if (lpa
& LPA_100HALF
) {
1898 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_100
;
1900 } else if (lpa
& LPA_10FULL
) {
1901 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1903 } else if (lpa
& LPA_10HALF
) {
1904 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1907 dprintk(KERN_DEBUG
"%s: bad ability %04x - falling back to 10HD.\n", dev
->name
, lpa
);
1908 newls
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
1913 if (np
->duplex
== newdup
&& np
->linkspeed
== newls
)
1916 dprintk(KERN_INFO
"%s: changing link setting from %d/%d to %d/%d.\n",
1917 dev
->name
, np
->linkspeed
, np
->duplex
, newls
, newdup
);
1919 np
->duplex
= newdup
;
1920 np
->linkspeed
= newls
;
1922 if (np
->gigabit
== PHY_GIGABIT
) {
1923 phyreg
= readl(base
+ NvRegRandomSeed
);
1924 phyreg
&= ~(0x3FF00);
1925 if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_10
)
1926 phyreg
|= NVREG_RNDSEED_FORCE3
;
1927 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_100
)
1928 phyreg
|= NVREG_RNDSEED_FORCE2
;
1929 else if ((np
->linkspeed
& 0xFFF) == NVREG_LINKSPEED_1000
)
1930 phyreg
|= NVREG_RNDSEED_FORCE
;
1931 writel(phyreg
, base
+ NvRegRandomSeed
);
1934 phyreg
= readl(base
+ NvRegPhyInterface
);
1935 phyreg
&= ~(PHY_HALF
|PHY_100
|PHY_1000
);
1936 if (np
->duplex
== 0)
1938 if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_100
)
1940 else if ((np
->linkspeed
& NVREG_LINKSPEED_MASK
) == NVREG_LINKSPEED_1000
)
1942 writel(phyreg
, base
+ NvRegPhyInterface
);
1944 writel(NVREG_MISC1_FORCE
| ( np
->duplex
? 0 : NVREG_MISC1_HD
),
1947 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
1953 static void nv_linkchange(struct net_device
*dev
)
1955 if (nv_update_linkspeed(dev
)) {
1956 if (!netif_carrier_ok(dev
)) {
1957 netif_carrier_on(dev
);
1958 printk(KERN_INFO
"%s: link up.\n", dev
->name
);
1962 if (netif_carrier_ok(dev
)) {
1963 netif_carrier_off(dev
);
1964 printk(KERN_INFO
"%s: link down.\n", dev
->name
);
1970 static void nv_link_irq(struct net_device
*dev
)
1972 u8 __iomem
*base
= get_hwbase(dev
);
1975 miistat
= readl(base
+ NvRegMIIStatus
);
1976 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
1977 dprintk(KERN_INFO
"%s: link change irq, status 0x%x.\n", dev
->name
, miistat
);
1979 if (miistat
& (NVREG_MIISTAT_LINKCHANGE
))
1981 dprintk(KERN_DEBUG
"%s: link change notification done.\n", dev
->name
);
1984 static irqreturn_t
nv_nic_irq(int foo
, void *data
, struct pt_regs
*regs
)
1986 struct net_device
*dev
= (struct net_device
*) data
;
1987 struct fe_priv
*np
= netdev_priv(dev
);
1988 u8 __iomem
*base
= get_hwbase(dev
);
1992 dprintk(KERN_DEBUG
"%s: nv_nic_irq\n", dev
->name
);
1995 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
)) {
1996 events
= readl(base
+ NvRegIrqStatus
) & NVREG_IRQSTAT_MASK
;
1997 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
1999 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQSTAT_MASK
;
2000 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegMSIXIrqStatus
);
2003 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
2004 if (!(events
& np
->irqmask
))
2007 spin_lock(&np
->lock
);
2009 spin_unlock(&np
->lock
);
2012 if (nv_alloc_rx(dev
)) {
2013 spin_lock(&np
->lock
);
2014 if (!np
->in_shutdown
)
2015 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2016 spin_unlock(&np
->lock
);
2019 if (events
& NVREG_IRQ_LINK
) {
2020 spin_lock(&np
->lock
);
2022 spin_unlock(&np
->lock
);
2024 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
2025 spin_lock(&np
->lock
);
2027 spin_unlock(&np
->lock
);
2028 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
2030 if (events
& (NVREG_IRQ_TX_ERR
)) {
2031 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
2034 if (events
& (NVREG_IRQ_UNKNOWN
)) {
2035 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
2038 if (i
> max_interrupt_work
) {
2039 spin_lock(&np
->lock
);
2040 /* disable interrupts on the nic */
2041 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
))
2042 writel(0, base
+ NvRegIrqMask
);
2044 writel(np
->irqmask
, base
+ NvRegIrqMask
);
2047 if (!np
->in_shutdown
) {
2048 np
->nic_poll_irq
= np
->irqmask
;
2049 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2051 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq.\n", dev
->name
, i
);
2052 spin_unlock(&np
->lock
);
2057 dprintk(KERN_DEBUG
"%s: nv_nic_irq completed\n", dev
->name
);
2059 return IRQ_RETVAL(i
);
2062 static irqreturn_t
nv_nic_irq_tx(int foo
, void *data
, struct pt_regs
*regs
)
2064 struct net_device
*dev
= (struct net_device
*) data
;
2065 struct fe_priv
*np
= netdev_priv(dev
);
2066 u8 __iomem
*base
= get_hwbase(dev
);
2070 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx\n", dev
->name
);
2073 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_TX_ALL
;
2074 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegMSIXIrqStatus
);
2076 dprintk(KERN_DEBUG
"%s: tx irq: %08x\n", dev
->name
, events
);
2077 if (!(events
& np
->irqmask
))
2080 spin_lock(&np
->lock
);
2082 spin_unlock(&np
->lock
);
2084 if (events
& (NVREG_IRQ_TX_ERR
)) {
2085 dprintk(KERN_DEBUG
"%s: received irq with events 0x%x. Probably TX fail.\n",
2088 if (i
> max_interrupt_work
) {
2089 spin_lock(&np
->lock
);
2090 /* disable interrupts on the nic */
2091 writel(NVREG_IRQ_TX_ALL
, base
+ NvRegIrqMask
);
2094 if (!np
->in_shutdown
) {
2095 np
->nic_poll_irq
|= NVREG_IRQ_TX_ALL
;
2096 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2098 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev
->name
, i
);
2099 spin_unlock(&np
->lock
);
2104 dprintk(KERN_DEBUG
"%s: nv_nic_irq_tx completed\n", dev
->name
);
2106 return IRQ_RETVAL(i
);
2109 static irqreturn_t
nv_nic_irq_rx(int foo
, void *data
, struct pt_regs
*regs
)
2111 struct net_device
*dev
= (struct net_device
*) data
;
2112 struct fe_priv
*np
= netdev_priv(dev
);
2113 u8 __iomem
*base
= get_hwbase(dev
);
2117 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx\n", dev
->name
);
2120 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_RX_ALL
;
2121 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegMSIXIrqStatus
);
2123 dprintk(KERN_DEBUG
"%s: rx irq: %08x\n", dev
->name
, events
);
2124 if (!(events
& np
->irqmask
))
2128 if (nv_alloc_rx(dev
)) {
2129 spin_lock(&np
->lock
);
2130 if (!np
->in_shutdown
)
2131 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2132 spin_unlock(&np
->lock
);
2135 if (i
> max_interrupt_work
) {
2136 spin_lock(&np
->lock
);
2137 /* disable interrupts on the nic */
2138 writel(NVREG_IRQ_RX_ALL
, base
+ NvRegIrqMask
);
2141 if (!np
->in_shutdown
) {
2142 np
->nic_poll_irq
|= NVREG_IRQ_RX_ALL
;
2143 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2145 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev
->name
, i
);
2146 spin_unlock(&np
->lock
);
2151 dprintk(KERN_DEBUG
"%s: nv_nic_irq_rx completed\n", dev
->name
);
2153 return IRQ_RETVAL(i
);
2156 static irqreturn_t
nv_nic_irq_other(int foo
, void *data
, struct pt_regs
*regs
)
2158 struct net_device
*dev
= (struct net_device
*) data
;
2159 struct fe_priv
*np
= netdev_priv(dev
);
2160 u8 __iomem
*base
= get_hwbase(dev
);
2164 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other\n", dev
->name
);
2167 events
= readl(base
+ NvRegMSIXIrqStatus
) & NVREG_IRQ_OTHER
;
2168 writel(NVREG_IRQ_OTHER
, base
+ NvRegMSIXIrqStatus
);
2170 dprintk(KERN_DEBUG
"%s: irq: %08x\n", dev
->name
, events
);
2171 if (!(events
& np
->irqmask
))
2174 if (events
& NVREG_IRQ_LINK
) {
2175 spin_lock(&np
->lock
);
2177 spin_unlock(&np
->lock
);
2179 if (np
->need_linktimer
&& time_after(jiffies
, np
->link_timeout
)) {
2180 spin_lock(&np
->lock
);
2182 spin_unlock(&np
->lock
);
2183 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
2185 if (events
& (NVREG_IRQ_UNKNOWN
)) {
2186 printk(KERN_DEBUG
"%s: received irq with unknown events 0x%x. Please report\n",
2189 if (i
> max_interrupt_work
) {
2190 spin_lock(&np
->lock
);
2191 /* disable interrupts on the nic */
2192 writel(NVREG_IRQ_OTHER
, base
+ NvRegIrqMask
);
2195 if (!np
->in_shutdown
) {
2196 np
->nic_poll_irq
|= NVREG_IRQ_OTHER
;
2197 mod_timer(&np
->nic_poll
, jiffies
+ POLL_WAIT
);
2199 printk(KERN_DEBUG
"%s: too many iterations (%d) in nv_nic_irq_other.\n", dev
->name
, i
);
2200 spin_unlock(&np
->lock
);
2205 dprintk(KERN_DEBUG
"%s: nv_nic_irq_other completed\n", dev
->name
);
2207 return IRQ_RETVAL(i
);
2210 static void nv_do_nic_poll(unsigned long data
)
2212 struct net_device
*dev
= (struct net_device
*) data
;
2213 struct fe_priv
*np
= netdev_priv(dev
);
2214 u8 __iomem
*base
= get_hwbase(dev
);
2218 * First disable irq(s) and then
2219 * reenable interrupts on the nic, we have to do this before calling
2220 * nv_nic_irq because that may decide to do otherwise
2223 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
2224 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
2225 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1))) {
2226 disable_irq(dev
->irq
);
2229 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
2230 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
2231 mask
|= NVREG_IRQ_RX_ALL
;
2233 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
2234 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
2235 mask
|= NVREG_IRQ_TX_ALL
;
2237 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
2238 disable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
2239 mask
|= NVREG_IRQ_OTHER
;
2242 np
->nic_poll_irq
= 0;
2244 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2246 writel(mask
, base
+ NvRegIrqMask
);
2249 if (!(np
->msi_flags
& NV_MSI_X_ENABLED
) ||
2250 ((np
->msi_flags
& NV_MSI_X_ENABLED
) &&
2251 ((np
->msi_flags
& NV_MSI_X_VECTORS_MASK
) == 0x1))) {
2252 nv_nic_irq((int) 0, (void *) data
, (struct pt_regs
*) NULL
);
2253 enable_irq(dev
->irq
);
2255 if (np
->nic_poll_irq
& NVREG_IRQ_RX_ALL
) {
2256 nv_nic_irq_rx((int) 0, (void *) data
, (struct pt_regs
*) NULL
);
2257 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
);
2259 if (np
->nic_poll_irq
& NVREG_IRQ_TX_ALL
) {
2260 nv_nic_irq_tx((int) 0, (void *) data
, (struct pt_regs
*) NULL
);
2261 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
);
2263 if (np
->nic_poll_irq
& NVREG_IRQ_OTHER
) {
2264 nv_nic_irq_other((int) 0, (void *) data
, (struct pt_regs
*) NULL
);
2265 enable_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
);
2270 #ifdef CONFIG_NET_POLL_CONTROLLER
2271 static void nv_poll_controller(struct net_device
*dev
)
2273 nv_do_nic_poll((unsigned long) dev
);
2277 static void nv_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
2279 struct fe_priv
*np
= netdev_priv(dev
);
2280 strcpy(info
->driver
, "forcedeth");
2281 strcpy(info
->version
, FORCEDETH_VERSION
);
2282 strcpy(info
->bus_info
, pci_name(np
->pci_dev
));
2285 static void nv_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
2287 struct fe_priv
*np
= netdev_priv(dev
);
2288 wolinfo
->supported
= WAKE_MAGIC
;
2290 spin_lock_irq(&np
->lock
);
2292 wolinfo
->wolopts
= WAKE_MAGIC
;
2293 spin_unlock_irq(&np
->lock
);
2296 static int nv_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wolinfo
)
2298 struct fe_priv
*np
= netdev_priv(dev
);
2299 u8 __iomem
*base
= get_hwbase(dev
);
2301 spin_lock_irq(&np
->lock
);
2302 if (wolinfo
->wolopts
== 0) {
2303 writel(0, base
+ NvRegWakeUpFlags
);
2306 if (wolinfo
->wolopts
& WAKE_MAGIC
) {
2307 writel(NVREG_WAKEUPFLAGS_ENABLE
, base
+ NvRegWakeUpFlags
);
2310 spin_unlock_irq(&np
->lock
);
2314 static int nv_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2316 struct fe_priv
*np
= netdev_priv(dev
);
2319 spin_lock_irq(&np
->lock
);
2320 ecmd
->port
= PORT_MII
;
2321 if (!netif_running(dev
)) {
2322 /* We do not track link speed / duplex setting if the
2323 * interface is disabled. Force a link check */
2324 nv_update_linkspeed(dev
);
2326 switch(np
->linkspeed
& (NVREG_LINKSPEED_MASK
)) {
2327 case NVREG_LINKSPEED_10
:
2328 ecmd
->speed
= SPEED_10
;
2330 case NVREG_LINKSPEED_100
:
2331 ecmd
->speed
= SPEED_100
;
2333 case NVREG_LINKSPEED_1000
:
2334 ecmd
->speed
= SPEED_1000
;
2337 ecmd
->duplex
= DUPLEX_HALF
;
2339 ecmd
->duplex
= DUPLEX_FULL
;
2341 ecmd
->autoneg
= np
->autoneg
;
2343 ecmd
->advertising
= ADVERTISED_MII
;
2345 ecmd
->advertising
|= ADVERTISED_Autoneg
;
2346 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
2348 adv
= np
->fixed_mode
;
2350 if (adv
& ADVERTISE_10HALF
)
2351 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
2352 if (adv
& ADVERTISE_10FULL
)
2353 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
2354 if (adv
& ADVERTISE_100HALF
)
2355 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
2356 if (adv
& ADVERTISE_100FULL
)
2357 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
2358 if (np
->autoneg
&& np
->gigabit
== PHY_GIGABIT
) {
2359 adv
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
2360 if (adv
& ADVERTISE_1000FULL
)
2361 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
2364 ecmd
->supported
= (SUPPORTED_Autoneg
|
2365 SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full
|
2366 SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full
|
2368 if (np
->gigabit
== PHY_GIGABIT
)
2369 ecmd
->supported
|= SUPPORTED_1000baseT_Full
;
2371 ecmd
->phy_address
= np
->phyaddr
;
2372 ecmd
->transceiver
= XCVR_EXTERNAL
;
2374 /* ignore maxtxpkt, maxrxpkt for now */
2375 spin_unlock_irq(&np
->lock
);
2379 static int nv_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2381 struct fe_priv
*np
= netdev_priv(dev
);
2383 if (ecmd
->port
!= PORT_MII
)
2385 if (ecmd
->transceiver
!= XCVR_EXTERNAL
)
2387 if (ecmd
->phy_address
!= np
->phyaddr
) {
2388 /* TODO: support switching between multiple phys. Should be
2389 * trivial, but not enabled due to lack of test hardware. */
2392 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2395 mask
= ADVERTISED_10baseT_Half
| ADVERTISED_10baseT_Full
|
2396 ADVERTISED_100baseT_Half
| ADVERTISED_100baseT_Full
;
2397 if (np
->gigabit
== PHY_GIGABIT
)
2398 mask
|= ADVERTISED_1000baseT_Full
;
2400 if ((ecmd
->advertising
& mask
) == 0)
2403 } else if (ecmd
->autoneg
== AUTONEG_DISABLE
) {
2404 /* Note: autonegotiation disable, speed 1000 intentionally
2405 * forbidden - noone should need that. */
2407 if (ecmd
->speed
!= SPEED_10
&& ecmd
->speed
!= SPEED_100
)
2409 if (ecmd
->duplex
!= DUPLEX_HALF
&& ecmd
->duplex
!= DUPLEX_FULL
)
2415 spin_lock_irq(&np
->lock
);
2416 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2421 /* advertise only what has been requested */
2422 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
2423 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
);
2424 if (ecmd
->advertising
& ADVERTISED_10baseT_Half
)
2425 adv
|= ADVERTISE_10HALF
;
2426 if (ecmd
->advertising
& ADVERTISED_10baseT_Full
)
2427 adv
|= ADVERTISE_10FULL
;
2428 if (ecmd
->advertising
& ADVERTISED_100baseT_Half
)
2429 adv
|= ADVERTISE_100HALF
;
2430 if (ecmd
->advertising
& ADVERTISED_100baseT_Full
)
2431 adv
|= ADVERTISE_100FULL
;
2432 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
2434 if (np
->gigabit
== PHY_GIGABIT
) {
2435 adv
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
2436 adv
&= ~ADVERTISE_1000FULL
;
2437 if (ecmd
->advertising
& ADVERTISED_1000baseT_Full
)
2438 adv
|= ADVERTISE_1000FULL
;
2439 mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, adv
);
2442 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
2443 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
2444 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
2451 adv
= mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, MII_READ
);
2452 adv
&= ~(ADVERTISE_ALL
| ADVERTISE_100BASE4
);
2453 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_HALF
)
2454 adv
|= ADVERTISE_10HALF
;
2455 if (ecmd
->speed
== SPEED_10
&& ecmd
->duplex
== DUPLEX_FULL
)
2456 adv
|= ADVERTISE_10FULL
;
2457 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_HALF
)
2458 adv
|= ADVERTISE_100HALF
;
2459 if (ecmd
->speed
== SPEED_100
&& ecmd
->duplex
== DUPLEX_FULL
)
2460 adv
|= ADVERTISE_100FULL
;
2461 mii_rw(dev
, np
->phyaddr
, MII_ADVERTISE
, adv
);
2462 np
->fixed_mode
= adv
;
2464 if (np
->gigabit
== PHY_GIGABIT
) {
2465 adv
= mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, MII_READ
);
2466 adv
&= ~ADVERTISE_1000FULL
;
2467 mii_rw(dev
, np
->phyaddr
, MII_1000BT_CR
, adv
);
2470 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
2471 bmcr
|= ~(BMCR_ANENABLE
|BMCR_SPEED100
|BMCR_FULLDPLX
);
2472 if (adv
& (ADVERTISE_10FULL
|ADVERTISE_100FULL
))
2473 bmcr
|= BMCR_FULLDPLX
;
2474 if (adv
& (ADVERTISE_100HALF
|ADVERTISE_100FULL
))
2475 bmcr
|= BMCR_SPEED100
;
2476 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
2478 if (netif_running(dev
)) {
2479 /* Wait a bit and then reconfigure the nic. */
2484 spin_unlock_irq(&np
->lock
);
2489 #define FORCEDETH_REGS_VER 1
2490 #define FORCEDETH_REGS_SIZE 0x400 /* 256 32-bit registers */
2492 static int nv_get_regs_len(struct net_device
*dev
)
2494 return FORCEDETH_REGS_SIZE
;
2497 static void nv_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
, void *buf
)
2499 struct fe_priv
*np
= netdev_priv(dev
);
2500 u8 __iomem
*base
= get_hwbase(dev
);
2504 regs
->version
= FORCEDETH_REGS_VER
;
2505 spin_lock_irq(&np
->lock
);
2506 for (i
=0;i
<FORCEDETH_REGS_SIZE
/sizeof(u32
);i
++)
2507 rbuf
[i
] = readl(base
+ i
*sizeof(u32
));
2508 spin_unlock_irq(&np
->lock
);
2511 static int nv_nway_reset(struct net_device
*dev
)
2513 struct fe_priv
*np
= netdev_priv(dev
);
2516 spin_lock_irq(&np
->lock
);
2520 bmcr
= mii_rw(dev
, np
->phyaddr
, MII_BMCR
, MII_READ
);
2521 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
2522 mii_rw(dev
, np
->phyaddr
, MII_BMCR
, bmcr
);
2528 spin_unlock_irq(&np
->lock
);
2533 static struct ethtool_ops ops
= {
2534 .get_drvinfo
= nv_get_drvinfo
,
2535 .get_link
= ethtool_op_get_link
,
2536 .get_wol
= nv_get_wol
,
2537 .set_wol
= nv_set_wol
,
2538 .get_settings
= nv_get_settings
,
2539 .set_settings
= nv_set_settings
,
2540 .get_regs_len
= nv_get_regs_len
,
2541 .get_regs
= nv_get_regs
,
2542 .nway_reset
= nv_nway_reset
,
2543 .get_perm_addr
= ethtool_op_get_perm_addr
,
2546 static void nv_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
2548 struct fe_priv
*np
= get_nvpriv(dev
);
2550 spin_lock_irq(&np
->lock
);
2552 /* save vlan group */
2556 /* enable vlan on MAC */
2557 np
->txrxctl_bits
|= NVREG_TXRXCTL_VLANSTRIP
| NVREG_TXRXCTL_VLANINS
;
2559 /* disable vlan on MAC */
2560 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANSTRIP
;
2561 np
->txrxctl_bits
&= ~NVREG_TXRXCTL_VLANINS
;
2564 writel(np
->txrxctl_bits
, get_hwbase(dev
) + NvRegTxRxControl
);
2566 spin_unlock_irq(&np
->lock
);
2569 static void nv_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
2574 static void set_msix_vector_map(struct net_device
*dev
, u32 vector
, u32 irqmask
)
2576 u8 __iomem
*base
= get_hwbase(dev
);
2580 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2581 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2582 * the remaining 8 interrupts.
2584 for (i
= 0; i
< 8; i
++) {
2585 if ((irqmask
>> i
) & 0x1) {
2586 msixmap
|= vector
<< (i
<< 2);
2589 writel(readl(base
+ NvRegMSIXMap0
) | msixmap
, base
+ NvRegMSIXMap0
);
2592 for (i
= 0; i
< 8; i
++) {
2593 if ((irqmask
>> (i
+ 8)) & 0x1) {
2594 msixmap
|= vector
<< (i
<< 2);
2597 writel(readl(base
+ NvRegMSIXMap1
) | msixmap
, base
+ NvRegMSIXMap1
);
2600 static int nv_open(struct net_device
*dev
)
2602 struct fe_priv
*np
= netdev_priv(dev
);
2603 u8 __iomem
*base
= get_hwbase(dev
);
2607 dprintk(KERN_DEBUG
"nv_open: begin\n");
2609 /* 1) erase previous misconfiguration */
2610 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2611 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
2612 writel(0, base
+ NvRegMulticastAddrB
);
2613 writel(0, base
+ NvRegMulticastMaskA
);
2614 writel(0, base
+ NvRegMulticastMaskB
);
2615 writel(0, base
+ NvRegPacketFilterFlags
);
2617 writel(0, base
+ NvRegTransmitterControl
);
2618 writel(0, base
+ NvRegReceiverControl
);
2620 writel(0, base
+ NvRegAdapterControl
);
2622 /* 2) initialize descriptor rings */
2624 oom
= nv_init_ring(dev
);
2626 writel(0, base
+ NvRegLinkSpeed
);
2627 writel(0, base
+ NvRegUnknownTransmitterReg
);
2629 writel(0, base
+ NvRegUnknownSetupReg6
);
2631 np
->in_shutdown
= 0;
2633 /* 3) set mac address */
2634 nv_copy_mac_to_hw(dev
);
2636 /* 4) give hw rings */
2637 setup_hw_rings(dev
, NV_SETUP_RX_RING
| NV_SETUP_TX_RING
);
2638 writel( ((RX_RING
-1) << NVREG_RINGSZ_RXSHIFT
) + ((TX_RING
-1) << NVREG_RINGSZ_TXSHIFT
),
2639 base
+ NvRegRingSizes
);
2641 /* 5) continue setup */
2642 writel(np
->linkspeed
, base
+ NvRegLinkSpeed
);
2643 writel(NVREG_UNKSETUP3_VAL1
, base
+ NvRegUnknownSetupReg3
);
2644 writel(np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
2645 writel(np
->vlanctl_bits
, base
+ NvRegVlanControl
);
2647 writel(NVREG_TXRXCTL_BIT1
|np
->txrxctl_bits
, base
+ NvRegTxRxControl
);
2648 reg_delay(dev
, NvRegUnknownSetupReg5
, NVREG_UNKSETUP5_BIT31
, NVREG_UNKSETUP5_BIT31
,
2649 NV_SETUP5_DELAY
, NV_SETUP5_DELAYMAX
,
2650 KERN_INFO
"open: SetupReg5, Bit 31 remained off\n");
2652 writel(0, base
+ NvRegUnknownSetupReg4
);
2653 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
2654 writel(NVREG_MIISTAT_MASK2
, base
+ NvRegMIIStatus
);
2656 /* 6) continue setup */
2657 writel(NVREG_MISC1_FORCE
| NVREG_MISC1_HD
, base
+ NvRegMisc1
);
2658 writel(readl(base
+ NvRegTransmitterStatus
), base
+ NvRegTransmitterStatus
);
2659 writel(NVREG_PFF_ALWAYS
, base
+ NvRegPacketFilterFlags
);
2660 writel(np
->rx_buf_sz
, base
+ NvRegOffloadConfig
);
2662 writel(readl(base
+ NvRegReceiverStatus
), base
+ NvRegReceiverStatus
);
2663 get_random_bytes(&i
, sizeof(i
));
2664 writel(NVREG_RNDSEED_FORCE
| (i
&NVREG_RNDSEED_MASK
), base
+ NvRegRandomSeed
);
2665 writel(NVREG_UNKSETUP1_VAL
, base
+ NvRegUnknownSetupReg1
);
2666 writel(NVREG_UNKSETUP2_VAL
, base
+ NvRegUnknownSetupReg2
);
2667 if (poll_interval
== -1) {
2668 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
)
2669 writel(NVREG_POLL_DEFAULT_THROUGHPUT
, base
+ NvRegPollingInterval
);
2671 writel(NVREG_POLL_DEFAULT_CPU
, base
+ NvRegPollingInterval
);
2674 writel(poll_interval
& 0xFFFF, base
+ NvRegPollingInterval
);
2675 writel(NVREG_UNKSETUP6_VAL
, base
+ NvRegUnknownSetupReg6
);
2676 writel((np
->phyaddr
<< NVREG_ADAPTCTL_PHYSHIFT
)|NVREG_ADAPTCTL_PHYVALID
|NVREG_ADAPTCTL_RUNNING
,
2677 base
+ NvRegAdapterControl
);
2678 writel(NVREG_MIISPEED_BIT8
|NVREG_MIIDELAY
, base
+ NvRegMIISpeed
);
2679 writel(NVREG_UNKSETUP4_VAL
, base
+ NvRegUnknownSetupReg4
);
2680 writel(NVREG_WAKEUPFLAGS_VAL
, base
+ NvRegWakeUpFlags
);
2682 i
= readl(base
+ NvRegPowerState
);
2683 if ( (i
& NVREG_POWERSTATE_POWEREDUP
) == 0)
2684 writel(NVREG_POWERSTATE_POWEREDUP
|i
, base
+ NvRegPowerState
);
2688 writel(readl(base
+ NvRegPowerState
) | NVREG_POWERSTATE_VALID
, base
+ NvRegPowerState
);
2690 writel(0, base
+ NvRegIrqMask
);
2692 writel(NVREG_MIISTAT_MASK2
, base
+ NvRegMIIStatus
);
2693 writel(NVREG_IRQSTAT_MASK
, base
+ NvRegIrqStatus
);
2696 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) {
2697 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
2698 np
->msi_x_entry
[i
].entry
= i
;
2700 if ((ret
= pci_enable_msix(np
->pci_dev
, np
->msi_x_entry
, (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
))) == 0) {
2701 np
->msi_flags
|= NV_MSI_X_ENABLED
;
2702 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
) {
2703 /* Request irq for rx handling */
2704 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_RX
].vector
, &nv_nic_irq_rx
, SA_SHIRQ
, dev
->name
, dev
) != 0) {
2705 printk(KERN_INFO
"forcedeth: request_irq failed for rx %d\n", ret
);
2706 pci_disable_msix(np
->pci_dev
);
2707 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2710 /* Request irq for tx handling */
2711 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_TX
].vector
, &nv_nic_irq_tx
, SA_SHIRQ
, dev
->name
, dev
) != 0) {
2712 printk(KERN_INFO
"forcedeth: request_irq failed for tx %d\n", ret
);
2713 pci_disable_msix(np
->pci_dev
);
2714 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2717 /* Request irq for link and timer handling */
2718 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_OTHER
].vector
, &nv_nic_irq_other
, SA_SHIRQ
, dev
->name
, dev
) != 0) {
2719 printk(KERN_INFO
"forcedeth: request_irq failed for link %d\n", ret
);
2720 pci_disable_msix(np
->pci_dev
);
2721 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2725 /* map interrupts to their respective vector */
2726 writel(0, base
+ NvRegMSIXMap0
);
2727 writel(0, base
+ NvRegMSIXMap1
);
2728 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_RX
, NVREG_IRQ_RX_ALL
);
2729 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_TX
, NVREG_IRQ_TX_ALL
);
2730 set_msix_vector_map(dev
, NV_MSI_X_VECTOR_OTHER
, NVREG_IRQ_OTHER
);
2732 /* Request irq for all interrupts */
2733 if (request_irq(np
->msi_x_entry
[NV_MSI_X_VECTOR_ALL
].vector
, &nv_nic_irq
, SA_SHIRQ
, dev
->name
, dev
) != 0) {
2734 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
2735 pci_disable_msix(np
->pci_dev
);
2736 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2740 /* map interrupts to vector 0 */
2741 writel(0, base
+ NvRegMSIXMap0
);
2742 writel(0, base
+ NvRegMSIXMap1
);
2746 if (ret
!= 0 && np
->msi_flags
& NV_MSI_CAPABLE
) {
2747 if ((ret
= pci_enable_msi(np
->pci_dev
)) == 0) {
2748 np
->msi_flags
|= NV_MSI_ENABLED
;
2749 if (request_irq(np
->pci_dev
->irq
, &nv_nic_irq
, SA_SHIRQ
, dev
->name
, dev
) != 0) {
2750 printk(KERN_INFO
"forcedeth: request_irq failed %d\n", ret
);
2751 pci_disable_msi(np
->pci_dev
);
2752 np
->msi_flags
&= ~NV_MSI_ENABLED
;
2756 /* map interrupts to vector 0 */
2757 writel(0, base
+ NvRegMSIMap0
);
2758 writel(0, base
+ NvRegMSIMap1
);
2759 /* enable msi vector 0 */
2760 writel(NVREG_MSI_VECTOR_0_ENABLED
, base
+ NvRegMSIIrqMask
);
2764 if (request_irq(np
->pci_dev
->irq
, &nv_nic_irq
, SA_SHIRQ
, dev
->name
, dev
) != 0)
2768 /* ask for interrupts */
2769 writel(np
->irqmask
, base
+ NvRegIrqMask
);
2771 spin_lock_irq(&np
->lock
);
2772 writel(NVREG_MCASTADDRA_FORCE
, base
+ NvRegMulticastAddrA
);
2773 writel(0, base
+ NvRegMulticastAddrB
);
2774 writel(0, base
+ NvRegMulticastMaskA
);
2775 writel(0, base
+ NvRegMulticastMaskB
);
2776 writel(NVREG_PFF_ALWAYS
|NVREG_PFF_MYADDR
, base
+ NvRegPacketFilterFlags
);
2777 /* One manual link speed update: Interrupts are enabled, future link
2778 * speed changes cause interrupts and are handled by nv_link_irq().
2782 miistat
= readl(base
+ NvRegMIIStatus
);
2783 writel(NVREG_MIISTAT_MASK
, base
+ NvRegMIIStatus
);
2784 dprintk(KERN_INFO
"startup: got 0x%08x.\n", miistat
);
2786 /* set linkspeed to invalid value, thus force nv_update_linkspeed
2789 ret
= nv_update_linkspeed(dev
);
2792 netif_start_queue(dev
);
2794 netif_carrier_on(dev
);
2796 printk("%s: no link during initialization.\n", dev
->name
);
2797 netif_carrier_off(dev
);
2800 mod_timer(&np
->oom_kick
, jiffies
+ OOM_REFILL
);
2801 spin_unlock_irq(&np
->lock
);
2809 static int nv_close(struct net_device
*dev
)
2811 struct fe_priv
*np
= netdev_priv(dev
);
2815 spin_lock_irq(&np
->lock
);
2816 np
->in_shutdown
= 1;
2817 spin_unlock_irq(&np
->lock
);
2818 synchronize_irq(dev
->irq
);
2820 del_timer_sync(&np
->oom_kick
);
2821 del_timer_sync(&np
->nic_poll
);
2823 netif_stop_queue(dev
);
2824 spin_lock_irq(&np
->lock
);
2829 /* disable interrupts on the nic or we will lock up */
2830 base
= get_hwbase(dev
);
2831 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
2832 writel(np
->irqmask
, base
+ NvRegIrqMask
);
2834 if (np
->msi_flags
& NV_MSI_ENABLED
)
2835 writel(0, base
+ NvRegMSIIrqMask
);
2836 writel(0, base
+ NvRegIrqMask
);
2839 dprintk(KERN_INFO
"%s: Irqmask is zero again\n", dev
->name
);
2841 spin_unlock_irq(&np
->lock
);
2843 if (np
->msi_flags
& NV_MSI_X_ENABLED
) {
2844 for (i
= 0; i
< (np
->msi_flags
& NV_MSI_X_VECTORS_MASK
); i
++) {
2845 free_irq(np
->msi_x_entry
[i
].vector
, dev
);
2847 pci_disable_msix(np
->pci_dev
);
2848 np
->msi_flags
&= ~NV_MSI_X_ENABLED
;
2850 free_irq(np
->pci_dev
->irq
, dev
);
2851 if (np
->msi_flags
& NV_MSI_ENABLED
) {
2852 pci_disable_msi(np
->pci_dev
);
2853 np
->msi_flags
&= ~NV_MSI_ENABLED
;
2862 /* special op: write back the misordered MAC address - otherwise
2863 * the next nv_probe would see a wrong address.
2865 writel(np
->orig_mac
[0], base
+ NvRegMacAddrA
);
2866 writel(np
->orig_mac
[1], base
+ NvRegMacAddrB
);
2868 /* FIXME: power down nic */
2873 static int __devinit
nv_probe(struct pci_dev
*pci_dev
, const struct pci_device_id
*id
)
2875 struct net_device
*dev
;
2881 dev
= alloc_etherdev(sizeof(struct fe_priv
));
2886 np
= netdev_priv(dev
);
2887 np
->pci_dev
= pci_dev
;
2888 spin_lock_init(&np
->lock
);
2889 SET_MODULE_OWNER(dev
);
2890 SET_NETDEV_DEV(dev
, &pci_dev
->dev
);
2892 init_timer(&np
->oom_kick
);
2893 np
->oom_kick
.data
= (unsigned long) dev
;
2894 np
->oom_kick
.function
= &nv_do_rx_refill
; /* timer handler */
2895 init_timer(&np
->nic_poll
);
2896 np
->nic_poll
.data
= (unsigned long) dev
;
2897 np
->nic_poll
.function
= &nv_do_nic_poll
; /* timer handler */
2899 err
= pci_enable_device(pci_dev
);
2901 printk(KERN_INFO
"forcedeth: pci_enable_dev failed (%d) for device %s\n",
2902 err
, pci_name(pci_dev
));
2906 pci_set_master(pci_dev
);
2908 err
= pci_request_regions(pci_dev
, DRV_NAME
);
2914 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
2915 dprintk(KERN_DEBUG
"%s: resource %d start %p len %ld flags 0x%08lx.\n",
2916 pci_name(pci_dev
), i
, (void*)pci_resource_start(pci_dev
, i
),
2917 pci_resource_len(pci_dev
, i
),
2918 pci_resource_flags(pci_dev
, i
));
2919 if (pci_resource_flags(pci_dev
, i
) & IORESOURCE_MEM
&&
2920 pci_resource_len(pci_dev
, i
) >= NV_PCI_REGSZ
) {
2921 addr
= pci_resource_start(pci_dev
, i
);
2925 if (i
== DEVICE_COUNT_RESOURCE
) {
2926 printk(KERN_INFO
"forcedeth: Couldn't find register window for device %s.\n",
2931 /* handle different descriptor versions */
2932 if (id
->driver_data
& DEV_HAS_HIGH_DMA
) {
2933 /* packet format 3: supports 40-bit addressing */
2934 np
->desc_ver
= DESC_VER_3
;
2935 if (pci_set_dma_mask(pci_dev
, 0x0000007fffffffffULL
)) {
2936 printk(KERN_INFO
"forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2939 if (pci_set_consistent_dma_mask(pci_dev
, 0x0000007fffffffffULL
)) {
2940 printk(KERN_INFO
"forcedeth: 64-bit DMA (consistent) failed for device %s.\n",
2944 dev
->features
|= NETIF_F_HIGHDMA
;
2945 printk(KERN_INFO
"forcedeth: using HIGHDMA\n");
2948 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_3
;
2949 } else if (id
->driver_data
& DEV_HAS_LARGEDESC
) {
2950 /* packet format 2: supports jumbo frames */
2951 np
->desc_ver
= DESC_VER_2
;
2952 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_2
;
2954 /* original packet format */
2955 np
->desc_ver
= DESC_VER_1
;
2956 np
->txrxctl_bits
= NVREG_TXRXCTL_DESC_1
;
2959 np
->pkt_limit
= NV_PKTLIMIT_1
;
2960 if (id
->driver_data
& DEV_HAS_LARGEDESC
)
2961 np
->pkt_limit
= NV_PKTLIMIT_2
;
2963 if (id
->driver_data
& DEV_HAS_CHECKSUM
) {
2964 np
->txrxctl_bits
|= NVREG_TXRXCTL_RXCHECK
;
2965 dev
->features
|= NETIF_F_HW_CSUM
| NETIF_F_SG
;
2967 dev
->features
|= NETIF_F_TSO
;
2971 np
->vlanctl_bits
= 0;
2972 if (id
->driver_data
& DEV_HAS_VLAN
) {
2973 np
->vlanctl_bits
= NVREG_VLANCONTROL_ENABLE
;
2974 dev
->features
|= NETIF_F_HW_VLAN_RX
| NETIF_F_HW_VLAN_TX
;
2975 dev
->vlan_rx_register
= nv_vlan_rx_register
;
2976 dev
->vlan_rx_kill_vid
= nv_vlan_rx_kill_vid
;
2980 if ((id
->driver_data
& DEV_HAS_MSI
) && !disable_msi
) {
2981 np
->msi_flags
|= NV_MSI_CAPABLE
;
2983 if ((id
->driver_data
& DEV_HAS_MSI_X
) && !disable_msix
) {
2984 np
->msi_flags
|= NV_MSI_X_CAPABLE
;
2988 np
->base
= ioremap(addr
, NV_PCI_REGSZ
);
2991 dev
->base_addr
= (unsigned long)np
->base
;
2993 dev
->irq
= pci_dev
->irq
;
2995 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
) {
2996 np
->rx_ring
.orig
= pci_alloc_consistent(pci_dev
,
2997 sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
),
2999 if (!np
->rx_ring
.orig
)
3001 np
->tx_ring
.orig
= &np
->rx_ring
.orig
[RX_RING
];
3003 np
->rx_ring
.ex
= pci_alloc_consistent(pci_dev
,
3004 sizeof(struct ring_desc_ex
) * (RX_RING
+ TX_RING
),
3006 if (!np
->rx_ring
.ex
)
3008 np
->tx_ring
.ex
= &np
->rx_ring
.ex
[RX_RING
];
3011 dev
->open
= nv_open
;
3012 dev
->stop
= nv_close
;
3013 dev
->hard_start_xmit
= nv_start_xmit
;
3014 dev
->get_stats
= nv_get_stats
;
3015 dev
->change_mtu
= nv_change_mtu
;
3016 dev
->set_mac_address
= nv_set_mac_address
;
3017 dev
->set_multicast_list
= nv_set_multicast
;
3018 #ifdef CONFIG_NET_POLL_CONTROLLER
3019 dev
->poll_controller
= nv_poll_controller
;
3021 SET_ETHTOOL_OPS(dev
, &ops
);
3022 dev
->tx_timeout
= nv_tx_timeout
;
3023 dev
->watchdog_timeo
= NV_WATCHDOG_TIMEO
;
3025 pci_set_drvdata(pci_dev
, dev
);
3027 /* read the mac address */
3028 base
= get_hwbase(dev
);
3029 np
->orig_mac
[0] = readl(base
+ NvRegMacAddrA
);
3030 np
->orig_mac
[1] = readl(base
+ NvRegMacAddrB
);
3032 dev
->dev_addr
[0] = (np
->orig_mac
[1] >> 8) & 0xff;
3033 dev
->dev_addr
[1] = (np
->orig_mac
[1] >> 0) & 0xff;
3034 dev
->dev_addr
[2] = (np
->orig_mac
[0] >> 24) & 0xff;
3035 dev
->dev_addr
[3] = (np
->orig_mac
[0] >> 16) & 0xff;
3036 dev
->dev_addr
[4] = (np
->orig_mac
[0] >> 8) & 0xff;
3037 dev
->dev_addr
[5] = (np
->orig_mac
[0] >> 0) & 0xff;
3038 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3040 if (!is_valid_ether_addr(dev
->perm_addr
)) {
3042 * Bad mac address. At least one bios sets the mac address
3043 * to 01:23:45:67:89:ab
3045 printk(KERN_ERR
"%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
3047 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3048 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3049 printk(KERN_ERR
"Please complain to your hardware vendor. Switching to a random MAC.\n");
3050 dev
->dev_addr
[0] = 0x00;
3051 dev
->dev_addr
[1] = 0x00;
3052 dev
->dev_addr
[2] = 0x6c;
3053 get_random_bytes(&dev
->dev_addr
[3], 3);
3056 dprintk(KERN_DEBUG
"%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev
),
3057 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3058 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3061 writel(0, base
+ NvRegWakeUpFlags
);
3064 if (np
->desc_ver
== DESC_VER_1
) {
3065 np
->tx_flags
= NV_TX_VALID
;
3067 np
->tx_flags
= NV_TX2_VALID
;
3069 if (optimization_mode
== NV_OPTIMIZATION_MODE_THROUGHPUT
) {
3070 np
->irqmask
= NVREG_IRQMASK_THROUGHPUT
;
3071 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
3072 np
->msi_flags
|= 0x0003;
3074 np
->irqmask
= NVREG_IRQMASK_CPU
;
3075 if (np
->msi_flags
& NV_MSI_X_CAPABLE
) /* set number of vectors */
3076 np
->msi_flags
|= 0x0001;
3079 if (id
->driver_data
& DEV_NEED_TIMERIRQ
)
3080 np
->irqmask
|= NVREG_IRQ_TIMER
;
3081 if (id
->driver_data
& DEV_NEED_LINKTIMER
) {
3082 dprintk(KERN_INFO
"%s: link timer on.\n", pci_name(pci_dev
));
3083 np
->need_linktimer
= 1;
3084 np
->link_timeout
= jiffies
+ LINK_TIMEOUT
;
3086 dprintk(KERN_INFO
"%s: link timer off.\n", pci_name(pci_dev
));
3087 np
->need_linktimer
= 0;
3090 /* find a suitable phy */
3091 for (i
= 1; i
<= 32; i
++) {
3093 int phyaddr
= i
& 0x1F;
3095 spin_lock_irq(&np
->lock
);
3096 id1
= mii_rw(dev
, phyaddr
, MII_PHYSID1
, MII_READ
);
3097 spin_unlock_irq(&np
->lock
);
3098 if (id1
< 0 || id1
== 0xffff)
3100 spin_lock_irq(&np
->lock
);
3101 id2
= mii_rw(dev
, phyaddr
, MII_PHYSID2
, MII_READ
);
3102 spin_unlock_irq(&np
->lock
);
3103 if (id2
< 0 || id2
== 0xffff)
3106 id1
= (id1
& PHYID1_OUI_MASK
) << PHYID1_OUI_SHFT
;
3107 id2
= (id2
& PHYID2_OUI_MASK
) >> PHYID2_OUI_SHFT
;
3108 dprintk(KERN_DEBUG
"%s: open: Found PHY %04x:%04x at address %d.\n",
3109 pci_name(pci_dev
), id1
, id2
, phyaddr
);
3110 np
->phyaddr
= phyaddr
;
3111 np
->phy_oui
= id1
| id2
;
3115 printk(KERN_INFO
"%s: open: Could not find a valid PHY.\n",
3123 /* set default link speed settings */
3124 np
->linkspeed
= NVREG_LINKSPEED_FORCE
|NVREG_LINKSPEED_10
;
3128 err
= register_netdev(dev
);
3130 printk(KERN_INFO
"forcedeth: unable to register netdev: %d\n", err
);
3133 printk(KERN_INFO
"%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
3134 dev
->name
, pci_dev
->subsystem_vendor
, pci_dev
->subsystem_device
,
3140 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
3141 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
),
3142 np
->rx_ring
.orig
, np
->ring_addr
);
3144 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (RX_RING
+ TX_RING
),
3145 np
->rx_ring
.ex
, np
->ring_addr
);
3146 pci_set_drvdata(pci_dev
, NULL
);
3148 iounmap(get_hwbase(dev
));
3150 pci_release_regions(pci_dev
);
3152 pci_disable_device(pci_dev
);
3159 static void __devexit
nv_remove(struct pci_dev
*pci_dev
)
3161 struct net_device
*dev
= pci_get_drvdata(pci_dev
);
3162 struct fe_priv
*np
= netdev_priv(dev
);
3164 unregister_netdev(dev
);
3166 /* free all structures */
3167 if (np
->desc_ver
== DESC_VER_1
|| np
->desc_ver
== DESC_VER_2
)
3168 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc
) * (RX_RING
+ TX_RING
), np
->rx_ring
.orig
, np
->ring_addr
);
3170 pci_free_consistent(np
->pci_dev
, sizeof(struct ring_desc_ex
) * (RX_RING
+ TX_RING
), np
->rx_ring
.ex
, np
->ring_addr
);
3171 iounmap(get_hwbase(dev
));
3172 pci_release_regions(pci_dev
);
3173 pci_disable_device(pci_dev
);
3175 pci_set_drvdata(pci_dev
, NULL
);
3178 static struct pci_device_id pci_tbl
[] = {
3179 { /* nForce Ethernet Controller */
3180 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_1
),
3181 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
3183 { /* nForce2 Ethernet Controller */
3184 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_2
),
3185 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
3187 { /* nForce3 Ethernet Controller */
3188 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_3
),
3189 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
,
3191 { /* nForce3 Ethernet Controller */
3192 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_4
),
3193 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
3195 { /* nForce3 Ethernet Controller */
3196 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_5
),
3197 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
3199 { /* nForce3 Ethernet Controller */
3200 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_6
),
3201 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
3203 { /* nForce3 Ethernet Controller */
3204 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_7
),
3205 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
,
3207 { /* CK804 Ethernet Controller */
3208 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_8
),
3209 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
3211 { /* CK804 Ethernet Controller */
3212 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_9
),
3213 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
3215 { /* MCP04 Ethernet Controller */
3216 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_10
),
3217 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
3219 { /* MCP04 Ethernet Controller */
3220 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_11
),
3221 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
,
3223 { /* MCP51 Ethernet Controller */
3224 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_12
),
3225 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
,
3227 { /* MCP51 Ethernet Controller */
3228 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_13
),
3229 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_HIGH_DMA
,
3231 { /* MCP55 Ethernet Controller */
3232 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_14
),
3233 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
,
3235 { /* MCP55 Ethernet Controller */
3236 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_NVENET_15
),
3237 .driver_data
= DEV_NEED_TIMERIRQ
|DEV_NEED_LINKTIMER
|DEV_HAS_LARGEDESC
|DEV_HAS_CHECKSUM
|DEV_HAS_HIGH_DMA
|DEV_HAS_VLAN
|DEV_HAS_MSI
|DEV_HAS_MSI_X
,
3242 static struct pci_driver driver
= {
3243 .name
= "forcedeth",
3244 .id_table
= pci_tbl
,
3246 .remove
= __devexit_p(nv_remove
),
3250 static int __init
init_nic(void)
3252 printk(KERN_INFO
"forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION
);
3253 return pci_module_init(&driver
);
3256 static void __exit
exit_nic(void)
3258 pci_unregister_driver(&driver
);
3261 module_param(max_interrupt_work
, int, 0);
3262 MODULE_PARM_DESC(max_interrupt_work
, "forcedeth maximum events handled per interrupt");
3263 module_param(optimization_mode
, int, 0);
3264 MODULE_PARM_DESC(optimization_mode
, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
3265 module_param(poll_interval
, int, 0);
3266 MODULE_PARM_DESC(poll_interval
, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
3267 module_param(disable_msi
, int, 0);
3268 MODULE_PARM_DESC(disable_msi
, "Disable MSI interrupts by setting to 1.");
3269 module_param(disable_msix
, int, 0);
3270 MODULE_PARM_DESC(disable_msix
, "Disable MSIX interrupts by setting to 1.");
3272 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
3273 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
3274 MODULE_LICENSE("GPL");
3276 MODULE_DEVICE_TABLE(pci
, pci_tbl
);
3278 module_init(init_nic
);
3279 module_exit(exit_nic
);