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[PATCH] forcedeth: deferral fixup
[deliverable/linux.git] / drivers / net / forcedeth.c
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
8 *
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
11 * countries.
12 *
13 * Copyright (C) 2003,4,5 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 *
33 * Changelog:
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
42 * irq mask updated
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
57 * open.
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
61 * the tx length.
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
69 * on close.
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
83 * capabilities.
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
91 * per-packet flags.
92 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
93 * 0.40: 19 Jul 2005: Add support for mac address change.
94 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
95 * of nv_remove
96 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
97 * in the second (and later) nv_open call
98 * 0.43: 10 Aug 2005: Add support for tx checksum.
99 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
101 * 0.46: 20 Oct 2005: Add irq optimization modes.
102 * 0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
103 * 0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
104 * 0.49: 10 Dec 2005: Fix tso for large buffers.
105 * 0.50: 20 Jan 2006: Add 8021pq tagging support.
106 * 0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
107 * 0.52: 20 Jan 2006: Add MSI/MSIX support.
108 * 0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
109 * 0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
110 * 0.55: 22 Mar 2006: Add flow control (pause frame).
111 * 0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
112 *
113 * Known bugs:
114 * We suspect that on some hardware no TX done interrupts are generated.
115 * This means recovery from netif_stop_queue only happens if the hw timer
116 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
117 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
118 * If your hardware reliably generates tx done interrupts, then you can remove
119 * DEV_NEED_TIMERIRQ from the driver_data flags.
120 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
121 * superfluous timer interrupts from the nic.
122 */
123 #define FORCEDETH_VERSION "0.56"
124 #define DRV_NAME "forcedeth"
125
126 #include <linux/module.h>
127 #include <linux/types.h>
128 #include <linux/pci.h>
129 #include <linux/interrupt.h>
130 #include <linux/netdevice.h>
131 #include <linux/etherdevice.h>
132 #include <linux/delay.h>
133 #include <linux/spinlock.h>
134 #include <linux/ethtool.h>
135 #include <linux/timer.h>
136 #include <linux/skbuff.h>
137 #include <linux/mii.h>
138 #include <linux/random.h>
139 #include <linux/init.h>
140 #include <linux/if_vlan.h>
141 #include <linux/dma-mapping.h>
142
143 #include <asm/irq.h>
144 #include <asm/io.h>
145 #include <asm/uaccess.h>
146 #include <asm/system.h>
147
148 #if 0
149 #define dprintk printk
150 #else
151 #define dprintk(x...) do { } while (0)
152 #endif
153
154
155 /*
156 * Hardware access:
157 */
158
159 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
160 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
161 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
162 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
163 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
164 #define DEV_HAS_VLAN 0x0020 /* device supports vlan tagging and striping */
165 #define DEV_HAS_MSI 0x0040 /* device supports MSI */
166 #define DEV_HAS_MSI_X 0x0080 /* device supports MSI-X */
167 #define DEV_HAS_POWER_CNTRL 0x0100 /* device supports power savings */
168 #define DEV_HAS_PAUSEFRAME_TX 0x0200 /* device supports tx pause frames */
169 #define DEV_HAS_STATISTICS 0x0400 /* device supports hw statistics */
170 #define DEV_HAS_TEST_EXTENDED 0x0800 /* device supports extended diagnostic test */
171
172 enum {
173 NvRegIrqStatus = 0x000,
174 #define NVREG_IRQSTAT_MIIEVENT 0x040
175 #define NVREG_IRQSTAT_MASK 0x1ff
176 NvRegIrqMask = 0x004,
177 #define NVREG_IRQ_RX_ERROR 0x0001
178 #define NVREG_IRQ_RX 0x0002
179 #define NVREG_IRQ_RX_NOBUF 0x0004
180 #define NVREG_IRQ_TX_ERR 0x0008
181 #define NVREG_IRQ_TX_OK 0x0010
182 #define NVREG_IRQ_TIMER 0x0020
183 #define NVREG_IRQ_LINK 0x0040
184 #define NVREG_IRQ_RX_FORCED 0x0080
185 #define NVREG_IRQ_TX_FORCED 0x0100
186 #define NVREG_IRQMASK_THROUGHPUT 0x00df
187 #define NVREG_IRQMASK_CPU 0x0040
188 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
189 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
190 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK)
191
192 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
193 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
194 NVREG_IRQ_TX_FORCED))
195
196 NvRegUnknownSetupReg6 = 0x008,
197 #define NVREG_UNKSETUP6_VAL 3
198
199 /*
200 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
201 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
202 */
203 NvRegPollingInterval = 0x00c,
204 #define NVREG_POLL_DEFAULT_THROUGHPUT 970
205 #define NVREG_POLL_DEFAULT_CPU 13
206 NvRegMSIMap0 = 0x020,
207 NvRegMSIMap1 = 0x024,
208 NvRegMSIIrqMask = 0x030,
209 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
210 NvRegMisc1 = 0x080,
211 #define NVREG_MISC1_PAUSE_TX 0x01
212 #define NVREG_MISC1_HD 0x02
213 #define NVREG_MISC1_FORCE 0x3b0f3c
214
215 NvRegMacReset = 0x3c,
216 #define NVREG_MAC_RESET_ASSERT 0x0F3
217 NvRegTransmitterControl = 0x084,
218 #define NVREG_XMITCTL_START 0x01
219 NvRegTransmitterStatus = 0x088,
220 #define NVREG_XMITSTAT_BUSY 0x01
221
222 NvRegPacketFilterFlags = 0x8c,
223 #define NVREG_PFF_PAUSE_RX 0x08
224 #define NVREG_PFF_ALWAYS 0x7F0000
225 #define NVREG_PFF_PROMISC 0x80
226 #define NVREG_PFF_MYADDR 0x20
227 #define NVREG_PFF_LOOPBACK 0x10
228
229 NvRegOffloadConfig = 0x90,
230 #define NVREG_OFFLOAD_HOMEPHY 0x601
231 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
232 NvRegReceiverControl = 0x094,
233 #define NVREG_RCVCTL_START 0x01
234 NvRegReceiverStatus = 0x98,
235 #define NVREG_RCVSTAT_BUSY 0x01
236
237 NvRegRandomSeed = 0x9c,
238 #define NVREG_RNDSEED_MASK 0x00ff
239 #define NVREG_RNDSEED_FORCE 0x7f00
240 #define NVREG_RNDSEED_FORCE2 0x2d00
241 #define NVREG_RNDSEED_FORCE3 0x7400
242
243 NvRegTxDeferral = 0xA0,
244 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
245 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
246 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
247 NvRegRxDeferral = 0xA4,
248 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
249 NvRegMacAddrA = 0xA8,
250 NvRegMacAddrB = 0xAC,
251 NvRegMulticastAddrA = 0xB0,
252 #define NVREG_MCASTADDRA_FORCE 0x01
253 NvRegMulticastAddrB = 0xB4,
254 NvRegMulticastMaskA = 0xB8,
255 NvRegMulticastMaskB = 0xBC,
256
257 NvRegPhyInterface = 0xC0,
258 #define PHY_RGMII 0x10000000
259
260 NvRegTxRingPhysAddr = 0x100,
261 NvRegRxRingPhysAddr = 0x104,
262 NvRegRingSizes = 0x108,
263 #define NVREG_RINGSZ_TXSHIFT 0
264 #define NVREG_RINGSZ_RXSHIFT 16
265 NvRegUnknownTransmitterReg = 0x10c,
266 NvRegLinkSpeed = 0x110,
267 #define NVREG_LINKSPEED_FORCE 0x10000
268 #define NVREG_LINKSPEED_10 1000
269 #define NVREG_LINKSPEED_100 100
270 #define NVREG_LINKSPEED_1000 50
271 #define NVREG_LINKSPEED_MASK (0xFFF)
272 NvRegUnknownSetupReg5 = 0x130,
273 #define NVREG_UNKSETUP5_BIT31 (1<<31)
274 NvRegUnknownSetupReg3 = 0x13c,
275 #define NVREG_UNKSETUP3_VAL1 0x200010
276 NvRegTxRxControl = 0x144,
277 #define NVREG_TXRXCTL_KICK 0x0001
278 #define NVREG_TXRXCTL_BIT1 0x0002
279 #define NVREG_TXRXCTL_BIT2 0x0004
280 #define NVREG_TXRXCTL_IDLE 0x0008
281 #define NVREG_TXRXCTL_RESET 0x0010
282 #define NVREG_TXRXCTL_RXCHECK 0x0400
283 #define NVREG_TXRXCTL_DESC_1 0
284 #define NVREG_TXRXCTL_DESC_2 0x02100
285 #define NVREG_TXRXCTL_DESC_3 0x02200
286 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
287 #define NVREG_TXRXCTL_VLANINS 0x00080
288 NvRegTxRingPhysAddrHigh = 0x148,
289 NvRegRxRingPhysAddrHigh = 0x14C,
290 NvRegTxPauseFrame = 0x170,
291 #define NVREG_TX_PAUSEFRAME_DISABLE 0x1ff0080
292 #define NVREG_TX_PAUSEFRAME_ENABLE 0x0c00030
293 NvRegMIIStatus = 0x180,
294 #define NVREG_MIISTAT_ERROR 0x0001
295 #define NVREG_MIISTAT_LINKCHANGE 0x0008
296 #define NVREG_MIISTAT_MASK 0x000f
297 #define NVREG_MIISTAT_MASK2 0x000f
298 NvRegUnknownSetupReg4 = 0x184,
299 #define NVREG_UNKSETUP4_VAL 8
300
301 NvRegAdapterControl = 0x188,
302 #define NVREG_ADAPTCTL_START 0x02
303 #define NVREG_ADAPTCTL_LINKUP 0x04
304 #define NVREG_ADAPTCTL_PHYVALID 0x40000
305 #define NVREG_ADAPTCTL_RUNNING 0x100000
306 #define NVREG_ADAPTCTL_PHYSHIFT 24
307 NvRegMIISpeed = 0x18c,
308 #define NVREG_MIISPEED_BIT8 (1<<8)
309 #define NVREG_MIIDELAY 5
310 NvRegMIIControl = 0x190,
311 #define NVREG_MIICTL_INUSE 0x08000
312 #define NVREG_MIICTL_WRITE 0x00400
313 #define NVREG_MIICTL_ADDRSHIFT 5
314 NvRegMIIData = 0x194,
315 NvRegWakeUpFlags = 0x200,
316 #define NVREG_WAKEUPFLAGS_VAL 0x7770
317 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
318 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
319 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
320 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
321 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
322 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
323 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
324 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
325 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
326 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
327
328 NvRegPatternCRC = 0x204,
329 NvRegPatternMask = 0x208,
330 NvRegPowerCap = 0x268,
331 #define NVREG_POWERCAP_D3SUPP (1<<30)
332 #define NVREG_POWERCAP_D2SUPP (1<<26)
333 #define NVREG_POWERCAP_D1SUPP (1<<25)
334 NvRegPowerState = 0x26c,
335 #define NVREG_POWERSTATE_POWEREDUP 0x8000
336 #define NVREG_POWERSTATE_VALID 0x0100
337 #define NVREG_POWERSTATE_MASK 0x0003
338 #define NVREG_POWERSTATE_D0 0x0000
339 #define NVREG_POWERSTATE_D1 0x0001
340 #define NVREG_POWERSTATE_D2 0x0002
341 #define NVREG_POWERSTATE_D3 0x0003
342 NvRegTxCnt = 0x280,
343 NvRegTxZeroReXmt = 0x284,
344 NvRegTxOneReXmt = 0x288,
345 NvRegTxManyReXmt = 0x28c,
346 NvRegTxLateCol = 0x290,
347 NvRegTxUnderflow = 0x294,
348 NvRegTxLossCarrier = 0x298,
349 NvRegTxExcessDef = 0x29c,
350 NvRegTxRetryErr = 0x2a0,
351 NvRegRxFrameErr = 0x2a4,
352 NvRegRxExtraByte = 0x2a8,
353 NvRegRxLateCol = 0x2ac,
354 NvRegRxRunt = 0x2b0,
355 NvRegRxFrameTooLong = 0x2b4,
356 NvRegRxOverflow = 0x2b8,
357 NvRegRxFCSErr = 0x2bc,
358 NvRegRxFrameAlignErr = 0x2c0,
359 NvRegRxLenErr = 0x2c4,
360 NvRegRxUnicast = 0x2c8,
361 NvRegRxMulticast = 0x2cc,
362 NvRegRxBroadcast = 0x2d0,
363 NvRegTxDef = 0x2d4,
364 NvRegTxFrame = 0x2d8,
365 NvRegRxCnt = 0x2dc,
366 NvRegTxPause = 0x2e0,
367 NvRegRxPause = 0x2e4,
368 NvRegRxDropFrame = 0x2e8,
369 NvRegVlanControl = 0x300,
370 #define NVREG_VLANCONTROL_ENABLE 0x2000
371 NvRegMSIXMap0 = 0x3e0,
372 NvRegMSIXMap1 = 0x3e4,
373 NvRegMSIXIrqStatus = 0x3f0,
374
375 NvRegPowerState2 = 0x600,
376 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11
377 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
378 };
379
380 /* Big endian: should work, but is untested */
381 struct ring_desc {
382 u32 PacketBuffer;
383 u32 FlagLen;
384 };
385
386 struct ring_desc_ex {
387 u32 PacketBufferHigh;
388 u32 PacketBufferLow;
389 u32 TxVlan;
390 u32 FlagLen;
391 };
392
393 typedef union _ring_type {
394 struct ring_desc* orig;
395 struct ring_desc_ex* ex;
396 } ring_type;
397
398 #define FLAG_MASK_V1 0xffff0000
399 #define FLAG_MASK_V2 0xffffc000
400 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
401 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
402
403 #define NV_TX_LASTPACKET (1<<16)
404 #define NV_TX_RETRYERROR (1<<19)
405 #define NV_TX_FORCED_INTERRUPT (1<<24)
406 #define NV_TX_DEFERRED (1<<26)
407 #define NV_TX_CARRIERLOST (1<<27)
408 #define NV_TX_LATECOLLISION (1<<28)
409 #define NV_TX_UNDERFLOW (1<<29)
410 #define NV_TX_ERROR (1<<30)
411 #define NV_TX_VALID (1<<31)
412
413 #define NV_TX2_LASTPACKET (1<<29)
414 #define NV_TX2_RETRYERROR (1<<18)
415 #define NV_TX2_FORCED_INTERRUPT (1<<30)
416 #define NV_TX2_DEFERRED (1<<25)
417 #define NV_TX2_CARRIERLOST (1<<26)
418 #define NV_TX2_LATECOLLISION (1<<27)
419 #define NV_TX2_UNDERFLOW (1<<28)
420 /* error and valid are the same for both */
421 #define NV_TX2_ERROR (1<<30)
422 #define NV_TX2_VALID (1<<31)
423 #define NV_TX2_TSO (1<<28)
424 #define NV_TX2_TSO_SHIFT 14
425 #define NV_TX2_TSO_MAX_SHIFT 14
426 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
427 #define NV_TX2_CHECKSUM_L3 (1<<27)
428 #define NV_TX2_CHECKSUM_L4 (1<<26)
429
430 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
431
432 #define NV_RX_DESCRIPTORVALID (1<<16)
433 #define NV_RX_MISSEDFRAME (1<<17)
434 #define NV_RX_SUBSTRACT1 (1<<18)
435 #define NV_RX_ERROR1 (1<<23)
436 #define NV_RX_ERROR2 (1<<24)
437 #define NV_RX_ERROR3 (1<<25)
438 #define NV_RX_ERROR4 (1<<26)
439 #define NV_RX_CRCERR (1<<27)
440 #define NV_RX_OVERFLOW (1<<28)
441 #define NV_RX_FRAMINGERR (1<<29)
442 #define NV_RX_ERROR (1<<30)
443 #define NV_RX_AVAIL (1<<31)
444
445 #define NV_RX2_CHECKSUMMASK (0x1C000000)
446 #define NV_RX2_CHECKSUMOK1 (0x10000000)
447 #define NV_RX2_CHECKSUMOK2 (0x14000000)
448 #define NV_RX2_CHECKSUMOK3 (0x18000000)
449 #define NV_RX2_DESCRIPTORVALID (1<<29)
450 #define NV_RX2_SUBSTRACT1 (1<<25)
451 #define NV_RX2_ERROR1 (1<<18)
452 #define NV_RX2_ERROR2 (1<<19)
453 #define NV_RX2_ERROR3 (1<<20)
454 #define NV_RX2_ERROR4 (1<<21)
455 #define NV_RX2_CRCERR (1<<22)
456 #define NV_RX2_OVERFLOW (1<<23)
457 #define NV_RX2_FRAMINGERR (1<<24)
458 /* error and avail are the same for both */
459 #define NV_RX2_ERROR (1<<30)
460 #define NV_RX2_AVAIL (1<<31)
461
462 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
463 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
464
465 /* Miscelaneous hardware related defines: */
466 #define NV_PCI_REGSZ_VER1 0x270
467 #define NV_PCI_REGSZ_VER2 0x604
468
469 /* various timeout delays: all in usec */
470 #define NV_TXRX_RESET_DELAY 4
471 #define NV_TXSTOP_DELAY1 10
472 #define NV_TXSTOP_DELAY1MAX 500000
473 #define NV_TXSTOP_DELAY2 100
474 #define NV_RXSTOP_DELAY1 10
475 #define NV_RXSTOP_DELAY1MAX 500000
476 #define NV_RXSTOP_DELAY2 100
477 #define NV_SETUP5_DELAY 5
478 #define NV_SETUP5_DELAYMAX 50000
479 #define NV_POWERUP_DELAY 5
480 #define NV_POWERUP_DELAYMAX 5000
481 #define NV_MIIBUSY_DELAY 50
482 #define NV_MIIPHY_DELAY 10
483 #define NV_MIIPHY_DELAYMAX 10000
484 #define NV_MAC_RESET_DELAY 64
485
486 #define NV_WAKEUPPATTERNS 5
487 #define NV_WAKEUPMASKENTRIES 4
488
489 /* General driver defaults */
490 #define NV_WATCHDOG_TIMEO (5*HZ)
491
492 #define RX_RING_DEFAULT 128
493 #define TX_RING_DEFAULT 256
494 #define RX_RING_MIN 128
495 #define TX_RING_MIN 64
496 #define RING_MAX_DESC_VER_1 1024
497 #define RING_MAX_DESC_VER_2_3 16384
498 /*
499 * Difference between the get and put pointers for the tx ring.
500 * This is used to throttle the amount of data outstanding in the
501 * tx ring.
502 */
503 #define TX_LIMIT_DIFFERENCE 1
504
505 /* rx/tx mac addr + type + vlan + align + slack*/
506 #define NV_RX_HEADERS (64)
507 /* even more slack. */
508 #define NV_RX_ALLOC_PAD (64)
509
510 /* maximum mtu size */
511 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
512 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
513
514 #define OOM_REFILL (1+HZ/20)
515 #define POLL_WAIT (1+HZ/100)
516 #define LINK_TIMEOUT (3*HZ)
517 #define STATS_INTERVAL (10*HZ)
518
519 /*
520 * desc_ver values:
521 * The nic supports three different descriptor types:
522 * - DESC_VER_1: Original
523 * - DESC_VER_2: support for jumbo frames.
524 * - DESC_VER_3: 64-bit format.
525 */
526 #define DESC_VER_1 1
527 #define DESC_VER_2 2
528 #define DESC_VER_3 3
529
530 /* PHY defines */
531 #define PHY_OUI_MARVELL 0x5043
532 #define PHY_OUI_CICADA 0x03f1
533 #define PHYID1_OUI_MASK 0x03ff
534 #define PHYID1_OUI_SHFT 6
535 #define PHYID2_OUI_MASK 0xfc00
536 #define PHYID2_OUI_SHFT 10
537 #define PHY_INIT1 0x0f000
538 #define PHY_INIT2 0x0e00
539 #define PHY_INIT3 0x01000
540 #define PHY_INIT4 0x0200
541 #define PHY_INIT5 0x0004
542 #define PHY_INIT6 0x02000
543 #define PHY_GIGABIT 0x0100
544
545 #define PHY_TIMEOUT 0x1
546 #define PHY_ERROR 0x2
547
548 #define PHY_100 0x1
549 #define PHY_1000 0x2
550 #define PHY_HALF 0x100
551
552 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
553 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
554 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
555 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
556 #define NV_PAUSEFRAME_RX_REQ 0x0010
557 #define NV_PAUSEFRAME_TX_REQ 0x0020
558 #define NV_PAUSEFRAME_AUTONEG 0x0040
559
560 /* MSI/MSI-X defines */
561 #define NV_MSI_X_MAX_VECTORS 8
562 #define NV_MSI_X_VECTORS_MASK 0x000f
563 #define NV_MSI_CAPABLE 0x0010
564 #define NV_MSI_X_CAPABLE 0x0020
565 #define NV_MSI_ENABLED 0x0040
566 #define NV_MSI_X_ENABLED 0x0080
567
568 #define NV_MSI_X_VECTOR_ALL 0x0
569 #define NV_MSI_X_VECTOR_RX 0x0
570 #define NV_MSI_X_VECTOR_TX 0x1
571 #define NV_MSI_X_VECTOR_OTHER 0x2
572
573 /* statistics */
574 struct nv_ethtool_str {
575 char name[ETH_GSTRING_LEN];
576 };
577
578 static const struct nv_ethtool_str nv_estats_str[] = {
579 { "tx_bytes" },
580 { "tx_zero_rexmt" },
581 { "tx_one_rexmt" },
582 { "tx_many_rexmt" },
583 { "tx_late_collision" },
584 { "tx_fifo_errors" },
585 { "tx_carrier_errors" },
586 { "tx_excess_deferral" },
587 { "tx_retry_error" },
588 { "tx_deferral" },
589 { "tx_packets" },
590 { "tx_pause" },
591 { "rx_frame_error" },
592 { "rx_extra_byte" },
593 { "rx_late_collision" },
594 { "rx_runt" },
595 { "rx_frame_too_long" },
596 { "rx_over_errors" },
597 { "rx_crc_errors" },
598 { "rx_frame_align_error" },
599 { "rx_length_error" },
600 { "rx_unicast" },
601 { "rx_multicast" },
602 { "rx_broadcast" },
603 { "rx_bytes" },
604 { "rx_pause" },
605 { "rx_drop_frame" },
606 { "rx_packets" },
607 { "rx_errors_total" }
608 };
609
610 struct nv_ethtool_stats {
611 u64 tx_bytes;
612 u64 tx_zero_rexmt;
613 u64 tx_one_rexmt;
614 u64 tx_many_rexmt;
615 u64 tx_late_collision;
616 u64 tx_fifo_errors;
617 u64 tx_carrier_errors;
618 u64 tx_excess_deferral;
619 u64 tx_retry_error;
620 u64 tx_deferral;
621 u64 tx_packets;
622 u64 tx_pause;
623 u64 rx_frame_error;
624 u64 rx_extra_byte;
625 u64 rx_late_collision;
626 u64 rx_runt;
627 u64 rx_frame_too_long;
628 u64 rx_over_errors;
629 u64 rx_crc_errors;
630 u64 rx_frame_align_error;
631 u64 rx_length_error;
632 u64 rx_unicast;
633 u64 rx_multicast;
634 u64 rx_broadcast;
635 u64 rx_bytes;
636 u64 rx_pause;
637 u64 rx_drop_frame;
638 u64 rx_packets;
639 u64 rx_errors_total;
640 };
641
642 /* diagnostics */
643 #define NV_TEST_COUNT_BASE 3
644 #define NV_TEST_COUNT_EXTENDED 4
645
646 static const struct nv_ethtool_str nv_etests_str[] = {
647 { "link (online/offline)" },
648 { "register (offline) " },
649 { "interrupt (offline) " },
650 { "loopback (offline) " }
651 };
652
653 struct register_test {
654 u32 reg;
655 u32 mask;
656 };
657
658 static const struct register_test nv_registers_test[] = {
659 { NvRegUnknownSetupReg6, 0x01 },
660 { NvRegMisc1, 0x03c },
661 { NvRegOffloadConfig, 0x03ff },
662 { NvRegMulticastAddrA, 0xffffffff },
663 { NvRegUnknownSetupReg3, 0x0ff },
664 { NvRegWakeUpFlags, 0x07777 },
665 { 0,0 }
666 };
667
668 /*
669 * SMP locking:
670 * All hardware access under dev->priv->lock, except the performance
671 * critical parts:
672 * - rx is (pseudo-) lockless: it relies on the single-threading provided
673 * by the arch code for interrupts.
674 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
675 * needs dev->priv->lock :-(
676 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
677 */
678
679 /* in dev: base, irq */
680 struct fe_priv {
681 spinlock_t lock;
682
683 /* General data:
684 * Locking: spin_lock(&np->lock); */
685 struct net_device_stats stats;
686 struct nv_ethtool_stats estats;
687 int in_shutdown;
688 u32 linkspeed;
689 int duplex;
690 int autoneg;
691 int fixed_mode;
692 int phyaddr;
693 int wolenabled;
694 unsigned int phy_oui;
695 u16 gigabit;
696 int intr_test;
697
698 /* General data: RO fields */
699 dma_addr_t ring_addr;
700 struct pci_dev *pci_dev;
701 u32 orig_mac[2];
702 u32 irqmask;
703 u32 desc_ver;
704 u32 txrxctl_bits;
705 u32 vlanctl_bits;
706 u32 driver_data;
707 u32 register_size;
708
709 void __iomem *base;
710
711 /* rx specific fields.
712 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
713 */
714 ring_type rx_ring;
715 unsigned int cur_rx, refill_rx;
716 struct sk_buff **rx_skbuff;
717 dma_addr_t *rx_dma;
718 unsigned int rx_buf_sz;
719 unsigned int pkt_limit;
720 struct timer_list oom_kick;
721 struct timer_list nic_poll;
722 struct timer_list stats_poll;
723 u32 nic_poll_irq;
724 int rx_ring_size;
725
726 /* media detection workaround.
727 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
728 */
729 int need_linktimer;
730 unsigned long link_timeout;
731 /*
732 * tx specific fields.
733 */
734 ring_type tx_ring;
735 unsigned int next_tx, nic_tx;
736 struct sk_buff **tx_skbuff;
737 dma_addr_t *tx_dma;
738 unsigned int *tx_dma_len;
739 u32 tx_flags;
740 int tx_ring_size;
741 int tx_limit_start;
742 int tx_limit_stop;
743
744 /* vlan fields */
745 struct vlan_group *vlangrp;
746
747 /* msi/msi-x fields */
748 u32 msi_flags;
749 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
750
751 /* flow control */
752 u32 pause_flags;
753 };
754
755 /*
756 * Maximum number of loops until we assume that a bit in the irq mask
757 * is stuck. Overridable with module param.
758 */
759 static int max_interrupt_work = 5;
760
761 /*
762 * Optimization can be either throuput mode or cpu mode
763 *
764 * Throughput Mode: Every tx and rx packet will generate an interrupt.
765 * CPU Mode: Interrupts are controlled by a timer.
766 */
767 enum {
768 NV_OPTIMIZATION_MODE_THROUGHPUT,
769 NV_OPTIMIZATION_MODE_CPU
770 };
771 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
772
773 /*
774 * Poll interval for timer irq
775 *
776 * This interval determines how frequent an interrupt is generated.
777 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
778 * Min = 0, and Max = 65535
779 */
780 static int poll_interval = -1;
781
782 /*
783 * MSI interrupts
784 */
785 enum {
786 NV_MSI_INT_DISABLED,
787 NV_MSI_INT_ENABLED
788 };
789 static int msi = NV_MSI_INT_ENABLED;
790
791 /*
792 * MSIX interrupts
793 */
794 enum {
795 NV_MSIX_INT_DISABLED,
796 NV_MSIX_INT_ENABLED
797 };
798 static int msix = NV_MSIX_INT_ENABLED;
799
800 /*
801 * DMA 64bit
802 */
803 enum {
804 NV_DMA_64BIT_DISABLED,
805 NV_DMA_64BIT_ENABLED
806 };
807 static int dma_64bit = NV_DMA_64BIT_ENABLED;
808
809 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
810 {
811 return netdev_priv(dev);
812 }
813
814 static inline u8 __iomem *get_hwbase(struct net_device *dev)
815 {
816 return ((struct fe_priv *)netdev_priv(dev))->base;
817 }
818
819 static inline void pci_push(u8 __iomem *base)
820 {
821 /* force out pending posted writes */
822 readl(base);
823 }
824
825 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
826 {
827 return le32_to_cpu(prd->FlagLen)
828 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
829 }
830
831 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
832 {
833 return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
834 }
835
836 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
837 int delay, int delaymax, const char *msg)
838 {
839 u8 __iomem *base = get_hwbase(dev);
840
841 pci_push(base);
842 do {
843 udelay(delay);
844 delaymax -= delay;
845 if (delaymax < 0) {
846 if (msg)
847 printk(msg);
848 return 1;
849 }
850 } while ((readl(base + offset) & mask) != target);
851 return 0;
852 }
853
854 #define NV_SETUP_RX_RING 0x01
855 #define NV_SETUP_TX_RING 0x02
856
857 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
858 {
859 struct fe_priv *np = get_nvpriv(dev);
860 u8 __iomem *base = get_hwbase(dev);
861
862 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
863 if (rxtx_flags & NV_SETUP_RX_RING) {
864 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
865 }
866 if (rxtx_flags & NV_SETUP_TX_RING) {
867 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
868 }
869 } else {
870 if (rxtx_flags & NV_SETUP_RX_RING) {
871 writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
872 writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
873 }
874 if (rxtx_flags & NV_SETUP_TX_RING) {
875 writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
876 writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
877 }
878 }
879 }
880
881 static void free_rings(struct net_device *dev)
882 {
883 struct fe_priv *np = get_nvpriv(dev);
884
885 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
886 if(np->rx_ring.orig)
887 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
888 np->rx_ring.orig, np->ring_addr);
889 } else {
890 if (np->rx_ring.ex)
891 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
892 np->rx_ring.ex, np->ring_addr);
893 }
894 if (np->rx_skbuff)
895 kfree(np->rx_skbuff);
896 if (np->rx_dma)
897 kfree(np->rx_dma);
898 if (np->tx_skbuff)
899 kfree(np->tx_skbuff);
900 if (np->tx_dma)
901 kfree(np->tx_dma);
902 if (np->tx_dma_len)
903 kfree(np->tx_dma_len);
904 }
905
906 static int using_multi_irqs(struct net_device *dev)
907 {
908 struct fe_priv *np = get_nvpriv(dev);
909
910 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
911 ((np->msi_flags & NV_MSI_X_ENABLED) &&
912 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
913 return 0;
914 else
915 return 1;
916 }
917
918 static void nv_enable_irq(struct net_device *dev)
919 {
920 struct fe_priv *np = get_nvpriv(dev);
921
922 if (!using_multi_irqs(dev)) {
923 if (np->msi_flags & NV_MSI_X_ENABLED)
924 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
925 else
926 enable_irq(dev->irq);
927 } else {
928 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
929 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
930 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
931 }
932 }
933
934 static void nv_disable_irq(struct net_device *dev)
935 {
936 struct fe_priv *np = get_nvpriv(dev);
937
938 if (!using_multi_irqs(dev)) {
939 if (np->msi_flags & NV_MSI_X_ENABLED)
940 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
941 else
942 disable_irq(dev->irq);
943 } else {
944 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
945 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
946 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
947 }
948 }
949
950 /* In MSIX mode, a write to irqmask behaves as XOR */
951 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
952 {
953 u8 __iomem *base = get_hwbase(dev);
954
955 writel(mask, base + NvRegIrqMask);
956 }
957
958 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
959 {
960 struct fe_priv *np = get_nvpriv(dev);
961 u8 __iomem *base = get_hwbase(dev);
962
963 if (np->msi_flags & NV_MSI_X_ENABLED) {
964 writel(mask, base + NvRegIrqMask);
965 } else {
966 if (np->msi_flags & NV_MSI_ENABLED)
967 writel(0, base + NvRegMSIIrqMask);
968 writel(0, base + NvRegIrqMask);
969 }
970 }
971
972 #define MII_READ (-1)
973 /* mii_rw: read/write a register on the PHY.
974 *
975 * Caller must guarantee serialization
976 */
977 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
978 {
979 u8 __iomem *base = get_hwbase(dev);
980 u32 reg;
981 int retval;
982
983 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
984
985 reg = readl(base + NvRegMIIControl);
986 if (reg & NVREG_MIICTL_INUSE) {
987 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
988 udelay(NV_MIIBUSY_DELAY);
989 }
990
991 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
992 if (value != MII_READ) {
993 writel(value, base + NvRegMIIData);
994 reg |= NVREG_MIICTL_WRITE;
995 }
996 writel(reg, base + NvRegMIIControl);
997
998 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
999 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1000 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1001 dev->name, miireg, addr);
1002 retval = -1;
1003 } else if (value != MII_READ) {
1004 /* it was a write operation - fewer failures are detectable */
1005 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1006 dev->name, value, miireg, addr);
1007 retval = 0;
1008 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1009 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1010 dev->name, miireg, addr);
1011 retval = -1;
1012 } else {
1013 retval = readl(base + NvRegMIIData);
1014 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1015 dev->name, miireg, addr, retval);
1016 }
1017
1018 return retval;
1019 }
1020
1021 static int phy_reset(struct net_device *dev)
1022 {
1023 struct fe_priv *np = netdev_priv(dev);
1024 u32 miicontrol;
1025 unsigned int tries = 0;
1026
1027 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1028 miicontrol |= BMCR_RESET;
1029 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1030 return -1;
1031 }
1032
1033 /* wait for 500ms */
1034 msleep(500);
1035
1036 /* must wait till reset is deasserted */
1037 while (miicontrol & BMCR_RESET) {
1038 msleep(10);
1039 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1040 /* FIXME: 100 tries seem excessive */
1041 if (tries++ > 100)
1042 return -1;
1043 }
1044 return 0;
1045 }
1046
1047 static int phy_init(struct net_device *dev)
1048 {
1049 struct fe_priv *np = get_nvpriv(dev);
1050 u8 __iomem *base = get_hwbase(dev);
1051 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1052
1053 /* set advertise register */
1054 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1055 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1056 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1057 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1058 return PHY_ERROR;
1059 }
1060
1061 /* get phy interface type */
1062 phyinterface = readl(base + NvRegPhyInterface);
1063
1064 /* see if gigabit phy */
1065 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1066 if (mii_status & PHY_GIGABIT) {
1067 np->gigabit = PHY_GIGABIT;
1068 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1069 mii_control_1000 &= ~ADVERTISE_1000HALF;
1070 if (phyinterface & PHY_RGMII)
1071 mii_control_1000 |= ADVERTISE_1000FULL;
1072 else
1073 mii_control_1000 &= ~ADVERTISE_1000FULL;
1074
1075 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1076 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1077 return PHY_ERROR;
1078 }
1079 }
1080 else
1081 np->gigabit = 0;
1082
1083 /* reset the phy */
1084 if (phy_reset(dev)) {
1085 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1086 return PHY_ERROR;
1087 }
1088
1089 /* phy vendor specific configuration */
1090 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1091 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1092 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
1093 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
1094 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1095 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1096 return PHY_ERROR;
1097 }
1098 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1099 phy_reserved |= PHY_INIT5;
1100 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1101 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1102 return PHY_ERROR;
1103 }
1104 }
1105 if (np->phy_oui == PHY_OUI_CICADA) {
1106 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1107 phy_reserved |= PHY_INIT6;
1108 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1109 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1110 return PHY_ERROR;
1111 }
1112 }
1113 /* some phys clear out pause advertisment on reset, set it back */
1114 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1115
1116 /* restart auto negotiation */
1117 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1118 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1119 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1120 return PHY_ERROR;
1121 }
1122
1123 return 0;
1124 }
1125
1126 static void nv_start_rx(struct net_device *dev)
1127 {
1128 struct fe_priv *np = netdev_priv(dev);
1129 u8 __iomem *base = get_hwbase(dev);
1130
1131 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1132 /* Already running? Stop it. */
1133 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
1134 writel(0, base + NvRegReceiverControl);
1135 pci_push(base);
1136 }
1137 writel(np->linkspeed, base + NvRegLinkSpeed);
1138 pci_push(base);
1139 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
1140 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1141 dev->name, np->duplex, np->linkspeed);
1142 pci_push(base);
1143 }
1144
1145 static void nv_stop_rx(struct net_device *dev)
1146 {
1147 u8 __iomem *base = get_hwbase(dev);
1148
1149 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1150 writel(0, base + NvRegReceiverControl);
1151 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1152 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1153 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1154
1155 udelay(NV_RXSTOP_DELAY2);
1156 writel(0, base + NvRegLinkSpeed);
1157 }
1158
1159 static void nv_start_tx(struct net_device *dev)
1160 {
1161 u8 __iomem *base = get_hwbase(dev);
1162
1163 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1164 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
1165 pci_push(base);
1166 }
1167
1168 static void nv_stop_tx(struct net_device *dev)
1169 {
1170 u8 __iomem *base = get_hwbase(dev);
1171
1172 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1173 writel(0, base + NvRegTransmitterControl);
1174 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1175 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1176 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1177
1178 udelay(NV_TXSTOP_DELAY2);
1179 writel(0, base + NvRegUnknownTransmitterReg);
1180 }
1181
1182 static void nv_txrx_reset(struct net_device *dev)
1183 {
1184 struct fe_priv *np = netdev_priv(dev);
1185 u8 __iomem *base = get_hwbase(dev);
1186
1187 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1188 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1189 pci_push(base);
1190 udelay(NV_TXRX_RESET_DELAY);
1191 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1192 pci_push(base);
1193 }
1194
1195 static void nv_mac_reset(struct net_device *dev)
1196 {
1197 struct fe_priv *np = netdev_priv(dev);
1198 u8 __iomem *base = get_hwbase(dev);
1199
1200 dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1201 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1202 pci_push(base);
1203 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1204 pci_push(base);
1205 udelay(NV_MAC_RESET_DELAY);
1206 writel(0, base + NvRegMacReset);
1207 pci_push(base);
1208 udelay(NV_MAC_RESET_DELAY);
1209 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1210 pci_push(base);
1211 }
1212
1213 /*
1214 * nv_get_stats: dev->get_stats function
1215 * Get latest stats value from the nic.
1216 * Called with read_lock(&dev_base_lock) held for read -
1217 * only synchronized against unregister_netdevice.
1218 */
1219 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1220 {
1221 struct fe_priv *np = netdev_priv(dev);
1222
1223 /* It seems that the nic always generates interrupts and doesn't
1224 * accumulate errors internally. Thus the current values in np->stats
1225 * are already up to date.
1226 */
1227 return &np->stats;
1228 }
1229
1230 /*
1231 * nv_alloc_rx: fill rx ring entries.
1232 * Return 1 if the allocations for the skbs failed and the
1233 * rx engine is without Available descriptors
1234 */
1235 static int nv_alloc_rx(struct net_device *dev)
1236 {
1237 struct fe_priv *np = netdev_priv(dev);
1238 unsigned int refill_rx = np->refill_rx;
1239 int nr;
1240
1241 while (np->cur_rx != refill_rx) {
1242 struct sk_buff *skb;
1243
1244 nr = refill_rx % np->rx_ring_size;
1245 if (np->rx_skbuff[nr] == NULL) {
1246
1247 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1248 if (!skb)
1249 break;
1250
1251 skb->dev = dev;
1252 np->rx_skbuff[nr] = skb;
1253 } else {
1254 skb = np->rx_skbuff[nr];
1255 }
1256 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data,
1257 skb->end-skb->data, PCI_DMA_FROMDEVICE);
1258 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1259 np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
1260 wmb();
1261 np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1262 } else {
1263 np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
1264 np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
1265 wmb();
1266 np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1267 }
1268 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
1269 dev->name, refill_rx);
1270 refill_rx++;
1271 }
1272 np->refill_rx = refill_rx;
1273 if (np->cur_rx - refill_rx == np->rx_ring_size)
1274 return 1;
1275 return 0;
1276 }
1277
1278 static void nv_do_rx_refill(unsigned long data)
1279 {
1280 struct net_device *dev = (struct net_device *) data;
1281 struct fe_priv *np = netdev_priv(dev);
1282
1283 if (!using_multi_irqs(dev)) {
1284 if (np->msi_flags & NV_MSI_X_ENABLED)
1285 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1286 else
1287 disable_irq(dev->irq);
1288 } else {
1289 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1290 }
1291 if (nv_alloc_rx(dev)) {
1292 spin_lock_irq(&np->lock);
1293 if (!np->in_shutdown)
1294 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1295 spin_unlock_irq(&np->lock);
1296 }
1297 if (!using_multi_irqs(dev)) {
1298 if (np->msi_flags & NV_MSI_X_ENABLED)
1299 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1300 else
1301 enable_irq(dev->irq);
1302 } else {
1303 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1304 }
1305 }
1306
1307 static void nv_init_rx(struct net_device *dev)
1308 {
1309 struct fe_priv *np = netdev_priv(dev);
1310 int i;
1311
1312 np->cur_rx = np->rx_ring_size;
1313 np->refill_rx = 0;
1314 for (i = 0; i < np->rx_ring_size; i++)
1315 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1316 np->rx_ring.orig[i].FlagLen = 0;
1317 else
1318 np->rx_ring.ex[i].FlagLen = 0;
1319 }
1320
1321 static void nv_init_tx(struct net_device *dev)
1322 {
1323 struct fe_priv *np = netdev_priv(dev);
1324 int i;
1325
1326 np->next_tx = np->nic_tx = 0;
1327 for (i = 0; i < np->tx_ring_size; i++) {
1328 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1329 np->tx_ring.orig[i].FlagLen = 0;
1330 else
1331 np->tx_ring.ex[i].FlagLen = 0;
1332 np->tx_skbuff[i] = NULL;
1333 np->tx_dma[i] = 0;
1334 }
1335 }
1336
1337 static int nv_init_ring(struct net_device *dev)
1338 {
1339 nv_init_tx(dev);
1340 nv_init_rx(dev);
1341 return nv_alloc_rx(dev);
1342 }
1343
1344 static int nv_release_txskb(struct net_device *dev, unsigned int skbnr)
1345 {
1346 struct fe_priv *np = netdev_priv(dev);
1347
1348 dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d\n",
1349 dev->name, skbnr);
1350
1351 if (np->tx_dma[skbnr]) {
1352 pci_unmap_page(np->pci_dev, np->tx_dma[skbnr],
1353 np->tx_dma_len[skbnr],
1354 PCI_DMA_TODEVICE);
1355 np->tx_dma[skbnr] = 0;
1356 }
1357
1358 if (np->tx_skbuff[skbnr]) {
1359 dev_kfree_skb_any(np->tx_skbuff[skbnr]);
1360 np->tx_skbuff[skbnr] = NULL;
1361 return 1;
1362 } else {
1363 return 0;
1364 }
1365 }
1366
1367 static void nv_drain_tx(struct net_device *dev)
1368 {
1369 struct fe_priv *np = netdev_priv(dev);
1370 unsigned int i;
1371
1372 for (i = 0; i < np->tx_ring_size; i++) {
1373 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1374 np->tx_ring.orig[i].FlagLen = 0;
1375 else
1376 np->tx_ring.ex[i].FlagLen = 0;
1377 if (nv_release_txskb(dev, i))
1378 np->stats.tx_dropped++;
1379 }
1380 }
1381
1382 static void nv_drain_rx(struct net_device *dev)
1383 {
1384 struct fe_priv *np = netdev_priv(dev);
1385 int i;
1386 for (i = 0; i < np->rx_ring_size; i++) {
1387 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1388 np->rx_ring.orig[i].FlagLen = 0;
1389 else
1390 np->rx_ring.ex[i].FlagLen = 0;
1391 wmb();
1392 if (np->rx_skbuff[i]) {
1393 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1394 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1395 PCI_DMA_FROMDEVICE);
1396 dev_kfree_skb(np->rx_skbuff[i]);
1397 np->rx_skbuff[i] = NULL;
1398 }
1399 }
1400 }
1401
1402 static void drain_ring(struct net_device *dev)
1403 {
1404 nv_drain_tx(dev);
1405 nv_drain_rx(dev);
1406 }
1407
1408 /*
1409 * nv_start_xmit: dev->hard_start_xmit function
1410 * Called with netif_tx_lock held.
1411 */
1412 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1413 {
1414 struct fe_priv *np = netdev_priv(dev);
1415 u32 tx_flags = 0;
1416 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1417 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1418 unsigned int nr = (np->next_tx - 1) % np->tx_ring_size;
1419 unsigned int start_nr = np->next_tx % np->tx_ring_size;
1420 unsigned int i;
1421 u32 offset = 0;
1422 u32 bcnt;
1423 u32 size = skb->len-skb->data_len;
1424 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1425 u32 tx_flags_vlan = 0;
1426
1427 /* add fragments to entries count */
1428 for (i = 0; i < fragments; i++) {
1429 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1430 ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1431 }
1432
1433 spin_lock_irq(&np->lock);
1434
1435 if ((np->next_tx - np->nic_tx + entries - 1) > np->tx_limit_stop) {
1436 spin_unlock_irq(&np->lock);
1437 netif_stop_queue(dev);
1438 return NETDEV_TX_BUSY;
1439 }
1440
1441 /* setup the header buffer */
1442 do {
1443 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1444 nr = (nr + 1) % np->tx_ring_size;
1445
1446 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1447 PCI_DMA_TODEVICE);
1448 np->tx_dma_len[nr] = bcnt;
1449
1450 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1451 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1452 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1453 } else {
1454 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1455 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1456 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1457 }
1458 tx_flags = np->tx_flags;
1459 offset += bcnt;
1460 size -= bcnt;
1461 } while(size);
1462
1463 /* setup the fragments */
1464 for (i = 0; i < fragments; i++) {
1465 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1466 u32 size = frag->size;
1467 offset = 0;
1468
1469 do {
1470 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1471 nr = (nr + 1) % np->tx_ring_size;
1472
1473 np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1474 PCI_DMA_TODEVICE);
1475 np->tx_dma_len[nr] = bcnt;
1476
1477 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1478 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1479 np->tx_ring.orig[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1480 } else {
1481 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1482 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1483 np->tx_ring.ex[nr].FlagLen = cpu_to_le32((bcnt-1) | tx_flags);
1484 }
1485 offset += bcnt;
1486 size -= bcnt;
1487 } while (size);
1488 }
1489
1490 /* set last fragment flag */
1491 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1492 np->tx_ring.orig[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1493 } else {
1494 np->tx_ring.ex[nr].FlagLen |= cpu_to_le32(tx_flags_extra);
1495 }
1496
1497 np->tx_skbuff[nr] = skb;
1498
1499 #ifdef NETIF_F_TSO
1500 if (skb_is_gso(skb))
1501 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1502 else
1503 #endif
1504 tx_flags_extra = (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1505
1506 /* vlan tag */
1507 if (np->vlangrp && vlan_tx_tag_present(skb)) {
1508 tx_flags_vlan = NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb);
1509 }
1510
1511 /* set tx flags */
1512 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1513 np->tx_ring.orig[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1514 } else {
1515 np->tx_ring.ex[start_nr].TxVlan = cpu_to_le32(tx_flags_vlan);
1516 np->tx_ring.ex[start_nr].FlagLen |= cpu_to_le32(tx_flags | tx_flags_extra);
1517 }
1518
1519 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet %d (entries %d) queued for transmission. tx_flags_extra: %x\n",
1520 dev->name, np->next_tx, entries, tx_flags_extra);
1521 {
1522 int j;
1523 for (j=0; j<64; j++) {
1524 if ((j%16) == 0)
1525 dprintk("\n%03x:", j);
1526 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1527 }
1528 dprintk("\n");
1529 }
1530
1531 np->next_tx += entries;
1532
1533 dev->trans_start = jiffies;
1534 spin_unlock_irq(&np->lock);
1535 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1536 pci_push(get_hwbase(dev));
1537 return NETDEV_TX_OK;
1538 }
1539
1540 /*
1541 * nv_tx_done: check for completed packets, release the skbs.
1542 *
1543 * Caller must own np->lock.
1544 */
1545 static void nv_tx_done(struct net_device *dev)
1546 {
1547 struct fe_priv *np = netdev_priv(dev);
1548 u32 Flags;
1549 unsigned int i;
1550 struct sk_buff *skb;
1551
1552 while (np->nic_tx != np->next_tx) {
1553 i = np->nic_tx % np->tx_ring_size;
1554
1555 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1556 Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1557 else
1558 Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1559
1560 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1561 dev->name, np->nic_tx, Flags);
1562 if (Flags & NV_TX_VALID)
1563 break;
1564 if (np->desc_ver == DESC_VER_1) {
1565 if (Flags & NV_TX_LASTPACKET) {
1566 skb = np->tx_skbuff[i];
1567 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1568 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1569 if (Flags & NV_TX_UNDERFLOW)
1570 np->stats.tx_fifo_errors++;
1571 if (Flags & NV_TX_CARRIERLOST)
1572 np->stats.tx_carrier_errors++;
1573 np->stats.tx_errors++;
1574 } else {
1575 np->stats.tx_packets++;
1576 np->stats.tx_bytes += skb->len;
1577 }
1578 }
1579 } else {
1580 if (Flags & NV_TX2_LASTPACKET) {
1581 skb = np->tx_skbuff[i];
1582 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1583 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1584 if (Flags & NV_TX2_UNDERFLOW)
1585 np->stats.tx_fifo_errors++;
1586 if (Flags & NV_TX2_CARRIERLOST)
1587 np->stats.tx_carrier_errors++;
1588 np->stats.tx_errors++;
1589 } else {
1590 np->stats.tx_packets++;
1591 np->stats.tx_bytes += skb->len;
1592 }
1593 }
1594 }
1595 nv_release_txskb(dev, i);
1596 np->nic_tx++;
1597 }
1598 if (np->next_tx - np->nic_tx < np->tx_limit_start)
1599 netif_wake_queue(dev);
1600 }
1601
1602 /*
1603 * nv_tx_timeout: dev->tx_timeout function
1604 * Called with netif_tx_lock held.
1605 */
1606 static void nv_tx_timeout(struct net_device *dev)
1607 {
1608 struct fe_priv *np = netdev_priv(dev);
1609 u8 __iomem *base = get_hwbase(dev);
1610 u32 status;
1611
1612 if (np->msi_flags & NV_MSI_X_ENABLED)
1613 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
1614 else
1615 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1616
1617 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
1618
1619 {
1620 int i;
1621
1622 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1623 dev->name, (unsigned long)np->ring_addr,
1624 np->next_tx, np->nic_tx);
1625 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1626 for (i=0;i<=np->register_size;i+= 32) {
1627 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1628 i,
1629 readl(base + i + 0), readl(base + i + 4),
1630 readl(base + i + 8), readl(base + i + 12),
1631 readl(base + i + 16), readl(base + i + 20),
1632 readl(base + i + 24), readl(base + i + 28));
1633 }
1634 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1635 for (i=0;i<np->tx_ring_size;i+= 4) {
1636 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1637 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1638 i,
1639 le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1640 le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1641 le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1642 le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1643 le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1644 le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1645 le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1646 le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1647 } else {
1648 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1649 i,
1650 le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1651 le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1652 le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1653 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1654 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1655 le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1656 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1657 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1658 le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1659 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1660 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1661 le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1662 }
1663 }
1664 }
1665
1666 spin_lock_irq(&np->lock);
1667
1668 /* 1) stop tx engine */
1669 nv_stop_tx(dev);
1670
1671 /* 2) check that the packets were not sent already: */
1672 nv_tx_done(dev);
1673
1674 /* 3) if there are dead entries: clear everything */
1675 if (np->next_tx != np->nic_tx) {
1676 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1677 nv_drain_tx(dev);
1678 np->next_tx = np->nic_tx = 0;
1679 setup_hw_rings(dev, NV_SETUP_TX_RING);
1680 netif_wake_queue(dev);
1681 }
1682
1683 /* 4) restart tx engine */
1684 nv_start_tx(dev);
1685 spin_unlock_irq(&np->lock);
1686 }
1687
1688 /*
1689 * Called when the nic notices a mismatch between the actual data len on the
1690 * wire and the len indicated in the 802 header
1691 */
1692 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1693 {
1694 int hdrlen; /* length of the 802 header */
1695 int protolen; /* length as stored in the proto field */
1696
1697 /* 1) calculate len according to header */
1698 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1699 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1700 hdrlen = VLAN_HLEN;
1701 } else {
1702 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1703 hdrlen = ETH_HLEN;
1704 }
1705 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1706 dev->name, datalen, protolen, hdrlen);
1707 if (protolen > ETH_DATA_LEN)
1708 return datalen; /* Value in proto field not a len, no checks possible */
1709
1710 protolen += hdrlen;
1711 /* consistency checks: */
1712 if (datalen > ETH_ZLEN) {
1713 if (datalen >= protolen) {
1714 /* more data on wire than in 802 header, trim of
1715 * additional data.
1716 */
1717 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1718 dev->name, protolen);
1719 return protolen;
1720 } else {
1721 /* less data on wire than mentioned in header.
1722 * Discard the packet.
1723 */
1724 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1725 dev->name);
1726 return -1;
1727 }
1728 } else {
1729 /* short packet. Accept only if 802 values are also short */
1730 if (protolen > ETH_ZLEN) {
1731 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1732 dev->name);
1733 return -1;
1734 }
1735 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1736 dev->name, datalen);
1737 return datalen;
1738 }
1739 }
1740
1741 static void nv_rx_process(struct net_device *dev)
1742 {
1743 struct fe_priv *np = netdev_priv(dev);
1744 u32 Flags;
1745 u32 vlanflags = 0;
1746
1747 for (;;) {
1748 struct sk_buff *skb;
1749 int len;
1750 int i;
1751 if (np->cur_rx - np->refill_rx >= np->rx_ring_size)
1752 break; /* we scanned the whole ring - do not continue */
1753
1754 i = np->cur_rx % np->rx_ring_size;
1755 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1756 Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1757 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1758 } else {
1759 Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1760 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1761 vlanflags = le32_to_cpu(np->rx_ring.ex[i].PacketBufferLow);
1762 }
1763
1764 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1765 dev->name, np->cur_rx, Flags);
1766
1767 if (Flags & NV_RX_AVAIL)
1768 break; /* still owned by hardware, */
1769
1770 /*
1771 * the packet is for us - immediately tear down the pci mapping.
1772 * TODO: check if a prefetch of the first cacheline improves
1773 * the performance.
1774 */
1775 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1776 np->rx_skbuff[i]->end-np->rx_skbuff[i]->data,
1777 PCI_DMA_FROMDEVICE);
1778
1779 {
1780 int j;
1781 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1782 for (j=0; j<64; j++) {
1783 if ((j%16) == 0)
1784 dprintk("\n%03x:", j);
1785 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1786 }
1787 dprintk("\n");
1788 }
1789 /* look at what we actually got: */
1790 if (np->desc_ver == DESC_VER_1) {
1791 if (!(Flags & NV_RX_DESCRIPTORVALID))
1792 goto next_pkt;
1793
1794 if (Flags & NV_RX_ERROR) {
1795 if (Flags & NV_RX_MISSEDFRAME) {
1796 np->stats.rx_missed_errors++;
1797 np->stats.rx_errors++;
1798 goto next_pkt;
1799 }
1800 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1801 np->stats.rx_errors++;
1802 goto next_pkt;
1803 }
1804 if (Flags & NV_RX_CRCERR) {
1805 np->stats.rx_crc_errors++;
1806 np->stats.rx_errors++;
1807 goto next_pkt;
1808 }
1809 if (Flags & NV_RX_OVERFLOW) {
1810 np->stats.rx_over_errors++;
1811 np->stats.rx_errors++;
1812 goto next_pkt;
1813 }
1814 if (Flags & NV_RX_ERROR4) {
1815 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1816 if (len < 0) {
1817 np->stats.rx_errors++;
1818 goto next_pkt;
1819 }
1820 }
1821 /* framing errors are soft errors. */
1822 if (Flags & NV_RX_FRAMINGERR) {
1823 if (Flags & NV_RX_SUBSTRACT1) {
1824 len--;
1825 }
1826 }
1827 }
1828 } else {
1829 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1830 goto next_pkt;
1831
1832 if (Flags & NV_RX2_ERROR) {
1833 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1834 np->stats.rx_errors++;
1835 goto next_pkt;
1836 }
1837 if (Flags & NV_RX2_CRCERR) {
1838 np->stats.rx_crc_errors++;
1839 np->stats.rx_errors++;
1840 goto next_pkt;
1841 }
1842 if (Flags & NV_RX2_OVERFLOW) {
1843 np->stats.rx_over_errors++;
1844 np->stats.rx_errors++;
1845 goto next_pkt;
1846 }
1847 if (Flags & NV_RX2_ERROR4) {
1848 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1849 if (len < 0) {
1850 np->stats.rx_errors++;
1851 goto next_pkt;
1852 }
1853 }
1854 /* framing errors are soft errors */
1855 if (Flags & NV_RX2_FRAMINGERR) {
1856 if (Flags & NV_RX2_SUBSTRACT1) {
1857 len--;
1858 }
1859 }
1860 }
1861 if (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) {
1862 Flags &= NV_RX2_CHECKSUMMASK;
1863 if (Flags == NV_RX2_CHECKSUMOK1 ||
1864 Flags == NV_RX2_CHECKSUMOK2 ||
1865 Flags == NV_RX2_CHECKSUMOK3) {
1866 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1867 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1868 } else {
1869 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1870 }
1871 }
1872 }
1873 /* got a valid packet - forward it to the network core */
1874 skb = np->rx_skbuff[i];
1875 np->rx_skbuff[i] = NULL;
1876
1877 skb_put(skb, len);
1878 skb->protocol = eth_type_trans(skb, dev);
1879 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1880 dev->name, np->cur_rx, len, skb->protocol);
1881 if (np->vlangrp && (vlanflags & NV_RX3_VLAN_TAG_PRESENT)) {
1882 vlan_hwaccel_rx(skb, np->vlangrp, vlanflags & NV_RX3_VLAN_TAG_MASK);
1883 } else {
1884 netif_rx(skb);
1885 }
1886 dev->last_rx = jiffies;
1887 np->stats.rx_packets++;
1888 np->stats.rx_bytes += len;
1889 next_pkt:
1890 np->cur_rx++;
1891 }
1892 }
1893
1894 static void set_bufsize(struct net_device *dev)
1895 {
1896 struct fe_priv *np = netdev_priv(dev);
1897
1898 if (dev->mtu <= ETH_DATA_LEN)
1899 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1900 else
1901 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1902 }
1903
1904 /*
1905 * nv_change_mtu: dev->change_mtu function
1906 * Called with dev_base_lock held for read.
1907 */
1908 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1909 {
1910 struct fe_priv *np = netdev_priv(dev);
1911 int old_mtu;
1912
1913 if (new_mtu < 64 || new_mtu > np->pkt_limit)
1914 return -EINVAL;
1915
1916 old_mtu = dev->mtu;
1917 dev->mtu = new_mtu;
1918
1919 /* return early if the buffer sizes will not change */
1920 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1921 return 0;
1922 if (old_mtu == new_mtu)
1923 return 0;
1924
1925 /* synchronized against open : rtnl_lock() held by caller */
1926 if (netif_running(dev)) {
1927 u8 __iomem *base = get_hwbase(dev);
1928 /*
1929 * It seems that the nic preloads valid ring entries into an
1930 * internal buffer. The procedure for flushing everything is
1931 * guessed, there is probably a simpler approach.
1932 * Changing the MTU is a rare event, it shouldn't matter.
1933 */
1934 nv_disable_irq(dev);
1935 netif_tx_lock_bh(dev);
1936 spin_lock(&np->lock);
1937 /* stop engines */
1938 nv_stop_rx(dev);
1939 nv_stop_tx(dev);
1940 nv_txrx_reset(dev);
1941 /* drain rx queue */
1942 nv_drain_rx(dev);
1943 nv_drain_tx(dev);
1944 /* reinit driver view of the rx queue */
1945 set_bufsize(dev);
1946 if (nv_init_ring(dev)) {
1947 if (!np->in_shutdown)
1948 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1949 }
1950 /* reinit nic view of the rx queue */
1951 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1952 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
1953 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
1954 base + NvRegRingSizes);
1955 pci_push(base);
1956 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1957 pci_push(base);
1958
1959 /* restart rx engine */
1960 nv_start_rx(dev);
1961 nv_start_tx(dev);
1962 spin_unlock(&np->lock);
1963 netif_tx_unlock_bh(dev);
1964 nv_enable_irq(dev);
1965 }
1966 return 0;
1967 }
1968
1969 static void nv_copy_mac_to_hw(struct net_device *dev)
1970 {
1971 u8 __iomem *base = get_hwbase(dev);
1972 u32 mac[2];
1973
1974 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1975 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1976 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1977
1978 writel(mac[0], base + NvRegMacAddrA);
1979 writel(mac[1], base + NvRegMacAddrB);
1980 }
1981
1982 /*
1983 * nv_set_mac_address: dev->set_mac_address function
1984 * Called with rtnl_lock() held.
1985 */
1986 static int nv_set_mac_address(struct net_device *dev, void *addr)
1987 {
1988 struct fe_priv *np = netdev_priv(dev);
1989 struct sockaddr *macaddr = (struct sockaddr*)addr;
1990
1991 if(!is_valid_ether_addr(macaddr->sa_data))
1992 return -EADDRNOTAVAIL;
1993
1994 /* synchronized against open : rtnl_lock() held by caller */
1995 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1996
1997 if (netif_running(dev)) {
1998 netif_tx_lock_bh(dev);
1999 spin_lock_irq(&np->lock);
2000
2001 /* stop rx engine */
2002 nv_stop_rx(dev);
2003
2004 /* set mac address */
2005 nv_copy_mac_to_hw(dev);
2006
2007 /* restart rx engine */
2008 nv_start_rx(dev);
2009 spin_unlock_irq(&np->lock);
2010 netif_tx_unlock_bh(dev);
2011 } else {
2012 nv_copy_mac_to_hw(dev);
2013 }
2014 return 0;
2015 }
2016
2017 /*
2018 * nv_set_multicast: dev->set_multicast function
2019 * Called with netif_tx_lock held.
2020 */
2021 static void nv_set_multicast(struct net_device *dev)
2022 {
2023 struct fe_priv *np = netdev_priv(dev);
2024 u8 __iomem *base = get_hwbase(dev);
2025 u32 addr[2];
2026 u32 mask[2];
2027 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2028
2029 memset(addr, 0, sizeof(addr));
2030 memset(mask, 0, sizeof(mask));
2031
2032 if (dev->flags & IFF_PROMISC) {
2033 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
2034 pff |= NVREG_PFF_PROMISC;
2035 } else {
2036 pff |= NVREG_PFF_MYADDR;
2037
2038 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2039 u32 alwaysOff[2];
2040 u32 alwaysOn[2];
2041
2042 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2043 if (dev->flags & IFF_ALLMULTI) {
2044 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2045 } else {
2046 struct dev_mc_list *walk;
2047
2048 walk = dev->mc_list;
2049 while (walk != NULL) {
2050 u32 a, b;
2051 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2052 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2053 alwaysOn[0] &= a;
2054 alwaysOff[0] &= ~a;
2055 alwaysOn[1] &= b;
2056 alwaysOff[1] &= ~b;
2057 walk = walk->next;
2058 }
2059 }
2060 addr[0] = alwaysOn[0];
2061 addr[1] = alwaysOn[1];
2062 mask[0] = alwaysOn[0] | alwaysOff[0];
2063 mask[1] = alwaysOn[1] | alwaysOff[1];
2064 }
2065 }
2066 addr[0] |= NVREG_MCASTADDRA_FORCE;
2067 pff |= NVREG_PFF_ALWAYS;
2068 spin_lock_irq(&np->lock);
2069 nv_stop_rx(dev);
2070 writel(addr[0], base + NvRegMulticastAddrA);
2071 writel(addr[1], base + NvRegMulticastAddrB);
2072 writel(mask[0], base + NvRegMulticastMaskA);
2073 writel(mask[1], base + NvRegMulticastMaskB);
2074 writel(pff, base + NvRegPacketFilterFlags);
2075 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2076 dev->name);
2077 nv_start_rx(dev);
2078 spin_unlock_irq(&np->lock);
2079 }
2080
2081 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2082 {
2083 struct fe_priv *np = netdev_priv(dev);
2084 u8 __iomem *base = get_hwbase(dev);
2085
2086 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2087
2088 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2089 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2090 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2091 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2092 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2093 } else {
2094 writel(pff, base + NvRegPacketFilterFlags);
2095 }
2096 }
2097 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2098 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2099 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2100 writel(NVREG_TX_PAUSEFRAME_ENABLE, base + NvRegTxPauseFrame);
2101 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2102 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2103 } else {
2104 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
2105 writel(regmisc, base + NvRegMisc1);
2106 }
2107 }
2108 }
2109
2110 /**
2111 * nv_update_linkspeed: Setup the MAC according to the link partner
2112 * @dev: Network device to be configured
2113 *
2114 * The function queries the PHY and checks if there is a link partner.
2115 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2116 * set to 10 MBit HD.
2117 *
2118 * The function returns 0 if there is no link partner and 1 if there is
2119 * a good link partner.
2120 */
2121 static int nv_update_linkspeed(struct net_device *dev)
2122 {
2123 struct fe_priv *np = netdev_priv(dev);
2124 u8 __iomem *base = get_hwbase(dev);
2125 int adv = 0;
2126 int lpa = 0;
2127 int adv_lpa, adv_pause, lpa_pause;
2128 int newls = np->linkspeed;
2129 int newdup = np->duplex;
2130 int mii_status;
2131 int retval = 0;
2132 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2133
2134 /* BMSR_LSTATUS is latched, read it twice:
2135 * we want the current value.
2136 */
2137 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2138 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2139
2140 if (!(mii_status & BMSR_LSTATUS)) {
2141 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2142 dev->name);
2143 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2144 newdup = 0;
2145 retval = 0;
2146 goto set_speed;
2147 }
2148
2149 if (np->autoneg == 0) {
2150 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2151 dev->name, np->fixed_mode);
2152 if (np->fixed_mode & LPA_100FULL) {
2153 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2154 newdup = 1;
2155 } else if (np->fixed_mode & LPA_100HALF) {
2156 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2157 newdup = 0;
2158 } else if (np->fixed_mode & LPA_10FULL) {
2159 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2160 newdup = 1;
2161 } else {
2162 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2163 newdup = 0;
2164 }
2165 retval = 1;
2166 goto set_speed;
2167 }
2168 /* check auto negotiation is complete */
2169 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2170 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2171 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2172 newdup = 0;
2173 retval = 0;
2174 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2175 goto set_speed;
2176 }
2177
2178 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2179 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2180 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2181 dev->name, adv, lpa);
2182
2183 retval = 1;
2184 if (np->gigabit == PHY_GIGABIT) {
2185 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2186 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2187
2188 if ((control_1000 & ADVERTISE_1000FULL) &&
2189 (status_1000 & LPA_1000FULL)) {
2190 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2191 dev->name);
2192 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2193 newdup = 1;
2194 goto set_speed;
2195 }
2196 }
2197
2198 /* FIXME: handle parallel detection properly */
2199 adv_lpa = lpa & adv;
2200 if (adv_lpa & LPA_100FULL) {
2201 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2202 newdup = 1;
2203 } else if (adv_lpa & LPA_100HALF) {
2204 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2205 newdup = 0;
2206 } else if (adv_lpa & LPA_10FULL) {
2207 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2208 newdup = 1;
2209 } else if (adv_lpa & LPA_10HALF) {
2210 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2211 newdup = 0;
2212 } else {
2213 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2214 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2215 newdup = 0;
2216 }
2217
2218 set_speed:
2219 if (np->duplex == newdup && np->linkspeed == newls)
2220 return retval;
2221
2222 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2223 dev->name, np->linkspeed, np->duplex, newls, newdup);
2224
2225 np->duplex = newdup;
2226 np->linkspeed = newls;
2227
2228 if (np->gigabit == PHY_GIGABIT) {
2229 phyreg = readl(base + NvRegRandomSeed);
2230 phyreg &= ~(0x3FF00);
2231 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2232 phyreg |= NVREG_RNDSEED_FORCE3;
2233 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2234 phyreg |= NVREG_RNDSEED_FORCE2;
2235 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2236 phyreg |= NVREG_RNDSEED_FORCE;
2237 writel(phyreg, base + NvRegRandomSeed);
2238 }
2239
2240 phyreg = readl(base + NvRegPhyInterface);
2241 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2242 if (np->duplex == 0)
2243 phyreg |= PHY_HALF;
2244 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2245 phyreg |= PHY_100;
2246 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2247 phyreg |= PHY_1000;
2248 writel(phyreg, base + NvRegPhyInterface);
2249
2250 if (phyreg & PHY_RGMII) {
2251 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2252 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2253 else
2254 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2255 } else {
2256 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2257 }
2258 writel(txreg, base + NvRegTxDeferral);
2259
2260 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2261 base + NvRegMisc1);
2262 pci_push(base);
2263 writel(np->linkspeed, base + NvRegLinkSpeed);
2264 pci_push(base);
2265
2266 pause_flags = 0;
2267 /* setup pause frame */
2268 if (np->duplex != 0) {
2269 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2270 adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2271 lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2272
2273 switch (adv_pause) {
2274 case (ADVERTISE_PAUSE_CAP):
2275 if (lpa_pause & LPA_PAUSE_CAP) {
2276 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2277 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2278 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2279 }
2280 break;
2281 case (ADVERTISE_PAUSE_ASYM):
2282 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2283 {
2284 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2285 }
2286 break;
2287 case (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM):
2288 if (lpa_pause & LPA_PAUSE_CAP)
2289 {
2290 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2291 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2292 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2293 }
2294 if (lpa_pause == LPA_PAUSE_ASYM)
2295 {
2296 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2297 }
2298 break;
2299 }
2300 } else {
2301 pause_flags = np->pause_flags;
2302 }
2303 }
2304 nv_update_pause(dev, pause_flags);
2305
2306 return retval;
2307 }
2308
2309 static void nv_linkchange(struct net_device *dev)
2310 {
2311 if (nv_update_linkspeed(dev)) {
2312 if (!netif_carrier_ok(dev)) {
2313 netif_carrier_on(dev);
2314 printk(KERN_INFO "%s: link up.\n", dev->name);
2315 nv_start_rx(dev);
2316 }
2317 } else {
2318 if (netif_carrier_ok(dev)) {
2319 netif_carrier_off(dev);
2320 printk(KERN_INFO "%s: link down.\n", dev->name);
2321 nv_stop_rx(dev);
2322 }
2323 }
2324 }
2325
2326 static void nv_link_irq(struct net_device *dev)
2327 {
2328 u8 __iomem *base = get_hwbase(dev);
2329 u32 miistat;
2330
2331 miistat = readl(base + NvRegMIIStatus);
2332 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2333 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2334
2335 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2336 nv_linkchange(dev);
2337 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2338 }
2339
2340 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
2341 {
2342 struct net_device *dev = (struct net_device *) data;
2343 struct fe_priv *np = netdev_priv(dev);
2344 u8 __iomem *base = get_hwbase(dev);
2345 u32 events;
2346 int i;
2347
2348 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2349
2350 for (i=0; ; i++) {
2351 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2352 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2353 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2354 } else {
2355 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2356 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2357 }
2358 pci_push(base);
2359 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2360 if (!(events & np->irqmask))
2361 break;
2362
2363 spin_lock(&np->lock);
2364 nv_tx_done(dev);
2365 spin_unlock(&np->lock);
2366
2367 nv_rx_process(dev);
2368 if (nv_alloc_rx(dev)) {
2369 spin_lock(&np->lock);
2370 if (!np->in_shutdown)
2371 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2372 spin_unlock(&np->lock);
2373 }
2374
2375 if (events & NVREG_IRQ_LINK) {
2376 spin_lock(&np->lock);
2377 nv_link_irq(dev);
2378 spin_unlock(&np->lock);
2379 }
2380 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2381 spin_lock(&np->lock);
2382 nv_linkchange(dev);
2383 spin_unlock(&np->lock);
2384 np->link_timeout = jiffies + LINK_TIMEOUT;
2385 }
2386 if (events & (NVREG_IRQ_TX_ERR)) {
2387 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2388 dev->name, events);
2389 }
2390 if (events & (NVREG_IRQ_UNKNOWN)) {
2391 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2392 dev->name, events);
2393 }
2394 if (i > max_interrupt_work) {
2395 spin_lock(&np->lock);
2396 /* disable interrupts on the nic */
2397 if (!(np->msi_flags & NV_MSI_X_ENABLED))
2398 writel(0, base + NvRegIrqMask);
2399 else
2400 writel(np->irqmask, base + NvRegIrqMask);
2401 pci_push(base);
2402
2403 if (!np->in_shutdown) {
2404 np->nic_poll_irq = np->irqmask;
2405 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2406 }
2407 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
2408 spin_unlock(&np->lock);
2409 break;
2410 }
2411
2412 }
2413 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
2414
2415 return IRQ_RETVAL(i);
2416 }
2417
2418 static irqreturn_t nv_nic_irq_tx(int foo, void *data, struct pt_regs *regs)
2419 {
2420 struct net_device *dev = (struct net_device *) data;
2421 struct fe_priv *np = netdev_priv(dev);
2422 u8 __iomem *base = get_hwbase(dev);
2423 u32 events;
2424 int i;
2425
2426 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
2427
2428 for (i=0; ; i++) {
2429 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
2430 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
2431 pci_push(base);
2432 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
2433 if (!(events & np->irqmask))
2434 break;
2435
2436 spin_lock_irq(&np->lock);
2437 nv_tx_done(dev);
2438 spin_unlock_irq(&np->lock);
2439
2440 if (events & (NVREG_IRQ_TX_ERR)) {
2441 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
2442 dev->name, events);
2443 }
2444 if (i > max_interrupt_work) {
2445 spin_lock_irq(&np->lock);
2446 /* disable interrupts on the nic */
2447 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
2448 pci_push(base);
2449
2450 if (!np->in_shutdown) {
2451 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
2452 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2453 }
2454 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
2455 spin_unlock_irq(&np->lock);
2456 break;
2457 }
2458
2459 }
2460 dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
2461
2462 return IRQ_RETVAL(i);
2463 }
2464
2465 static irqreturn_t nv_nic_irq_rx(int foo, void *data, struct pt_regs *regs)
2466 {
2467 struct net_device *dev = (struct net_device *) data;
2468 struct fe_priv *np = netdev_priv(dev);
2469 u8 __iomem *base = get_hwbase(dev);
2470 u32 events;
2471 int i;
2472
2473 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
2474
2475 for (i=0; ; i++) {
2476 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
2477 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
2478 pci_push(base);
2479 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
2480 if (!(events & np->irqmask))
2481 break;
2482
2483 nv_rx_process(dev);
2484 if (nv_alloc_rx(dev)) {
2485 spin_lock_irq(&np->lock);
2486 if (!np->in_shutdown)
2487 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2488 spin_unlock_irq(&np->lock);
2489 }
2490
2491 if (i > max_interrupt_work) {
2492 spin_lock_irq(&np->lock);
2493 /* disable interrupts on the nic */
2494 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
2495 pci_push(base);
2496
2497 if (!np->in_shutdown) {
2498 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
2499 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2500 }
2501 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
2502 spin_unlock_irq(&np->lock);
2503 break;
2504 }
2505
2506 }
2507 dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
2508
2509 return IRQ_RETVAL(i);
2510 }
2511
2512 static irqreturn_t nv_nic_irq_other(int foo, void *data, struct pt_regs *regs)
2513 {
2514 struct net_device *dev = (struct net_device *) data;
2515 struct fe_priv *np = netdev_priv(dev);
2516 u8 __iomem *base = get_hwbase(dev);
2517 u32 events;
2518 int i;
2519
2520 dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
2521
2522 for (i=0; ; i++) {
2523 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
2524 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
2525 pci_push(base);
2526 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2527 if (!(events & np->irqmask))
2528 break;
2529
2530 if (events & NVREG_IRQ_LINK) {
2531 spin_lock_irq(&np->lock);
2532 nv_link_irq(dev);
2533 spin_unlock_irq(&np->lock);
2534 }
2535 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
2536 spin_lock_irq(&np->lock);
2537 nv_linkchange(dev);
2538 spin_unlock_irq(&np->lock);
2539 np->link_timeout = jiffies + LINK_TIMEOUT;
2540 }
2541 if (events & (NVREG_IRQ_UNKNOWN)) {
2542 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
2543 dev->name, events);
2544 }
2545 if (i > max_interrupt_work) {
2546 spin_lock_irq(&np->lock);
2547 /* disable interrupts on the nic */
2548 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
2549 pci_push(base);
2550
2551 if (!np->in_shutdown) {
2552 np->nic_poll_irq |= NVREG_IRQ_OTHER;
2553 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
2554 }
2555 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
2556 spin_unlock_irq(&np->lock);
2557 break;
2558 }
2559
2560 }
2561 dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
2562
2563 return IRQ_RETVAL(i);
2564 }
2565
2566 static irqreturn_t nv_nic_irq_test(int foo, void *data, struct pt_regs *regs)
2567 {
2568 struct net_device *dev = (struct net_device *) data;
2569 struct fe_priv *np = netdev_priv(dev);
2570 u8 __iomem *base = get_hwbase(dev);
2571 u32 events;
2572
2573 dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
2574
2575 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2576 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2577 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
2578 } else {
2579 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2580 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
2581 }
2582 pci_push(base);
2583 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
2584 if (!(events & NVREG_IRQ_TIMER))
2585 return IRQ_RETVAL(0);
2586
2587 spin_lock(&np->lock);
2588 np->intr_test = 1;
2589 spin_unlock(&np->lock);
2590
2591 dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
2592
2593 return IRQ_RETVAL(1);
2594 }
2595
2596 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
2597 {
2598 u8 __iomem *base = get_hwbase(dev);
2599 int i;
2600 u32 msixmap = 0;
2601
2602 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
2603 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
2604 * the remaining 8 interrupts.
2605 */
2606 for (i = 0; i < 8; i++) {
2607 if ((irqmask >> i) & 0x1) {
2608 msixmap |= vector << (i << 2);
2609 }
2610 }
2611 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
2612
2613 msixmap = 0;
2614 for (i = 0; i < 8; i++) {
2615 if ((irqmask >> (i + 8)) & 0x1) {
2616 msixmap |= vector << (i << 2);
2617 }
2618 }
2619 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
2620 }
2621
2622 static int nv_request_irq(struct net_device *dev, int intr_test)
2623 {
2624 struct fe_priv *np = get_nvpriv(dev);
2625 u8 __iomem *base = get_hwbase(dev);
2626 int ret = 1;
2627 int i;
2628
2629 if (np->msi_flags & NV_MSI_X_CAPABLE) {
2630 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2631 np->msi_x_entry[i].entry = i;
2632 }
2633 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
2634 np->msi_flags |= NV_MSI_X_ENABLED;
2635 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
2636 /* Request irq for rx handling */
2637 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
2638 printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
2639 pci_disable_msix(np->pci_dev);
2640 np->msi_flags &= ~NV_MSI_X_ENABLED;
2641 goto out_err;
2642 }
2643 /* Request irq for tx handling */
2644 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
2645 printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
2646 pci_disable_msix(np->pci_dev);
2647 np->msi_flags &= ~NV_MSI_X_ENABLED;
2648 goto out_free_rx;
2649 }
2650 /* Request irq for link and timer handling */
2651 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
2652 printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
2653 pci_disable_msix(np->pci_dev);
2654 np->msi_flags &= ~NV_MSI_X_ENABLED;
2655 goto out_free_tx;
2656 }
2657 /* map interrupts to their respective vector */
2658 writel(0, base + NvRegMSIXMap0);
2659 writel(0, base + NvRegMSIXMap1);
2660 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
2661 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
2662 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
2663 } else {
2664 /* Request irq for all interrupts */
2665 if ((!intr_test &&
2666 request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2667 (intr_test &&
2668 request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2669 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2670 pci_disable_msix(np->pci_dev);
2671 np->msi_flags &= ~NV_MSI_X_ENABLED;
2672 goto out_err;
2673 }
2674
2675 /* map interrupts to vector 0 */
2676 writel(0, base + NvRegMSIXMap0);
2677 writel(0, base + NvRegMSIXMap1);
2678 }
2679 }
2680 }
2681 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
2682 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
2683 np->msi_flags |= NV_MSI_ENABLED;
2684 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2685 (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0)) {
2686 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
2687 pci_disable_msi(np->pci_dev);
2688 np->msi_flags &= ~NV_MSI_ENABLED;
2689 goto out_err;
2690 }
2691
2692 /* map interrupts to vector 0 */
2693 writel(0, base + NvRegMSIMap0);
2694 writel(0, base + NvRegMSIMap1);
2695 /* enable msi vector 0 */
2696 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
2697 }
2698 }
2699 if (ret != 0) {
2700 if ((!intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq, IRQF_SHARED, dev->name, dev) != 0) ||
2701 (intr_test && request_irq(np->pci_dev->irq, &nv_nic_irq_test, IRQF_SHARED, dev->name, dev) != 0))
2702 goto out_err;
2703
2704 }
2705
2706 return 0;
2707 out_free_tx:
2708 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
2709 out_free_rx:
2710 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
2711 out_err:
2712 return 1;
2713 }
2714
2715 static void nv_free_irq(struct net_device *dev)
2716 {
2717 struct fe_priv *np = get_nvpriv(dev);
2718 int i;
2719
2720 if (np->msi_flags & NV_MSI_X_ENABLED) {
2721 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
2722 free_irq(np->msi_x_entry[i].vector, dev);
2723 }
2724 pci_disable_msix(np->pci_dev);
2725 np->msi_flags &= ~NV_MSI_X_ENABLED;
2726 } else {
2727 free_irq(np->pci_dev->irq, dev);
2728 if (np->msi_flags & NV_MSI_ENABLED) {
2729 pci_disable_msi(np->pci_dev);
2730 np->msi_flags &= ~NV_MSI_ENABLED;
2731 }
2732 }
2733 }
2734
2735 static void nv_do_nic_poll(unsigned long data)
2736 {
2737 struct net_device *dev = (struct net_device *) data;
2738 struct fe_priv *np = netdev_priv(dev);
2739 u8 __iomem *base = get_hwbase(dev);
2740 u32 mask = 0;
2741
2742 /*
2743 * First disable irq(s) and then
2744 * reenable interrupts on the nic, we have to do this before calling
2745 * nv_nic_irq because that may decide to do otherwise
2746 */
2747
2748 if (!using_multi_irqs(dev)) {
2749 if (np->msi_flags & NV_MSI_X_ENABLED)
2750 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2751 else
2752 disable_irq_lockdep(dev->irq);
2753 mask = np->irqmask;
2754 } else {
2755 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2756 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2757 mask |= NVREG_IRQ_RX_ALL;
2758 }
2759 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2760 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2761 mask |= NVREG_IRQ_TX_ALL;
2762 }
2763 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2764 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2765 mask |= NVREG_IRQ_OTHER;
2766 }
2767 }
2768 np->nic_poll_irq = 0;
2769
2770 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
2771
2772 writel(mask, base + NvRegIrqMask);
2773 pci_push(base);
2774
2775 if (!using_multi_irqs(dev)) {
2776 nv_nic_irq(0, dev, NULL);
2777 if (np->msi_flags & NV_MSI_X_ENABLED)
2778 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
2779 else
2780 enable_irq_lockdep(dev->irq);
2781 } else {
2782 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
2783 nv_nic_irq_rx(0, dev, NULL);
2784 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
2785 }
2786 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
2787 nv_nic_irq_tx(0, dev, NULL);
2788 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
2789 }
2790 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
2791 nv_nic_irq_other(0, dev, NULL);
2792 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
2793 }
2794 }
2795 }
2796
2797 #ifdef CONFIG_NET_POLL_CONTROLLER
2798 static void nv_poll_controller(struct net_device *dev)
2799 {
2800 nv_do_nic_poll((unsigned long) dev);
2801 }
2802 #endif
2803
2804 static void nv_do_stats_poll(unsigned long data)
2805 {
2806 struct net_device *dev = (struct net_device *) data;
2807 struct fe_priv *np = netdev_priv(dev);
2808 u8 __iomem *base = get_hwbase(dev);
2809
2810 np->estats.tx_bytes += readl(base + NvRegTxCnt);
2811 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
2812 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
2813 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
2814 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
2815 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
2816 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
2817 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
2818 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
2819 np->estats.tx_deferral += readl(base + NvRegTxDef);
2820 np->estats.tx_packets += readl(base + NvRegTxFrame);
2821 np->estats.tx_pause += readl(base + NvRegTxPause);
2822 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
2823 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
2824 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
2825 np->estats.rx_runt += readl(base + NvRegRxRunt);
2826 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
2827 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
2828 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
2829 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
2830 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
2831 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
2832 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
2833 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
2834 np->estats.rx_bytes += readl(base + NvRegRxCnt);
2835 np->estats.rx_pause += readl(base + NvRegRxPause);
2836 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
2837 np->estats.rx_packets =
2838 np->estats.rx_unicast +
2839 np->estats.rx_multicast +
2840 np->estats.rx_broadcast;
2841 np->estats.rx_errors_total =
2842 np->estats.rx_crc_errors +
2843 np->estats.rx_over_errors +
2844 np->estats.rx_frame_error +
2845 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
2846 np->estats.rx_late_collision +
2847 np->estats.rx_runt +
2848 np->estats.rx_frame_too_long;
2849
2850 if (!np->in_shutdown)
2851 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
2852 }
2853
2854 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2855 {
2856 struct fe_priv *np = netdev_priv(dev);
2857 strcpy(info->driver, "forcedeth");
2858 strcpy(info->version, FORCEDETH_VERSION);
2859 strcpy(info->bus_info, pci_name(np->pci_dev));
2860 }
2861
2862 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2863 {
2864 struct fe_priv *np = netdev_priv(dev);
2865 wolinfo->supported = WAKE_MAGIC;
2866
2867 spin_lock_irq(&np->lock);
2868 if (np->wolenabled)
2869 wolinfo->wolopts = WAKE_MAGIC;
2870 spin_unlock_irq(&np->lock);
2871 }
2872
2873 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
2874 {
2875 struct fe_priv *np = netdev_priv(dev);
2876 u8 __iomem *base = get_hwbase(dev);
2877 u32 flags = 0;
2878
2879 if (wolinfo->wolopts == 0) {
2880 np->wolenabled = 0;
2881 } else if (wolinfo->wolopts & WAKE_MAGIC) {
2882 np->wolenabled = 1;
2883 flags = NVREG_WAKEUPFLAGS_ENABLE;
2884 }
2885 if (netif_running(dev)) {
2886 spin_lock_irq(&np->lock);
2887 writel(flags, base + NvRegWakeUpFlags);
2888 spin_unlock_irq(&np->lock);
2889 }
2890 return 0;
2891 }
2892
2893 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2894 {
2895 struct fe_priv *np = netdev_priv(dev);
2896 int adv;
2897
2898 spin_lock_irq(&np->lock);
2899 ecmd->port = PORT_MII;
2900 if (!netif_running(dev)) {
2901 /* We do not track link speed / duplex setting if the
2902 * interface is disabled. Force a link check */
2903 if (nv_update_linkspeed(dev)) {
2904 if (!netif_carrier_ok(dev))
2905 netif_carrier_on(dev);
2906 } else {
2907 if (netif_carrier_ok(dev))
2908 netif_carrier_off(dev);
2909 }
2910 }
2911
2912 if (netif_carrier_ok(dev)) {
2913 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
2914 case NVREG_LINKSPEED_10:
2915 ecmd->speed = SPEED_10;
2916 break;
2917 case NVREG_LINKSPEED_100:
2918 ecmd->speed = SPEED_100;
2919 break;
2920 case NVREG_LINKSPEED_1000:
2921 ecmd->speed = SPEED_1000;
2922 break;
2923 }
2924 ecmd->duplex = DUPLEX_HALF;
2925 if (np->duplex)
2926 ecmd->duplex = DUPLEX_FULL;
2927 } else {
2928 ecmd->speed = -1;
2929 ecmd->duplex = -1;
2930 }
2931
2932 ecmd->autoneg = np->autoneg;
2933
2934 ecmd->advertising = ADVERTISED_MII;
2935 if (np->autoneg) {
2936 ecmd->advertising |= ADVERTISED_Autoneg;
2937 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2938 if (adv & ADVERTISE_10HALF)
2939 ecmd->advertising |= ADVERTISED_10baseT_Half;
2940 if (adv & ADVERTISE_10FULL)
2941 ecmd->advertising |= ADVERTISED_10baseT_Full;
2942 if (adv & ADVERTISE_100HALF)
2943 ecmd->advertising |= ADVERTISED_100baseT_Half;
2944 if (adv & ADVERTISE_100FULL)
2945 ecmd->advertising |= ADVERTISED_100baseT_Full;
2946 if (np->gigabit == PHY_GIGABIT) {
2947 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2948 if (adv & ADVERTISE_1000FULL)
2949 ecmd->advertising |= ADVERTISED_1000baseT_Full;
2950 }
2951 }
2952 ecmd->supported = (SUPPORTED_Autoneg |
2953 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2954 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2955 SUPPORTED_MII);
2956 if (np->gigabit == PHY_GIGABIT)
2957 ecmd->supported |= SUPPORTED_1000baseT_Full;
2958
2959 ecmd->phy_address = np->phyaddr;
2960 ecmd->transceiver = XCVR_EXTERNAL;
2961
2962 /* ignore maxtxpkt, maxrxpkt for now */
2963 spin_unlock_irq(&np->lock);
2964 return 0;
2965 }
2966
2967 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2968 {
2969 struct fe_priv *np = netdev_priv(dev);
2970
2971 if (ecmd->port != PORT_MII)
2972 return -EINVAL;
2973 if (ecmd->transceiver != XCVR_EXTERNAL)
2974 return -EINVAL;
2975 if (ecmd->phy_address != np->phyaddr) {
2976 /* TODO: support switching between multiple phys. Should be
2977 * trivial, but not enabled due to lack of test hardware. */
2978 return -EINVAL;
2979 }
2980 if (ecmd->autoneg == AUTONEG_ENABLE) {
2981 u32 mask;
2982
2983 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2984 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
2985 if (np->gigabit == PHY_GIGABIT)
2986 mask |= ADVERTISED_1000baseT_Full;
2987
2988 if ((ecmd->advertising & mask) == 0)
2989 return -EINVAL;
2990
2991 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2992 /* Note: autonegotiation disable, speed 1000 intentionally
2993 * forbidden - noone should need that. */
2994
2995 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2996 return -EINVAL;
2997 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2998 return -EINVAL;
2999 } else {
3000 return -EINVAL;
3001 }
3002
3003 netif_carrier_off(dev);
3004 if (netif_running(dev)) {
3005 nv_disable_irq(dev);
3006 netif_tx_lock_bh(dev);
3007 spin_lock(&np->lock);
3008 /* stop engines */
3009 nv_stop_rx(dev);
3010 nv_stop_tx(dev);
3011 spin_unlock(&np->lock);
3012 netif_tx_unlock_bh(dev);
3013 }
3014
3015 if (ecmd->autoneg == AUTONEG_ENABLE) {
3016 int adv, bmcr;
3017
3018 np->autoneg = 1;
3019
3020 /* advertise only what has been requested */
3021 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3022 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3023 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3024 adv |= ADVERTISE_10HALF;
3025 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3026 adv |= ADVERTISE_10FULL;
3027 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3028 adv |= ADVERTISE_100HALF;
3029 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3030 adv |= ADVERTISE_100FULL;
3031 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3032 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3033 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3034 adv |= ADVERTISE_PAUSE_ASYM;
3035 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3036
3037 if (np->gigabit == PHY_GIGABIT) {
3038 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3039 adv &= ~ADVERTISE_1000FULL;
3040 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3041 adv |= ADVERTISE_1000FULL;
3042 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3043 }
3044
3045 if (netif_running(dev))
3046 printk(KERN_INFO "%s: link down.\n", dev->name);
3047 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3048 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3049 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3050
3051 } else {
3052 int adv, bmcr;
3053
3054 np->autoneg = 0;
3055
3056 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3057 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3058 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3059 adv |= ADVERTISE_10HALF;
3060 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3061 adv |= ADVERTISE_10FULL;
3062 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3063 adv |= ADVERTISE_100HALF;
3064 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3065 adv |= ADVERTISE_100FULL;
3066 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3067 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3068 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3069 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3070 }
3071 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3072 adv |= ADVERTISE_PAUSE_ASYM;
3073 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3074 }
3075 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3076 np->fixed_mode = adv;
3077
3078 if (np->gigabit == PHY_GIGABIT) {
3079 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3080 adv &= ~ADVERTISE_1000FULL;
3081 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3082 }
3083
3084 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3085 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3086 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3087 bmcr |= BMCR_FULLDPLX;
3088 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3089 bmcr |= BMCR_SPEED100;
3090 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3091 if (np->phy_oui == PHY_OUI_MARVELL) {
3092 /* reset the phy */
3093 if (phy_reset(dev)) {
3094 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3095 return -EINVAL;
3096 }
3097 } else if (netif_running(dev)) {
3098 /* Wait a bit and then reconfigure the nic. */
3099 udelay(10);
3100 nv_linkchange(dev);
3101 }
3102 }
3103
3104 if (netif_running(dev)) {
3105 nv_start_rx(dev);
3106 nv_start_tx(dev);
3107 nv_enable_irq(dev);
3108 }
3109
3110 return 0;
3111 }
3112
3113 #define FORCEDETH_REGS_VER 1
3114
3115 static int nv_get_regs_len(struct net_device *dev)
3116 {
3117 struct fe_priv *np = netdev_priv(dev);
3118 return np->register_size;
3119 }
3120
3121 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
3122 {
3123 struct fe_priv *np = netdev_priv(dev);
3124 u8 __iomem *base = get_hwbase(dev);
3125 u32 *rbuf = buf;
3126 int i;
3127
3128 regs->version = FORCEDETH_REGS_VER;
3129 spin_lock_irq(&np->lock);
3130 for (i = 0;i <= np->register_size/sizeof(u32); i++)
3131 rbuf[i] = readl(base + i*sizeof(u32));
3132 spin_unlock_irq(&np->lock);
3133 }
3134
3135 static int nv_nway_reset(struct net_device *dev)
3136 {
3137 struct fe_priv *np = netdev_priv(dev);
3138 int ret;
3139
3140 if (np->autoneg) {
3141 int bmcr;
3142
3143 netif_carrier_off(dev);
3144 if (netif_running(dev)) {
3145 nv_disable_irq(dev);
3146 netif_tx_lock_bh(dev);
3147 spin_lock(&np->lock);
3148 /* stop engines */
3149 nv_stop_rx(dev);
3150 nv_stop_tx(dev);
3151 spin_unlock(&np->lock);
3152 netif_tx_unlock_bh(dev);
3153 printk(KERN_INFO "%s: link down.\n", dev->name);
3154 }
3155
3156 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3157 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3158 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3159
3160 if (netif_running(dev)) {
3161 nv_start_rx(dev);
3162 nv_start_tx(dev);
3163 nv_enable_irq(dev);
3164 }
3165 ret = 0;
3166 } else {
3167 ret = -EINVAL;
3168 }
3169
3170 return ret;
3171 }
3172
3173 static int nv_set_tso(struct net_device *dev, u32 value)
3174 {
3175 struct fe_priv *np = netdev_priv(dev);
3176
3177 if ((np->driver_data & DEV_HAS_CHECKSUM))
3178 return ethtool_op_set_tso(dev, value);
3179 else
3180 return -EOPNOTSUPP;
3181 }
3182
3183 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3184 {
3185 struct fe_priv *np = netdev_priv(dev);
3186
3187 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3188 ring->rx_mini_max_pending = 0;
3189 ring->rx_jumbo_max_pending = 0;
3190 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
3191
3192 ring->rx_pending = np->rx_ring_size;
3193 ring->rx_mini_pending = 0;
3194 ring->rx_jumbo_pending = 0;
3195 ring->tx_pending = np->tx_ring_size;
3196 }
3197
3198 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
3199 {
3200 struct fe_priv *np = netdev_priv(dev);
3201 u8 __iomem *base = get_hwbase(dev);
3202 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff, *rx_dma, *tx_dma, *tx_dma_len;
3203 dma_addr_t ring_addr;
3204
3205 if (ring->rx_pending < RX_RING_MIN ||
3206 ring->tx_pending < TX_RING_MIN ||
3207 ring->rx_mini_pending != 0 ||
3208 ring->rx_jumbo_pending != 0 ||
3209 (np->desc_ver == DESC_VER_1 &&
3210 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
3211 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
3212 (np->desc_ver != DESC_VER_1 &&
3213 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
3214 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
3215 return -EINVAL;
3216 }
3217
3218 /* allocate new rings */
3219 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3220 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3221 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3222 &ring_addr);
3223 } else {
3224 rxtx_ring = pci_alloc_consistent(np->pci_dev,
3225 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3226 &ring_addr);
3227 }
3228 rx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->rx_pending, GFP_KERNEL);
3229 rx_dma = kmalloc(sizeof(dma_addr_t) * ring->rx_pending, GFP_KERNEL);
3230 tx_skbuff = kmalloc(sizeof(struct sk_buff*) * ring->tx_pending, GFP_KERNEL);
3231 tx_dma = kmalloc(sizeof(dma_addr_t) * ring->tx_pending, GFP_KERNEL);
3232 tx_dma_len = kmalloc(sizeof(unsigned int) * ring->tx_pending, GFP_KERNEL);
3233 if (!rxtx_ring || !rx_skbuff || !rx_dma || !tx_skbuff || !tx_dma || !tx_dma_len) {
3234 /* fall back to old rings */
3235 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3236 if(rxtx_ring)
3237 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
3238 rxtx_ring, ring_addr);
3239 } else {
3240 if (rxtx_ring)
3241 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
3242 rxtx_ring, ring_addr);
3243 }
3244 if (rx_skbuff)
3245 kfree(rx_skbuff);
3246 if (rx_dma)
3247 kfree(rx_dma);
3248 if (tx_skbuff)
3249 kfree(tx_skbuff);
3250 if (tx_dma)
3251 kfree(tx_dma);
3252 if (tx_dma_len)
3253 kfree(tx_dma_len);
3254 goto exit;
3255 }
3256
3257 if (netif_running(dev)) {
3258 nv_disable_irq(dev);
3259 netif_tx_lock_bh(dev);
3260 spin_lock(&np->lock);
3261 /* stop engines */
3262 nv_stop_rx(dev);
3263 nv_stop_tx(dev);
3264 nv_txrx_reset(dev);
3265 /* drain queues */
3266 nv_drain_rx(dev);
3267 nv_drain_tx(dev);
3268 /* delete queues */
3269 free_rings(dev);
3270 }
3271
3272 /* set new values */
3273 np->rx_ring_size = ring->rx_pending;
3274 np->tx_ring_size = ring->tx_pending;
3275 np->tx_limit_stop = ring->tx_pending - TX_LIMIT_DIFFERENCE;
3276 np->tx_limit_start = ring->tx_pending - TX_LIMIT_DIFFERENCE - 1;
3277 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3278 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
3279 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
3280 } else {
3281 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
3282 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
3283 }
3284 np->rx_skbuff = (struct sk_buff**)rx_skbuff;
3285 np->rx_dma = (dma_addr_t*)rx_dma;
3286 np->tx_skbuff = (struct sk_buff**)tx_skbuff;
3287 np->tx_dma = (dma_addr_t*)tx_dma;
3288 np->tx_dma_len = (unsigned int*)tx_dma_len;
3289 np->ring_addr = ring_addr;
3290
3291 memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
3292 memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
3293 memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
3294 memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
3295 memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
3296
3297 if (netif_running(dev)) {
3298 /* reinit driver view of the queues */
3299 set_bufsize(dev);
3300 if (nv_init_ring(dev)) {
3301 if (!np->in_shutdown)
3302 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3303 }
3304
3305 /* reinit nic view of the queues */
3306 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3307 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3308 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3309 base + NvRegRingSizes);
3310 pci_push(base);
3311 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3312 pci_push(base);
3313
3314 /* restart engines */
3315 nv_start_rx(dev);
3316 nv_start_tx(dev);
3317 spin_unlock(&np->lock);
3318 netif_tx_unlock_bh(dev);
3319 nv_enable_irq(dev);
3320 }
3321 return 0;
3322 exit:
3323 return -ENOMEM;
3324 }
3325
3326 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3327 {
3328 struct fe_priv *np = netdev_priv(dev);
3329
3330 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
3331 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
3332 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
3333 }
3334
3335 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
3336 {
3337 struct fe_priv *np = netdev_priv(dev);
3338 int adv, bmcr;
3339
3340 if ((!np->autoneg && np->duplex == 0) ||
3341 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
3342 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
3343 dev->name);
3344 return -EINVAL;
3345 }
3346 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
3347 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
3348 return -EINVAL;
3349 }
3350
3351 netif_carrier_off(dev);
3352 if (netif_running(dev)) {
3353 nv_disable_irq(dev);
3354 netif_tx_lock_bh(dev);
3355 spin_lock(&np->lock);
3356 /* stop engines */
3357 nv_stop_rx(dev);
3358 nv_stop_tx(dev);
3359 spin_unlock(&np->lock);
3360 netif_tx_unlock_bh(dev);
3361 }
3362
3363 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
3364 if (pause->rx_pause)
3365 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
3366 if (pause->tx_pause)
3367 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
3368
3369 if (np->autoneg && pause->autoneg) {
3370 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
3371
3372 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3373 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3374 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
3375 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3376 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3377 adv |= ADVERTISE_PAUSE_ASYM;
3378 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3379
3380 if (netif_running(dev))
3381 printk(KERN_INFO "%s: link down.\n", dev->name);
3382 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3383 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3384 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3385 } else {
3386 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3387 if (pause->rx_pause)
3388 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3389 if (pause->tx_pause)
3390 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3391
3392 if (!netif_running(dev))
3393 nv_update_linkspeed(dev);
3394 else
3395 nv_update_pause(dev, np->pause_flags);
3396 }
3397
3398 if (netif_running(dev)) {
3399 nv_start_rx(dev);
3400 nv_start_tx(dev);
3401 nv_enable_irq(dev);
3402 }
3403 return 0;
3404 }
3405
3406 static u32 nv_get_rx_csum(struct net_device *dev)
3407 {
3408 struct fe_priv *np = netdev_priv(dev);
3409 return (np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) != 0;
3410 }
3411
3412 static int nv_set_rx_csum(struct net_device *dev, u32 data)
3413 {
3414 struct fe_priv *np = netdev_priv(dev);
3415 u8 __iomem *base = get_hwbase(dev);
3416 int retcode = 0;
3417
3418 if (np->driver_data & DEV_HAS_CHECKSUM) {
3419
3420 if (((np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && data) ||
3421 (!(np->txrxctl_bits & NVREG_TXRXCTL_RXCHECK) && !data)) {
3422 /* already set or unset */
3423 return 0;
3424 }
3425
3426 if (data) {
3427 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
3428 } else if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) {
3429 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
3430 } else {
3431 printk(KERN_INFO "Can not disable rx checksum if vlan is enabled\n");
3432 return -EINVAL;
3433 }
3434
3435 if (netif_running(dev)) {
3436 spin_lock_irq(&np->lock);
3437 writel(np->txrxctl_bits, base + NvRegTxRxControl);
3438 spin_unlock_irq(&np->lock);
3439 }
3440 } else {
3441 return -EINVAL;
3442 }
3443
3444 return retcode;
3445 }
3446
3447 static int nv_set_tx_csum(struct net_device *dev, u32 data)
3448 {
3449 struct fe_priv *np = netdev_priv(dev);
3450
3451 if (np->driver_data & DEV_HAS_CHECKSUM)
3452 return ethtool_op_set_tx_hw_csum(dev, data);
3453 else
3454 return -EOPNOTSUPP;
3455 }
3456
3457 static int nv_set_sg(struct net_device *dev, u32 data)
3458 {
3459 struct fe_priv *np = netdev_priv(dev);
3460
3461 if (np->driver_data & DEV_HAS_CHECKSUM)
3462 return ethtool_op_set_sg(dev, data);
3463 else
3464 return -EOPNOTSUPP;
3465 }
3466
3467 static int nv_get_stats_count(struct net_device *dev)
3468 {
3469 struct fe_priv *np = netdev_priv(dev);
3470
3471 if (np->driver_data & DEV_HAS_STATISTICS)
3472 return (sizeof(struct nv_ethtool_stats)/sizeof(u64));
3473 else
3474 return 0;
3475 }
3476
3477 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
3478 {
3479 struct fe_priv *np = netdev_priv(dev);
3480
3481 /* update stats */
3482 nv_do_stats_poll((unsigned long)dev);
3483
3484 memcpy(buffer, &np->estats, nv_get_stats_count(dev)*sizeof(u64));
3485 }
3486
3487 static int nv_self_test_count(struct net_device *dev)
3488 {
3489 struct fe_priv *np = netdev_priv(dev);
3490
3491 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
3492 return NV_TEST_COUNT_EXTENDED;
3493 else
3494 return NV_TEST_COUNT_BASE;
3495 }
3496
3497 static int nv_link_test(struct net_device *dev)
3498 {
3499 struct fe_priv *np = netdev_priv(dev);
3500 int mii_status;
3501
3502 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3503 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3504
3505 /* check phy link status */
3506 if (!(mii_status & BMSR_LSTATUS))
3507 return 0;
3508 else
3509 return 1;
3510 }
3511
3512 static int nv_register_test(struct net_device *dev)
3513 {
3514 u8 __iomem *base = get_hwbase(dev);
3515 int i = 0;
3516 u32 orig_read, new_read;
3517
3518 do {
3519 orig_read = readl(base + nv_registers_test[i].reg);
3520
3521 /* xor with mask to toggle bits */
3522 orig_read ^= nv_registers_test[i].mask;
3523
3524 writel(orig_read, base + nv_registers_test[i].reg);
3525
3526 new_read = readl(base + nv_registers_test[i].reg);
3527
3528 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
3529 return 0;
3530
3531 /* restore original value */
3532 orig_read ^= nv_registers_test[i].mask;
3533 writel(orig_read, base + nv_registers_test[i].reg);
3534
3535 } while (nv_registers_test[++i].reg != 0);
3536
3537 return 1;
3538 }
3539
3540 static int nv_interrupt_test(struct net_device *dev)
3541 {
3542 struct fe_priv *np = netdev_priv(dev);
3543 u8 __iomem *base = get_hwbase(dev);
3544 int ret = 1;
3545 int testcnt;
3546 u32 save_msi_flags, save_poll_interval = 0;
3547
3548 if (netif_running(dev)) {
3549 /* free current irq */
3550 nv_free_irq(dev);
3551 save_poll_interval = readl(base+NvRegPollingInterval);
3552 }
3553
3554 /* flag to test interrupt handler */
3555 np->intr_test = 0;
3556
3557 /* setup test irq */
3558 save_msi_flags = np->msi_flags;
3559 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
3560 np->msi_flags |= 0x001; /* setup 1 vector */
3561 if (nv_request_irq(dev, 1))
3562 return 0;
3563
3564 /* setup timer interrupt */
3565 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3566 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3567
3568 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3569
3570 /* wait for at least one interrupt */
3571 msleep(100);
3572
3573 spin_lock_irq(&np->lock);
3574
3575 /* flag should be set within ISR */
3576 testcnt = np->intr_test;
3577 if (!testcnt)
3578 ret = 2;
3579
3580 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
3581 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3582 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3583 else
3584 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3585
3586 spin_unlock_irq(&np->lock);
3587
3588 nv_free_irq(dev);
3589
3590 np->msi_flags = save_msi_flags;
3591
3592 if (netif_running(dev)) {
3593 writel(save_poll_interval, base + NvRegPollingInterval);
3594 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3595 /* restore original irq */
3596 if (nv_request_irq(dev, 0))
3597 return 0;
3598 }
3599
3600 return ret;
3601 }
3602
3603 static int nv_loopback_test(struct net_device *dev)
3604 {
3605 struct fe_priv *np = netdev_priv(dev);
3606 u8 __iomem *base = get_hwbase(dev);
3607 struct sk_buff *tx_skb, *rx_skb;
3608 dma_addr_t test_dma_addr;
3609 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
3610 u32 Flags;
3611 int len, i, pkt_len;
3612 u8 *pkt_data;
3613 u32 filter_flags = 0;
3614 u32 misc1_flags = 0;
3615 int ret = 1;
3616
3617 if (netif_running(dev)) {
3618 nv_disable_irq(dev);
3619 filter_flags = readl(base + NvRegPacketFilterFlags);
3620 misc1_flags = readl(base + NvRegMisc1);
3621 } else {
3622 nv_txrx_reset(dev);
3623 }
3624
3625 /* reinit driver view of the rx queue */
3626 set_bufsize(dev);
3627 nv_init_ring(dev);
3628
3629 /* setup hardware for loopback */
3630 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
3631 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
3632
3633 /* reinit nic view of the rx queue */
3634 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3635 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3636 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3637 base + NvRegRingSizes);
3638 pci_push(base);
3639
3640 /* restart rx engine */
3641 nv_start_rx(dev);
3642 nv_start_tx(dev);
3643
3644 /* setup packet for tx */
3645 pkt_len = ETH_DATA_LEN;
3646 tx_skb = dev_alloc_skb(pkt_len);
3647 pkt_data = skb_put(tx_skb, pkt_len);
3648 for (i = 0; i < pkt_len; i++)
3649 pkt_data[i] = (u8)(i & 0xff);
3650 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
3651 tx_skb->end-tx_skb->data, PCI_DMA_FROMDEVICE);
3652
3653 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3654 np->tx_ring.orig[0].PacketBuffer = cpu_to_le32(test_dma_addr);
3655 np->tx_ring.orig[0].FlagLen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3656 } else {
3657 np->tx_ring.ex[0].PacketBufferHigh = cpu_to_le64(test_dma_addr) >> 32;
3658 np->tx_ring.ex[0].PacketBufferLow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
3659 np->tx_ring.ex[0].FlagLen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
3660 }
3661 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3662 pci_push(get_hwbase(dev));
3663
3664 msleep(500);
3665
3666 /* check for rx of the packet */
3667 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3668 Flags = le32_to_cpu(np->rx_ring.orig[0].FlagLen);
3669 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
3670
3671 } else {
3672 Flags = le32_to_cpu(np->rx_ring.ex[0].FlagLen);
3673 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
3674 }
3675
3676 if (Flags & NV_RX_AVAIL) {
3677 ret = 0;
3678 } else if (np->desc_ver == DESC_VER_1) {
3679 if (Flags & NV_RX_ERROR)
3680 ret = 0;
3681 } else {
3682 if (Flags & NV_RX2_ERROR) {
3683 ret = 0;
3684 }
3685 }
3686
3687 if (ret) {
3688 if (len != pkt_len) {
3689 ret = 0;
3690 dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
3691 dev->name, len, pkt_len);
3692 } else {
3693 rx_skb = np->rx_skbuff[0];
3694 for (i = 0; i < pkt_len; i++) {
3695 if (rx_skb->data[i] != (u8)(i & 0xff)) {
3696 ret = 0;
3697 dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
3698 dev->name, i);
3699 break;
3700 }
3701 }
3702 }
3703 } else {
3704 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
3705 }
3706
3707 pci_unmap_page(np->pci_dev, test_dma_addr,
3708 tx_skb->end-tx_skb->data,
3709 PCI_DMA_TODEVICE);
3710 dev_kfree_skb_any(tx_skb);
3711
3712 /* stop engines */
3713 nv_stop_rx(dev);
3714 nv_stop_tx(dev);
3715 nv_txrx_reset(dev);
3716 /* drain rx queue */
3717 nv_drain_rx(dev);
3718 nv_drain_tx(dev);
3719
3720 if (netif_running(dev)) {
3721 writel(misc1_flags, base + NvRegMisc1);
3722 writel(filter_flags, base + NvRegPacketFilterFlags);
3723 nv_enable_irq(dev);
3724 }
3725
3726 return ret;
3727 }
3728
3729 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
3730 {
3731 struct fe_priv *np = netdev_priv(dev);
3732 u8 __iomem *base = get_hwbase(dev);
3733 int result;
3734 memset(buffer, 0, nv_self_test_count(dev)*sizeof(u64));
3735
3736 if (!nv_link_test(dev)) {
3737 test->flags |= ETH_TEST_FL_FAILED;
3738 buffer[0] = 1;
3739 }
3740
3741 if (test->flags & ETH_TEST_FL_OFFLINE) {
3742 if (netif_running(dev)) {
3743 netif_stop_queue(dev);
3744 netif_tx_lock_bh(dev);
3745 spin_lock_irq(&np->lock);
3746 nv_disable_hw_interrupts(dev, np->irqmask);
3747 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3748 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3749 } else {
3750 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3751 }
3752 /* stop engines */
3753 nv_stop_rx(dev);
3754 nv_stop_tx(dev);
3755 nv_txrx_reset(dev);
3756 /* drain rx queue */
3757 nv_drain_rx(dev);
3758 nv_drain_tx(dev);
3759 spin_unlock_irq(&np->lock);
3760 netif_tx_unlock_bh(dev);
3761 }
3762
3763 if (!nv_register_test(dev)) {
3764 test->flags |= ETH_TEST_FL_FAILED;
3765 buffer[1] = 1;
3766 }
3767
3768 result = nv_interrupt_test(dev);
3769 if (result != 1) {
3770 test->flags |= ETH_TEST_FL_FAILED;
3771 buffer[2] = 1;
3772 }
3773 if (result == 0) {
3774 /* bail out */
3775 return;
3776 }
3777
3778 if (!nv_loopback_test(dev)) {
3779 test->flags |= ETH_TEST_FL_FAILED;
3780 buffer[3] = 1;
3781 }
3782
3783 if (netif_running(dev)) {
3784 /* reinit driver view of the rx queue */
3785 set_bufsize(dev);
3786 if (nv_init_ring(dev)) {
3787 if (!np->in_shutdown)
3788 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3789 }
3790 /* reinit nic view of the rx queue */
3791 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3792 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3793 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3794 base + NvRegRingSizes);
3795 pci_push(base);
3796 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3797 pci_push(base);
3798 /* restart rx engine */
3799 nv_start_rx(dev);
3800 nv_start_tx(dev);
3801 netif_start_queue(dev);
3802 nv_enable_hw_interrupts(dev, np->irqmask);
3803 }
3804 }
3805 }
3806
3807 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
3808 {
3809 switch (stringset) {
3810 case ETH_SS_STATS:
3811 memcpy(buffer, &nv_estats_str, nv_get_stats_count(dev)*sizeof(struct nv_ethtool_str));
3812 break;
3813 case ETH_SS_TEST:
3814 memcpy(buffer, &nv_etests_str, nv_self_test_count(dev)*sizeof(struct nv_ethtool_str));
3815 break;
3816 }
3817 }
3818
3819 static struct ethtool_ops ops = {
3820 .get_drvinfo = nv_get_drvinfo,
3821 .get_link = ethtool_op_get_link,
3822 .get_wol = nv_get_wol,
3823 .set_wol = nv_set_wol,
3824 .get_settings = nv_get_settings,
3825 .set_settings = nv_set_settings,
3826 .get_regs_len = nv_get_regs_len,
3827 .get_regs = nv_get_regs,
3828 .nway_reset = nv_nway_reset,
3829 .get_perm_addr = ethtool_op_get_perm_addr,
3830 .get_tso = ethtool_op_get_tso,
3831 .set_tso = nv_set_tso,
3832 .get_ringparam = nv_get_ringparam,
3833 .set_ringparam = nv_set_ringparam,
3834 .get_pauseparam = nv_get_pauseparam,
3835 .set_pauseparam = nv_set_pauseparam,
3836 .get_rx_csum = nv_get_rx_csum,
3837 .set_rx_csum = nv_set_rx_csum,
3838 .get_tx_csum = ethtool_op_get_tx_csum,
3839 .set_tx_csum = nv_set_tx_csum,
3840 .get_sg = ethtool_op_get_sg,
3841 .set_sg = nv_set_sg,
3842 .get_strings = nv_get_strings,
3843 .get_stats_count = nv_get_stats_count,
3844 .get_ethtool_stats = nv_get_ethtool_stats,
3845 .self_test_count = nv_self_test_count,
3846 .self_test = nv_self_test,
3847 };
3848
3849 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
3850 {
3851 struct fe_priv *np = get_nvpriv(dev);
3852
3853 spin_lock_irq(&np->lock);
3854
3855 /* save vlan group */
3856 np->vlangrp = grp;
3857
3858 if (grp) {
3859 /* enable vlan on MAC */
3860 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
3861 } else {
3862 /* disable vlan on MAC */
3863 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
3864 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
3865 }
3866
3867 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3868
3869 spin_unlock_irq(&np->lock);
3870 };
3871
3872 static void nv_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
3873 {
3874 /* nothing to do */
3875 };
3876
3877 static int nv_open(struct net_device *dev)
3878 {
3879 struct fe_priv *np = netdev_priv(dev);
3880 u8 __iomem *base = get_hwbase(dev);
3881 int ret = 1;
3882 int oom, i;
3883
3884 dprintk(KERN_DEBUG "nv_open: begin\n");
3885
3886 /* 1) erase previous misconfiguration */
3887 if (np->driver_data & DEV_HAS_POWER_CNTRL)
3888 nv_mac_reset(dev);
3889 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
3890 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
3891 writel(0, base + NvRegMulticastAddrB);
3892 writel(0, base + NvRegMulticastMaskA);
3893 writel(0, base + NvRegMulticastMaskB);
3894 writel(0, base + NvRegPacketFilterFlags);
3895
3896 writel(0, base + NvRegTransmitterControl);
3897 writel(0, base + NvRegReceiverControl);
3898
3899 writel(0, base + NvRegAdapterControl);
3900
3901 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
3902 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3903
3904 /* 2) initialize descriptor rings */
3905 set_bufsize(dev);
3906 oom = nv_init_ring(dev);
3907
3908 writel(0, base + NvRegLinkSpeed);
3909 writel(0, base + NvRegUnknownTransmitterReg);
3910 nv_txrx_reset(dev);
3911 writel(0, base + NvRegUnknownSetupReg6);
3912
3913 np->in_shutdown = 0;
3914
3915 /* 3) set mac address */
3916 nv_copy_mac_to_hw(dev);
3917
3918 /* 4) give hw rings */
3919 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3920 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3921 base + NvRegRingSizes);
3922
3923 /* 5) continue setup */
3924 writel(np->linkspeed, base + NvRegLinkSpeed);
3925 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
3926 writel(np->txrxctl_bits, base + NvRegTxRxControl);
3927 writel(np->vlanctl_bits, base + NvRegVlanControl);
3928 pci_push(base);
3929 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
3930 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
3931 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
3932 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
3933
3934 writel(0, base + NvRegUnknownSetupReg4);
3935 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3936 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3937
3938 /* 6) continue setup */
3939 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
3940 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
3941 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
3942 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3943
3944 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
3945 get_random_bytes(&i, sizeof(i));
3946 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
3947 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
3948 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
3949 if (poll_interval == -1) {
3950 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
3951 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
3952 else
3953 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
3954 }
3955 else
3956 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
3957 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
3958 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
3959 base + NvRegAdapterControl);
3960 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
3961 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
3962 if (np->wolenabled)
3963 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
3964
3965 i = readl(base + NvRegPowerState);
3966 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
3967 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
3968
3969 pci_push(base);
3970 udelay(10);
3971 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
3972
3973 nv_disable_hw_interrupts(dev, np->irqmask);
3974 pci_push(base);
3975 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
3976 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3977 pci_push(base);
3978
3979 if (nv_request_irq(dev, 0)) {
3980 goto out_drain;
3981 }
3982
3983 /* ask for interrupts */
3984 nv_enable_hw_interrupts(dev, np->irqmask);
3985
3986 spin_lock_irq(&np->lock);
3987 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
3988 writel(0, base + NvRegMulticastAddrB);
3989 writel(0, base + NvRegMulticastMaskA);
3990 writel(0, base + NvRegMulticastMaskB);
3991 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
3992 /* One manual link speed update: Interrupts are enabled, future link
3993 * speed changes cause interrupts and are handled by nv_link_irq().
3994 */
3995 {
3996 u32 miistat;
3997 miistat = readl(base + NvRegMIIStatus);
3998 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
3999 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4000 }
4001 /* set linkspeed to invalid value, thus force nv_update_linkspeed
4002 * to init hw */
4003 np->linkspeed = 0;
4004 ret = nv_update_linkspeed(dev);
4005 nv_start_rx(dev);
4006 nv_start_tx(dev);
4007 netif_start_queue(dev);
4008 if (ret) {
4009 netif_carrier_on(dev);
4010 } else {
4011 printk("%s: no link during initialization.\n", dev->name);
4012 netif_carrier_off(dev);
4013 }
4014 if (oom)
4015 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4016
4017 /* start statistics timer */
4018 if (np->driver_data & DEV_HAS_STATISTICS)
4019 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4020
4021 spin_unlock_irq(&np->lock);
4022
4023 return 0;
4024 out_drain:
4025 drain_ring(dev);
4026 return ret;
4027 }
4028
4029 static int nv_close(struct net_device *dev)
4030 {
4031 struct fe_priv *np = netdev_priv(dev);
4032 u8 __iomem *base;
4033
4034 spin_lock_irq(&np->lock);
4035 np->in_shutdown = 1;
4036 spin_unlock_irq(&np->lock);
4037 synchronize_irq(dev->irq);
4038
4039 del_timer_sync(&np->oom_kick);
4040 del_timer_sync(&np->nic_poll);
4041 del_timer_sync(&np->stats_poll);
4042
4043 netif_stop_queue(dev);
4044 spin_lock_irq(&np->lock);
4045 nv_stop_tx(dev);
4046 nv_stop_rx(dev);
4047 nv_txrx_reset(dev);
4048
4049 /* disable interrupts on the nic or we will lock up */
4050 base = get_hwbase(dev);
4051 nv_disable_hw_interrupts(dev, np->irqmask);
4052 pci_push(base);
4053 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4054
4055 spin_unlock_irq(&np->lock);
4056
4057 nv_free_irq(dev);
4058
4059 drain_ring(dev);
4060
4061 if (np->wolenabled)
4062 nv_start_rx(dev);
4063
4064 /* special op: write back the misordered MAC address - otherwise
4065 * the next nv_probe would see a wrong address.
4066 */
4067 writel(np->orig_mac[0], base + NvRegMacAddrA);
4068 writel(np->orig_mac[1], base + NvRegMacAddrB);
4069
4070 /* FIXME: power down nic */
4071
4072 return 0;
4073 }
4074
4075 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4076 {
4077 struct net_device *dev;
4078 struct fe_priv *np;
4079 unsigned long addr;
4080 u8 __iomem *base;
4081 int err, i;
4082 u32 powerstate;
4083
4084 dev = alloc_etherdev(sizeof(struct fe_priv));
4085 err = -ENOMEM;
4086 if (!dev)
4087 goto out;
4088
4089 np = netdev_priv(dev);
4090 np->pci_dev = pci_dev;
4091 spin_lock_init(&np->lock);
4092 SET_MODULE_OWNER(dev);
4093 SET_NETDEV_DEV(dev, &pci_dev->dev);
4094
4095 init_timer(&np->oom_kick);
4096 np->oom_kick.data = (unsigned long) dev;
4097 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
4098 init_timer(&np->nic_poll);
4099 np->nic_poll.data = (unsigned long) dev;
4100 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
4101 init_timer(&np->stats_poll);
4102 np->stats_poll.data = (unsigned long) dev;
4103 np->stats_poll.function = &nv_do_stats_poll; /* timer handler */
4104
4105 err = pci_enable_device(pci_dev);
4106 if (err) {
4107 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
4108 err, pci_name(pci_dev));
4109 goto out_free;
4110 }
4111
4112 pci_set_master(pci_dev);
4113
4114 err = pci_request_regions(pci_dev, DRV_NAME);
4115 if (err < 0)
4116 goto out_disable;
4117
4118 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS))
4119 np->register_size = NV_PCI_REGSZ_VER2;
4120 else
4121 np->register_size = NV_PCI_REGSZ_VER1;
4122
4123 err = -EINVAL;
4124 addr = 0;
4125 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4126 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
4127 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
4128 pci_resource_len(pci_dev, i),
4129 pci_resource_flags(pci_dev, i));
4130 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
4131 pci_resource_len(pci_dev, i) >= np->register_size) {
4132 addr = pci_resource_start(pci_dev, i);
4133 break;
4134 }
4135 }
4136 if (i == DEVICE_COUNT_RESOURCE) {
4137 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
4138 pci_name(pci_dev));
4139 goto out_relreg;
4140 }
4141
4142 /* copy of driver data */
4143 np->driver_data = id->driver_data;
4144
4145 /* handle different descriptor versions */
4146 if (id->driver_data & DEV_HAS_HIGH_DMA) {
4147 /* packet format 3: supports 40-bit addressing */
4148 np->desc_ver = DESC_VER_3;
4149 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
4150 if (dma_64bit) {
4151 if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4152 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
4153 pci_name(pci_dev));
4154 } else {
4155 dev->features |= NETIF_F_HIGHDMA;
4156 printk(KERN_INFO "forcedeth: using HIGHDMA\n");
4157 }
4158 if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
4159 printk(KERN_INFO "forcedeth: 64-bit DMA (consistent) failed, using 32-bit ring buffers for device %s.\n",
4160 pci_name(pci_dev));
4161 }
4162 }
4163 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
4164 /* packet format 2: supports jumbo frames */
4165 np->desc_ver = DESC_VER_2;
4166 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
4167 } else {
4168 /* original packet format */
4169 np->desc_ver = DESC_VER_1;
4170 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
4171 }
4172
4173 np->pkt_limit = NV_PKTLIMIT_1;
4174 if (id->driver_data & DEV_HAS_LARGEDESC)
4175 np->pkt_limit = NV_PKTLIMIT_2;
4176
4177 if (id->driver_data & DEV_HAS_CHECKSUM) {
4178 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4179 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
4180 #ifdef NETIF_F_TSO
4181 dev->features |= NETIF_F_TSO;
4182 #endif
4183 }
4184
4185 np->vlanctl_bits = 0;
4186 if (id->driver_data & DEV_HAS_VLAN) {
4187 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
4188 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
4189 dev->vlan_rx_register = nv_vlan_rx_register;
4190 dev->vlan_rx_kill_vid = nv_vlan_rx_kill_vid;
4191 }
4192
4193 np->msi_flags = 0;
4194 if ((id->driver_data & DEV_HAS_MSI) && msi) {
4195 np->msi_flags |= NV_MSI_CAPABLE;
4196 }
4197 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
4198 np->msi_flags |= NV_MSI_X_CAPABLE;
4199 }
4200
4201 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
4202 if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
4203 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
4204 }
4205
4206
4207 err = -ENOMEM;
4208 np->base = ioremap(addr, np->register_size);
4209 if (!np->base)
4210 goto out_relreg;
4211 dev->base_addr = (unsigned long)np->base;
4212
4213 dev->irq = pci_dev->irq;
4214
4215 np->rx_ring_size = RX_RING_DEFAULT;
4216 np->tx_ring_size = TX_RING_DEFAULT;
4217 np->tx_limit_stop = np->tx_ring_size - TX_LIMIT_DIFFERENCE;
4218 np->tx_limit_start = np->tx_ring_size - TX_LIMIT_DIFFERENCE - 1;
4219
4220 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4221 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
4222 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
4223 &np->ring_addr);
4224 if (!np->rx_ring.orig)
4225 goto out_unmap;
4226 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4227 } else {
4228 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
4229 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
4230 &np->ring_addr);
4231 if (!np->rx_ring.ex)
4232 goto out_unmap;
4233 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4234 }
4235 np->rx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->rx_ring_size, GFP_KERNEL);
4236 np->rx_dma = kmalloc(sizeof(dma_addr_t) * np->rx_ring_size, GFP_KERNEL);
4237 np->tx_skbuff = kmalloc(sizeof(struct sk_buff*) * np->tx_ring_size, GFP_KERNEL);
4238 np->tx_dma = kmalloc(sizeof(dma_addr_t) * np->tx_ring_size, GFP_KERNEL);
4239 np->tx_dma_len = kmalloc(sizeof(unsigned int) * np->tx_ring_size, GFP_KERNEL);
4240 if (!np->rx_skbuff || !np->rx_dma || !np->tx_skbuff || !np->tx_dma || !np->tx_dma_len)
4241 goto out_freering;
4242 memset(np->rx_skbuff, 0, sizeof(struct sk_buff*) * np->rx_ring_size);
4243 memset(np->rx_dma, 0, sizeof(dma_addr_t) * np->rx_ring_size);
4244 memset(np->tx_skbuff, 0, sizeof(struct sk_buff*) * np->tx_ring_size);
4245 memset(np->tx_dma, 0, sizeof(dma_addr_t) * np->tx_ring_size);
4246 memset(np->tx_dma_len, 0, sizeof(unsigned int) * np->tx_ring_size);
4247
4248 dev->open = nv_open;
4249 dev->stop = nv_close;
4250 dev->hard_start_xmit = nv_start_xmit;
4251 dev->get_stats = nv_get_stats;
4252 dev->change_mtu = nv_change_mtu;
4253 dev->set_mac_address = nv_set_mac_address;
4254 dev->set_multicast_list = nv_set_multicast;
4255 #ifdef CONFIG_NET_POLL_CONTROLLER
4256 dev->poll_controller = nv_poll_controller;
4257 #endif
4258 SET_ETHTOOL_OPS(dev, &ops);
4259 dev->tx_timeout = nv_tx_timeout;
4260 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
4261
4262 pci_set_drvdata(pci_dev, dev);
4263
4264 /* read the mac address */
4265 base = get_hwbase(dev);
4266 np->orig_mac[0] = readl(base + NvRegMacAddrA);
4267 np->orig_mac[1] = readl(base + NvRegMacAddrB);
4268
4269 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
4270 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
4271 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
4272 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
4273 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
4274 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
4275 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4276
4277 if (!is_valid_ether_addr(dev->perm_addr)) {
4278 /*
4279 * Bad mac address. At least one bios sets the mac address
4280 * to 01:23:45:67:89:ab
4281 */
4282 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
4283 pci_name(pci_dev),
4284 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4285 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4286 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
4287 dev->dev_addr[0] = 0x00;
4288 dev->dev_addr[1] = 0x00;
4289 dev->dev_addr[2] = 0x6c;
4290 get_random_bytes(&dev->dev_addr[3], 3);
4291 }
4292
4293 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
4294 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
4295 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4296
4297 /* disable WOL */
4298 writel(0, base + NvRegWakeUpFlags);
4299 np->wolenabled = 0;
4300
4301 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
4302 u8 revision_id;
4303 pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id);
4304
4305 /* take phy and nic out of low power mode */
4306 powerstate = readl(base + NvRegPowerState2);
4307 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
4308 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
4309 id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
4310 revision_id >= 0xA3)
4311 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
4312 writel(powerstate, base + NvRegPowerState2);
4313 }
4314
4315 if (np->desc_ver == DESC_VER_1) {
4316 np->tx_flags = NV_TX_VALID;
4317 } else {
4318 np->tx_flags = NV_TX2_VALID;
4319 }
4320 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
4321 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
4322 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4323 np->msi_flags |= 0x0003;
4324 } else {
4325 np->irqmask = NVREG_IRQMASK_CPU;
4326 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
4327 np->msi_flags |= 0x0001;
4328 }
4329
4330 if (id->driver_data & DEV_NEED_TIMERIRQ)
4331 np->irqmask |= NVREG_IRQ_TIMER;
4332 if (id->driver_data & DEV_NEED_LINKTIMER) {
4333 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
4334 np->need_linktimer = 1;
4335 np->link_timeout = jiffies + LINK_TIMEOUT;
4336 } else {
4337 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
4338 np->need_linktimer = 0;
4339 }
4340
4341 /* find a suitable phy */
4342 for (i = 1; i <= 32; i++) {
4343 int id1, id2;
4344 int phyaddr = i & 0x1F;
4345
4346 spin_lock_irq(&np->lock);
4347 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
4348 spin_unlock_irq(&np->lock);
4349 if (id1 < 0 || id1 == 0xffff)
4350 continue;
4351 spin_lock_irq(&np->lock);
4352 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
4353 spin_unlock_irq(&np->lock);
4354 if (id2 < 0 || id2 == 0xffff)
4355 continue;
4356
4357 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
4358 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
4359 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
4360 pci_name(pci_dev), id1, id2, phyaddr);
4361 np->phyaddr = phyaddr;
4362 np->phy_oui = id1 | id2;
4363 break;
4364 }
4365 if (i == 33) {
4366 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
4367 pci_name(pci_dev));
4368 goto out_error;
4369 }
4370
4371 /* reset it */
4372 phy_init(dev);
4373
4374 /* set default link speed settings */
4375 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
4376 np->duplex = 0;
4377 np->autoneg = 1;
4378
4379 err = register_netdev(dev);
4380 if (err) {
4381 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
4382 goto out_error;
4383 }
4384 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
4385 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
4386 pci_name(pci_dev));
4387
4388 return 0;
4389
4390 out_error:
4391 pci_set_drvdata(pci_dev, NULL);
4392 out_freering:
4393 free_rings(dev);
4394 out_unmap:
4395 iounmap(get_hwbase(dev));
4396 out_relreg:
4397 pci_release_regions(pci_dev);
4398 out_disable:
4399 pci_disable_device(pci_dev);
4400 out_free:
4401 free_netdev(dev);
4402 out:
4403 return err;
4404 }
4405
4406 static void __devexit nv_remove(struct pci_dev *pci_dev)
4407 {
4408 struct net_device *dev = pci_get_drvdata(pci_dev);
4409
4410 unregister_netdev(dev);
4411
4412 /* free all structures */
4413 free_rings(dev);
4414 iounmap(get_hwbase(dev));
4415 pci_release_regions(pci_dev);
4416 pci_disable_device(pci_dev);
4417 free_netdev(dev);
4418 pci_set_drvdata(pci_dev, NULL);
4419 }
4420
4421 static struct pci_device_id pci_tbl[] = {
4422 { /* nForce Ethernet Controller */
4423 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
4424 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4425 },
4426 { /* nForce2 Ethernet Controller */
4427 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
4428 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4429 },
4430 { /* nForce3 Ethernet Controller */
4431 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
4432 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
4433 },
4434 { /* nForce3 Ethernet Controller */
4435 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
4436 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4437 },
4438 { /* nForce3 Ethernet Controller */
4439 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
4440 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4441 },
4442 { /* nForce3 Ethernet Controller */
4443 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
4444 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4445 },
4446 { /* nForce3 Ethernet Controller */
4447 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
4448 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
4449 },
4450 { /* CK804 Ethernet Controller */
4451 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
4452 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4453 },
4454 { /* CK804 Ethernet Controller */
4455 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
4456 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4457 },
4458 { /* MCP04 Ethernet Controller */
4459 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
4460 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4461 },
4462 { /* MCP04 Ethernet Controller */
4463 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
4464 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
4465 },
4466 { /* MCP51 Ethernet Controller */
4467 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
4468 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4469 },
4470 { /* MCP51 Ethernet Controller */
4471 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
4472 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL,
4473 },
4474 { /* MCP55 Ethernet Controller */
4475 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
4476 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4477 },
4478 { /* MCP55 Ethernet Controller */
4479 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
4480 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4481 },
4482 { /* MCP61 Ethernet Controller */
4483 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
4484 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4485 },
4486 { /* MCP61 Ethernet Controller */
4487 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
4488 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4489 },
4490 { /* MCP61 Ethernet Controller */
4491 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
4492 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4493 },
4494 { /* MCP61 Ethernet Controller */
4495 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
4496 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4497 },
4498 { /* MCP65 Ethernet Controller */
4499 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
4500 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4501 },
4502 { /* MCP65 Ethernet Controller */
4503 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
4504 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4505 },
4506 { /* MCP65 Ethernet Controller */
4507 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
4508 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4509 },
4510 { /* MCP65 Ethernet Controller */
4511 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
4512 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS|DEV_HAS_TEST_EXTENDED,
4513 },
4514 {0,},
4515 };
4516
4517 static struct pci_driver driver = {
4518 .name = "forcedeth",
4519 .id_table = pci_tbl,
4520 .probe = nv_probe,
4521 .remove = __devexit_p(nv_remove),
4522 };
4523
4524
4525 static int __init init_nic(void)
4526 {
4527 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
4528 return pci_module_init(&driver);
4529 }
4530
4531 static void __exit exit_nic(void)
4532 {
4533 pci_unregister_driver(&driver);
4534 }
4535
4536 module_param(max_interrupt_work, int, 0);
4537 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
4538 module_param(optimization_mode, int, 0);
4539 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
4540 module_param(poll_interval, int, 0);
4541 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
4542 module_param(msi, int, 0);
4543 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
4544 module_param(msix, int, 0);
4545 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
4546 module_param(dma_64bit, int, 0);
4547 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
4548
4549 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
4550 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
4551 MODULE_LICENSE("GPL");
4552
4553 MODULE_DEVICE_TABLE(pci, pci_tbl);
4554
4555 module_init(init_nic);
4556 module_exit(exit_nic);
Linux kernel - Deliverables
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