e990f728d51b790b9fa5dd9dc757d84c6d34ada5
[deliverable/linux.git] / drivers / net / fs_enet / mac-fcc.c
1 /*
2 * FCC driver for Motorola MPC82xx (PQ2).
3 *
4 * Copyright (c) 2003 Intracom S.A.
5 * by Pantelis Antoniou <panto@intracom.gr>
6 *
7 * 2005 (c) MontaVista Software, Inc.
8 * Vitaly Bordug <vbordug@ru.mvista.com>
9 *
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/string.h>
19 #include <linux/ptrace.h>
20 #include <linux/errno.h>
21 #include <linux/ioport.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/skbuff.h>
29 #include <linux/spinlock.h>
30 #include <linux/mii.h>
31 #include <linux/ethtool.h>
32 #include <linux/bitops.h>
33 #include <linux/fs.h>
34 #include <linux/platform_device.h>
35 #include <linux/phy.h>
36
37 #include <asm/immap_cpm2.h>
38 #include <asm/mpc8260.h>
39 #include <asm/cpm2.h>
40
41 #include <asm/pgtable.h>
42 #include <asm/irq.h>
43 #include <asm/uaccess.h>
44
45 #include "fs_enet.h"
46
47 /*************************************************/
48
49 /* FCC access macros */
50
51 /* write, read, set bits, clear bits */
52 #define W32(_p, _m, _v) out_be32(&(_p)->_m, (_v))
53 #define R32(_p, _m) in_be32(&(_p)->_m)
54 #define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v))
55 #define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v))
56
57 #define W16(_p, _m, _v) out_be16(&(_p)->_m, (_v))
58 #define R16(_p, _m) in_be16(&(_p)->_m)
59 #define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v))
60 #define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v))
61
62 #define W8(_p, _m, _v) out_8(&(_p)->_m, (_v))
63 #define R8(_p, _m) in_8(&(_p)->_m)
64 #define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v))
65 #define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v))
66
67 /*************************************************/
68
69 #define FCC_MAX_MULTICAST_ADDRS 64
70
71 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
72 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
73 #define mk_mii_end 0
74
75 #define MAX_CR_CMD_LOOPS 10000
76
77 static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 mcn, u32 op)
78 {
79 const struct fs_platform_info *fpi = fep->fpi;
80 cpm2_map_t *immap = fs_enet_immap;
81 cpm_cpm2_t *cpmp = &immap->im_cpm;
82 u32 v;
83 int i;
84
85 /* Currently I don't know what feature call will look like. But
86 I guess there'd be something like do_cpm_cmd() which will require page & sblock */
87 v = mk_cr_cmd(fpi->cp_page, fpi->cp_block, mcn, op);
88 W32(cpmp, cp_cpcr, v | CPM_CR_FLG);
89 for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
90 if ((R32(cpmp, cp_cpcr) & CPM_CR_FLG) == 0)
91 break;
92
93 if (i >= MAX_CR_CMD_LOOPS) {
94 printk(KERN_ERR "%s(): Not able to issue CPM command\n",
95 __FUNCTION__);
96 return 1;
97 }
98
99 return 0;
100 }
101
102 static int do_pd_setup(struct fs_enet_private *fep)
103 {
104 struct platform_device *pdev = to_platform_device(fep->dev);
105 struct resource *r;
106
107 /* Fill out IRQ field */
108 fep->interrupt = platform_get_irq(pdev, 0);
109 if (fep->interrupt < 0)
110 return -EINVAL;
111
112 /* Attach the memory for the FCC Parameter RAM */
113 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_pram");
114 fep->fcc.ep = (void *)ioremap(r->start, r->end - r->start + 1);
115 if (fep->fcc.ep == NULL)
116 return -EINVAL;
117
118 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_regs");
119 fep->fcc.fccp = (void *)ioremap(r->start, r->end - r->start + 1);
120 if (fep->fcc.fccp == NULL)
121 return -EINVAL;
122
123 if (fep->fpi->fcc_regs_c) {
124
125 fep->fcc.fcccp = (void *)fep->fpi->fcc_regs_c;
126 } else {
127 r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
128 "fcc_regs_c");
129 fep->fcc.fcccp = (void *)ioremap(r->start,
130 r->end - r->start + 1);
131 }
132
133 if (fep->fcc.fcccp == NULL)
134 return -EINVAL;
135
136 fep->fcc.mem = (void *)fep->fpi->mem_offset;
137 if (fep->fcc.mem == NULL)
138 return -EINVAL;
139
140 return 0;
141 }
142
143 #define FCC_NAPI_RX_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB)
144 #define FCC_RX_EVENT (FCC_ENET_RXF)
145 #define FCC_TX_EVENT (FCC_ENET_TXB)
146 #define FCC_ERR_EVENT_MSK (FCC_ENET_TXE | FCC_ENET_BSY)
147
148 static int setup_data(struct net_device *dev)
149 {
150 struct fs_enet_private *fep = netdev_priv(dev);
151 const struct fs_platform_info *fpi = fep->fpi;
152
153 fep->fcc.idx = fs_get_fcc_index(fpi->fs_no);
154 if ((unsigned int)fep->fcc.idx >= 3) /* max 3 FCCs */
155 return -EINVAL;
156
157 if (do_pd_setup(fep) != 0)
158 return -EINVAL;
159
160 fep->ev_napi_rx = FCC_NAPI_RX_EVENT_MSK;
161 fep->ev_rx = FCC_RX_EVENT;
162 fep->ev_tx = FCC_TX_EVENT;
163 fep->ev_err = FCC_ERR_EVENT_MSK;
164
165 return 0;
166 }
167
168 static int allocate_bd(struct net_device *dev)
169 {
170 struct fs_enet_private *fep = netdev_priv(dev);
171 const struct fs_platform_info *fpi = fep->fpi;
172
173 fep->ring_base = dma_alloc_coherent(fep->dev,
174 (fpi->tx_ring + fpi->rx_ring) *
175 sizeof(cbd_t), &fep->ring_mem_addr,
176 GFP_KERNEL);
177 if (fep->ring_base == NULL)
178 return -ENOMEM;
179
180 return 0;
181 }
182
183 static void free_bd(struct net_device *dev)
184 {
185 struct fs_enet_private *fep = netdev_priv(dev);
186 const struct fs_platform_info *fpi = fep->fpi;
187
188 if (fep->ring_base)
189 dma_free_coherent(fep->dev,
190 (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t),
191 fep->ring_base, fep->ring_mem_addr);
192 }
193
194 static void cleanup_data(struct net_device *dev)
195 {
196 /* nothing */
197 }
198
199 static void set_promiscuous_mode(struct net_device *dev)
200 {
201 struct fs_enet_private *fep = netdev_priv(dev);
202 fcc_t *fccp = fep->fcc.fccp;
203
204 S32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
205 }
206
207 static void set_multicast_start(struct net_device *dev)
208 {
209 struct fs_enet_private *fep = netdev_priv(dev);
210 fcc_enet_t *ep = fep->fcc.ep;
211
212 W32(ep, fen_gaddrh, 0);
213 W32(ep, fen_gaddrl, 0);
214 }
215
216 static void set_multicast_one(struct net_device *dev, const u8 *mac)
217 {
218 struct fs_enet_private *fep = netdev_priv(dev);
219 fcc_enet_t *ep = fep->fcc.ep;
220 u16 taddrh, taddrm, taddrl;
221
222 taddrh = ((u16)mac[5] << 8) | mac[4];
223 taddrm = ((u16)mac[3] << 8) | mac[2];
224 taddrl = ((u16)mac[1] << 8) | mac[0];
225
226 W16(ep, fen_taddrh, taddrh);
227 W16(ep, fen_taddrm, taddrm);
228 W16(ep, fen_taddrl, taddrl);
229 fcc_cr_cmd(fep, 0x0C, CPM_CR_SET_GADDR);
230 }
231
232 static void set_multicast_finish(struct net_device *dev)
233 {
234 struct fs_enet_private *fep = netdev_priv(dev);
235 fcc_t *fccp = fep->fcc.fccp;
236 fcc_enet_t *ep = fep->fcc.ep;
237
238 /* clear promiscuous always */
239 C32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
240
241 /* if all multi or too many multicasts; just enable all */
242 if ((dev->flags & IFF_ALLMULTI) != 0 ||
243 dev->mc_count > FCC_MAX_MULTICAST_ADDRS) {
244
245 W32(ep, fen_gaddrh, 0xffffffff);
246 W32(ep, fen_gaddrl, 0xffffffff);
247 }
248
249 /* read back */
250 fep->fcc.gaddrh = R32(ep, fen_gaddrh);
251 fep->fcc.gaddrl = R32(ep, fen_gaddrl);
252 }
253
254 static void set_multicast_list(struct net_device *dev)
255 {
256 struct dev_mc_list *pmc;
257
258 if ((dev->flags & IFF_PROMISC) == 0) {
259 set_multicast_start(dev);
260 for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
261 set_multicast_one(dev, pmc->dmi_addr);
262 set_multicast_finish(dev);
263 } else
264 set_promiscuous_mode(dev);
265 }
266
267 static void restart(struct net_device *dev)
268 {
269 struct fs_enet_private *fep = netdev_priv(dev);
270 const struct fs_platform_info *fpi = fep->fpi;
271 fcc_t *fccp = fep->fcc.fccp;
272 fcc_c_t *fcccp = fep->fcc.fcccp;
273 fcc_enet_t *ep = fep->fcc.ep;
274 dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
275 u16 paddrh, paddrm, paddrl;
276 u16 mem_addr;
277 const unsigned char *mac;
278 int i;
279
280 C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
281
282 /* clear everything (slow & steady does it) */
283 for (i = 0; i < sizeof(*ep); i++)
284 out_8((char *)ep + i, 0);
285
286 /* get physical address */
287 rx_bd_base_phys = fep->ring_mem_addr;
288 tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
289
290 /* point to bds */
291 W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys);
292 W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys);
293
294 /* Set maximum bytes per receive buffer.
295 * It must be a multiple of 32.
296 */
297 W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE);
298
299 W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
300 W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
301
302 /* Allocate space in the reserved FCC area of DPRAM for the
303 * internal buffers. No one uses this space (yet), so we
304 * can do this. Later, we will add resource management for
305 * this area.
306 */
307
308 mem_addr = (u32) fep->fcc.mem; /* de-fixup dpram offset */
309
310 W16(ep, fen_genfcc.fcc_riptr, (mem_addr & 0xffff));
311 W16(ep, fen_genfcc.fcc_tiptr, ((mem_addr + 32) & 0xffff));
312 W16(ep, fen_padptr, mem_addr + 64);
313
314 /* fill with special symbol... */
315 memset(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32);
316
317 W32(ep, fen_genfcc.fcc_rbptr, 0);
318 W32(ep, fen_genfcc.fcc_tbptr, 0);
319 W32(ep, fen_genfcc.fcc_rcrc, 0);
320 W32(ep, fen_genfcc.fcc_tcrc, 0);
321 W16(ep, fen_genfcc.fcc_res1, 0);
322 W32(ep, fen_genfcc.fcc_res2, 0);
323
324 /* no CAM */
325 W32(ep, fen_camptr, 0);
326
327 /* Set CRC preset and mask */
328 W32(ep, fen_cmask, 0xdebb20e3);
329 W32(ep, fen_cpres, 0xffffffff);
330
331 W32(ep, fen_crcec, 0); /* CRC Error counter */
332 W32(ep, fen_alec, 0); /* alignment error counter */
333 W32(ep, fen_disfc, 0); /* discard frame counter */
334 W16(ep, fen_retlim, 15); /* Retry limit threshold */
335 W16(ep, fen_pper, 0); /* Normal persistence */
336
337 /* set group address */
338 W32(ep, fen_gaddrh, fep->fcc.gaddrh);
339 W32(ep, fen_gaddrl, fep->fcc.gaddrh);
340
341 /* Clear hash filter tables */
342 W32(ep, fen_iaddrh, 0);
343 W32(ep, fen_iaddrl, 0);
344
345 /* Clear the Out-of-sequence TxBD */
346 W16(ep, fen_tfcstat, 0);
347 W16(ep, fen_tfclen, 0);
348 W32(ep, fen_tfcptr, 0);
349
350 W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */
351 W16(ep, fen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */
352
353 /* set address */
354 mac = dev->dev_addr;
355 paddrh = ((u16)mac[5] << 8) | mac[4];
356 paddrm = ((u16)mac[3] << 8) | mac[2];
357 paddrl = ((u16)mac[1] << 8) | mac[0];
358
359 W16(ep, fen_paddrh, paddrh);
360 W16(ep, fen_paddrm, paddrm);
361 W16(ep, fen_paddrl, paddrl);
362
363 W16(ep, fen_taddrh, 0);
364 W16(ep, fen_taddrm, 0);
365 W16(ep, fen_taddrl, 0);
366
367 W16(ep, fen_maxd1, 1520); /* maximum DMA1 length */
368 W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */
369
370 /* Clear stat counters, in case we ever enable RMON */
371 W32(ep, fen_octc, 0);
372 W32(ep, fen_colc, 0);
373 W32(ep, fen_broc, 0);
374 W32(ep, fen_mulc, 0);
375 W32(ep, fen_uspc, 0);
376 W32(ep, fen_frgc, 0);
377 W32(ep, fen_ospc, 0);
378 W32(ep, fen_jbrc, 0);
379 W32(ep, fen_p64c, 0);
380 W32(ep, fen_p65c, 0);
381 W32(ep, fen_p128c, 0);
382 W32(ep, fen_p256c, 0);
383 W32(ep, fen_p512c, 0);
384 W32(ep, fen_p1024c, 0);
385
386 W16(ep, fen_rfthr, 0); /* Suggested by manual */
387 W16(ep, fen_rfcnt, 0);
388 W16(ep, fen_cftype, 0);
389
390 fs_init_bds(dev);
391
392 /* adjust to speed (for RMII mode) */
393 if (fpi->use_rmii) {
394 if (fep->phydev->speed == 100)
395 C8(fcccp, fcc_gfemr, 0x20);
396 else
397 S8(fcccp, fcc_gfemr, 0x20);
398 }
399
400 fcc_cr_cmd(fep, 0x0c, CPM_CR_INIT_TRX);
401
402 /* clear events */
403 W16(fccp, fcc_fcce, 0xffff);
404
405 /* Enable interrupts we wish to service */
406 W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
407
408 /* Set GFMR to enable Ethernet operating mode */
409 W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
410
411 /* set sync/delimiters */
412 W16(fccp, fcc_fdsr, 0xd555);
413
414 W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC);
415
416 if (fpi->use_rmii)
417 S32(fccp, fcc_fpsmr, FCC_PSMR_RMII);
418
419 /* adjust to duplex mode */
420 if (fep->phydev->duplex)
421 S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
422 else
423 C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
424
425 S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
426 }
427
428 static void stop(struct net_device *dev)
429 {
430 struct fs_enet_private *fep = netdev_priv(dev);
431 fcc_t *fccp = fep->fcc.fccp;
432
433 /* stop ethernet */
434 C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
435
436 /* clear events */
437 W16(fccp, fcc_fcce, 0xffff);
438
439 /* clear interrupt mask */
440 W16(fccp, fcc_fccm, 0);
441
442 fs_cleanup_bds(dev);
443 }
444
445 static void pre_request_irq(struct net_device *dev, int irq)
446 {
447 /* nothing */
448 }
449
450 static void post_free_irq(struct net_device *dev, int irq)
451 {
452 /* nothing */
453 }
454
455 static void napi_clear_rx_event(struct net_device *dev)
456 {
457 struct fs_enet_private *fep = netdev_priv(dev);
458 fcc_t *fccp = fep->fcc.fccp;
459
460 W16(fccp, fcc_fcce, FCC_NAPI_RX_EVENT_MSK);
461 }
462
463 static void napi_enable_rx(struct net_device *dev)
464 {
465 struct fs_enet_private *fep = netdev_priv(dev);
466 fcc_t *fccp = fep->fcc.fccp;
467
468 S16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
469 }
470
471 static void napi_disable_rx(struct net_device *dev)
472 {
473 struct fs_enet_private *fep = netdev_priv(dev);
474 fcc_t *fccp = fep->fcc.fccp;
475
476 C16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
477 }
478
479 static void rx_bd_done(struct net_device *dev)
480 {
481 /* nothing */
482 }
483
484 static void tx_kickstart(struct net_device *dev)
485 {
486 struct fs_enet_private *fep = netdev_priv(dev);
487 fcc_t *fccp = fep->fcc.fccp;
488
489 S16(fccp, fcc_ftodr, 0x8000);
490 }
491
492 static u32 get_int_events(struct net_device *dev)
493 {
494 struct fs_enet_private *fep = netdev_priv(dev);
495 fcc_t *fccp = fep->fcc.fccp;
496
497 return (u32)R16(fccp, fcc_fcce);
498 }
499
500 static void clear_int_events(struct net_device *dev, u32 int_events)
501 {
502 struct fs_enet_private *fep = netdev_priv(dev);
503 fcc_t *fccp = fep->fcc.fccp;
504
505 W16(fccp, fcc_fcce, int_events & 0xffff);
506 }
507
508 static void ev_error(struct net_device *dev, u32 int_events)
509 {
510 printk(KERN_WARNING DRV_MODULE_NAME
511 ": %s FS_ENET ERROR(s) 0x%x\n", dev->name, int_events);
512 }
513
514 int get_regs(struct net_device *dev, void *p, int *sizep)
515 {
516 struct fs_enet_private *fep = netdev_priv(dev);
517
518 if (*sizep < sizeof(fcc_t) + sizeof(fcc_c_t) + sizeof(fcc_enet_t))
519 return -EINVAL;
520
521 memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t));
522 p = (char *)p + sizeof(fcc_t);
523
524 memcpy_fromio(p, fep->fcc.fcccp, sizeof(fcc_c_t));
525 p = (char *)p + sizeof(fcc_c_t);
526
527 memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t));
528
529 return 0;
530 }
531
532 int get_regs_len(struct net_device *dev)
533 {
534 return sizeof(fcc_t) + sizeof(fcc_c_t) + sizeof(fcc_enet_t);
535 }
536
537 /* Some transmit errors cause the transmitter to shut
538 * down. We now issue a restart transmit. Since the
539 * errors close the BD and update the pointers, the restart
540 * _should_ pick up without having to reset any of our
541 * pointers either. Also, To workaround 8260 device erratum
542 * CPM37, we must disable and then re-enable the transmitter
543 * following a Late Collision, Underrun, or Retry Limit error.
544 */
545 void tx_restart(struct net_device *dev)
546 {
547 struct fs_enet_private *fep = netdev_priv(dev);
548 fcc_t *fccp = fep->fcc.fccp;
549
550 C32(fccp, fcc_gfmr, FCC_GFMR_ENT);
551 udelay(10);
552 S32(fccp, fcc_gfmr, FCC_GFMR_ENT);
553
554 fcc_cr_cmd(fep, 0x0C, CPM_CR_RESTART_TX);
555 }
556
557 /*************************************************************************/
558
559 const struct fs_ops fs_fcc_ops = {
560 .setup_data = setup_data,
561 .cleanup_data = cleanup_data,
562 .set_multicast_list = set_multicast_list,
563 .restart = restart,
564 .stop = stop,
565 .pre_request_irq = pre_request_irq,
566 .post_free_irq = post_free_irq,
567 .napi_clear_rx_event = napi_clear_rx_event,
568 .napi_enable_rx = napi_enable_rx,
569 .napi_disable_rx = napi_disable_rx,
570 .rx_bd_done = rx_bd_done,
571 .tx_kickstart = tx_kickstart,
572 .get_int_events = get_int_events,
573 .clear_int_events = clear_int_events,
574 .ev_error = ev_error,
575 .get_regs = get_regs,
576 .get_regs_len = get_regs_len,
577 .tx_restart = tx_restart,
578 .allocate_bd = allocate_bd,
579 .free_bd = free_bd,
580 };
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