[POWERPC] Add support for PORTA and PORTB odr registers
[deliverable/linux.git] / drivers / net / fs_enet / mac-fcc.c
1 /*
2 * FCC driver for Motorola MPC82xx (PQ2).
3 *
4 * Copyright (c) 2003 Intracom S.A.
5 * by Pantelis Antoniou <panto@intracom.gr>
6 *
7 * 2005 (c) MontaVista Software, Inc.
8 * Vitaly Bordug <vbordug@ru.mvista.com>
9 *
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/string.h>
19 #include <linux/ptrace.h>
20 #include <linux/errno.h>
21 #include <linux/ioport.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/skbuff.h>
29 #include <linux/spinlock.h>
30 #include <linux/mii.h>
31 #include <linux/ethtool.h>
32 #include <linux/bitops.h>
33 #include <linux/fs.h>
34 #include <linux/platform_device.h>
35 #include <linux/phy.h>
36
37 #include <asm/immap_cpm2.h>
38 #include <asm/mpc8260.h>
39 #include <asm/cpm2.h>
40
41 #include <asm/pgtable.h>
42 #include <asm/irq.h>
43 #include <asm/uaccess.h>
44
45 #ifdef CONFIG_PPC_CPM_NEW_BINDING
46 #include <asm/of_device.h>
47 #endif
48
49 #include "fs_enet.h"
50
51 /*************************************************/
52
53 /* FCC access macros */
54
55 /* write, read, set bits, clear bits */
56 #define W32(_p, _m, _v) out_be32(&(_p)->_m, (_v))
57 #define R32(_p, _m) in_be32(&(_p)->_m)
58 #define S32(_p, _m, _v) W32(_p, _m, R32(_p, _m) | (_v))
59 #define C32(_p, _m, _v) W32(_p, _m, R32(_p, _m) & ~(_v))
60
61 #define W16(_p, _m, _v) out_be16(&(_p)->_m, (_v))
62 #define R16(_p, _m) in_be16(&(_p)->_m)
63 #define S16(_p, _m, _v) W16(_p, _m, R16(_p, _m) | (_v))
64 #define C16(_p, _m, _v) W16(_p, _m, R16(_p, _m) & ~(_v))
65
66 #define W8(_p, _m, _v) out_8(&(_p)->_m, (_v))
67 #define R8(_p, _m) in_8(&(_p)->_m)
68 #define S8(_p, _m, _v) W8(_p, _m, R8(_p, _m) | (_v))
69 #define C8(_p, _m, _v) W8(_p, _m, R8(_p, _m) & ~(_v))
70
71 /*************************************************/
72
73 #define FCC_MAX_MULTICAST_ADDRS 64
74
75 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
76 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
77 #define mk_mii_end 0
78
79 #define MAX_CR_CMD_LOOPS 10000
80
81 static inline int fcc_cr_cmd(struct fs_enet_private *fep, u32 op)
82 {
83 const struct fs_platform_info *fpi = fep->fpi;
84 int i;
85
86 W32(cpmp, cp_cpcr, fpi->cp_command | op | CPM_CR_FLG);
87 for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
88 if ((R32(cpmp, cp_cpcr) & CPM_CR_FLG) == 0)
89 return 0;
90
91 printk(KERN_ERR "%s(): Not able to issue CPM command\n",
92 __FUNCTION__);
93 return 1;
94 }
95
96 static int do_pd_setup(struct fs_enet_private *fep)
97 {
98 #ifdef CONFIG_PPC_CPM_NEW_BINDING
99 struct of_device *ofdev = to_of_device(fep->dev);
100 struct fs_platform_info *fpi = fep->fpi;
101 int ret = -EINVAL;
102
103 fep->interrupt = of_irq_to_resource(ofdev->node, 0, NULL);
104 if (fep->interrupt == NO_IRQ)
105 goto out;
106
107 fep->fcc.fccp = of_iomap(ofdev->node, 0);
108 if (!fep->fcc.fccp)
109 goto out;
110
111 fep->fcc.ep = of_iomap(ofdev->node, 1);
112 if (!fep->fcc.ep)
113 goto out_fccp;
114
115 fep->fcc.fcccp = of_iomap(ofdev->node, 2);
116 if (!fep->fcc.fcccp)
117 goto out_ep;
118
119 fep->fcc.mem = (void __iomem *)cpm2_immr;
120 fpi->dpram_offset = cpm_dpalloc(128, 8);
121 if (IS_ERR_VALUE(fpi->dpram_offset)) {
122 ret = fpi->dpram_offset;
123 goto out_fcccp;
124 }
125
126 return 0;
127
128 out_fcccp:
129 iounmap(fep->fcc.fcccp);
130 out_ep:
131 iounmap(fep->fcc.ep);
132 out_fccp:
133 iounmap(fep->fcc.fccp);
134 out:
135 return ret;
136 #else
137 struct platform_device *pdev = to_platform_device(fep->dev);
138 struct resource *r;
139
140 /* Fill out IRQ field */
141 fep->interrupt = platform_get_irq(pdev, 0);
142 if (fep->interrupt < 0)
143 return -EINVAL;
144
145 /* Attach the memory for the FCC Parameter RAM */
146 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_pram");
147 fep->fcc.ep = ioremap(r->start, r->end - r->start + 1);
148 if (fep->fcc.ep == NULL)
149 return -EINVAL;
150
151 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fcc_regs");
152 fep->fcc.fccp = ioremap(r->start, r->end - r->start + 1);
153 if (fep->fcc.fccp == NULL)
154 return -EINVAL;
155
156 if (fep->fpi->fcc_regs_c) {
157 fep->fcc.fcccp = (void __iomem *)fep->fpi->fcc_regs_c;
158 } else {
159 r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
160 "fcc_regs_c");
161 fep->fcc.fcccp = ioremap(r->start,
162 r->end - r->start + 1);
163 }
164
165 if (fep->fcc.fcccp == NULL)
166 return -EINVAL;
167
168 fep->fcc.mem = (void __iomem *)fep->fpi->mem_offset;
169 if (fep->fcc.mem == NULL)
170 return -EINVAL;
171
172 return 0;
173 #endif
174 }
175
176 #define FCC_NAPI_RX_EVENT_MSK (FCC_ENET_RXF | FCC_ENET_RXB)
177 #define FCC_RX_EVENT (FCC_ENET_RXF)
178 #define FCC_TX_EVENT (FCC_ENET_TXB)
179 #define FCC_ERR_EVENT_MSK (FCC_ENET_TXE | FCC_ENET_BSY)
180
181 static int setup_data(struct net_device *dev)
182 {
183 struct fs_enet_private *fep = netdev_priv(dev);
184 #ifndef CONFIG_PPC_CPM_NEW_BINDING
185 struct fs_platform_info *fpi = fep->fpi;
186
187 fpi->cp_command = (fpi->cp_page << 26) |
188 (fpi->cp_block << 21) |
189 (12 << 6);
190
191 fep->fcc.idx = fs_get_fcc_index(fpi->fs_no);
192 if ((unsigned int)fep->fcc.idx >= 3) /* max 3 FCCs */
193 return -EINVAL;
194 #endif
195
196 if (do_pd_setup(fep) != 0)
197 return -EINVAL;
198
199 fep->ev_napi_rx = FCC_NAPI_RX_EVENT_MSK;
200 fep->ev_rx = FCC_RX_EVENT;
201 fep->ev_tx = FCC_TX_EVENT;
202 fep->ev_err = FCC_ERR_EVENT_MSK;
203
204 return 0;
205 }
206
207 static int allocate_bd(struct net_device *dev)
208 {
209 struct fs_enet_private *fep = netdev_priv(dev);
210 const struct fs_platform_info *fpi = fep->fpi;
211
212 fep->ring_base = (void __iomem __force *)dma_alloc_coherent(fep->dev,
213 (fpi->tx_ring + fpi->rx_ring) *
214 sizeof(cbd_t), &fep->ring_mem_addr,
215 GFP_KERNEL);
216 if (fep->ring_base == NULL)
217 return -ENOMEM;
218
219 return 0;
220 }
221
222 static void free_bd(struct net_device *dev)
223 {
224 struct fs_enet_private *fep = netdev_priv(dev);
225 const struct fs_platform_info *fpi = fep->fpi;
226
227 if (fep->ring_base)
228 dma_free_coherent(fep->dev,
229 (fpi->tx_ring + fpi->rx_ring) * sizeof(cbd_t),
230 (void __force *)fep->ring_base, fep->ring_mem_addr);
231 }
232
233 static void cleanup_data(struct net_device *dev)
234 {
235 /* nothing */
236 }
237
238 static void set_promiscuous_mode(struct net_device *dev)
239 {
240 struct fs_enet_private *fep = netdev_priv(dev);
241 fcc_t __iomem *fccp = fep->fcc.fccp;
242
243 S32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
244 }
245
246 static void set_multicast_start(struct net_device *dev)
247 {
248 struct fs_enet_private *fep = netdev_priv(dev);
249 fcc_enet_t __iomem *ep = fep->fcc.ep;
250
251 W32(ep, fen_gaddrh, 0);
252 W32(ep, fen_gaddrl, 0);
253 }
254
255 static void set_multicast_one(struct net_device *dev, const u8 *mac)
256 {
257 struct fs_enet_private *fep = netdev_priv(dev);
258 fcc_enet_t __iomem *ep = fep->fcc.ep;
259 u16 taddrh, taddrm, taddrl;
260
261 taddrh = ((u16)mac[5] << 8) | mac[4];
262 taddrm = ((u16)mac[3] << 8) | mac[2];
263 taddrl = ((u16)mac[1] << 8) | mac[0];
264
265 W16(ep, fen_taddrh, taddrh);
266 W16(ep, fen_taddrm, taddrm);
267 W16(ep, fen_taddrl, taddrl);
268 fcc_cr_cmd(fep, CPM_CR_SET_GADDR);
269 }
270
271 static void set_multicast_finish(struct net_device *dev)
272 {
273 struct fs_enet_private *fep = netdev_priv(dev);
274 fcc_t __iomem *fccp = fep->fcc.fccp;
275 fcc_enet_t __iomem *ep = fep->fcc.ep;
276
277 /* clear promiscuous always */
278 C32(fccp, fcc_fpsmr, FCC_PSMR_PRO);
279
280 /* if all multi or too many multicasts; just enable all */
281 if ((dev->flags & IFF_ALLMULTI) != 0 ||
282 dev->mc_count > FCC_MAX_MULTICAST_ADDRS) {
283
284 W32(ep, fen_gaddrh, 0xffffffff);
285 W32(ep, fen_gaddrl, 0xffffffff);
286 }
287
288 /* read back */
289 fep->fcc.gaddrh = R32(ep, fen_gaddrh);
290 fep->fcc.gaddrl = R32(ep, fen_gaddrl);
291 }
292
293 static void set_multicast_list(struct net_device *dev)
294 {
295 struct dev_mc_list *pmc;
296
297 if ((dev->flags & IFF_PROMISC) == 0) {
298 set_multicast_start(dev);
299 for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
300 set_multicast_one(dev, pmc->dmi_addr);
301 set_multicast_finish(dev);
302 } else
303 set_promiscuous_mode(dev);
304 }
305
306 static void restart(struct net_device *dev)
307 {
308 struct fs_enet_private *fep = netdev_priv(dev);
309 const struct fs_platform_info *fpi = fep->fpi;
310 fcc_t __iomem *fccp = fep->fcc.fccp;
311 fcc_c_t __iomem *fcccp = fep->fcc.fcccp;
312 fcc_enet_t __iomem *ep = fep->fcc.ep;
313 dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
314 u16 paddrh, paddrm, paddrl;
315 #ifndef CONFIG_PPC_CPM_NEW_BINDING
316 u16 mem_addr;
317 #endif
318 const unsigned char *mac;
319 int i;
320
321 C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
322
323 /* clear everything (slow & steady does it) */
324 for (i = 0; i < sizeof(*ep); i++)
325 out_8((u8 __iomem *)ep + i, 0);
326
327 /* get physical address */
328 rx_bd_base_phys = fep->ring_mem_addr;
329 tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
330
331 /* point to bds */
332 W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys);
333 W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys);
334
335 /* Set maximum bytes per receive buffer.
336 * It must be a multiple of 32.
337 */
338 W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE);
339
340 W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
341 W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
342
343 /* Allocate space in the reserved FCC area of DPRAM for the
344 * internal buffers. No one uses this space (yet), so we
345 * can do this. Later, we will add resource management for
346 * this area.
347 */
348
349 #ifdef CONFIG_PPC_CPM_NEW_BINDING
350 W16(ep, fen_genfcc.fcc_riptr, fpi->dpram_offset);
351 W16(ep, fen_genfcc.fcc_tiptr, fpi->dpram_offset + 32);
352
353 W16(ep, fen_padptr, fpi->dpram_offset + 64);
354 #else
355 mem_addr = (u32) fep->fcc.mem; /* de-fixup dpram offset */
356
357 W16(ep, fen_genfcc.fcc_riptr, (mem_addr & 0xffff));
358 W16(ep, fen_genfcc.fcc_tiptr, ((mem_addr + 32) & 0xffff));
359
360 W16(ep, fen_padptr, mem_addr + 64);
361 #endif
362
363 /* fill with special symbol... */
364 memset_io(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32);
365
366 W32(ep, fen_genfcc.fcc_rbptr, 0);
367 W32(ep, fen_genfcc.fcc_tbptr, 0);
368 W32(ep, fen_genfcc.fcc_rcrc, 0);
369 W32(ep, fen_genfcc.fcc_tcrc, 0);
370 W16(ep, fen_genfcc.fcc_res1, 0);
371 W32(ep, fen_genfcc.fcc_res2, 0);
372
373 /* no CAM */
374 W32(ep, fen_camptr, 0);
375
376 /* Set CRC preset and mask */
377 W32(ep, fen_cmask, 0xdebb20e3);
378 W32(ep, fen_cpres, 0xffffffff);
379
380 W32(ep, fen_crcec, 0); /* CRC Error counter */
381 W32(ep, fen_alec, 0); /* alignment error counter */
382 W32(ep, fen_disfc, 0); /* discard frame counter */
383 W16(ep, fen_retlim, 15); /* Retry limit threshold */
384 W16(ep, fen_pper, 0); /* Normal persistence */
385
386 /* set group address */
387 W32(ep, fen_gaddrh, fep->fcc.gaddrh);
388 W32(ep, fen_gaddrl, fep->fcc.gaddrh);
389
390 /* Clear hash filter tables */
391 W32(ep, fen_iaddrh, 0);
392 W32(ep, fen_iaddrl, 0);
393
394 /* Clear the Out-of-sequence TxBD */
395 W16(ep, fen_tfcstat, 0);
396 W16(ep, fen_tfclen, 0);
397 W32(ep, fen_tfcptr, 0);
398
399 W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */
400 W16(ep, fen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */
401
402 /* set address */
403 mac = dev->dev_addr;
404 paddrh = ((u16)mac[5] << 8) | mac[4];
405 paddrm = ((u16)mac[3] << 8) | mac[2];
406 paddrl = ((u16)mac[1] << 8) | mac[0];
407
408 W16(ep, fen_paddrh, paddrh);
409 W16(ep, fen_paddrm, paddrm);
410 W16(ep, fen_paddrl, paddrl);
411
412 W16(ep, fen_taddrh, 0);
413 W16(ep, fen_taddrm, 0);
414 W16(ep, fen_taddrl, 0);
415
416 W16(ep, fen_maxd1, 1520); /* maximum DMA1 length */
417 W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */
418
419 /* Clear stat counters, in case we ever enable RMON */
420 W32(ep, fen_octc, 0);
421 W32(ep, fen_colc, 0);
422 W32(ep, fen_broc, 0);
423 W32(ep, fen_mulc, 0);
424 W32(ep, fen_uspc, 0);
425 W32(ep, fen_frgc, 0);
426 W32(ep, fen_ospc, 0);
427 W32(ep, fen_jbrc, 0);
428 W32(ep, fen_p64c, 0);
429 W32(ep, fen_p65c, 0);
430 W32(ep, fen_p128c, 0);
431 W32(ep, fen_p256c, 0);
432 W32(ep, fen_p512c, 0);
433 W32(ep, fen_p1024c, 0);
434
435 W16(ep, fen_rfthr, 0); /* Suggested by manual */
436 W16(ep, fen_rfcnt, 0);
437 W16(ep, fen_cftype, 0);
438
439 fs_init_bds(dev);
440
441 /* adjust to speed (for RMII mode) */
442 if (fpi->use_rmii) {
443 if (fep->phydev->speed == 100)
444 C8(fcccp, fcc_gfemr, 0x20);
445 else
446 S8(fcccp, fcc_gfemr, 0x20);
447 }
448
449 fcc_cr_cmd(fep, CPM_CR_INIT_TRX);
450
451 /* clear events */
452 W16(fccp, fcc_fcce, 0xffff);
453
454 /* Enable interrupts we wish to service */
455 W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
456
457 /* Set GFMR to enable Ethernet operating mode */
458 W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
459
460 /* set sync/delimiters */
461 W16(fccp, fcc_fdsr, 0xd555);
462
463 W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC);
464
465 if (fpi->use_rmii)
466 S32(fccp, fcc_fpsmr, FCC_PSMR_RMII);
467
468 /* adjust to duplex mode */
469 if (fep->phydev->duplex)
470 S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
471 else
472 C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
473
474 S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
475 }
476
477 static void stop(struct net_device *dev)
478 {
479 struct fs_enet_private *fep = netdev_priv(dev);
480 fcc_t __iomem *fccp = fep->fcc.fccp;
481
482 /* stop ethernet */
483 C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
484
485 /* clear events */
486 W16(fccp, fcc_fcce, 0xffff);
487
488 /* clear interrupt mask */
489 W16(fccp, fcc_fccm, 0);
490
491 fs_cleanup_bds(dev);
492 }
493
494 static void pre_request_irq(struct net_device *dev, int irq)
495 {
496 /* nothing */
497 }
498
499 static void post_free_irq(struct net_device *dev, int irq)
500 {
501 /* nothing */
502 }
503
504 static void napi_clear_rx_event(struct net_device *dev)
505 {
506 struct fs_enet_private *fep = netdev_priv(dev);
507 fcc_t __iomem *fccp = fep->fcc.fccp;
508
509 W16(fccp, fcc_fcce, FCC_NAPI_RX_EVENT_MSK);
510 }
511
512 static void napi_enable_rx(struct net_device *dev)
513 {
514 struct fs_enet_private *fep = netdev_priv(dev);
515 fcc_t __iomem *fccp = fep->fcc.fccp;
516
517 S16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
518 }
519
520 static void napi_disable_rx(struct net_device *dev)
521 {
522 struct fs_enet_private *fep = netdev_priv(dev);
523 fcc_t __iomem *fccp = fep->fcc.fccp;
524
525 C16(fccp, fcc_fccm, FCC_NAPI_RX_EVENT_MSK);
526 }
527
528 static void rx_bd_done(struct net_device *dev)
529 {
530 /* nothing */
531 }
532
533 static void tx_kickstart(struct net_device *dev)
534 {
535 struct fs_enet_private *fep = netdev_priv(dev);
536 fcc_t __iomem *fccp = fep->fcc.fccp;
537
538 S16(fccp, fcc_ftodr, 0x8000);
539 }
540
541 static u32 get_int_events(struct net_device *dev)
542 {
543 struct fs_enet_private *fep = netdev_priv(dev);
544 fcc_t __iomem *fccp = fep->fcc.fccp;
545
546 return (u32)R16(fccp, fcc_fcce);
547 }
548
549 static void clear_int_events(struct net_device *dev, u32 int_events)
550 {
551 struct fs_enet_private *fep = netdev_priv(dev);
552 fcc_t __iomem *fccp = fep->fcc.fccp;
553
554 W16(fccp, fcc_fcce, int_events & 0xffff);
555 }
556
557 static void ev_error(struct net_device *dev, u32 int_events)
558 {
559 printk(KERN_WARNING DRV_MODULE_NAME
560 ": %s FS_ENET ERROR(s) 0x%x\n", dev->name, int_events);
561 }
562
563 static int get_regs(struct net_device *dev, void *p, int *sizep)
564 {
565 struct fs_enet_private *fep = netdev_priv(dev);
566
567 if (*sizep < sizeof(fcc_t) + sizeof(fcc_enet_t) + 1)
568 return -EINVAL;
569
570 memcpy_fromio(p, fep->fcc.fccp, sizeof(fcc_t));
571 p = (char *)p + sizeof(fcc_t);
572
573 memcpy_fromio(p, fep->fcc.ep, sizeof(fcc_enet_t));
574 p = (char *)p + sizeof(fcc_enet_t);
575
576 memcpy_fromio(p, fep->fcc.fcccp, 1);
577 return 0;
578 }
579
580 static int get_regs_len(struct net_device *dev)
581 {
582 return sizeof(fcc_t) + sizeof(fcc_enet_t) + 1;
583 }
584
585 /* Some transmit errors cause the transmitter to shut
586 * down. We now issue a restart transmit. Since the
587 * errors close the BD and update the pointers, the restart
588 * _should_ pick up without having to reset any of our
589 * pointers either. Also, To workaround 8260 device erratum
590 * CPM37, we must disable and then re-enable the transmitter
591 * following a Late Collision, Underrun, or Retry Limit error.
592 */
593 static void tx_restart(struct net_device *dev)
594 {
595 struct fs_enet_private *fep = netdev_priv(dev);
596 fcc_t __iomem *fccp = fep->fcc.fccp;
597
598 C32(fccp, fcc_gfmr, FCC_GFMR_ENT);
599 udelay(10);
600 S32(fccp, fcc_gfmr, FCC_GFMR_ENT);
601
602 fcc_cr_cmd(fep, CPM_CR_RESTART_TX);
603 }
604
605 /*************************************************************************/
606
607 const struct fs_ops fs_fcc_ops = {
608 .setup_data = setup_data,
609 .cleanup_data = cleanup_data,
610 .set_multicast_list = set_multicast_list,
611 .restart = restart,
612 .stop = stop,
613 .pre_request_irq = pre_request_irq,
614 .post_free_irq = post_free_irq,
615 .napi_clear_rx_event = napi_clear_rx_event,
616 .napi_enable_rx = napi_enable_rx,
617 .napi_disable_rx = napi_disable_rx,
618 .rx_bd_done = rx_bd_done,
619 .tx_kickstart = tx_kickstart,
620 .get_int_events = get_int_events,
621 .clear_int_events = clear_int_events,
622 .ev_error = ev_error,
623 .get_regs = get_regs,
624 .get_regs_len = get_regs_len,
625 .tx_restart = tx_restart,
626 .allocate_bd = allocate_bd,
627 .free_bd = free_bd,
628 };
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