2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * Gianfar: AKA Lambda Draconis, "Dragon"
29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
36 * last descriptor of the ring.
38 * When a packet is received, the RXF bit in the
39 * IEVENT register is set, triggering an interrupt when the
40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
43 * of frames or amount of time have passed). In NAPI, the
44 * interrupt handler will signal there is work to be done, and
45 * exit. This method will start at the last known empty
46 * descriptor, and process every subsequent descriptor until there
47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
65 #include <linux/kernel.h>
66 #include <linux/string.h>
67 #include <linux/errno.h>
68 #include <linux/unistd.h>
69 #include <linux/slab.h>
70 #include <linux/interrupt.h>
71 #include <linux/init.h>
72 #include <linux/delay.h>
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/if_vlan.h>
77 #include <linux/spinlock.h>
79 #include <linux/of_mdio.h>
80 #include <linux/of_platform.h>
82 #include <linux/tcp.h>
83 #include <linux/udp.h>
85 #include <linux/net_tstamp.h>
89 #include <asm/uaccess.h>
90 #include <linux/module.h>
91 #include <linux/dma-mapping.h>
92 #include <linux/crc32.h>
93 #include <linux/mii.h>
94 #include <linux/phy.h>
95 #include <linux/phy_fixed.h>
99 #include "fsl_pq_mdio.h"
101 #define TX_TIMEOUT (1*HZ)
102 #undef BRIEF_GFAR_ERRORS
103 #undef VERBOSE_GFAR_ERRORS
105 const char gfar_driver_name
[] = "Gianfar Ethernet";
106 const char gfar_driver_version
[] = "1.3";
108 static int gfar_enet_open(struct net_device
*dev
);
109 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
110 static void gfar_reset_task(struct work_struct
*work
);
111 static void gfar_timeout(struct net_device
*dev
);
112 static int gfar_close(struct net_device
*dev
);
113 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
114 static void gfar_new_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
115 struct sk_buff
*skb
);
116 static int gfar_set_mac_address(struct net_device
*dev
);
117 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
118 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
119 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
120 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
121 static void adjust_link(struct net_device
*dev
);
122 static void init_registers(struct net_device
*dev
);
123 static int init_phy(struct net_device
*dev
);
124 static int gfar_probe(struct of_device
*ofdev
,
125 const struct of_device_id
*match
);
126 static int gfar_remove(struct of_device
*ofdev
);
127 static void free_skb_resources(struct gfar_private
*priv
);
128 static void gfar_set_multi(struct net_device
*dev
);
129 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
130 static void gfar_configure_serdes(struct net_device
*dev
);
131 static int gfar_poll(struct napi_struct
*napi
, int budget
);
132 #ifdef CONFIG_NET_POLL_CONTROLLER
133 static void gfar_netpoll(struct net_device
*dev
);
135 int gfar_clean_rx_ring(struct gfar_priv_rx_q
*rx_queue
, int rx_work_limit
);
136 static int gfar_clean_tx_ring(struct gfar_priv_tx_q
*tx_queue
);
137 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
139 static void gfar_vlan_rx_register(struct net_device
*netdev
,
140 struct vlan_group
*grp
);
141 void gfar_halt(struct net_device
*dev
);
142 static void gfar_halt_nodisable(struct net_device
*dev
);
143 void gfar_start(struct net_device
*dev
);
144 static void gfar_clear_exact_match(struct net_device
*dev
);
145 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
146 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
148 MODULE_AUTHOR("Freescale Semiconductor, Inc");
149 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150 MODULE_LICENSE("GPL");
152 static void gfar_init_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
159 lstatus
= BD_LFLAG(RXBD_EMPTY
| RXBD_INTERRUPT
);
160 if (bdp
== rx_queue
->rx_bd_base
+ rx_queue
->rx_ring_size
- 1)
161 lstatus
|= BD_LFLAG(RXBD_WRAP
);
165 bdp
->lstatus
= lstatus
;
168 static int gfar_init_bds(struct net_device
*ndev
)
170 struct gfar_private
*priv
= netdev_priv(ndev
);
171 struct gfar_priv_tx_q
*tx_queue
= NULL
;
172 struct gfar_priv_rx_q
*rx_queue
= NULL
;
177 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
178 tx_queue
= priv
->tx_queue
[i
];
179 /* Initialize some variables in our dev structure */
180 tx_queue
->num_txbdfree
= tx_queue
->tx_ring_size
;
181 tx_queue
->dirty_tx
= tx_queue
->tx_bd_base
;
182 tx_queue
->cur_tx
= tx_queue
->tx_bd_base
;
183 tx_queue
->skb_curtx
= 0;
184 tx_queue
->skb_dirtytx
= 0;
186 /* Initialize Transmit Descriptor Ring */
187 txbdp
= tx_queue
->tx_bd_base
;
188 for (j
= 0; j
< tx_queue
->tx_ring_size
; j
++) {
194 /* Set the last descriptor in the ring to indicate wrap */
196 txbdp
->status
|= TXBD_WRAP
;
199 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
200 rx_queue
= priv
->rx_queue
[i
];
201 rx_queue
->cur_rx
= rx_queue
->rx_bd_base
;
202 rx_queue
->skb_currx
= 0;
203 rxbdp
= rx_queue
->rx_bd_base
;
205 for (j
= 0; j
< rx_queue
->rx_ring_size
; j
++) {
206 struct sk_buff
*skb
= rx_queue
->rx_skbuff
[j
];
209 gfar_init_rxbdp(rx_queue
, rxbdp
,
212 skb
= gfar_new_skb(ndev
);
214 pr_err("%s: Can't allocate RX buffers\n",
216 goto err_rxalloc_fail
;
218 rx_queue
->rx_skbuff
[j
] = skb
;
220 gfar_new_rxbdp(rx_queue
, rxbdp
, skb
);
231 free_skb_resources(priv
);
235 static int gfar_alloc_skb_resources(struct net_device
*ndev
)
240 struct gfar_private
*priv
= netdev_priv(ndev
);
241 struct device
*dev
= &priv
->ofdev
->dev
;
242 struct gfar_priv_tx_q
*tx_queue
= NULL
;
243 struct gfar_priv_rx_q
*rx_queue
= NULL
;
245 priv
->total_tx_ring_size
= 0;
246 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
247 priv
->total_tx_ring_size
+= priv
->tx_queue
[i
]->tx_ring_size
;
249 priv
->total_rx_ring_size
= 0;
250 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
251 priv
->total_rx_ring_size
+= priv
->rx_queue
[i
]->rx_ring_size
;
253 /* Allocate memory for the buffer descriptors */
254 vaddr
= dma_alloc_coherent(dev
,
255 sizeof(struct txbd8
) * priv
->total_tx_ring_size
+
256 sizeof(struct rxbd8
) * priv
->total_rx_ring_size
,
259 if (netif_msg_ifup(priv
))
260 pr_err("%s: Could not allocate buffer descriptors!\n",
265 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
266 tx_queue
= priv
->tx_queue
[i
];
267 tx_queue
->tx_bd_base
= (struct txbd8
*) vaddr
;
268 tx_queue
->tx_bd_dma_base
= addr
;
269 tx_queue
->dev
= ndev
;
270 /* enet DMA only understands physical addresses */
271 addr
+= sizeof(struct txbd8
) *tx_queue
->tx_ring_size
;
272 vaddr
+= sizeof(struct txbd8
) *tx_queue
->tx_ring_size
;
275 /* Start the rx descriptor ring where the tx ring leaves off */
276 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
277 rx_queue
= priv
->rx_queue
[i
];
278 rx_queue
->rx_bd_base
= (struct rxbd8
*) vaddr
;
279 rx_queue
->rx_bd_dma_base
= addr
;
280 rx_queue
->dev
= ndev
;
281 addr
+= sizeof (struct rxbd8
) * rx_queue
->rx_ring_size
;
282 vaddr
+= sizeof (struct rxbd8
) * rx_queue
->rx_ring_size
;
285 /* Setup the skbuff rings */
286 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
287 tx_queue
= priv
->tx_queue
[i
];
288 tx_queue
->tx_skbuff
= kmalloc(sizeof(*tx_queue
->tx_skbuff
) *
289 tx_queue
->tx_ring_size
, GFP_KERNEL
);
290 if (!tx_queue
->tx_skbuff
) {
291 if (netif_msg_ifup(priv
))
292 pr_err("%s: Could not allocate tx_skbuff\n",
297 for (k
= 0; k
< tx_queue
->tx_ring_size
; k
++)
298 tx_queue
->tx_skbuff
[k
] = NULL
;
301 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
302 rx_queue
= priv
->rx_queue
[i
];
303 rx_queue
->rx_skbuff
= kmalloc(sizeof(*rx_queue
->rx_skbuff
) *
304 rx_queue
->rx_ring_size
, GFP_KERNEL
);
306 if (!rx_queue
->rx_skbuff
) {
307 if (netif_msg_ifup(priv
))
308 pr_err("%s: Could not allocate rx_skbuff\n",
313 for (j
= 0; j
< rx_queue
->rx_ring_size
; j
++)
314 rx_queue
->rx_skbuff
[j
] = NULL
;
317 if (gfar_init_bds(ndev
))
323 free_skb_resources(priv
);
327 static void gfar_init_tx_rx_base(struct gfar_private
*priv
)
329 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
333 baddr
= ®s
->tbase0
;
334 for(i
= 0; i
< priv
->num_tx_queues
; i
++) {
335 gfar_write(baddr
, priv
->tx_queue
[i
]->tx_bd_dma_base
);
339 baddr
= ®s
->rbase0
;
340 for(i
= 0; i
< priv
->num_rx_queues
; i
++) {
341 gfar_write(baddr
, priv
->rx_queue
[i
]->rx_bd_dma_base
);
346 static void gfar_init_mac(struct net_device
*ndev
)
348 struct gfar_private
*priv
= netdev_priv(ndev
);
349 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
354 /* write the tx/rx base registers */
355 gfar_init_tx_rx_base(priv
);
357 /* Configure the coalescing support */
358 gfar_configure_coalescing(priv
, 0xFF, 0xFF);
360 if (priv
->rx_filer_enable
) {
361 rctrl
|= RCTRL_FILREN
;
362 /* Program the RIR0 reg with the required distribution */
363 gfar_write(®s
->rir0
, DEFAULT_RIR0
);
366 if (priv
->rx_csum_enable
)
367 rctrl
|= RCTRL_CHECKSUMMING
;
369 if (priv
->extended_hash
) {
370 rctrl
|= RCTRL_EXTHASH
;
372 gfar_clear_exact_match(ndev
);
377 rctrl
&= ~RCTRL_PAL_MASK
;
378 rctrl
|= RCTRL_PADDING(priv
->padding
);
381 /* Insert receive time stamps into padding alignment bytes */
382 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
) {
383 rctrl
&= ~RCTRL_PAL_MASK
;
384 rctrl
|= RCTRL_PRSDEP_INIT
| RCTRL_TS_ENABLE
| RCTRL_PADDING(8);
388 /* keep vlan related bits if it's enabled */
390 rctrl
|= RCTRL_VLEX
| RCTRL_PRSDEP_INIT
;
391 tctrl
|= TCTRL_VLINS
;
394 /* Init rctrl based on our settings */
395 gfar_write(®s
->rctrl
, rctrl
);
397 if (ndev
->features
& NETIF_F_IP_CSUM
)
398 tctrl
|= TCTRL_INIT_CSUM
;
400 tctrl
|= TCTRL_TXSCHED_PRIO
;
402 gfar_write(®s
->tctrl
, tctrl
);
404 /* Set the extraction length and index */
405 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
406 ATTRELI_EI(priv
->rx_stash_index
);
408 gfar_write(®s
->attreli
, attrs
);
410 /* Start with defaults, and add stashing or locking
411 * depending on the approprate variables */
412 attrs
= ATTR_INIT_SETTINGS
;
414 if (priv
->bd_stash_en
)
415 attrs
|= ATTR_BDSTASH
;
417 if (priv
->rx_stash_size
!= 0)
418 attrs
|= ATTR_BUFSTASH
;
420 gfar_write(®s
->attr
, attrs
);
422 gfar_write(®s
->fifo_tx_thr
, priv
->fifo_threshold
);
423 gfar_write(®s
->fifo_tx_starve
, priv
->fifo_starve
);
424 gfar_write(®s
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
427 static struct net_device_stats
*gfar_get_stats(struct net_device
*dev
)
429 struct gfar_private
*priv
= netdev_priv(dev
);
430 struct netdev_queue
*txq
;
431 unsigned long rx_packets
= 0, rx_bytes
= 0, rx_dropped
= 0;
432 unsigned long tx_packets
= 0, tx_bytes
= 0;
435 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
436 rx_packets
+= priv
->rx_queue
[i
]->stats
.rx_packets
;
437 rx_bytes
+= priv
->rx_queue
[i
]->stats
.rx_bytes
;
438 rx_dropped
+= priv
->rx_queue
[i
]->stats
.rx_dropped
;
441 dev
->stats
.rx_packets
= rx_packets
;
442 dev
->stats
.rx_bytes
= rx_bytes
;
443 dev
->stats
.rx_dropped
= rx_dropped
;
445 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
446 txq
= netdev_get_tx_queue(dev
, i
);
447 tx_bytes
+= txq
->tx_bytes
;
448 tx_packets
+= txq
->tx_packets
;
451 dev
->stats
.tx_bytes
= tx_bytes
;
452 dev
->stats
.tx_packets
= tx_packets
;
457 static const struct net_device_ops gfar_netdev_ops
= {
458 .ndo_open
= gfar_enet_open
,
459 .ndo_start_xmit
= gfar_start_xmit
,
460 .ndo_stop
= gfar_close
,
461 .ndo_change_mtu
= gfar_change_mtu
,
462 .ndo_set_multicast_list
= gfar_set_multi
,
463 .ndo_tx_timeout
= gfar_timeout
,
464 .ndo_do_ioctl
= gfar_ioctl
,
465 .ndo_get_stats
= gfar_get_stats
,
466 .ndo_vlan_rx_register
= gfar_vlan_rx_register
,
467 .ndo_set_mac_address
= eth_mac_addr
,
468 .ndo_validate_addr
= eth_validate_addr
,
469 #ifdef CONFIG_NET_POLL_CONTROLLER
470 .ndo_poll_controller
= gfar_netpoll
,
474 unsigned int ftp_rqfpr
[MAX_FILER_IDX
+ 1];
475 unsigned int ftp_rqfcr
[MAX_FILER_IDX
+ 1];
477 void lock_rx_qs(struct gfar_private
*priv
)
481 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
482 spin_lock(&priv
->rx_queue
[i
]->rxlock
);
485 void lock_tx_qs(struct gfar_private
*priv
)
489 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
490 spin_lock(&priv
->tx_queue
[i
]->txlock
);
493 void unlock_rx_qs(struct gfar_private
*priv
)
497 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
498 spin_unlock(&priv
->rx_queue
[i
]->rxlock
);
501 void unlock_tx_qs(struct gfar_private
*priv
)
505 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
506 spin_unlock(&priv
->tx_queue
[i
]->txlock
);
509 /* Returns 1 if incoming frames use an FCB */
510 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
512 return priv
->vlgrp
|| priv
->rx_csum_enable
||
513 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
);
516 static void free_tx_pointers(struct gfar_private
*priv
)
520 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
521 kfree(priv
->tx_queue
[i
]);
524 static void free_rx_pointers(struct gfar_private
*priv
)
528 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
529 kfree(priv
->rx_queue
[i
]);
532 static void unmap_group_regs(struct gfar_private
*priv
)
536 for (i
= 0; i
< MAXGROUPS
; i
++)
537 if (priv
->gfargrp
[i
].regs
)
538 iounmap(priv
->gfargrp
[i
].regs
);
541 static void disable_napi(struct gfar_private
*priv
)
545 for (i
= 0; i
< priv
->num_grps
; i
++)
546 napi_disable(&priv
->gfargrp
[i
].napi
);
549 static void enable_napi(struct gfar_private
*priv
)
553 for (i
= 0; i
< priv
->num_grps
; i
++)
554 napi_enable(&priv
->gfargrp
[i
].napi
);
557 static int gfar_parse_group(struct device_node
*np
,
558 struct gfar_private
*priv
, const char *model
)
563 addr
= of_translate_address(np
,
564 of_get_address(np
, 0, &size
, NULL
));
565 priv
->gfargrp
[priv
->num_grps
].regs
= ioremap(addr
, size
);
567 if (!priv
->gfargrp
[priv
->num_grps
].regs
)
570 priv
->gfargrp
[priv
->num_grps
].interruptTransmit
=
571 irq_of_parse_and_map(np
, 0);
573 /* If we aren't the FEC we have multiple interrupts */
574 if (model
&& strcasecmp(model
, "FEC")) {
575 priv
->gfargrp
[priv
->num_grps
].interruptReceive
=
576 irq_of_parse_and_map(np
, 1);
577 priv
->gfargrp
[priv
->num_grps
].interruptError
=
578 irq_of_parse_and_map(np
,2);
579 if (priv
->gfargrp
[priv
->num_grps
].interruptTransmit
< 0 ||
580 priv
->gfargrp
[priv
->num_grps
].interruptReceive
< 0 ||
581 priv
->gfargrp
[priv
->num_grps
].interruptError
< 0) {
586 priv
->gfargrp
[priv
->num_grps
].grp_id
= priv
->num_grps
;
587 priv
->gfargrp
[priv
->num_grps
].priv
= priv
;
588 spin_lock_init(&priv
->gfargrp
[priv
->num_grps
].grplock
);
589 if(priv
->mode
== MQ_MG_MODE
) {
590 queue_mask
= (u32
*)of_get_property(np
,
591 "fsl,rx-bit-map", NULL
);
592 priv
->gfargrp
[priv
->num_grps
].rx_bit_map
=
593 queue_mask
? *queue_mask
:(DEFAULT_MAPPING
>> priv
->num_grps
);
594 queue_mask
= (u32
*)of_get_property(np
,
595 "fsl,tx-bit-map", NULL
);
596 priv
->gfargrp
[priv
->num_grps
].tx_bit_map
=
597 queue_mask
? *queue_mask
: (DEFAULT_MAPPING
>> priv
->num_grps
);
599 priv
->gfargrp
[priv
->num_grps
].rx_bit_map
= 0xFF;
600 priv
->gfargrp
[priv
->num_grps
].tx_bit_map
= 0xFF;
607 static int gfar_of_init(struct of_device
*ofdev
, struct net_device
**pdev
)
611 const void *mac_addr
;
613 struct net_device
*dev
= NULL
;
614 struct gfar_private
*priv
= NULL
;
615 struct device_node
*np
= ofdev
->node
;
616 struct device_node
*child
= NULL
;
618 const u32
*stash_len
;
619 const u32
*stash_idx
;
620 unsigned int num_tx_qs
, num_rx_qs
;
621 u32
*tx_queues
, *rx_queues
;
623 if (!np
|| !of_device_is_available(np
))
626 /* parse the num of tx and rx queues */
627 tx_queues
= (u32
*)of_get_property(np
, "fsl,num_tx_queues", NULL
);
628 num_tx_qs
= tx_queues
? *tx_queues
: 1;
630 if (num_tx_qs
> MAX_TX_QS
) {
631 printk(KERN_ERR
"num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
632 num_tx_qs
, MAX_TX_QS
);
633 printk(KERN_ERR
"Cannot do alloc_etherdev, aborting\n");
637 rx_queues
= (u32
*)of_get_property(np
, "fsl,num_rx_queues", NULL
);
638 num_rx_qs
= rx_queues
? *rx_queues
: 1;
640 if (num_rx_qs
> MAX_RX_QS
) {
641 printk(KERN_ERR
"num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
642 num_tx_qs
, MAX_TX_QS
);
643 printk(KERN_ERR
"Cannot do alloc_etherdev, aborting\n");
647 *pdev
= alloc_etherdev_mq(sizeof(*priv
), num_tx_qs
);
652 priv
= netdev_priv(dev
);
653 priv
->node
= ofdev
->node
;
656 dev
->num_tx_queues
= num_tx_qs
;
657 dev
->real_num_tx_queues
= num_tx_qs
;
658 priv
->num_tx_queues
= num_tx_qs
;
659 priv
->num_rx_queues
= num_rx_qs
;
660 priv
->num_grps
= 0x0;
662 model
= of_get_property(np
, "model", NULL
);
664 for (i
= 0; i
< MAXGROUPS
; i
++)
665 priv
->gfargrp
[i
].regs
= NULL
;
667 /* Parse and initialize group specific information */
668 if (of_device_is_compatible(np
, "fsl,etsec2")) {
669 priv
->mode
= MQ_MG_MODE
;
670 for_each_child_of_node(np
, child
) {
671 err
= gfar_parse_group(child
, priv
, model
);
676 priv
->mode
= SQ_SG_MODE
;
677 err
= gfar_parse_group(np
, priv
, model
);
682 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
683 priv
->tx_queue
[i
] = NULL
;
684 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
685 priv
->rx_queue
[i
] = NULL
;
687 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
688 priv
->tx_queue
[i
] = (struct gfar_priv_tx_q
*)kzalloc(
689 sizeof (struct gfar_priv_tx_q
), GFP_KERNEL
);
690 if (!priv
->tx_queue
[i
]) {
692 goto tx_alloc_failed
;
694 priv
->tx_queue
[i
]->tx_skbuff
= NULL
;
695 priv
->tx_queue
[i
]->qindex
= i
;
696 priv
->tx_queue
[i
]->dev
= dev
;
697 spin_lock_init(&(priv
->tx_queue
[i
]->txlock
));
700 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
701 priv
->rx_queue
[i
] = (struct gfar_priv_rx_q
*)kzalloc(
702 sizeof (struct gfar_priv_rx_q
), GFP_KERNEL
);
703 if (!priv
->rx_queue
[i
]) {
705 goto rx_alloc_failed
;
707 priv
->rx_queue
[i
]->rx_skbuff
= NULL
;
708 priv
->rx_queue
[i
]->qindex
= i
;
709 priv
->rx_queue
[i
]->dev
= dev
;
710 spin_lock_init(&(priv
->rx_queue
[i
]->rxlock
));
714 stash
= of_get_property(np
, "bd-stash", NULL
);
717 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BD_STASHING
;
718 priv
->bd_stash_en
= 1;
721 stash_len
= of_get_property(np
, "rx-stash-len", NULL
);
724 priv
->rx_stash_size
= *stash_len
;
726 stash_idx
= of_get_property(np
, "rx-stash-idx", NULL
);
729 priv
->rx_stash_index
= *stash_idx
;
731 if (stash_len
|| stash_idx
)
732 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BUF_STASHING
;
734 mac_addr
= of_get_mac_address(np
);
736 memcpy(dev
->dev_addr
, mac_addr
, MAC_ADDR_LEN
);
738 if (model
&& !strcasecmp(model
, "TSEC"))
740 FSL_GIANFAR_DEV_HAS_GIGABIT
|
741 FSL_GIANFAR_DEV_HAS_COALESCE
|
742 FSL_GIANFAR_DEV_HAS_RMON
|
743 FSL_GIANFAR_DEV_HAS_MULTI_INTR
;
744 if (model
&& !strcasecmp(model
, "eTSEC"))
746 FSL_GIANFAR_DEV_HAS_GIGABIT
|
747 FSL_GIANFAR_DEV_HAS_COALESCE
|
748 FSL_GIANFAR_DEV_HAS_RMON
|
749 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
750 FSL_GIANFAR_DEV_HAS_PADDING
|
751 FSL_GIANFAR_DEV_HAS_CSUM
|
752 FSL_GIANFAR_DEV_HAS_VLAN
|
753 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
|
754 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
|
755 FSL_GIANFAR_DEV_HAS_TIMER
;
757 ctype
= of_get_property(np
, "phy-connection-type", NULL
);
759 /* We only care about rgmii-id. The rest are autodetected */
760 if (ctype
&& !strcmp(ctype
, "rgmii-id"))
761 priv
->interface
= PHY_INTERFACE_MODE_RGMII_ID
;
763 priv
->interface
= PHY_INTERFACE_MODE_MII
;
765 if (of_get_property(np
, "fsl,magic-packet", NULL
))
766 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
;
768 priv
->phy_node
= of_parse_phandle(np
, "phy-handle", 0);
770 /* Find the TBI PHY. If it's not there, we don't support SGMII */
771 priv
->tbi_node
= of_parse_phandle(np
, "tbi-handle", 0);
776 free_rx_pointers(priv
);
778 free_tx_pointers(priv
);
780 unmap_group_regs(priv
);
785 static int gfar_hwtstamp_ioctl(struct net_device
*netdev
,
786 struct ifreq
*ifr
, int cmd
)
788 struct hwtstamp_config config
;
789 struct gfar_private
*priv
= netdev_priv(netdev
);
791 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
794 /* reserved for future extensions */
798 switch (config
.tx_type
) {
799 case HWTSTAMP_TX_OFF
:
800 priv
->hwts_tx_en
= 0;
803 if (!(priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
))
805 priv
->hwts_tx_en
= 1;
811 switch (config
.rx_filter
) {
812 case HWTSTAMP_FILTER_NONE
:
813 priv
->hwts_rx_en
= 0;
816 if (!(priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
))
818 priv
->hwts_rx_en
= 1;
819 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
823 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
827 /* Ioctl MII Interface */
828 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
830 struct gfar_private
*priv
= netdev_priv(dev
);
832 if (!netif_running(dev
))
835 if (cmd
== SIOCSHWTSTAMP
)
836 return gfar_hwtstamp_ioctl(dev
, rq
, cmd
);
841 return phy_mii_ioctl(priv
->phydev
, if_mii(rq
), cmd
);
844 static unsigned int reverse_bitmap(unsigned int bit_map
, unsigned int max_qs
)
846 unsigned int new_bit_map
= 0x0;
847 int mask
= 0x1 << (max_qs
- 1), i
;
848 for (i
= 0; i
< max_qs
; i
++) {
850 new_bit_map
= new_bit_map
+ (1 << i
);
856 static u32
cluster_entry_per_class(struct gfar_private
*priv
, u32 rqfar
,
859 u32 rqfpr
= FPR_FILER_MASK
;
863 rqfcr
= RQFCR_CLE
| RQFCR_PID_MASK
| RQFCR_CMP_EXACT
;
864 ftp_rqfpr
[rqfar
] = rqfpr
;
865 ftp_rqfcr
[rqfar
] = rqfcr
;
866 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
869 rqfcr
= RQFCR_CMP_NOMATCH
;
870 ftp_rqfpr
[rqfar
] = rqfpr
;
871 ftp_rqfcr
[rqfar
] = rqfcr
;
872 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
875 rqfcr
= RQFCR_CMP_EXACT
| RQFCR_PID_PARSE
| RQFCR_CLE
| RQFCR_AND
;
877 ftp_rqfcr
[rqfar
] = rqfcr
;
878 ftp_rqfpr
[rqfar
] = rqfpr
;
879 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
882 rqfcr
= RQFCR_CMP_EXACT
| RQFCR_PID_MASK
| RQFCR_AND
;
884 ftp_rqfcr
[rqfar
] = rqfcr
;
885 ftp_rqfpr
[rqfar
] = rqfpr
;
886 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
891 static void gfar_init_filer_table(struct gfar_private
*priv
)
894 u32 rqfar
= MAX_FILER_IDX
;
896 u32 rqfpr
= FPR_FILER_MASK
;
899 rqfcr
= RQFCR_CMP_MATCH
;
900 ftp_rqfcr
[rqfar
] = rqfcr
;
901 ftp_rqfpr
[rqfar
] = rqfpr
;
902 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
904 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
);
905 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
| RQFPR_UDP
);
906 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
| RQFPR_TCP
);
907 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
);
908 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
| RQFPR_UDP
);
909 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
| RQFPR_TCP
);
911 /* cur_filer_idx indicated the fisrt non-masked rule */
912 priv
->cur_filer_idx
= rqfar
;
914 /* Rest are masked rules */
915 rqfcr
= RQFCR_CMP_NOMATCH
;
916 for (i
= 0; i
< rqfar
; i
++) {
917 ftp_rqfcr
[i
] = rqfcr
;
918 ftp_rqfpr
[i
] = rqfpr
;
919 gfar_write_filer(priv
, i
, rqfcr
, rqfpr
);
923 /* Set up the ethernet device structure, private data,
924 * and anything else we need before we start */
925 static int gfar_probe(struct of_device
*ofdev
,
926 const struct of_device_id
*match
)
929 struct net_device
*dev
= NULL
;
930 struct gfar_private
*priv
= NULL
;
931 struct gfar __iomem
*regs
= NULL
;
932 int err
= 0, i
, grp_idx
= 0;
934 u32 rstat
= 0, tstat
= 0, rqueue
= 0, tqueue
= 0;
938 err
= gfar_of_init(ofdev
, &dev
);
943 priv
= netdev_priv(dev
);
946 priv
->node
= ofdev
->node
;
947 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
949 spin_lock_init(&priv
->bflock
);
950 INIT_WORK(&priv
->reset_task
, gfar_reset_task
);
952 dev_set_drvdata(&ofdev
->dev
, priv
);
953 regs
= priv
->gfargrp
[0].regs
;
955 /* Stop the DMA engine now, in case it was running before */
956 /* (The firmware could have used it, and left it running). */
959 /* Reset MAC layer */
960 gfar_write(®s
->maccfg1
, MACCFG1_SOFT_RESET
);
962 /* We need to delay at least 3 TX clocks */
965 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
966 gfar_write(®s
->maccfg1
, tempval
);
968 /* Initialize MACCFG2. */
969 gfar_write(®s
->maccfg2
, MACCFG2_INIT_SETTINGS
);
971 /* Initialize ECNTRL */
972 gfar_write(®s
->ecntrl
, ECNTRL_INIT_SETTINGS
);
974 /* Set the dev->base_addr to the gfar reg region */
975 dev
->base_addr
= (unsigned long) regs
;
977 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
979 /* Fill in the dev structure */
980 dev
->watchdog_timeo
= TX_TIMEOUT
;
982 dev
->netdev_ops
= &gfar_netdev_ops
;
983 dev
->ethtool_ops
= &gfar_ethtool_ops
;
985 /* Register for napi ...We are registering NAPI for each grp */
986 for (i
= 0; i
< priv
->num_grps
; i
++)
987 netif_napi_add(dev
, &priv
->gfargrp
[i
].napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
989 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
990 priv
->rx_csum_enable
= 1;
991 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_HIGHDMA
;
993 priv
->rx_csum_enable
= 0;
997 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
)
998 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
1000 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
1001 priv
->extended_hash
= 1;
1002 priv
->hash_width
= 9;
1004 priv
->hash_regs
[0] = ®s
->igaddr0
;
1005 priv
->hash_regs
[1] = ®s
->igaddr1
;
1006 priv
->hash_regs
[2] = ®s
->igaddr2
;
1007 priv
->hash_regs
[3] = ®s
->igaddr3
;
1008 priv
->hash_regs
[4] = ®s
->igaddr4
;
1009 priv
->hash_regs
[5] = ®s
->igaddr5
;
1010 priv
->hash_regs
[6] = ®s
->igaddr6
;
1011 priv
->hash_regs
[7] = ®s
->igaddr7
;
1012 priv
->hash_regs
[8] = ®s
->gaddr0
;
1013 priv
->hash_regs
[9] = ®s
->gaddr1
;
1014 priv
->hash_regs
[10] = ®s
->gaddr2
;
1015 priv
->hash_regs
[11] = ®s
->gaddr3
;
1016 priv
->hash_regs
[12] = ®s
->gaddr4
;
1017 priv
->hash_regs
[13] = ®s
->gaddr5
;
1018 priv
->hash_regs
[14] = ®s
->gaddr6
;
1019 priv
->hash_regs
[15] = ®s
->gaddr7
;
1022 priv
->extended_hash
= 0;
1023 priv
->hash_width
= 8;
1025 priv
->hash_regs
[0] = ®s
->gaddr0
;
1026 priv
->hash_regs
[1] = ®s
->gaddr1
;
1027 priv
->hash_regs
[2] = ®s
->gaddr2
;
1028 priv
->hash_regs
[3] = ®s
->gaddr3
;
1029 priv
->hash_regs
[4] = ®s
->gaddr4
;
1030 priv
->hash_regs
[5] = ®s
->gaddr5
;
1031 priv
->hash_regs
[6] = ®s
->gaddr6
;
1032 priv
->hash_regs
[7] = ®s
->gaddr7
;
1035 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
1036 priv
->padding
= DEFAULT_PADDING
;
1040 if (dev
->features
& NETIF_F_IP_CSUM
||
1041 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
)
1042 dev
->hard_header_len
+= GMAC_FCB_LEN
;
1044 /* Program the isrg regs only if number of grps > 1 */
1045 if (priv
->num_grps
> 1) {
1046 baddr
= ®s
->isrg0
;
1047 for (i
= 0; i
< priv
->num_grps
; i
++) {
1048 isrg
|= (priv
->gfargrp
[i
].rx_bit_map
<< ISRG_SHIFT_RX
);
1049 isrg
|= (priv
->gfargrp
[i
].tx_bit_map
<< ISRG_SHIFT_TX
);
1050 gfar_write(baddr
, isrg
);
1056 /* Need to reverse the bit maps as bit_map's MSB is q0
1057 * but, for_each_set_bit parses from right to left, which
1058 * basically reverses the queue numbers */
1059 for (i
= 0; i
< priv
->num_grps
; i
++) {
1060 priv
->gfargrp
[i
].tx_bit_map
= reverse_bitmap(
1061 priv
->gfargrp
[i
].tx_bit_map
, MAX_TX_QS
);
1062 priv
->gfargrp
[i
].rx_bit_map
= reverse_bitmap(
1063 priv
->gfargrp
[i
].rx_bit_map
, MAX_RX_QS
);
1066 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1067 * also assign queues to groups */
1068 for (grp_idx
= 0; grp_idx
< priv
->num_grps
; grp_idx
++) {
1069 priv
->gfargrp
[grp_idx
].num_rx_queues
= 0x0;
1070 for_each_set_bit(i
, &priv
->gfargrp
[grp_idx
].rx_bit_map
,
1071 priv
->num_rx_queues
) {
1072 priv
->gfargrp
[grp_idx
].num_rx_queues
++;
1073 priv
->rx_queue
[i
]->grp
= &priv
->gfargrp
[grp_idx
];
1074 rstat
= rstat
| (RSTAT_CLEAR_RHALT
>> i
);
1075 rqueue
= rqueue
| ((RQUEUE_EN0
| RQUEUE_EX0
) >> i
);
1077 priv
->gfargrp
[grp_idx
].num_tx_queues
= 0x0;
1078 for_each_set_bit(i
, &priv
->gfargrp
[grp_idx
].tx_bit_map
,
1079 priv
->num_tx_queues
) {
1080 priv
->gfargrp
[grp_idx
].num_tx_queues
++;
1081 priv
->tx_queue
[i
]->grp
= &priv
->gfargrp
[grp_idx
];
1082 tstat
= tstat
| (TSTAT_CLEAR_THALT
>> i
);
1083 tqueue
= tqueue
| (TQUEUE_EN0
>> i
);
1085 priv
->gfargrp
[grp_idx
].rstat
= rstat
;
1086 priv
->gfargrp
[grp_idx
].tstat
= tstat
;
1090 gfar_write(®s
->rqueue
, rqueue
);
1091 gfar_write(®s
->tqueue
, tqueue
);
1093 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
1095 /* Initializing some of the rx/tx queue level parameters */
1096 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
1097 priv
->tx_queue
[i
]->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
1098 priv
->tx_queue
[i
]->num_txbdfree
= DEFAULT_TX_RING_SIZE
;
1099 priv
->tx_queue
[i
]->txcoalescing
= DEFAULT_TX_COALESCE
;
1100 priv
->tx_queue
[i
]->txic
= DEFAULT_TXIC
;
1103 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
1104 priv
->rx_queue
[i
]->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
1105 priv
->rx_queue
[i
]->rxcoalescing
= DEFAULT_RX_COALESCE
;
1106 priv
->rx_queue
[i
]->rxic
= DEFAULT_RXIC
;
1109 /* enable filer if using multiple RX queues*/
1110 if(priv
->num_rx_queues
> 1)
1111 priv
->rx_filer_enable
= 1;
1112 /* Enable most messages by default */
1113 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
1115 /* Carrier starts down, phylib will bring it up */
1116 netif_carrier_off(dev
);
1118 err
= register_netdev(dev
);
1121 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
1126 device_init_wakeup(&dev
->dev
,
1127 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1129 /* fill out IRQ number and name fields */
1130 len_devname
= strlen(dev
->name
);
1131 for (i
= 0; i
< priv
->num_grps
; i
++) {
1132 strncpy(&priv
->gfargrp
[i
].int_name_tx
[0], dev
->name
,
1134 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1135 strncpy(&priv
->gfargrp
[i
].int_name_tx
[len_devname
],
1136 "_g", sizeof("_g"));
1137 priv
->gfargrp
[i
].int_name_tx
[
1138 strlen(priv
->gfargrp
[i
].int_name_tx
)] = i
+48;
1139 strncpy(&priv
->gfargrp
[i
].int_name_tx
[strlen(
1140 priv
->gfargrp
[i
].int_name_tx
)],
1141 "_tx", sizeof("_tx") + 1);
1143 strncpy(&priv
->gfargrp
[i
].int_name_rx
[0], dev
->name
,
1145 strncpy(&priv
->gfargrp
[i
].int_name_rx
[len_devname
],
1146 "_g", sizeof("_g"));
1147 priv
->gfargrp
[i
].int_name_rx
[
1148 strlen(priv
->gfargrp
[i
].int_name_rx
)] = i
+48;
1149 strncpy(&priv
->gfargrp
[i
].int_name_rx
[strlen(
1150 priv
->gfargrp
[i
].int_name_rx
)],
1151 "_rx", sizeof("_rx") + 1);
1153 strncpy(&priv
->gfargrp
[i
].int_name_er
[0], dev
->name
,
1155 strncpy(&priv
->gfargrp
[i
].int_name_er
[len_devname
],
1156 "_g", sizeof("_g"));
1157 priv
->gfargrp
[i
].int_name_er
[strlen(
1158 priv
->gfargrp
[i
].int_name_er
)] = i
+48;
1159 strncpy(&priv
->gfargrp
[i
].int_name_er
[strlen(\
1160 priv
->gfargrp
[i
].int_name_er
)],
1161 "_er", sizeof("_er") + 1);
1163 priv
->gfargrp
[i
].int_name_tx
[len_devname
] = '\0';
1166 /* Initialize the filer table */
1167 gfar_init_filer_table(priv
);
1169 /* Create all the sysfs files */
1170 gfar_init_sysfs(dev
);
1172 /* Print out the device info */
1173 printk(KERN_INFO DEVICE_NAME
"%pM\n", dev
->name
, dev
->dev_addr
);
1175 /* Even more device info helps when determining which kernel */
1176 /* provided which set of benchmarks. */
1177 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
1178 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
1179 printk(KERN_INFO
"%s: RX BD ring size for Q[%d]: %d\n",
1180 dev
->name
, i
, priv
->rx_queue
[i
]->rx_ring_size
);
1181 for(i
= 0; i
< priv
->num_tx_queues
; i
++)
1182 printk(KERN_INFO
"%s: TX BD ring size for Q[%d]: %d\n",
1183 dev
->name
, i
, priv
->tx_queue
[i
]->tx_ring_size
);
1188 unmap_group_regs(priv
);
1189 free_tx_pointers(priv
);
1190 free_rx_pointers(priv
);
1192 of_node_put(priv
->phy_node
);
1194 of_node_put(priv
->tbi_node
);
1199 static int gfar_remove(struct of_device
*ofdev
)
1201 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
1204 of_node_put(priv
->phy_node
);
1206 of_node_put(priv
->tbi_node
);
1208 dev_set_drvdata(&ofdev
->dev
, NULL
);
1210 unregister_netdev(priv
->ndev
);
1211 unmap_group_regs(priv
);
1212 free_netdev(priv
->ndev
);
1219 static int gfar_suspend(struct device
*dev
)
1221 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1222 struct net_device
*ndev
= priv
->ndev
;
1223 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1224 unsigned long flags
;
1227 int magic_packet
= priv
->wol_en
&&
1228 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1230 netif_device_detach(ndev
);
1232 if (netif_running(ndev
)) {
1234 local_irq_save(flags
);
1238 gfar_halt_nodisable(ndev
);
1240 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1241 tempval
= gfar_read(®s
->maccfg1
);
1243 tempval
&= ~MACCFG1_TX_EN
;
1246 tempval
&= ~MACCFG1_RX_EN
;
1248 gfar_write(®s
->maccfg1
, tempval
);
1252 local_irq_restore(flags
);
1257 /* Enable interrupt on Magic Packet */
1258 gfar_write(®s
->imask
, IMASK_MAG
);
1260 /* Enable Magic Packet mode */
1261 tempval
= gfar_read(®s
->maccfg2
);
1262 tempval
|= MACCFG2_MPEN
;
1263 gfar_write(®s
->maccfg2
, tempval
);
1265 phy_stop(priv
->phydev
);
1272 static int gfar_resume(struct device
*dev
)
1274 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1275 struct net_device
*ndev
= priv
->ndev
;
1276 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1277 unsigned long flags
;
1279 int magic_packet
= priv
->wol_en
&&
1280 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1282 if (!netif_running(ndev
)) {
1283 netif_device_attach(ndev
);
1287 if (!magic_packet
&& priv
->phydev
)
1288 phy_start(priv
->phydev
);
1290 /* Disable Magic Packet mode, in case something
1293 local_irq_save(flags
);
1297 tempval
= gfar_read(®s
->maccfg2
);
1298 tempval
&= ~MACCFG2_MPEN
;
1299 gfar_write(®s
->maccfg2
, tempval
);
1305 local_irq_restore(flags
);
1307 netif_device_attach(ndev
);
1314 static int gfar_restore(struct device
*dev
)
1316 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1317 struct net_device
*ndev
= priv
->ndev
;
1319 if (!netif_running(ndev
))
1322 gfar_init_bds(ndev
);
1323 init_registers(ndev
);
1324 gfar_set_mac_address(ndev
);
1325 gfar_init_mac(ndev
);
1330 priv
->oldduplex
= -1;
1333 phy_start(priv
->phydev
);
1335 netif_device_attach(ndev
);
1341 static struct dev_pm_ops gfar_pm_ops
= {
1342 .suspend
= gfar_suspend
,
1343 .resume
= gfar_resume
,
1344 .freeze
= gfar_suspend
,
1345 .thaw
= gfar_resume
,
1346 .restore
= gfar_restore
,
1349 #define GFAR_PM_OPS (&gfar_pm_ops)
1351 static int gfar_legacy_suspend(struct of_device
*ofdev
, pm_message_t state
)
1353 return gfar_suspend(&ofdev
->dev
);
1356 static int gfar_legacy_resume(struct of_device
*ofdev
)
1358 return gfar_resume(&ofdev
->dev
);
1363 #define GFAR_PM_OPS NULL
1364 #define gfar_legacy_suspend NULL
1365 #define gfar_legacy_resume NULL
1369 /* Reads the controller's registers to determine what interface
1370 * connects it to the PHY.
1372 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
1374 struct gfar_private
*priv
= netdev_priv(dev
);
1375 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1378 ecntrl
= gfar_read(®s
->ecntrl
);
1380 if (ecntrl
& ECNTRL_SGMII_MODE
)
1381 return PHY_INTERFACE_MODE_SGMII
;
1383 if (ecntrl
& ECNTRL_TBI_MODE
) {
1384 if (ecntrl
& ECNTRL_REDUCED_MODE
)
1385 return PHY_INTERFACE_MODE_RTBI
;
1387 return PHY_INTERFACE_MODE_TBI
;
1390 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
1391 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
1392 return PHY_INTERFACE_MODE_RMII
;
1394 phy_interface_t interface
= priv
->interface
;
1397 * This isn't autodetected right now, so it must
1398 * be set by the device tree or platform code.
1400 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
1401 return PHY_INTERFACE_MODE_RGMII_ID
;
1403 return PHY_INTERFACE_MODE_RGMII
;
1407 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
1408 return PHY_INTERFACE_MODE_GMII
;
1410 return PHY_INTERFACE_MODE_MII
;
1414 /* Initializes driver's PHY state, and attaches to the PHY.
1415 * Returns 0 on success.
1417 static int init_phy(struct net_device
*dev
)
1419 struct gfar_private
*priv
= netdev_priv(dev
);
1420 uint gigabit_support
=
1421 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
1422 SUPPORTED_1000baseT_Full
: 0;
1423 phy_interface_t interface
;
1427 priv
->oldduplex
= -1;
1429 interface
= gfar_get_interface(dev
);
1431 priv
->phydev
= of_phy_connect(dev
, priv
->phy_node
, &adjust_link
, 0,
1434 priv
->phydev
= of_phy_connect_fixed_link(dev
, &adjust_link
,
1436 if (!priv
->phydev
) {
1437 dev_err(&dev
->dev
, "could not attach to PHY\n");
1441 if (interface
== PHY_INTERFACE_MODE_SGMII
)
1442 gfar_configure_serdes(dev
);
1444 /* Remove any features not supported by the controller */
1445 priv
->phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
1446 priv
->phydev
->advertising
= priv
->phydev
->supported
;
1452 * Initialize TBI PHY interface for communicating with the
1453 * SERDES lynx PHY on the chip. We communicate with this PHY
1454 * through the MDIO bus on each controller, treating it as a
1455 * "normal" PHY at the address found in the TBIPA register. We assume
1456 * that the TBIPA register is valid. Either the MDIO bus code will set
1457 * it to a value that doesn't conflict with other PHYs on the bus, or the
1458 * value doesn't matter, as there are no other PHYs on the bus.
1460 static void gfar_configure_serdes(struct net_device
*dev
)
1462 struct gfar_private
*priv
= netdev_priv(dev
);
1463 struct phy_device
*tbiphy
;
1465 if (!priv
->tbi_node
) {
1466 dev_warn(&dev
->dev
, "error: SGMII mode requires that the "
1467 "device tree specify a tbi-handle\n");
1471 tbiphy
= of_phy_find_device(priv
->tbi_node
);
1473 dev_err(&dev
->dev
, "error: Could not get TBI device\n");
1478 * If the link is already up, we must already be ok, and don't need to
1479 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1480 * everything for us? Resetting it takes the link down and requires
1481 * several seconds for it to come back.
1483 if (phy_read(tbiphy
, MII_BMSR
) & BMSR_LSTATUS
)
1486 /* Single clk mode, mii mode off(for serdes communication) */
1487 phy_write(tbiphy
, MII_TBICON
, TBICON_CLK_SELECT
);
1489 phy_write(tbiphy
, MII_ADVERTISE
,
1490 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
1491 ADVERTISE_1000XPSE_ASYM
);
1493 phy_write(tbiphy
, MII_BMCR
, BMCR_ANENABLE
|
1494 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
1497 static void init_registers(struct net_device
*dev
)
1499 struct gfar_private
*priv
= netdev_priv(dev
);
1500 struct gfar __iomem
*regs
= NULL
;
1503 for (i
= 0; i
< priv
->num_grps
; i
++) {
1504 regs
= priv
->gfargrp
[i
].regs
;
1506 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
1508 /* Initialize IMASK */
1509 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1512 regs
= priv
->gfargrp
[0].regs
;
1513 /* Init hash registers to zero */
1514 gfar_write(®s
->igaddr0
, 0);
1515 gfar_write(®s
->igaddr1
, 0);
1516 gfar_write(®s
->igaddr2
, 0);
1517 gfar_write(®s
->igaddr3
, 0);
1518 gfar_write(®s
->igaddr4
, 0);
1519 gfar_write(®s
->igaddr5
, 0);
1520 gfar_write(®s
->igaddr6
, 0);
1521 gfar_write(®s
->igaddr7
, 0);
1523 gfar_write(®s
->gaddr0
, 0);
1524 gfar_write(®s
->gaddr1
, 0);
1525 gfar_write(®s
->gaddr2
, 0);
1526 gfar_write(®s
->gaddr3
, 0);
1527 gfar_write(®s
->gaddr4
, 0);
1528 gfar_write(®s
->gaddr5
, 0);
1529 gfar_write(®s
->gaddr6
, 0);
1530 gfar_write(®s
->gaddr7
, 0);
1532 /* Zero out the rmon mib registers if it has them */
1533 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
1534 memset_io(&(regs
->rmon
), 0, sizeof (struct rmon_mib
));
1536 /* Mask off the CAM interrupts */
1537 gfar_write(®s
->rmon
.cam1
, 0xffffffff);
1538 gfar_write(®s
->rmon
.cam2
, 0xffffffff);
1541 /* Initialize the max receive buffer length */
1542 gfar_write(®s
->mrblr
, priv
->rx_buffer_size
);
1544 /* Initialize the Minimum Frame Length Register */
1545 gfar_write(®s
->minflr
, MINFLR_INIT_SETTINGS
);
1549 /* Halt the receive and transmit queues */
1550 static void gfar_halt_nodisable(struct net_device
*dev
)
1552 struct gfar_private
*priv
= netdev_priv(dev
);
1553 struct gfar __iomem
*regs
= NULL
;
1557 for (i
= 0; i
< priv
->num_grps
; i
++) {
1558 regs
= priv
->gfargrp
[i
].regs
;
1559 /* Mask all interrupts */
1560 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1562 /* Clear all interrupts */
1563 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
1566 regs
= priv
->gfargrp
[0].regs
;
1567 /* Stop the DMA, and wait for it to stop */
1568 tempval
= gfar_read(®s
->dmactrl
);
1569 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
1570 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
1571 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
1572 gfar_write(®s
->dmactrl
, tempval
);
1574 while (!(gfar_read(®s
->ievent
) &
1575 (IEVENT_GRSC
| IEVENT_GTSC
)))
1580 /* Halt the receive and transmit queues */
1581 void gfar_halt(struct net_device
*dev
)
1583 struct gfar_private
*priv
= netdev_priv(dev
);
1584 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1587 gfar_halt_nodisable(dev
);
1589 /* Disable Rx and Tx */
1590 tempval
= gfar_read(®s
->maccfg1
);
1591 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
1592 gfar_write(®s
->maccfg1
, tempval
);
1595 static void free_grp_irqs(struct gfar_priv_grp
*grp
)
1597 free_irq(grp
->interruptError
, grp
);
1598 free_irq(grp
->interruptTransmit
, grp
);
1599 free_irq(grp
->interruptReceive
, grp
);
1602 void stop_gfar(struct net_device
*dev
)
1604 struct gfar_private
*priv
= netdev_priv(dev
);
1605 unsigned long flags
;
1608 phy_stop(priv
->phydev
);
1612 local_irq_save(flags
);
1620 local_irq_restore(flags
);
1623 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1624 for (i
= 0; i
< priv
->num_grps
; i
++)
1625 free_grp_irqs(&priv
->gfargrp
[i
]);
1627 for (i
= 0; i
< priv
->num_grps
; i
++)
1628 free_irq(priv
->gfargrp
[i
].interruptTransmit
,
1632 free_skb_resources(priv
);
1635 static void free_skb_tx_queue(struct gfar_priv_tx_q
*tx_queue
)
1637 struct txbd8
*txbdp
;
1638 struct gfar_private
*priv
= netdev_priv(tx_queue
->dev
);
1641 txbdp
= tx_queue
->tx_bd_base
;
1643 for (i
= 0; i
< tx_queue
->tx_ring_size
; i
++) {
1644 if (!tx_queue
->tx_skbuff
[i
])
1647 dma_unmap_single(&priv
->ofdev
->dev
, txbdp
->bufPtr
,
1648 txbdp
->length
, DMA_TO_DEVICE
);
1650 for (j
= 0; j
< skb_shinfo(tx_queue
->tx_skbuff
[i
])->nr_frags
;
1653 dma_unmap_page(&priv
->ofdev
->dev
, txbdp
->bufPtr
,
1654 txbdp
->length
, DMA_TO_DEVICE
);
1657 dev_kfree_skb_any(tx_queue
->tx_skbuff
[i
]);
1658 tx_queue
->tx_skbuff
[i
] = NULL
;
1660 kfree(tx_queue
->tx_skbuff
);
1663 static void free_skb_rx_queue(struct gfar_priv_rx_q
*rx_queue
)
1665 struct rxbd8
*rxbdp
;
1666 struct gfar_private
*priv
= netdev_priv(rx_queue
->dev
);
1669 rxbdp
= rx_queue
->rx_bd_base
;
1671 for (i
= 0; i
< rx_queue
->rx_ring_size
; i
++) {
1672 if (rx_queue
->rx_skbuff
[i
]) {
1673 dma_unmap_single(&priv
->ofdev
->dev
,
1674 rxbdp
->bufPtr
, priv
->rx_buffer_size
,
1676 dev_kfree_skb_any(rx_queue
->rx_skbuff
[i
]);
1677 rx_queue
->rx_skbuff
[i
] = NULL
;
1683 kfree(rx_queue
->rx_skbuff
);
1686 /* If there are any tx skbs or rx skbs still around, free them.
1687 * Then free tx_skbuff and rx_skbuff */
1688 static void free_skb_resources(struct gfar_private
*priv
)
1690 struct gfar_priv_tx_q
*tx_queue
= NULL
;
1691 struct gfar_priv_rx_q
*rx_queue
= NULL
;
1694 /* Go through all the buffer descriptors and free their data buffers */
1695 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
1696 tx_queue
= priv
->tx_queue
[i
];
1697 if(tx_queue
->tx_skbuff
)
1698 free_skb_tx_queue(tx_queue
);
1701 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
1702 rx_queue
= priv
->rx_queue
[i
];
1703 if(rx_queue
->rx_skbuff
)
1704 free_skb_rx_queue(rx_queue
);
1707 dma_free_coherent(&priv
->ofdev
->dev
,
1708 sizeof(struct txbd8
) * priv
->total_tx_ring_size
+
1709 sizeof(struct rxbd8
) * priv
->total_rx_ring_size
,
1710 priv
->tx_queue
[0]->tx_bd_base
,
1711 priv
->tx_queue
[0]->tx_bd_dma_base
);
1714 void gfar_start(struct net_device
*dev
)
1716 struct gfar_private
*priv
= netdev_priv(dev
);
1717 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1721 /* Enable Rx and Tx in MACCFG1 */
1722 tempval
= gfar_read(®s
->maccfg1
);
1723 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
1724 gfar_write(®s
->maccfg1
, tempval
);
1726 /* Initialize DMACTRL to have WWR and WOP */
1727 tempval
= gfar_read(®s
->dmactrl
);
1728 tempval
|= DMACTRL_INIT_SETTINGS
;
1729 gfar_write(®s
->dmactrl
, tempval
);
1731 /* Make sure we aren't stopped */
1732 tempval
= gfar_read(®s
->dmactrl
);
1733 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
1734 gfar_write(®s
->dmactrl
, tempval
);
1736 for (i
= 0; i
< priv
->num_grps
; i
++) {
1737 regs
= priv
->gfargrp
[i
].regs
;
1738 /* Clear THLT/RHLT, so that the DMA starts polling now */
1739 gfar_write(®s
->tstat
, priv
->gfargrp
[i
].tstat
);
1740 gfar_write(®s
->rstat
, priv
->gfargrp
[i
].rstat
);
1741 /* Unmask the interrupts we look for */
1742 gfar_write(®s
->imask
, IMASK_DEFAULT
);
1745 dev
->trans_start
= jiffies
;
1748 void gfar_configure_coalescing(struct gfar_private
*priv
,
1749 unsigned long tx_mask
, unsigned long rx_mask
)
1751 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1755 /* Backward compatible case ---- even if we enable
1756 * multiple queues, there's only single reg to program
1758 gfar_write(®s
->txic
, 0);
1759 if(likely(priv
->tx_queue
[0]->txcoalescing
))
1760 gfar_write(®s
->txic
, priv
->tx_queue
[0]->txic
);
1762 gfar_write(®s
->rxic
, 0);
1763 if(unlikely(priv
->rx_queue
[0]->rxcoalescing
))
1764 gfar_write(®s
->rxic
, priv
->rx_queue
[0]->rxic
);
1766 if (priv
->mode
== MQ_MG_MODE
) {
1767 baddr
= ®s
->txic0
;
1768 for_each_set_bit(i
, &tx_mask
, priv
->num_tx_queues
) {
1769 if (likely(priv
->tx_queue
[i
]->txcoalescing
)) {
1770 gfar_write(baddr
+ i
, 0);
1771 gfar_write(baddr
+ i
, priv
->tx_queue
[i
]->txic
);
1775 baddr
= ®s
->rxic0
;
1776 for_each_set_bit(i
, &rx_mask
, priv
->num_rx_queues
) {
1777 if (likely(priv
->rx_queue
[i
]->rxcoalescing
)) {
1778 gfar_write(baddr
+ i
, 0);
1779 gfar_write(baddr
+ i
, priv
->rx_queue
[i
]->rxic
);
1785 static int register_grp_irqs(struct gfar_priv_grp
*grp
)
1787 struct gfar_private
*priv
= grp
->priv
;
1788 struct net_device
*dev
= priv
->ndev
;
1791 /* If the device has multiple interrupts, register for
1792 * them. Otherwise, only register for the one */
1793 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1794 /* Install our interrupt handlers for Error,
1795 * Transmit, and Receive */
1796 if ((err
= request_irq(grp
->interruptError
, gfar_error
, 0,
1797 grp
->int_name_er
,grp
)) < 0) {
1798 if (netif_msg_intr(priv
))
1799 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1800 dev
->name
, grp
->interruptError
);
1805 if ((err
= request_irq(grp
->interruptTransmit
, gfar_transmit
,
1806 0, grp
->int_name_tx
, grp
)) < 0) {
1807 if (netif_msg_intr(priv
))
1808 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1809 dev
->name
, grp
->interruptTransmit
);
1813 if ((err
= request_irq(grp
->interruptReceive
, gfar_receive
, 0,
1814 grp
->int_name_rx
, grp
)) < 0) {
1815 if (netif_msg_intr(priv
))
1816 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1817 dev
->name
, grp
->interruptReceive
);
1821 if ((err
= request_irq(grp
->interruptTransmit
, gfar_interrupt
, 0,
1822 grp
->int_name_tx
, grp
)) < 0) {
1823 if (netif_msg_intr(priv
))
1824 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1825 dev
->name
, grp
->interruptTransmit
);
1833 free_irq(grp
->interruptTransmit
, grp
);
1835 free_irq(grp
->interruptError
, grp
);
1841 /* Bring the controller up and running */
1842 int startup_gfar(struct net_device
*ndev
)
1844 struct gfar_private
*priv
= netdev_priv(ndev
);
1845 struct gfar __iomem
*regs
= NULL
;
1848 for (i
= 0; i
< priv
->num_grps
; i
++) {
1849 regs
= priv
->gfargrp
[i
].regs
;
1850 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1853 regs
= priv
->gfargrp
[0].regs
;
1854 err
= gfar_alloc_skb_resources(ndev
);
1858 gfar_init_mac(ndev
);
1860 for (i
= 0; i
< priv
->num_grps
; i
++) {
1861 err
= register_grp_irqs(&priv
->gfargrp
[i
]);
1863 for (j
= 0; j
< i
; j
++)
1864 free_grp_irqs(&priv
->gfargrp
[j
]);
1869 /* Start the controller */
1872 phy_start(priv
->phydev
);
1874 gfar_configure_coalescing(priv
, 0xFF, 0xFF);
1879 free_skb_resources(priv
);
1883 /* Called when something needs to use the ethernet device */
1884 /* Returns 0 for success. */
1885 static int gfar_enet_open(struct net_device
*dev
)
1887 struct gfar_private
*priv
= netdev_priv(dev
);
1892 skb_queue_head_init(&priv
->rx_recycle
);
1894 /* Initialize a bunch of registers */
1895 init_registers(dev
);
1897 gfar_set_mac_address(dev
);
1899 err
= init_phy(dev
);
1906 err
= startup_gfar(dev
);
1912 netif_tx_start_all_queues(dev
);
1914 device_set_wakeup_enable(&dev
->dev
, priv
->wol_en
);
1919 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
)
1921 struct txfcb
*fcb
= (struct txfcb
*)skb_push(skb
, GMAC_FCB_LEN
);
1923 memset(fcb
, 0, GMAC_FCB_LEN
);
1928 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
1932 /* If we're here, it's a IP packet with a TCP or UDP
1933 * payload. We set it to checksum, using a pseudo-header
1936 flags
= TXFCB_DEFAULT
;
1938 /* Tell the controller what the protocol is */
1939 /* And provide the already calculated phcs */
1940 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
1942 fcb
->phcs
= udp_hdr(skb
)->check
;
1944 fcb
->phcs
= tcp_hdr(skb
)->check
;
1946 /* l3os is the distance between the start of the
1947 * frame (skb->data) and the start of the IP hdr.
1948 * l4os is the distance between the start of the
1949 * l3 hdr and the l4 hdr */
1950 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
1951 fcb
->l4os
= skb_network_header_len(skb
);
1956 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
1958 fcb
->flags
|= TXFCB_VLN
;
1959 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1962 static inline struct txbd8
*skip_txbd(struct txbd8
*bdp
, int stride
,
1963 struct txbd8
*base
, int ring_size
)
1965 struct txbd8
*new_bd
= bdp
+ stride
;
1967 return (new_bd
>= (base
+ ring_size
)) ? (new_bd
- ring_size
) : new_bd
;
1970 static inline struct txbd8
*next_txbd(struct txbd8
*bdp
, struct txbd8
*base
,
1973 return skip_txbd(bdp
, 1, base
, ring_size
);
1976 /* This is called by the kernel when a frame is ready for transmission. */
1977 /* It is pointed to by the dev->hard_start_xmit function pointer */
1978 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1980 struct gfar_private
*priv
= netdev_priv(dev
);
1981 struct gfar_priv_tx_q
*tx_queue
= NULL
;
1982 struct netdev_queue
*txq
;
1983 struct gfar __iomem
*regs
= NULL
;
1984 struct txfcb
*fcb
= NULL
;
1985 struct txbd8
*txbdp
, *txbdp_start
, *base
, *txbdp_tstamp
= NULL
;
1987 int i
, rq
= 0, do_tstamp
= 0;
1989 unsigned long flags
;
1990 unsigned int nr_frags
, nr_txbds
, length
;
1991 union skb_shared_tx
*shtx
;
1993 rq
= skb
->queue_mapping
;
1994 tx_queue
= priv
->tx_queue
[rq
];
1995 txq
= netdev_get_tx_queue(dev
, rq
);
1996 base
= tx_queue
->tx_bd_base
;
1997 regs
= tx_queue
->grp
->regs
;
2000 /* check if time stamp should be generated */
2001 if (unlikely(shtx
->hardware
&& priv
->hwts_tx_en
))
2004 /* make space for additional header when fcb is needed */
2005 if (((skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
2006 (priv
->vlgrp
&& vlan_tx_tag_present(skb
)) ||
2007 unlikely(do_tstamp
)) &&
2008 (skb_headroom(skb
) < GMAC_FCB_LEN
)) {
2009 struct sk_buff
*skb_new
;
2011 skb_new
= skb_realloc_headroom(skb
, GMAC_FCB_LEN
);
2013 dev
->stats
.tx_errors
++;
2015 return NETDEV_TX_OK
;
2021 /* total number of fragments in the SKB */
2022 nr_frags
= skb_shinfo(skb
)->nr_frags
;
2024 /* calculate the required number of TxBDs for this skb */
2025 if (unlikely(do_tstamp
))
2026 nr_txbds
= nr_frags
+ 2;
2028 nr_txbds
= nr_frags
+ 1;
2030 /* check if there is space to queue this packet */
2031 if (nr_txbds
> tx_queue
->num_txbdfree
) {
2032 /* no space, stop the queue */
2033 netif_tx_stop_queue(txq
);
2034 dev
->stats
.tx_fifo_errors
++;
2035 return NETDEV_TX_BUSY
;
2038 /* Update transmit stats */
2039 txq
->tx_bytes
+= skb
->len
;
2042 txbdp
= txbdp_start
= tx_queue
->cur_tx
;
2043 lstatus
= txbdp
->lstatus
;
2045 /* Time stamp insertion requires one additional TxBD */
2046 if (unlikely(do_tstamp
))
2047 txbdp_tstamp
= txbdp
= next_txbd(txbdp
, base
,
2048 tx_queue
->tx_ring_size
);
2050 if (nr_frags
== 0) {
2051 if (unlikely(do_tstamp
))
2052 txbdp_tstamp
->lstatus
|= BD_LFLAG(TXBD_LAST
|
2055 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
2057 /* Place the fragment addresses and lengths into the TxBDs */
2058 for (i
= 0; i
< nr_frags
; i
++) {
2059 /* Point at the next BD, wrapping as needed */
2060 txbdp
= next_txbd(txbdp
, base
, tx_queue
->tx_ring_size
);
2062 length
= skb_shinfo(skb
)->frags
[i
].size
;
2064 lstatus
= txbdp
->lstatus
| length
|
2065 BD_LFLAG(TXBD_READY
);
2067 /* Handle the last BD specially */
2068 if (i
== nr_frags
- 1)
2069 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
2071 bufaddr
= dma_map_page(&priv
->ofdev
->dev
,
2072 skb_shinfo(skb
)->frags
[i
].page
,
2073 skb_shinfo(skb
)->frags
[i
].page_offset
,
2077 /* set the TxBD length and buffer pointer */
2078 txbdp
->bufPtr
= bufaddr
;
2079 txbdp
->lstatus
= lstatus
;
2082 lstatus
= txbdp_start
->lstatus
;
2085 /* Set up checksumming */
2086 if (CHECKSUM_PARTIAL
== skb
->ip_summed
) {
2087 fcb
= gfar_add_fcb(skb
);
2088 lstatus
|= BD_LFLAG(TXBD_TOE
);
2089 gfar_tx_checksum(skb
, fcb
);
2092 if (priv
->vlgrp
&& vlan_tx_tag_present(skb
)) {
2093 if (unlikely(NULL
== fcb
)) {
2094 fcb
= gfar_add_fcb(skb
);
2095 lstatus
|= BD_LFLAG(TXBD_TOE
);
2098 gfar_tx_vlan(skb
, fcb
);
2101 /* Setup tx hardware time stamping if requested */
2102 if (unlikely(do_tstamp
)) {
2103 shtx
->in_progress
= 1;
2105 fcb
= gfar_add_fcb(skb
);
2107 lstatus
|= BD_LFLAG(TXBD_TOE
);
2110 txbdp_start
->bufPtr
= dma_map_single(&priv
->ofdev
->dev
, skb
->data
,
2111 skb_headlen(skb
), DMA_TO_DEVICE
);
2114 * If time stamping is requested one additional TxBD must be set up. The
2115 * first TxBD points to the FCB and must have a data length of
2116 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2117 * the full frame length.
2119 if (unlikely(do_tstamp
)) {
2120 txbdp_tstamp
->bufPtr
= txbdp_start
->bufPtr
+ GMAC_FCB_LEN
;
2121 txbdp_tstamp
->lstatus
|= BD_LFLAG(TXBD_READY
) |
2122 (skb_headlen(skb
) - GMAC_FCB_LEN
);
2123 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | GMAC_FCB_LEN
;
2125 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | skb_headlen(skb
);
2129 * We can work in parallel with gfar_clean_tx_ring(), except
2130 * when modifying num_txbdfree. Note that we didn't grab the lock
2131 * when we were reading the num_txbdfree and checking for available
2132 * space, that's because outside of this function it can only grow,
2133 * and once we've got needed space, it cannot suddenly disappear.
2135 * The lock also protects us from gfar_error(), which can modify
2136 * regs->tstat and thus retrigger the transfers, which is why we
2137 * also must grab the lock before setting ready bit for the first
2138 * to be transmitted BD.
2140 spin_lock_irqsave(&tx_queue
->txlock
, flags
);
2143 * The powerpc-specific eieio() is used, as wmb() has too strong
2144 * semantics (it requires synchronization between cacheable and
2145 * uncacheable mappings, which eieio doesn't provide and which we
2146 * don't need), thus requiring a more expensive sync instruction. At
2147 * some point, the set of architecture-independent barrier functions
2148 * should be expanded to include weaker barriers.
2152 txbdp_start
->lstatus
= lstatus
;
2154 eieio(); /* force lstatus write before tx_skbuff */
2156 tx_queue
->tx_skbuff
[tx_queue
->skb_curtx
] = skb
;
2158 /* Update the current skb pointer to the next entry we will use
2159 * (wrapping if necessary) */
2160 tx_queue
->skb_curtx
= (tx_queue
->skb_curtx
+ 1) &
2161 TX_RING_MOD_MASK(tx_queue
->tx_ring_size
);
2163 tx_queue
->cur_tx
= next_txbd(txbdp
, base
, tx_queue
->tx_ring_size
);
2165 /* reduce TxBD free count */
2166 tx_queue
->num_txbdfree
-= (nr_txbds
);
2168 dev
->trans_start
= jiffies
;
2170 /* If the next BD still needs to be cleaned up, then the bds
2171 are full. We need to tell the kernel to stop sending us stuff. */
2172 if (!tx_queue
->num_txbdfree
) {
2173 netif_tx_stop_queue(txq
);
2175 dev
->stats
.tx_fifo_errors
++;
2178 /* Tell the DMA to go go go */
2179 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
>> tx_queue
->qindex
);
2182 spin_unlock_irqrestore(&tx_queue
->txlock
, flags
);
2184 return NETDEV_TX_OK
;
2187 /* Stops the kernel queue, and halts the controller */
2188 static int gfar_close(struct net_device
*dev
)
2190 struct gfar_private
*priv
= netdev_priv(dev
);
2194 skb_queue_purge(&priv
->rx_recycle
);
2195 cancel_work_sync(&priv
->reset_task
);
2198 /* Disconnect from the PHY */
2199 phy_disconnect(priv
->phydev
);
2200 priv
->phydev
= NULL
;
2202 netif_tx_stop_all_queues(dev
);
2207 /* Changes the mac address if the controller is not running. */
2208 static int gfar_set_mac_address(struct net_device
*dev
)
2210 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
2216 /* Enables and disables VLAN insertion/extraction */
2217 static void gfar_vlan_rx_register(struct net_device
*dev
,
2218 struct vlan_group
*grp
)
2220 struct gfar_private
*priv
= netdev_priv(dev
);
2221 struct gfar __iomem
*regs
= NULL
;
2222 unsigned long flags
;
2225 regs
= priv
->gfargrp
[0].regs
;
2226 local_irq_save(flags
);
2232 /* Enable VLAN tag insertion */
2233 tempval
= gfar_read(®s
->tctrl
);
2234 tempval
|= TCTRL_VLINS
;
2236 gfar_write(®s
->tctrl
, tempval
);
2238 /* Enable VLAN tag extraction */
2239 tempval
= gfar_read(®s
->rctrl
);
2240 tempval
|= (RCTRL_VLEX
| RCTRL_PRSDEP_INIT
);
2241 gfar_write(®s
->rctrl
, tempval
);
2243 /* Disable VLAN tag insertion */
2244 tempval
= gfar_read(®s
->tctrl
);
2245 tempval
&= ~TCTRL_VLINS
;
2246 gfar_write(®s
->tctrl
, tempval
);
2248 /* Disable VLAN tag extraction */
2249 tempval
= gfar_read(®s
->rctrl
);
2250 tempval
&= ~RCTRL_VLEX
;
2251 /* If parse is no longer required, then disable parser */
2252 if (tempval
& RCTRL_REQ_PARSER
)
2253 tempval
|= RCTRL_PRSDEP_INIT
;
2255 tempval
&= ~RCTRL_PRSDEP_INIT
;
2256 gfar_write(®s
->rctrl
, tempval
);
2259 gfar_change_mtu(dev
, dev
->mtu
);
2262 local_irq_restore(flags
);
2265 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
2267 int tempsize
, tempval
;
2268 struct gfar_private
*priv
= netdev_priv(dev
);
2269 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
2270 int oldsize
= priv
->rx_buffer_size
;
2271 int frame_size
= new_mtu
+ ETH_HLEN
;
2274 frame_size
+= VLAN_HLEN
;
2276 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
2277 if (netif_msg_drv(priv
))
2278 printk(KERN_ERR
"%s: Invalid MTU setting\n",
2283 if (gfar_uses_fcb(priv
))
2284 frame_size
+= GMAC_FCB_LEN
;
2286 frame_size
+= priv
->padding
;
2289 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
2290 INCREMENTAL_BUFFER_SIZE
;
2292 /* Only stop and start the controller if it isn't already
2293 * stopped, and we changed something */
2294 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
2297 priv
->rx_buffer_size
= tempsize
;
2301 gfar_write(®s
->mrblr
, priv
->rx_buffer_size
);
2302 gfar_write(®s
->maxfrm
, priv
->rx_buffer_size
);
2304 /* If the mtu is larger than the max size for standard
2305 * ethernet frames (ie, a jumbo frame), then set maccfg2
2306 * to allow huge frames, and to check the length */
2307 tempval
= gfar_read(®s
->maccfg2
);
2309 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
2310 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
2312 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
2314 gfar_write(®s
->maccfg2
, tempval
);
2316 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
2322 /* gfar_reset_task gets scheduled when a packet has not been
2323 * transmitted after a set amount of time.
2324 * For now, assume that clearing out all the structures, and
2325 * starting over will fix the problem.
2327 static void gfar_reset_task(struct work_struct
*work
)
2329 struct gfar_private
*priv
= container_of(work
, struct gfar_private
,
2331 struct net_device
*dev
= priv
->ndev
;
2333 if (dev
->flags
& IFF_UP
) {
2334 netif_tx_stop_all_queues(dev
);
2337 netif_tx_start_all_queues(dev
);
2340 netif_tx_schedule_all(dev
);
2343 static void gfar_timeout(struct net_device
*dev
)
2345 struct gfar_private
*priv
= netdev_priv(dev
);
2347 dev
->stats
.tx_errors
++;
2348 schedule_work(&priv
->reset_task
);
2351 /* Interrupt Handler for Transmit complete */
2352 static int gfar_clean_tx_ring(struct gfar_priv_tx_q
*tx_queue
)
2354 struct net_device
*dev
= tx_queue
->dev
;
2355 struct gfar_private
*priv
= netdev_priv(dev
);
2356 struct gfar_priv_rx_q
*rx_queue
= NULL
;
2357 struct txbd8
*bdp
, *next
= NULL
;
2358 struct txbd8
*lbdp
= NULL
;
2359 struct txbd8
*base
= tx_queue
->tx_bd_base
;
2360 struct sk_buff
*skb
;
2362 int tx_ring_size
= tx_queue
->tx_ring_size
;
2363 int frags
= 0, nr_txbds
= 0;
2368 union skb_shared_tx
*shtx
;
2370 rx_queue
= priv
->rx_queue
[tx_queue
->qindex
];
2371 bdp
= tx_queue
->dirty_tx
;
2372 skb_dirtytx
= tx_queue
->skb_dirtytx
;
2374 while ((skb
= tx_queue
->tx_skbuff
[skb_dirtytx
])) {
2375 unsigned long flags
;
2377 frags
= skb_shinfo(skb
)->nr_frags
;
2380 * When time stamping, one additional TxBD must be freed.
2381 * Also, we need to dma_unmap_single() the TxPAL.
2384 if (unlikely(shtx
->in_progress
))
2385 nr_txbds
= frags
+ 2;
2387 nr_txbds
= frags
+ 1;
2389 lbdp
= skip_txbd(bdp
, nr_txbds
- 1, base
, tx_ring_size
);
2391 lstatus
= lbdp
->lstatus
;
2393 /* Only clean completed frames */
2394 if ((lstatus
& BD_LFLAG(TXBD_READY
)) &&
2395 (lstatus
& BD_LENGTH_MASK
))
2398 if (unlikely(shtx
->in_progress
)) {
2399 next
= next_txbd(bdp
, base
, tx_ring_size
);
2400 buflen
= next
->length
+ GMAC_FCB_LEN
;
2402 buflen
= bdp
->length
;
2404 dma_unmap_single(&priv
->ofdev
->dev
, bdp
->bufPtr
,
2405 buflen
, DMA_TO_DEVICE
);
2407 if (unlikely(shtx
->in_progress
)) {
2408 struct skb_shared_hwtstamps shhwtstamps
;
2409 u64
*ns
= (u64
*) (((u32
)skb
->data
+ 0x10) & ~0x7);
2410 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
2411 shhwtstamps
.hwtstamp
= ns_to_ktime(*ns
);
2412 skb_tstamp_tx(skb
, &shhwtstamps
);
2413 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2417 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2418 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
2420 for (i
= 0; i
< frags
; i
++) {
2421 dma_unmap_page(&priv
->ofdev
->dev
,
2425 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2426 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
2430 * If there's room in the queue (limit it to rx_buffer_size)
2431 * we add this skb back into the pool, if it's the right size
2433 if (skb_queue_len(&priv
->rx_recycle
) < rx_queue
->rx_ring_size
&&
2434 skb_recycle_check(skb
, priv
->rx_buffer_size
+
2436 __skb_queue_head(&priv
->rx_recycle
, skb
);
2438 dev_kfree_skb_any(skb
);
2440 tx_queue
->tx_skbuff
[skb_dirtytx
] = NULL
;
2442 skb_dirtytx
= (skb_dirtytx
+ 1) &
2443 TX_RING_MOD_MASK(tx_ring_size
);
2446 spin_lock_irqsave(&tx_queue
->txlock
, flags
);
2447 tx_queue
->num_txbdfree
+= nr_txbds
;
2448 spin_unlock_irqrestore(&tx_queue
->txlock
, flags
);
2451 /* If we freed a buffer, we can restart transmission, if necessary */
2452 if (__netif_subqueue_stopped(dev
, tx_queue
->qindex
) && tx_queue
->num_txbdfree
)
2453 netif_wake_subqueue(dev
, tx_queue
->qindex
);
2455 /* Update dirty indicators */
2456 tx_queue
->skb_dirtytx
= skb_dirtytx
;
2457 tx_queue
->dirty_tx
= bdp
;
2462 static void gfar_schedule_cleanup(struct gfar_priv_grp
*gfargrp
)
2464 unsigned long flags
;
2466 spin_lock_irqsave(&gfargrp
->grplock
, flags
);
2467 if (napi_schedule_prep(&gfargrp
->napi
)) {
2468 gfar_write(&gfargrp
->regs
->imask
, IMASK_RTX_DISABLED
);
2469 __napi_schedule(&gfargrp
->napi
);
2472 * Clear IEVENT, so interrupts aren't called again
2473 * because of the packets that have already arrived.
2475 gfar_write(&gfargrp
->regs
->ievent
, IEVENT_RTX_MASK
);
2477 spin_unlock_irqrestore(&gfargrp
->grplock
, flags
);
2481 /* Interrupt Handler for Transmit complete */
2482 static irqreturn_t
gfar_transmit(int irq
, void *grp_id
)
2484 gfar_schedule_cleanup((struct gfar_priv_grp
*)grp_id
);
2488 static void gfar_new_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
2489 struct sk_buff
*skb
)
2491 struct net_device
*dev
= rx_queue
->dev
;
2492 struct gfar_private
*priv
= netdev_priv(dev
);
2495 buf
= dma_map_single(&priv
->ofdev
->dev
, skb
->data
,
2496 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
2497 gfar_init_rxbdp(rx_queue
, bdp
, buf
);
2501 struct sk_buff
* gfar_new_skb(struct net_device
*dev
)
2503 unsigned int alignamount
;
2504 struct gfar_private
*priv
= netdev_priv(dev
);
2505 struct sk_buff
*skb
= NULL
;
2507 skb
= __skb_dequeue(&priv
->rx_recycle
);
2509 skb
= netdev_alloc_skb(dev
,
2510 priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
2515 alignamount
= RXBUF_ALIGNMENT
-
2516 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
2518 /* We need the data buffer to be aligned properly. We will reserve
2519 * as many bytes as needed to align the data properly
2521 skb_reserve(skb
, alignamount
);
2522 GFAR_CB(skb
)->alignamount
= alignamount
;
2527 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
2529 struct gfar_private
*priv
= netdev_priv(dev
);
2530 struct net_device_stats
*stats
= &dev
->stats
;
2531 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
2533 /* If the packet was truncated, none of the other errors
2535 if (status
& RXBD_TRUNCATED
) {
2536 stats
->rx_length_errors
++;
2542 /* Count the errors, if there were any */
2543 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
2544 stats
->rx_length_errors
++;
2546 if (status
& RXBD_LARGE
)
2551 if (status
& RXBD_NONOCTET
) {
2552 stats
->rx_frame_errors
++;
2553 estats
->rx_nonoctet
++;
2555 if (status
& RXBD_CRCERR
) {
2556 estats
->rx_crcerr
++;
2557 stats
->rx_crc_errors
++;
2559 if (status
& RXBD_OVERRUN
) {
2560 estats
->rx_overrun
++;
2561 stats
->rx_crc_errors
++;
2565 irqreturn_t
gfar_receive(int irq
, void *grp_id
)
2567 gfar_schedule_cleanup((struct gfar_priv_grp
*)grp_id
);
2571 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
2573 /* If valid headers were found, and valid sums
2574 * were verified, then we tell the kernel that no
2575 * checksumming is necessary. Otherwise, it is */
2576 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
2577 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2579 skb
->ip_summed
= CHECKSUM_NONE
;
2583 /* gfar_process_frame() -- handle one incoming packet if skb
2585 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
2588 struct gfar_private
*priv
= netdev_priv(dev
);
2589 struct rxfcb
*fcb
= NULL
;
2593 /* fcb is at the beginning if exists */
2594 fcb
= (struct rxfcb
*)skb
->data
;
2596 /* Remove the FCB from the skb */
2597 /* Remove the padded bytes, if there are any */
2599 skb_record_rx_queue(skb
, fcb
->rq
);
2600 skb_pull(skb
, amount_pull
);
2603 /* Get receive timestamp from the skb */
2604 if (priv
->hwts_rx_en
) {
2605 struct skb_shared_hwtstamps
*shhwtstamps
= skb_hwtstamps(skb
);
2606 u64
*ns
= (u64
*) skb
->data
;
2607 memset(shhwtstamps
, 0, sizeof(*shhwtstamps
));
2608 shhwtstamps
->hwtstamp
= ns_to_ktime(*ns
);
2612 skb_pull(skb
, priv
->padding
);
2614 if (priv
->rx_csum_enable
)
2615 gfar_rx_checksum(skb
, fcb
);
2617 /* Tell the skb what kind of packet this is */
2618 skb
->protocol
= eth_type_trans(skb
, dev
);
2620 /* Send the packet up the stack */
2621 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
)))
2622 ret
= vlan_hwaccel_receive_skb(skb
, priv
->vlgrp
, fcb
->vlctl
);
2624 ret
= netif_receive_skb(skb
);
2626 if (NET_RX_DROP
== ret
)
2627 priv
->extra_stats
.kernel_dropped
++;
2632 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2633 * until the budget/quota has been reached. Returns the number
2636 int gfar_clean_rx_ring(struct gfar_priv_rx_q
*rx_queue
, int rx_work_limit
)
2638 struct net_device
*dev
= rx_queue
->dev
;
2639 struct rxbd8
*bdp
, *base
;
2640 struct sk_buff
*skb
;
2644 struct gfar_private
*priv
= netdev_priv(dev
);
2646 /* Get the first full descriptor */
2647 bdp
= rx_queue
->cur_rx
;
2648 base
= rx_queue
->rx_bd_base
;
2650 amount_pull
= (gfar_uses_fcb(priv
) ? GMAC_FCB_LEN
: 0);
2652 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
2653 struct sk_buff
*newskb
;
2656 /* Add another skb for the future */
2657 newskb
= gfar_new_skb(dev
);
2659 skb
= rx_queue
->rx_skbuff
[rx_queue
->skb_currx
];
2661 dma_unmap_single(&priv
->ofdev
->dev
, bdp
->bufPtr
,
2662 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
2664 /* We drop the frame if we failed to allocate a new buffer */
2665 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
2666 bdp
->status
& RXBD_ERR
)) {
2667 count_errors(bdp
->status
, dev
);
2669 if (unlikely(!newskb
))
2673 * We need to un-reserve() the skb to what it
2674 * was before gfar_new_skb() re-aligned
2675 * it to an RXBUF_ALIGNMENT boundary
2676 * before we put the skb back on the
2679 skb_reserve(skb
, -GFAR_CB(skb
)->alignamount
);
2680 __skb_queue_head(&priv
->rx_recycle
, skb
);
2683 /* Increment the number of packets */
2684 rx_queue
->stats
.rx_packets
++;
2688 pkt_len
= bdp
->length
- ETH_FCS_LEN
;
2689 /* Remove the FCS from the packet length */
2690 skb_put(skb
, pkt_len
);
2691 rx_queue
->stats
.rx_bytes
+= pkt_len
;
2692 skb_record_rx_queue(skb
, rx_queue
->qindex
);
2693 gfar_process_frame(dev
, skb
, amount_pull
);
2696 if (netif_msg_rx_err(priv
))
2698 "%s: Missing skb!\n", dev
->name
);
2699 rx_queue
->stats
.rx_dropped
++;
2700 priv
->extra_stats
.rx_skbmissing
++;
2705 rx_queue
->rx_skbuff
[rx_queue
->skb_currx
] = newskb
;
2707 /* Setup the new bdp */
2708 gfar_new_rxbdp(rx_queue
, bdp
, newskb
);
2710 /* Update to the next pointer */
2711 bdp
= next_bd(bdp
, base
, rx_queue
->rx_ring_size
);
2713 /* update to point at the next skb */
2714 rx_queue
->skb_currx
=
2715 (rx_queue
->skb_currx
+ 1) &
2716 RX_RING_MOD_MASK(rx_queue
->rx_ring_size
);
2719 /* Update the current rxbd pointer to be the next one */
2720 rx_queue
->cur_rx
= bdp
;
2725 static int gfar_poll(struct napi_struct
*napi
, int budget
)
2727 struct gfar_priv_grp
*gfargrp
= container_of(napi
,
2728 struct gfar_priv_grp
, napi
);
2729 struct gfar_private
*priv
= gfargrp
->priv
;
2730 struct gfar __iomem
*regs
= gfargrp
->regs
;
2731 struct gfar_priv_tx_q
*tx_queue
= NULL
;
2732 struct gfar_priv_rx_q
*rx_queue
= NULL
;
2733 int rx_cleaned
= 0, budget_per_queue
= 0, rx_cleaned_per_queue
= 0;
2734 int tx_cleaned
= 0, i
, left_over_budget
= budget
;
2735 unsigned long serviced_queues
= 0;
2738 num_queues
= gfargrp
->num_rx_queues
;
2739 budget_per_queue
= budget
/num_queues
;
2741 /* Clear IEVENT, so interrupts aren't called again
2742 * because of the packets that have already arrived */
2743 gfar_write(®s
->ievent
, IEVENT_RTX_MASK
);
2745 while (num_queues
&& left_over_budget
) {
2747 budget_per_queue
= left_over_budget
/num_queues
;
2748 left_over_budget
= 0;
2750 for_each_set_bit(i
, &gfargrp
->rx_bit_map
, priv
->num_rx_queues
) {
2751 if (test_bit(i
, &serviced_queues
))
2753 rx_queue
= priv
->rx_queue
[i
];
2754 tx_queue
= priv
->tx_queue
[rx_queue
->qindex
];
2756 tx_cleaned
+= gfar_clean_tx_ring(tx_queue
);
2757 rx_cleaned_per_queue
= gfar_clean_rx_ring(rx_queue
,
2759 rx_cleaned
+= rx_cleaned_per_queue
;
2760 if(rx_cleaned_per_queue
< budget_per_queue
) {
2761 left_over_budget
= left_over_budget
+
2762 (budget_per_queue
- rx_cleaned_per_queue
);
2763 set_bit(i
, &serviced_queues
);
2772 if (rx_cleaned
< budget
) {
2773 napi_complete(napi
);
2775 /* Clear the halt bit in RSTAT */
2776 gfar_write(®s
->rstat
, gfargrp
->rstat
);
2778 gfar_write(®s
->imask
, IMASK_DEFAULT
);
2780 /* If we are coalescing interrupts, update the timer */
2781 /* Otherwise, clear it */
2782 gfar_configure_coalescing(priv
,
2783 gfargrp
->rx_bit_map
, gfargrp
->tx_bit_map
);
2789 #ifdef CONFIG_NET_POLL_CONTROLLER
2791 * Polling 'interrupt' - used by things like netconsole to send skbs
2792 * without having to re-enable interrupts. It's not called while
2793 * the interrupt routine is executing.
2795 static void gfar_netpoll(struct net_device
*dev
)
2797 struct gfar_private
*priv
= netdev_priv(dev
);
2800 /* If the device has multiple interrupts, run tx/rx */
2801 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
2802 for (i
= 0; i
< priv
->num_grps
; i
++) {
2803 disable_irq(priv
->gfargrp
[i
].interruptTransmit
);
2804 disable_irq(priv
->gfargrp
[i
].interruptReceive
);
2805 disable_irq(priv
->gfargrp
[i
].interruptError
);
2806 gfar_interrupt(priv
->gfargrp
[i
].interruptTransmit
,
2808 enable_irq(priv
->gfargrp
[i
].interruptError
);
2809 enable_irq(priv
->gfargrp
[i
].interruptReceive
);
2810 enable_irq(priv
->gfargrp
[i
].interruptTransmit
);
2813 for (i
= 0; i
< priv
->num_grps
; i
++) {
2814 disable_irq(priv
->gfargrp
[i
].interruptTransmit
);
2815 gfar_interrupt(priv
->gfargrp
[i
].interruptTransmit
,
2817 enable_irq(priv
->gfargrp
[i
].interruptTransmit
);
2823 /* The interrupt handler for devices with one interrupt */
2824 static irqreturn_t
gfar_interrupt(int irq
, void *grp_id
)
2826 struct gfar_priv_grp
*gfargrp
= grp_id
;
2828 /* Save ievent for future reference */
2829 u32 events
= gfar_read(&gfargrp
->regs
->ievent
);
2831 /* Check for reception */
2832 if (events
& IEVENT_RX_MASK
)
2833 gfar_receive(irq
, grp_id
);
2835 /* Check for transmit completion */
2836 if (events
& IEVENT_TX_MASK
)
2837 gfar_transmit(irq
, grp_id
);
2839 /* Check for errors */
2840 if (events
& IEVENT_ERR_MASK
)
2841 gfar_error(irq
, grp_id
);
2846 /* Called every time the controller might need to be made
2847 * aware of new link state. The PHY code conveys this
2848 * information through variables in the phydev structure, and this
2849 * function converts those variables into the appropriate
2850 * register values, and can bring down the device if needed.
2852 static void adjust_link(struct net_device
*dev
)
2854 struct gfar_private
*priv
= netdev_priv(dev
);
2855 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
2856 unsigned long flags
;
2857 struct phy_device
*phydev
= priv
->phydev
;
2860 local_irq_save(flags
);
2864 u32 tempval
= gfar_read(®s
->maccfg2
);
2865 u32 ecntrl
= gfar_read(®s
->ecntrl
);
2867 /* Now we make sure that we can be in full duplex mode.
2868 * If not, we operate in half-duplex mode. */
2869 if (phydev
->duplex
!= priv
->oldduplex
) {
2871 if (!(phydev
->duplex
))
2872 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
2874 tempval
|= MACCFG2_FULL_DUPLEX
;
2876 priv
->oldduplex
= phydev
->duplex
;
2879 if (phydev
->speed
!= priv
->oldspeed
) {
2881 switch (phydev
->speed
) {
2884 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
2886 ecntrl
&= ~(ECNTRL_R100
);
2891 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
2893 /* Reduced mode distinguishes
2894 * between 10 and 100 */
2895 if (phydev
->speed
== SPEED_100
)
2896 ecntrl
|= ECNTRL_R100
;
2898 ecntrl
&= ~(ECNTRL_R100
);
2901 if (netif_msg_link(priv
))
2903 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2904 dev
->name
, phydev
->speed
);
2908 priv
->oldspeed
= phydev
->speed
;
2911 gfar_write(®s
->maccfg2
, tempval
);
2912 gfar_write(®s
->ecntrl
, ecntrl
);
2914 if (!priv
->oldlink
) {
2918 } else if (priv
->oldlink
) {
2922 priv
->oldduplex
= -1;
2925 if (new_state
&& netif_msg_link(priv
))
2926 phy_print_status(phydev
);
2928 local_irq_restore(flags
);
2931 /* Update the hash table based on the current list of multicast
2932 * addresses we subscribe to. Also, change the promiscuity of
2933 * the device based on the flags (this function is called
2934 * whenever dev->flags is changed */
2935 static void gfar_set_multi(struct net_device
*dev
)
2937 struct netdev_hw_addr
*ha
;
2938 struct gfar_private
*priv
= netdev_priv(dev
);
2939 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
2942 if (dev
->flags
& IFF_PROMISC
) {
2943 /* Set RCTRL to PROM */
2944 tempval
= gfar_read(®s
->rctrl
);
2945 tempval
|= RCTRL_PROM
;
2946 gfar_write(®s
->rctrl
, tempval
);
2948 /* Set RCTRL to not PROM */
2949 tempval
= gfar_read(®s
->rctrl
);
2950 tempval
&= ~(RCTRL_PROM
);
2951 gfar_write(®s
->rctrl
, tempval
);
2954 if (dev
->flags
& IFF_ALLMULTI
) {
2955 /* Set the hash to rx all multicast frames */
2956 gfar_write(®s
->igaddr0
, 0xffffffff);
2957 gfar_write(®s
->igaddr1
, 0xffffffff);
2958 gfar_write(®s
->igaddr2
, 0xffffffff);
2959 gfar_write(®s
->igaddr3
, 0xffffffff);
2960 gfar_write(®s
->igaddr4
, 0xffffffff);
2961 gfar_write(®s
->igaddr5
, 0xffffffff);
2962 gfar_write(®s
->igaddr6
, 0xffffffff);
2963 gfar_write(®s
->igaddr7
, 0xffffffff);
2964 gfar_write(®s
->gaddr0
, 0xffffffff);
2965 gfar_write(®s
->gaddr1
, 0xffffffff);
2966 gfar_write(®s
->gaddr2
, 0xffffffff);
2967 gfar_write(®s
->gaddr3
, 0xffffffff);
2968 gfar_write(®s
->gaddr4
, 0xffffffff);
2969 gfar_write(®s
->gaddr5
, 0xffffffff);
2970 gfar_write(®s
->gaddr6
, 0xffffffff);
2971 gfar_write(®s
->gaddr7
, 0xffffffff);
2976 /* zero out the hash */
2977 gfar_write(®s
->igaddr0
, 0x0);
2978 gfar_write(®s
->igaddr1
, 0x0);
2979 gfar_write(®s
->igaddr2
, 0x0);
2980 gfar_write(®s
->igaddr3
, 0x0);
2981 gfar_write(®s
->igaddr4
, 0x0);
2982 gfar_write(®s
->igaddr5
, 0x0);
2983 gfar_write(®s
->igaddr6
, 0x0);
2984 gfar_write(®s
->igaddr7
, 0x0);
2985 gfar_write(®s
->gaddr0
, 0x0);
2986 gfar_write(®s
->gaddr1
, 0x0);
2987 gfar_write(®s
->gaddr2
, 0x0);
2988 gfar_write(®s
->gaddr3
, 0x0);
2989 gfar_write(®s
->gaddr4
, 0x0);
2990 gfar_write(®s
->gaddr5
, 0x0);
2991 gfar_write(®s
->gaddr6
, 0x0);
2992 gfar_write(®s
->gaddr7
, 0x0);
2994 /* If we have extended hash tables, we need to
2995 * clear the exact match registers to prepare for
2997 if (priv
->extended_hash
) {
2998 em_num
= GFAR_EM_NUM
+ 1;
2999 gfar_clear_exact_match(dev
);
3006 if (netdev_mc_empty(dev
))
3009 /* Parse the list, and set the appropriate bits */
3010 netdev_for_each_mc_addr(ha
, dev
) {
3012 gfar_set_mac_for_addr(dev
, idx
, ha
->addr
);
3015 gfar_set_hash_for_addr(dev
, ha
->addr
);
3023 /* Clears each of the exact match registers to zero, so they
3024 * don't interfere with normal reception */
3025 static void gfar_clear_exact_match(struct net_device
*dev
)
3028 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
3030 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
3031 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
3034 /* Set the appropriate hash bit for the given addr */
3035 /* The algorithm works like so:
3036 * 1) Take the Destination Address (ie the multicast address), and
3037 * do a CRC on it (little endian), and reverse the bits of the
3039 * 2) Use the 8 most significant bits as a hash into a 256-entry
3040 * table. The table is controlled through 8 32-bit registers:
3041 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3042 * gaddr7. This means that the 3 most significant bits in the
3043 * hash index which gaddr register to use, and the 5 other bits
3044 * indicate which bit (assuming an IBM numbering scheme, which
3045 * for PowerPC (tm) is usually the case) in the register holds
3047 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
3050 struct gfar_private
*priv
= netdev_priv(dev
);
3051 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
3052 int width
= priv
->hash_width
;
3053 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
3054 u8 whichreg
= result
>> (32 - width
+ 5);
3055 u32 value
= (1 << (31-whichbit
));
3057 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
3059 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
3065 /* There are multiple MAC Address register pairs on some controllers
3066 * This function sets the numth pair to a given address
3068 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
3070 struct gfar_private
*priv
= netdev_priv(dev
);
3071 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
3073 char tmpbuf
[MAC_ADDR_LEN
];
3075 u32 __iomem
*macptr
= ®s
->macstnaddr1
;
3079 /* Now copy it into the mac registers backwards, cuz */
3080 /* little endian is silly */
3081 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
3082 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
3084 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
3086 tempval
= *((u32
*) (tmpbuf
+ 4));
3088 gfar_write(macptr
+1, tempval
);
3091 /* GFAR error interrupt handler */
3092 static irqreturn_t
gfar_error(int irq
, void *grp_id
)
3094 struct gfar_priv_grp
*gfargrp
= grp_id
;
3095 struct gfar __iomem
*regs
= gfargrp
->regs
;
3096 struct gfar_private
*priv
= gfargrp
->priv
;
3097 struct net_device
*dev
= priv
->ndev
;
3099 /* Save ievent for future reference */
3100 u32 events
= gfar_read(®s
->ievent
);
3103 gfar_write(®s
->ievent
, events
& IEVENT_ERR_MASK
);
3105 /* Magic Packet is not an error. */
3106 if ((priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
) &&
3107 (events
& IEVENT_MAG
))
3108 events
&= ~IEVENT_MAG
;
3111 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
3112 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
3113 dev
->name
, events
, gfar_read(®s
->imask
));
3115 /* Update the error counters */
3116 if (events
& IEVENT_TXE
) {
3117 dev
->stats
.tx_errors
++;
3119 if (events
& IEVENT_LC
)
3120 dev
->stats
.tx_window_errors
++;
3121 if (events
& IEVENT_CRL
)
3122 dev
->stats
.tx_aborted_errors
++;
3123 if (events
& IEVENT_XFUN
) {
3124 unsigned long flags
;
3126 if (netif_msg_tx_err(priv
))
3127 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
3128 "packet dropped.\n", dev
->name
);
3129 dev
->stats
.tx_dropped
++;
3130 priv
->extra_stats
.tx_underrun
++;
3132 local_irq_save(flags
);
3135 /* Reactivate the Tx Queues */
3136 gfar_write(®s
->tstat
, gfargrp
->tstat
);
3139 local_irq_restore(flags
);
3141 if (netif_msg_tx_err(priv
))
3142 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
3144 if (events
& IEVENT_BSY
) {
3145 dev
->stats
.rx_errors
++;
3146 priv
->extra_stats
.rx_bsy
++;
3148 gfar_receive(irq
, grp_id
);
3150 if (netif_msg_rx_err(priv
))
3151 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
3152 dev
->name
, gfar_read(®s
->rstat
));
3154 if (events
& IEVENT_BABR
) {
3155 dev
->stats
.rx_errors
++;
3156 priv
->extra_stats
.rx_babr
++;
3158 if (netif_msg_rx_err(priv
))
3159 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
3161 if (events
& IEVENT_EBERR
) {
3162 priv
->extra_stats
.eberr
++;
3163 if (netif_msg_rx_err(priv
))
3164 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
3166 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
3167 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
3169 if (events
& IEVENT_BABT
) {
3170 priv
->extra_stats
.tx_babt
++;
3171 if (netif_msg_tx_err(priv
))
3172 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
3177 static struct of_device_id gfar_match
[] =
3181 .compatible
= "gianfar",
3184 .compatible
= "fsl,etsec2",
3188 MODULE_DEVICE_TABLE(of
, gfar_match
);
3190 /* Structure for a device driver */
3191 static struct of_platform_driver gfar_driver
= {
3192 .name
= "fsl-gianfar",
3193 .match_table
= gfar_match
,
3195 .probe
= gfar_probe
,
3196 .remove
= gfar_remove
,
3197 .suspend
= gfar_legacy_suspend
,
3198 .resume
= gfar_legacy_resume
,
3199 .driver
.pm
= GFAR_PM_OPS
,
3202 static int __init
gfar_init(void)
3204 return of_register_platform_driver(&gfar_driver
);
3207 static void __exit
gfar_exit(void)
3209 of_unregister_platform_driver(&gfar_driver
);
3212 module_init(gfar_init
);
3213 module_exit(gfar_exit
);