2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
78 #include <linux/of_platform.h>
80 #include <linux/tcp.h>
81 #include <linux/udp.h>
86 #include <asm/uaccess.h>
87 #include <linux/module.h>
88 #include <linux/dma-mapping.h>
89 #include <linux/crc32.h>
90 #include <linux/mii.h>
91 #include <linux/phy.h>
92 #include <linux/phy_fixed.h>
96 #include "fsl_pq_mdio.h"
98 #define TX_TIMEOUT (1*HZ)
99 #undef BRIEF_GFAR_ERRORS
100 #undef VERBOSE_GFAR_ERRORS
102 const char gfar_driver_name
[] = "Gianfar Ethernet";
103 const char gfar_driver_version
[] = "1.3";
105 static int gfar_enet_open(struct net_device
*dev
);
106 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
107 static void gfar_reset_task(struct work_struct
*work
);
108 static void gfar_timeout(struct net_device
*dev
);
109 static int gfar_close(struct net_device
*dev
);
110 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
111 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
112 struct sk_buff
*skb
);
113 static int gfar_set_mac_address(struct net_device
*dev
);
114 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
115 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
116 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
117 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
118 static void adjust_link(struct net_device
*dev
);
119 static void init_registers(struct net_device
*dev
);
120 static int init_phy(struct net_device
*dev
);
121 static int gfar_probe(struct of_device
*ofdev
,
122 const struct of_device_id
*match
);
123 static int gfar_remove(struct of_device
*ofdev
);
124 static void free_skb_resources(struct gfar_private
*priv
);
125 static void gfar_set_multi(struct net_device
*dev
);
126 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
127 static void gfar_configure_serdes(struct net_device
*dev
);
128 static int gfar_poll(struct napi_struct
*napi
, int budget
);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device
*dev
);
132 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
);
133 static int gfar_clean_tx_ring(struct net_device
*dev
);
134 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
136 static void gfar_vlan_rx_register(struct net_device
*netdev
,
137 struct vlan_group
*grp
);
138 void gfar_halt(struct net_device
*dev
);
139 static void gfar_halt_nodisable(struct net_device
*dev
);
140 void gfar_start(struct net_device
*dev
);
141 static void gfar_clear_exact_match(struct net_device
*dev
);
142 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
144 MODULE_AUTHOR("Freescale Semiconductor, Inc");
145 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
146 MODULE_LICENSE("GPL");
148 /* Returns 1 if incoming frames use an FCB */
149 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
151 return priv
->vlgrp
|| priv
->rx_csum_enable
;
154 static int gfar_of_init(struct net_device
*dev
)
156 struct device_node
*phy
, *mdio
;
157 const unsigned int *id
;
160 const void *mac_addr
;
164 struct gfar_private
*priv
= netdev_priv(dev
);
165 struct device_node
*np
= priv
->node
;
166 char bus_name
[MII_BUS_ID_SIZE
];
168 const u32
*stash_len
;
169 const u32
*stash_idx
;
171 if (!np
|| !of_device_is_available(np
))
174 /* get a pointer to the register memory */
175 addr
= of_translate_address(np
, of_get_address(np
, 0, &size
, NULL
));
176 priv
->regs
= ioremap(addr
, size
);
178 if (priv
->regs
== NULL
)
181 priv
->interruptTransmit
= irq_of_parse_and_map(np
, 0);
183 model
= of_get_property(np
, "model", NULL
);
185 /* If we aren't the FEC we have multiple interrupts */
186 if (model
&& strcasecmp(model
, "FEC")) {
187 priv
->interruptReceive
= irq_of_parse_and_map(np
, 1);
189 priv
->interruptError
= irq_of_parse_and_map(np
, 2);
191 if (priv
->interruptTransmit
< 0 ||
192 priv
->interruptReceive
< 0 ||
193 priv
->interruptError
< 0) {
199 stash
= of_get_property(np
, "bd-stash", NULL
);
202 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BD_STASHING
;
203 priv
->bd_stash_en
= 1;
206 stash_len
= of_get_property(np
, "rx-stash-len", NULL
);
209 priv
->rx_stash_size
= *stash_len
;
211 stash_idx
= of_get_property(np
, "rx-stash-idx", NULL
);
214 priv
->rx_stash_index
= *stash_idx
;
216 if (stash_len
|| stash_idx
)
217 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BUF_STASHING
;
219 mac_addr
= of_get_mac_address(np
);
221 memcpy(dev
->dev_addr
, mac_addr
, MAC_ADDR_LEN
);
223 if (model
&& !strcasecmp(model
, "TSEC"))
225 FSL_GIANFAR_DEV_HAS_GIGABIT
|
226 FSL_GIANFAR_DEV_HAS_COALESCE
|
227 FSL_GIANFAR_DEV_HAS_RMON
|
228 FSL_GIANFAR_DEV_HAS_MULTI_INTR
;
229 if (model
&& !strcasecmp(model
, "eTSEC"))
231 FSL_GIANFAR_DEV_HAS_GIGABIT
|
232 FSL_GIANFAR_DEV_HAS_COALESCE
|
233 FSL_GIANFAR_DEV_HAS_RMON
|
234 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
235 FSL_GIANFAR_DEV_HAS_PADDING
|
236 FSL_GIANFAR_DEV_HAS_CSUM
|
237 FSL_GIANFAR_DEV_HAS_VLAN
|
238 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
|
239 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
;
241 ctype
= of_get_property(np
, "phy-connection-type", NULL
);
243 /* We only care about rgmii-id. The rest are autodetected */
244 if (ctype
&& !strcmp(ctype
, "rgmii-id"))
245 priv
->interface
= PHY_INTERFACE_MODE_RGMII_ID
;
247 priv
->interface
= PHY_INTERFACE_MODE_MII
;
249 if (of_get_property(np
, "fsl,magic-packet", NULL
))
250 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
;
252 ph
= of_get_property(np
, "phy-handle", NULL
);
256 fixed_link
= (u32
*)of_get_property(np
, "fixed-link", NULL
);
262 snprintf(priv
->phy_bus_id
, sizeof(priv
->phy_bus_id
),
263 PHY_ID_FMT
, "0", fixed_link
[0]);
265 phy
= of_find_node_by_phandle(*ph
);
272 mdio
= of_get_parent(phy
);
274 id
= of_get_property(phy
, "reg", NULL
);
279 fsl_pq_mdio_bus_name(bus_name
, mdio
);
280 snprintf(priv
->phy_bus_id
, sizeof(priv
->phy_bus_id
), "%s:%02x",
284 /* Find the TBI PHY. If it's not there, we don't support SGMII */
285 ph
= of_get_property(np
, "tbi-handle", NULL
);
287 struct device_node
*tbi
= of_find_node_by_phandle(*ph
);
288 struct of_device
*ofdev
;
294 mdio
= of_get_parent(tbi
);
298 ofdev
= of_find_device_by_node(mdio
);
302 id
= of_get_property(tbi
, "reg", NULL
);
308 bus
= dev_get_drvdata(&ofdev
->dev
);
310 priv
->tbiphy
= bus
->phy_map
[*id
];
320 /* Ioctl MII Interface */
321 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
323 struct gfar_private
*priv
= netdev_priv(dev
);
325 if (!netif_running(dev
))
331 return phy_mii_ioctl(priv
->phydev
, if_mii(rq
), cmd
);
334 /* Set up the ethernet device structure, private data,
335 * and anything else we need before we start */
336 static int gfar_probe(struct of_device
*ofdev
,
337 const struct of_device_id
*match
)
340 struct net_device
*dev
= NULL
;
341 struct gfar_private
*priv
= NULL
;
342 DECLARE_MAC_BUF(mac
);
346 /* Create an ethernet device instance */
347 dev
= alloc_etherdev(sizeof (*priv
));
352 priv
= netdev_priv(dev
);
354 priv
->node
= ofdev
->node
;
356 err
= gfar_of_init(dev
);
361 spin_lock_init(&priv
->txlock
);
362 spin_lock_init(&priv
->rxlock
);
363 spin_lock_init(&priv
->bflock
);
364 INIT_WORK(&priv
->reset_task
, gfar_reset_task
);
366 dev_set_drvdata(&ofdev
->dev
, priv
);
368 /* Stop the DMA engine now, in case it was running before */
369 /* (The firmware could have used it, and left it running). */
372 /* Reset MAC layer */
373 gfar_write(&priv
->regs
->maccfg1
, MACCFG1_SOFT_RESET
);
375 /* We need to delay at least 3 TX clocks */
378 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
379 gfar_write(&priv
->regs
->maccfg1
, tempval
);
381 /* Initialize MACCFG2. */
382 gfar_write(&priv
->regs
->maccfg2
, MACCFG2_INIT_SETTINGS
);
384 /* Initialize ECNTRL */
385 gfar_write(&priv
->regs
->ecntrl
, ECNTRL_INIT_SETTINGS
);
387 /* Set the dev->base_addr to the gfar reg region */
388 dev
->base_addr
= (unsigned long) (priv
->regs
);
390 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
392 /* Fill in the dev structure */
393 dev
->open
= gfar_enet_open
;
394 dev
->hard_start_xmit
= gfar_start_xmit
;
395 dev
->tx_timeout
= gfar_timeout
;
396 dev
->watchdog_timeo
= TX_TIMEOUT
;
397 netif_napi_add(dev
, &priv
->napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
398 #ifdef CONFIG_NET_POLL_CONTROLLER
399 dev
->poll_controller
= gfar_netpoll
;
401 dev
->stop
= gfar_close
;
402 dev
->change_mtu
= gfar_change_mtu
;
404 dev
->set_multicast_list
= gfar_set_multi
;
406 dev
->ethtool_ops
= &gfar_ethtool_ops
;
407 dev
->do_ioctl
= gfar_ioctl
;
409 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
410 priv
->rx_csum_enable
= 1;
411 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
| NETIF_F_HIGHDMA
;
413 priv
->rx_csum_enable
= 0;
417 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
418 dev
->vlan_rx_register
= gfar_vlan_rx_register
;
420 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
423 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
424 priv
->extended_hash
= 1;
425 priv
->hash_width
= 9;
427 priv
->hash_regs
[0] = &priv
->regs
->igaddr0
;
428 priv
->hash_regs
[1] = &priv
->regs
->igaddr1
;
429 priv
->hash_regs
[2] = &priv
->regs
->igaddr2
;
430 priv
->hash_regs
[3] = &priv
->regs
->igaddr3
;
431 priv
->hash_regs
[4] = &priv
->regs
->igaddr4
;
432 priv
->hash_regs
[5] = &priv
->regs
->igaddr5
;
433 priv
->hash_regs
[6] = &priv
->regs
->igaddr6
;
434 priv
->hash_regs
[7] = &priv
->regs
->igaddr7
;
435 priv
->hash_regs
[8] = &priv
->regs
->gaddr0
;
436 priv
->hash_regs
[9] = &priv
->regs
->gaddr1
;
437 priv
->hash_regs
[10] = &priv
->regs
->gaddr2
;
438 priv
->hash_regs
[11] = &priv
->regs
->gaddr3
;
439 priv
->hash_regs
[12] = &priv
->regs
->gaddr4
;
440 priv
->hash_regs
[13] = &priv
->regs
->gaddr5
;
441 priv
->hash_regs
[14] = &priv
->regs
->gaddr6
;
442 priv
->hash_regs
[15] = &priv
->regs
->gaddr7
;
445 priv
->extended_hash
= 0;
446 priv
->hash_width
= 8;
448 priv
->hash_regs
[0] = &priv
->regs
->gaddr0
;
449 priv
->hash_regs
[1] = &priv
->regs
->gaddr1
;
450 priv
->hash_regs
[2] = &priv
->regs
->gaddr2
;
451 priv
->hash_regs
[3] = &priv
->regs
->gaddr3
;
452 priv
->hash_regs
[4] = &priv
->regs
->gaddr4
;
453 priv
->hash_regs
[5] = &priv
->regs
->gaddr5
;
454 priv
->hash_regs
[6] = &priv
->regs
->gaddr6
;
455 priv
->hash_regs
[7] = &priv
->regs
->gaddr7
;
458 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
459 priv
->padding
= DEFAULT_PADDING
;
463 if (dev
->features
& NETIF_F_IP_CSUM
)
464 dev
->hard_header_len
+= GMAC_FCB_LEN
;
466 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
467 priv
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
468 priv
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
469 priv
->num_txbdfree
= DEFAULT_TX_RING_SIZE
;
471 priv
->txcoalescing
= DEFAULT_TX_COALESCE
;
472 priv
->txic
= DEFAULT_TXIC
;
473 priv
->rxcoalescing
= DEFAULT_RX_COALESCE
;
474 priv
->rxic
= DEFAULT_RXIC
;
476 /* Enable most messages by default */
477 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
479 /* Carrier starts down, phylib will bring it up */
480 netif_carrier_off(dev
);
482 err
= register_netdev(dev
);
485 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
490 device_init_wakeup(&dev
->dev
,
491 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
493 /* fill out IRQ number and name fields */
494 len_devname
= strlen(dev
->name
);
495 strncpy(&priv
->int_name_tx
[0], dev
->name
, len_devname
);
496 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
497 strncpy(&priv
->int_name_tx
[len_devname
],
498 "_tx", sizeof("_tx") + 1);
500 strncpy(&priv
->int_name_rx
[0], dev
->name
, len_devname
);
501 strncpy(&priv
->int_name_rx
[len_devname
],
502 "_rx", sizeof("_rx") + 1);
504 strncpy(&priv
->int_name_er
[0], dev
->name
, len_devname
);
505 strncpy(&priv
->int_name_er
[len_devname
],
506 "_er", sizeof("_er") + 1);
508 priv
->int_name_tx
[len_devname
] = '\0';
510 /* Create all the sysfs files */
511 gfar_init_sysfs(dev
);
513 /* Print out the device info */
514 printk(KERN_INFO DEVICE_NAME
"%pM\n", dev
->name
, dev
->dev_addr
);
516 /* Even more device info helps when determining which kernel */
517 /* provided which set of benchmarks. */
518 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
519 printk(KERN_INFO
"%s: %d/%d RX/TX BD ring size\n",
520 dev
->name
, priv
->rx_ring_size
, priv
->tx_ring_size
);
531 static int gfar_remove(struct of_device
*ofdev
)
533 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
535 dev_set_drvdata(&ofdev
->dev
, NULL
);
538 free_netdev(priv
->dev
);
544 static int gfar_suspend(struct of_device
*ofdev
, pm_message_t state
)
546 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
547 struct net_device
*dev
= priv
->dev
;
551 int magic_packet
= priv
->wol_en
&&
552 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
554 netif_device_detach(dev
);
556 if (netif_running(dev
)) {
557 spin_lock_irqsave(&priv
->txlock
, flags
);
558 spin_lock(&priv
->rxlock
);
560 gfar_halt_nodisable(dev
);
562 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
563 tempval
= gfar_read(&priv
->regs
->maccfg1
);
565 tempval
&= ~MACCFG1_TX_EN
;
568 tempval
&= ~MACCFG1_RX_EN
;
570 gfar_write(&priv
->regs
->maccfg1
, tempval
);
572 spin_unlock(&priv
->rxlock
);
573 spin_unlock_irqrestore(&priv
->txlock
, flags
);
575 napi_disable(&priv
->napi
);
578 /* Enable interrupt on Magic Packet */
579 gfar_write(&priv
->regs
->imask
, IMASK_MAG
);
581 /* Enable Magic Packet mode */
582 tempval
= gfar_read(&priv
->regs
->maccfg2
);
583 tempval
|= MACCFG2_MPEN
;
584 gfar_write(&priv
->regs
->maccfg2
, tempval
);
586 phy_stop(priv
->phydev
);
593 static int gfar_resume(struct of_device
*ofdev
)
595 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
596 struct net_device
*dev
= priv
->dev
;
599 int magic_packet
= priv
->wol_en
&&
600 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
602 if (!netif_running(dev
)) {
603 netif_device_attach(dev
);
607 if (!magic_packet
&& priv
->phydev
)
608 phy_start(priv
->phydev
);
610 /* Disable Magic Packet mode, in case something
614 spin_lock_irqsave(&priv
->txlock
, flags
);
615 spin_lock(&priv
->rxlock
);
617 tempval
= gfar_read(&priv
->regs
->maccfg2
);
618 tempval
&= ~MACCFG2_MPEN
;
619 gfar_write(&priv
->regs
->maccfg2
, tempval
);
623 spin_unlock(&priv
->rxlock
);
624 spin_unlock_irqrestore(&priv
->txlock
, flags
);
626 netif_device_attach(dev
);
628 napi_enable(&priv
->napi
);
633 #define gfar_suspend NULL
634 #define gfar_resume NULL
637 /* Reads the controller's registers to determine what interface
638 * connects it to the PHY.
640 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
642 struct gfar_private
*priv
= netdev_priv(dev
);
643 u32 ecntrl
= gfar_read(&priv
->regs
->ecntrl
);
645 if (ecntrl
& ECNTRL_SGMII_MODE
)
646 return PHY_INTERFACE_MODE_SGMII
;
648 if (ecntrl
& ECNTRL_TBI_MODE
) {
649 if (ecntrl
& ECNTRL_REDUCED_MODE
)
650 return PHY_INTERFACE_MODE_RTBI
;
652 return PHY_INTERFACE_MODE_TBI
;
655 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
656 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
657 return PHY_INTERFACE_MODE_RMII
;
659 phy_interface_t interface
= priv
->interface
;
662 * This isn't autodetected right now, so it must
663 * be set by the device tree or platform code.
665 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
666 return PHY_INTERFACE_MODE_RGMII_ID
;
668 return PHY_INTERFACE_MODE_RGMII
;
672 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
673 return PHY_INTERFACE_MODE_GMII
;
675 return PHY_INTERFACE_MODE_MII
;
679 /* Initializes driver's PHY state, and attaches to the PHY.
680 * Returns 0 on success.
682 static int init_phy(struct net_device
*dev
)
684 struct gfar_private
*priv
= netdev_priv(dev
);
685 uint gigabit_support
=
686 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
687 SUPPORTED_1000baseT_Full
: 0;
688 struct phy_device
*phydev
;
689 phy_interface_t interface
;
693 priv
->oldduplex
= -1;
695 interface
= gfar_get_interface(dev
);
697 phydev
= phy_connect(dev
, priv
->phy_bus_id
, &adjust_link
, 0, interface
);
699 if (interface
== PHY_INTERFACE_MODE_SGMII
)
700 gfar_configure_serdes(dev
);
702 if (IS_ERR(phydev
)) {
703 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
704 return PTR_ERR(phydev
);
707 /* Remove any features not supported by the controller */
708 phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
709 phydev
->advertising
= phydev
->supported
;
711 priv
->phydev
= phydev
;
717 * Initialize TBI PHY interface for communicating with the
718 * SERDES lynx PHY on the chip. We communicate with this PHY
719 * through the MDIO bus on each controller, treating it as a
720 * "normal" PHY at the address found in the TBIPA register. We assume
721 * that the TBIPA register is valid. Either the MDIO bus code will set
722 * it to a value that doesn't conflict with other PHYs on the bus, or the
723 * value doesn't matter, as there are no other PHYs on the bus.
725 static void gfar_configure_serdes(struct net_device
*dev
)
727 struct gfar_private
*priv
= netdev_priv(dev
);
730 printk(KERN_WARNING
"SGMII mode requires that the device "
731 "tree specify a tbi-handle\n");
736 * If the link is already up, we must already be ok, and don't need to
737 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
738 * everything for us? Resetting it takes the link down and requires
739 * several seconds for it to come back.
741 if (phy_read(priv
->tbiphy
, MII_BMSR
) & BMSR_LSTATUS
)
744 /* Single clk mode, mii mode off(for serdes communication) */
745 phy_write(priv
->tbiphy
, MII_TBICON
, TBICON_CLK_SELECT
);
747 phy_write(priv
->tbiphy
, MII_ADVERTISE
,
748 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
749 ADVERTISE_1000XPSE_ASYM
);
751 phy_write(priv
->tbiphy
, MII_BMCR
, BMCR_ANENABLE
|
752 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
755 static void init_registers(struct net_device
*dev
)
757 struct gfar_private
*priv
= netdev_priv(dev
);
760 gfar_write(&priv
->regs
->ievent
, IEVENT_INIT_CLEAR
);
762 /* Initialize IMASK */
763 gfar_write(&priv
->regs
->imask
, IMASK_INIT_CLEAR
);
765 /* Init hash registers to zero */
766 gfar_write(&priv
->regs
->igaddr0
, 0);
767 gfar_write(&priv
->regs
->igaddr1
, 0);
768 gfar_write(&priv
->regs
->igaddr2
, 0);
769 gfar_write(&priv
->regs
->igaddr3
, 0);
770 gfar_write(&priv
->regs
->igaddr4
, 0);
771 gfar_write(&priv
->regs
->igaddr5
, 0);
772 gfar_write(&priv
->regs
->igaddr6
, 0);
773 gfar_write(&priv
->regs
->igaddr7
, 0);
775 gfar_write(&priv
->regs
->gaddr0
, 0);
776 gfar_write(&priv
->regs
->gaddr1
, 0);
777 gfar_write(&priv
->regs
->gaddr2
, 0);
778 gfar_write(&priv
->regs
->gaddr3
, 0);
779 gfar_write(&priv
->regs
->gaddr4
, 0);
780 gfar_write(&priv
->regs
->gaddr5
, 0);
781 gfar_write(&priv
->regs
->gaddr6
, 0);
782 gfar_write(&priv
->regs
->gaddr7
, 0);
784 /* Zero out the rmon mib registers if it has them */
785 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
786 memset_io(&(priv
->regs
->rmon
), 0, sizeof (struct rmon_mib
));
788 /* Mask off the CAM interrupts */
789 gfar_write(&priv
->regs
->rmon
.cam1
, 0xffffffff);
790 gfar_write(&priv
->regs
->rmon
.cam2
, 0xffffffff);
793 /* Initialize the max receive buffer length */
794 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
796 /* Initialize the Minimum Frame Length Register */
797 gfar_write(&priv
->regs
->minflr
, MINFLR_INIT_SETTINGS
);
801 /* Halt the receive and transmit queues */
802 static void gfar_halt_nodisable(struct net_device
*dev
)
804 struct gfar_private
*priv
= netdev_priv(dev
);
805 struct gfar __iomem
*regs
= priv
->regs
;
808 /* Mask all interrupts */
809 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
811 /* Clear all interrupts */
812 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
814 /* Stop the DMA, and wait for it to stop */
815 tempval
= gfar_read(&priv
->regs
->dmactrl
);
816 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
817 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
818 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
819 gfar_write(&priv
->regs
->dmactrl
, tempval
);
821 while (!(gfar_read(&priv
->regs
->ievent
) &
822 (IEVENT_GRSC
| IEVENT_GTSC
)))
827 /* Halt the receive and transmit queues */
828 void gfar_halt(struct net_device
*dev
)
830 struct gfar_private
*priv
= netdev_priv(dev
);
831 struct gfar __iomem
*regs
= priv
->regs
;
834 gfar_halt_nodisable(dev
);
836 /* Disable Rx and Tx */
837 tempval
= gfar_read(®s
->maccfg1
);
838 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
839 gfar_write(®s
->maccfg1
, tempval
);
842 void stop_gfar(struct net_device
*dev
)
844 struct gfar_private
*priv
= netdev_priv(dev
);
845 struct gfar __iomem
*regs
= priv
->regs
;
848 phy_stop(priv
->phydev
);
851 spin_lock_irqsave(&priv
->txlock
, flags
);
852 spin_lock(&priv
->rxlock
);
856 spin_unlock(&priv
->rxlock
);
857 spin_unlock_irqrestore(&priv
->txlock
, flags
);
860 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
861 free_irq(priv
->interruptError
, dev
);
862 free_irq(priv
->interruptTransmit
, dev
);
863 free_irq(priv
->interruptReceive
, dev
);
865 free_irq(priv
->interruptTransmit
, dev
);
868 free_skb_resources(priv
);
870 dma_free_coherent(&dev
->dev
,
871 sizeof(struct txbd8
)*priv
->tx_ring_size
872 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
874 gfar_read(®s
->tbase0
));
877 /* If there are any tx skbs or rx skbs still around, free them.
878 * Then free tx_skbuff and rx_skbuff */
879 static void free_skb_resources(struct gfar_private
*priv
)
885 /* Go through all the buffer descriptors and free their data buffers */
886 txbdp
= priv
->tx_bd_base
;
888 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
889 if (!priv
->tx_skbuff
[i
])
892 dma_unmap_single(&priv
->dev
->dev
, txbdp
->bufPtr
,
893 txbdp
->length
, DMA_TO_DEVICE
);
895 for (j
= 0; j
< skb_shinfo(priv
->tx_skbuff
[i
])->nr_frags
; j
++) {
897 dma_unmap_page(&priv
->dev
->dev
, txbdp
->bufPtr
,
898 txbdp
->length
, DMA_TO_DEVICE
);
901 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
902 priv
->tx_skbuff
[i
] = NULL
;
905 kfree(priv
->tx_skbuff
);
907 rxbdp
= priv
->rx_bd_base
;
909 /* rx_skbuff is not guaranteed to be allocated, so only
910 * free it and its contents if it is allocated */
911 if(priv
->rx_skbuff
!= NULL
) {
912 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
913 if (priv
->rx_skbuff
[i
]) {
914 dma_unmap_single(&priv
->dev
->dev
, rxbdp
->bufPtr
,
915 priv
->rx_buffer_size
,
918 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
919 priv
->rx_skbuff
[i
] = NULL
;
928 kfree(priv
->rx_skbuff
);
932 void gfar_start(struct net_device
*dev
)
934 struct gfar_private
*priv
= netdev_priv(dev
);
935 struct gfar __iomem
*regs
= priv
->regs
;
938 /* Enable Rx and Tx in MACCFG1 */
939 tempval
= gfar_read(®s
->maccfg1
);
940 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
941 gfar_write(®s
->maccfg1
, tempval
);
943 /* Initialize DMACTRL to have WWR and WOP */
944 tempval
= gfar_read(&priv
->regs
->dmactrl
);
945 tempval
|= DMACTRL_INIT_SETTINGS
;
946 gfar_write(&priv
->regs
->dmactrl
, tempval
);
948 /* Make sure we aren't stopped */
949 tempval
= gfar_read(&priv
->regs
->dmactrl
);
950 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
951 gfar_write(&priv
->regs
->dmactrl
, tempval
);
953 /* Clear THLT/RHLT, so that the DMA starts polling now */
954 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
);
955 gfar_write(®s
->rstat
, RSTAT_CLEAR_RHALT
);
957 /* Unmask the interrupts we look for */
958 gfar_write(®s
->imask
, IMASK_DEFAULT
);
960 dev
->trans_start
= jiffies
;
963 /* Bring the controller up and running */
964 int startup_gfar(struct net_device
*dev
)
971 struct gfar_private
*priv
= netdev_priv(dev
);
972 struct gfar __iomem
*regs
= priv
->regs
;
977 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
979 /* Allocate memory for the buffer descriptors */
980 vaddr
= (unsigned long) dma_alloc_coherent(&dev
->dev
,
981 sizeof (struct txbd8
) * priv
->tx_ring_size
+
982 sizeof (struct rxbd8
) * priv
->rx_ring_size
,
986 if (netif_msg_ifup(priv
))
987 printk(KERN_ERR
"%s: Could not allocate buffer descriptors!\n",
992 priv
->tx_bd_base
= (struct txbd8
*) vaddr
;
994 /* enet DMA only understands physical addresses */
995 gfar_write(®s
->tbase0
, addr
);
997 /* Start the rx descriptor ring where the tx ring leaves off */
998 addr
= addr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
999 vaddr
= vaddr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
1000 priv
->rx_bd_base
= (struct rxbd8
*) vaddr
;
1001 gfar_write(®s
->rbase0
, addr
);
1003 /* Setup the skbuff rings */
1005 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
1006 priv
->tx_ring_size
, GFP_KERNEL
);
1008 if (NULL
== priv
->tx_skbuff
) {
1009 if (netif_msg_ifup(priv
))
1010 printk(KERN_ERR
"%s: Could not allocate tx_skbuff\n",
1016 for (i
= 0; i
< priv
->tx_ring_size
; i
++)
1017 priv
->tx_skbuff
[i
] = NULL
;
1020 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
1021 priv
->rx_ring_size
, GFP_KERNEL
);
1023 if (NULL
== priv
->rx_skbuff
) {
1024 if (netif_msg_ifup(priv
))
1025 printk(KERN_ERR
"%s: Could not allocate rx_skbuff\n",
1031 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
1032 priv
->rx_skbuff
[i
] = NULL
;
1034 /* Initialize some variables in our dev structure */
1035 priv
->num_txbdfree
= priv
->tx_ring_size
;
1036 priv
->dirty_tx
= priv
->cur_tx
= priv
->tx_bd_base
;
1037 priv
->cur_rx
= priv
->rx_bd_base
;
1038 priv
->skb_curtx
= priv
->skb_dirtytx
= 0;
1039 priv
->skb_currx
= 0;
1041 /* Initialize Transmit Descriptor Ring */
1042 txbdp
= priv
->tx_bd_base
;
1043 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
1049 /* Set the last descriptor in the ring to indicate wrap */
1051 txbdp
->status
|= TXBD_WRAP
;
1053 rxbdp
= priv
->rx_bd_base
;
1054 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
1055 struct sk_buff
*skb
;
1057 skb
= gfar_new_skb(dev
);
1060 printk(KERN_ERR
"%s: Can't allocate RX buffers\n",
1063 goto err_rxalloc_fail
;
1066 priv
->rx_skbuff
[i
] = skb
;
1068 gfar_new_rxbdp(dev
, rxbdp
, skb
);
1073 /* Set the last descriptor in the ring to wrap */
1075 rxbdp
->status
|= RXBD_WRAP
;
1077 /* If the device has multiple interrupts, register for
1078 * them. Otherwise, only register for the one */
1079 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1080 /* Install our interrupt handlers for Error,
1081 * Transmit, and Receive */
1082 if (request_irq(priv
->interruptError
, gfar_error
,
1083 0, priv
->int_name_er
, dev
) < 0) {
1084 if (netif_msg_intr(priv
))
1085 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1086 dev
->name
, priv
->interruptError
);
1092 if (request_irq(priv
->interruptTransmit
, gfar_transmit
,
1093 0, priv
->int_name_tx
, dev
) < 0) {
1094 if (netif_msg_intr(priv
))
1095 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1096 dev
->name
, priv
->interruptTransmit
);
1103 if (request_irq(priv
->interruptReceive
, gfar_receive
,
1104 0, priv
->int_name_rx
, dev
) < 0) {
1105 if (netif_msg_intr(priv
))
1106 printk(KERN_ERR
"%s: Can't get IRQ %d (receive0)\n",
1107 dev
->name
, priv
->interruptReceive
);
1113 if (request_irq(priv
->interruptTransmit
, gfar_interrupt
,
1114 0, priv
->int_name_tx
, dev
) < 0) {
1115 if (netif_msg_intr(priv
))
1116 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
1117 dev
->name
, priv
->interruptTransmit
);
1124 phy_start(priv
->phydev
);
1126 /* Configure the coalescing support */
1127 gfar_write(®s
->txic
, 0);
1128 if (priv
->txcoalescing
)
1129 gfar_write(®s
->txic
, priv
->txic
);
1131 gfar_write(®s
->rxic
, 0);
1132 if (priv
->rxcoalescing
)
1133 gfar_write(®s
->rxic
, priv
->rxic
);
1135 if (priv
->rx_csum_enable
)
1136 rctrl
|= RCTRL_CHECKSUMMING
;
1138 if (priv
->extended_hash
) {
1139 rctrl
|= RCTRL_EXTHASH
;
1141 gfar_clear_exact_match(dev
);
1142 rctrl
|= RCTRL_EMEN
;
1145 if (priv
->padding
) {
1146 rctrl
&= ~RCTRL_PAL_MASK
;
1147 rctrl
|= RCTRL_PADDING(priv
->padding
);
1150 /* Init rctrl based on our settings */
1151 gfar_write(&priv
->regs
->rctrl
, rctrl
);
1153 if (dev
->features
& NETIF_F_IP_CSUM
)
1154 gfar_write(&priv
->regs
->tctrl
, TCTRL_INIT_CSUM
);
1156 /* Set the extraction length and index */
1157 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
1158 ATTRELI_EI(priv
->rx_stash_index
);
1160 gfar_write(&priv
->regs
->attreli
, attrs
);
1162 /* Start with defaults, and add stashing or locking
1163 * depending on the approprate variables */
1164 attrs
= ATTR_INIT_SETTINGS
;
1166 if (priv
->bd_stash_en
)
1167 attrs
|= ATTR_BDSTASH
;
1169 if (priv
->rx_stash_size
!= 0)
1170 attrs
|= ATTR_BUFSTASH
;
1172 gfar_write(&priv
->regs
->attr
, attrs
);
1174 gfar_write(&priv
->regs
->fifo_tx_thr
, priv
->fifo_threshold
);
1175 gfar_write(&priv
->regs
->fifo_tx_starve
, priv
->fifo_starve
);
1176 gfar_write(&priv
->regs
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
1178 /* Start the controller */
1184 free_irq(priv
->interruptTransmit
, dev
);
1186 free_irq(priv
->interruptError
, dev
);
1190 free_skb_resources(priv
);
1192 dma_free_coherent(&dev
->dev
,
1193 sizeof(struct txbd8
)*priv
->tx_ring_size
1194 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
1196 gfar_read(®s
->tbase0
));
1201 /* Called when something needs to use the ethernet device */
1202 /* Returns 0 for success. */
1203 static int gfar_enet_open(struct net_device
*dev
)
1205 struct gfar_private
*priv
= netdev_priv(dev
);
1208 napi_enable(&priv
->napi
);
1210 skb_queue_head_init(&priv
->rx_recycle
);
1212 /* Initialize a bunch of registers */
1213 init_registers(dev
);
1215 gfar_set_mac_address(dev
);
1217 err
= init_phy(dev
);
1220 napi_disable(&priv
->napi
);
1224 err
= startup_gfar(dev
);
1226 napi_disable(&priv
->napi
);
1230 netif_start_queue(dev
);
1232 device_set_wakeup_enable(&dev
->dev
, priv
->wol_en
);
1237 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
)
1239 struct txfcb
*fcb
= (struct txfcb
*)skb_push (skb
, GMAC_FCB_LEN
);
1241 cacheable_memzero(fcb
, GMAC_FCB_LEN
);
1246 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
1250 /* If we're here, it's a IP packet with a TCP or UDP
1251 * payload. We set it to checksum, using a pseudo-header
1254 flags
= TXFCB_DEFAULT
;
1256 /* Tell the controller what the protocol is */
1257 /* And provide the already calculated phcs */
1258 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
1260 fcb
->phcs
= udp_hdr(skb
)->check
;
1262 fcb
->phcs
= tcp_hdr(skb
)->check
;
1264 /* l3os is the distance between the start of the
1265 * frame (skb->data) and the start of the IP hdr.
1266 * l4os is the distance between the start of the
1267 * l3 hdr and the l4 hdr */
1268 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
1269 fcb
->l4os
= skb_network_header_len(skb
);
1274 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
1276 fcb
->flags
|= TXFCB_VLN
;
1277 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1280 static inline struct txbd8
*skip_txbd(struct txbd8
*bdp
, int stride
,
1281 struct txbd8
*base
, int ring_size
)
1283 struct txbd8
*new_bd
= bdp
+ stride
;
1285 return (new_bd
>= (base
+ ring_size
)) ? (new_bd
- ring_size
) : new_bd
;
1288 static inline struct txbd8
*next_txbd(struct txbd8
*bdp
, struct txbd8
*base
,
1291 return skip_txbd(bdp
, 1, base
, ring_size
);
1294 /* This is called by the kernel when a frame is ready for transmission. */
1295 /* It is pointed to by the dev->hard_start_xmit function pointer */
1296 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1298 struct gfar_private
*priv
= netdev_priv(dev
);
1299 struct txfcb
*fcb
= NULL
;
1300 struct txbd8
*txbdp
, *txbdp_start
, *base
;
1304 unsigned long flags
;
1305 unsigned int nr_frags
, length
;
1307 base
= priv
->tx_bd_base
;
1309 /* total number of fragments in the SKB */
1310 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1312 spin_lock_irqsave(&priv
->txlock
, flags
);
1314 /* check if there is space to queue this packet */
1315 if (nr_frags
> priv
->num_txbdfree
) {
1316 /* no space, stop the queue */
1317 netif_stop_queue(dev
);
1318 dev
->stats
.tx_fifo_errors
++;
1319 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1320 return NETDEV_TX_BUSY
;
1323 /* Update transmit stats */
1324 dev
->stats
.tx_bytes
+= skb
->len
;
1326 txbdp
= txbdp_start
= priv
->cur_tx
;
1328 if (nr_frags
== 0) {
1329 lstatus
= txbdp
->lstatus
| BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
1331 /* Place the fragment addresses and lengths into the TxBDs */
1332 for (i
= 0; i
< nr_frags
; i
++) {
1333 /* Point at the next BD, wrapping as needed */
1334 txbdp
= next_txbd(txbdp
, base
, priv
->tx_ring_size
);
1336 length
= skb_shinfo(skb
)->frags
[i
].size
;
1338 lstatus
= txbdp
->lstatus
| length
|
1339 BD_LFLAG(TXBD_READY
);
1341 /* Handle the last BD specially */
1342 if (i
== nr_frags
- 1)
1343 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
1345 bufaddr
= dma_map_page(&dev
->dev
,
1346 skb_shinfo(skb
)->frags
[i
].page
,
1347 skb_shinfo(skb
)->frags
[i
].page_offset
,
1351 /* set the TxBD length and buffer pointer */
1352 txbdp
->bufPtr
= bufaddr
;
1353 txbdp
->lstatus
= lstatus
;
1356 lstatus
= txbdp_start
->lstatus
;
1359 /* Set up checksumming */
1360 if (CHECKSUM_PARTIAL
== skb
->ip_summed
) {
1361 fcb
= gfar_add_fcb(skb
);
1362 lstatus
|= BD_LFLAG(TXBD_TOE
);
1363 gfar_tx_checksum(skb
, fcb
);
1366 if (priv
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1367 if (unlikely(NULL
== fcb
)) {
1368 fcb
= gfar_add_fcb(skb
);
1369 lstatus
|= BD_LFLAG(TXBD_TOE
);
1372 gfar_tx_vlan(skb
, fcb
);
1375 /* setup the TxBD length and buffer pointer for the first BD */
1376 priv
->tx_skbuff
[priv
->skb_curtx
] = skb
;
1377 txbdp_start
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1378 skb_headlen(skb
), DMA_TO_DEVICE
);
1380 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | skb_headlen(skb
);
1383 * The powerpc-specific eieio() is used, as wmb() has too strong
1384 * semantics (it requires synchronization between cacheable and
1385 * uncacheable mappings, which eieio doesn't provide and which we
1386 * don't need), thus requiring a more expensive sync instruction. At
1387 * some point, the set of architecture-independent barrier functions
1388 * should be expanded to include weaker barriers.
1392 txbdp_start
->lstatus
= lstatus
;
1394 /* Update the current skb pointer to the next entry we will use
1395 * (wrapping if necessary) */
1396 priv
->skb_curtx
= (priv
->skb_curtx
+ 1) &
1397 TX_RING_MOD_MASK(priv
->tx_ring_size
);
1399 priv
->cur_tx
= next_txbd(txbdp
, base
, priv
->tx_ring_size
);
1401 /* reduce TxBD free count */
1402 priv
->num_txbdfree
-= (nr_frags
+ 1);
1404 dev
->trans_start
= jiffies
;
1406 /* If the next BD still needs to be cleaned up, then the bds
1407 are full. We need to tell the kernel to stop sending us stuff. */
1408 if (!priv
->num_txbdfree
) {
1409 netif_stop_queue(dev
);
1411 dev
->stats
.tx_fifo_errors
++;
1414 /* Tell the DMA to go go go */
1415 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1418 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1423 /* Stops the kernel queue, and halts the controller */
1424 static int gfar_close(struct net_device
*dev
)
1426 struct gfar_private
*priv
= netdev_priv(dev
);
1428 napi_disable(&priv
->napi
);
1430 skb_queue_purge(&priv
->rx_recycle
);
1431 cancel_work_sync(&priv
->reset_task
);
1434 /* Disconnect from the PHY */
1435 phy_disconnect(priv
->phydev
);
1436 priv
->phydev
= NULL
;
1438 netif_stop_queue(dev
);
1443 /* Changes the mac address if the controller is not running. */
1444 static int gfar_set_mac_address(struct net_device
*dev
)
1446 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
1452 /* Enables and disables VLAN insertion/extraction */
1453 static void gfar_vlan_rx_register(struct net_device
*dev
,
1454 struct vlan_group
*grp
)
1456 struct gfar_private
*priv
= netdev_priv(dev
);
1457 unsigned long flags
;
1460 spin_lock_irqsave(&priv
->rxlock
, flags
);
1465 /* Enable VLAN tag insertion */
1466 tempval
= gfar_read(&priv
->regs
->tctrl
);
1467 tempval
|= TCTRL_VLINS
;
1469 gfar_write(&priv
->regs
->tctrl
, tempval
);
1471 /* Enable VLAN tag extraction */
1472 tempval
= gfar_read(&priv
->regs
->rctrl
);
1473 tempval
|= RCTRL_VLEX
;
1474 tempval
|= (RCTRL_VLEX
| RCTRL_PRSDEP_INIT
);
1475 gfar_write(&priv
->regs
->rctrl
, tempval
);
1477 /* Disable VLAN tag insertion */
1478 tempval
= gfar_read(&priv
->regs
->tctrl
);
1479 tempval
&= ~TCTRL_VLINS
;
1480 gfar_write(&priv
->regs
->tctrl
, tempval
);
1482 /* Disable VLAN tag extraction */
1483 tempval
= gfar_read(&priv
->regs
->rctrl
);
1484 tempval
&= ~RCTRL_VLEX
;
1485 /* If parse is no longer required, then disable parser */
1486 if (tempval
& RCTRL_REQ_PARSER
)
1487 tempval
|= RCTRL_PRSDEP_INIT
;
1489 tempval
&= ~RCTRL_PRSDEP_INIT
;
1490 gfar_write(&priv
->regs
->rctrl
, tempval
);
1493 gfar_change_mtu(dev
, dev
->mtu
);
1495 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1498 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
1500 int tempsize
, tempval
;
1501 struct gfar_private
*priv
= netdev_priv(dev
);
1502 int oldsize
= priv
->rx_buffer_size
;
1503 int frame_size
= new_mtu
+ ETH_HLEN
;
1506 frame_size
+= VLAN_HLEN
;
1508 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
1509 if (netif_msg_drv(priv
))
1510 printk(KERN_ERR
"%s: Invalid MTU setting\n",
1515 if (gfar_uses_fcb(priv
))
1516 frame_size
+= GMAC_FCB_LEN
;
1518 frame_size
+= priv
->padding
;
1521 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
1522 INCREMENTAL_BUFFER_SIZE
;
1524 /* Only stop and start the controller if it isn't already
1525 * stopped, and we changed something */
1526 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1529 priv
->rx_buffer_size
= tempsize
;
1533 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
1534 gfar_write(&priv
->regs
->maxfrm
, priv
->rx_buffer_size
);
1536 /* If the mtu is larger than the max size for standard
1537 * ethernet frames (ie, a jumbo frame), then set maccfg2
1538 * to allow huge frames, and to check the length */
1539 tempval
= gfar_read(&priv
->regs
->maccfg2
);
1541 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
1542 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1544 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1546 gfar_write(&priv
->regs
->maccfg2
, tempval
);
1548 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1554 /* gfar_reset_task gets scheduled when a packet has not been
1555 * transmitted after a set amount of time.
1556 * For now, assume that clearing out all the structures, and
1557 * starting over will fix the problem.
1559 static void gfar_reset_task(struct work_struct
*work
)
1561 struct gfar_private
*priv
= container_of(work
, struct gfar_private
,
1563 struct net_device
*dev
= priv
->dev
;
1565 if (dev
->flags
& IFF_UP
) {
1570 netif_tx_schedule_all(dev
);
1573 static void gfar_timeout(struct net_device
*dev
)
1575 struct gfar_private
*priv
= netdev_priv(dev
);
1577 dev
->stats
.tx_errors
++;
1578 schedule_work(&priv
->reset_task
);
1581 /* Interrupt Handler for Transmit complete */
1582 static int gfar_clean_tx_ring(struct net_device
*dev
)
1584 struct gfar_private
*priv
= netdev_priv(dev
);
1586 struct txbd8
*lbdp
= NULL
;
1587 struct txbd8
*base
= priv
->tx_bd_base
;
1588 struct sk_buff
*skb
;
1590 int tx_ring_size
= priv
->tx_ring_size
;
1596 bdp
= priv
->dirty_tx
;
1597 skb_dirtytx
= priv
->skb_dirtytx
;
1599 while ((skb
= priv
->tx_skbuff
[skb_dirtytx
])) {
1600 frags
= skb_shinfo(skb
)->nr_frags
;
1601 lbdp
= skip_txbd(bdp
, frags
, base
, tx_ring_size
);
1603 lstatus
= lbdp
->lstatus
;
1605 /* Only clean completed frames */
1606 if ((lstatus
& BD_LFLAG(TXBD_READY
)) &&
1607 (lstatus
& BD_LENGTH_MASK
))
1610 dma_unmap_single(&dev
->dev
,
1615 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
1616 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
1618 for (i
= 0; i
< frags
; i
++) {
1619 dma_unmap_page(&dev
->dev
,
1623 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
1624 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
1628 * If there's room in the queue (limit it to rx_buffer_size)
1629 * we add this skb back into the pool, if it's the right size
1631 if (skb_queue_len(&priv
->rx_recycle
) < priv
->rx_ring_size
&&
1632 skb_recycle_check(skb
, priv
->rx_buffer_size
+
1634 __skb_queue_head(&priv
->rx_recycle
, skb
);
1636 dev_kfree_skb_any(skb
);
1638 priv
->tx_skbuff
[skb_dirtytx
] = NULL
;
1640 skb_dirtytx
= (skb_dirtytx
+ 1) &
1641 TX_RING_MOD_MASK(tx_ring_size
);
1644 priv
->num_txbdfree
+= frags
+ 1;
1647 /* If we freed a buffer, we can restart transmission, if necessary */
1648 if (netif_queue_stopped(dev
) && priv
->num_txbdfree
)
1649 netif_wake_queue(dev
);
1651 /* Update dirty indicators */
1652 priv
->skb_dirtytx
= skb_dirtytx
;
1653 priv
->dirty_tx
= bdp
;
1655 dev
->stats
.tx_packets
+= howmany
;
1660 static void gfar_schedule_cleanup(struct net_device
*dev
)
1662 struct gfar_private
*priv
= netdev_priv(dev
);
1663 unsigned long flags
;
1665 spin_lock_irqsave(&priv
->txlock
, flags
);
1666 spin_lock(&priv
->rxlock
);
1668 if (napi_schedule_prep(&priv
->napi
)) {
1669 gfar_write(&priv
->regs
->imask
, IMASK_RTX_DISABLED
);
1670 __napi_schedule(&priv
->napi
);
1673 spin_unlock(&priv
->rxlock
);
1674 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1677 /* Interrupt Handler for Transmit complete */
1678 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
)
1680 gfar_schedule_cleanup((struct net_device
*)dev_id
);
1684 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
1685 struct sk_buff
*skb
)
1687 struct gfar_private
*priv
= netdev_priv(dev
);
1690 bdp
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1691 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1693 lstatus
= BD_LFLAG(RXBD_EMPTY
| RXBD_INTERRUPT
);
1695 if (bdp
== priv
->rx_bd_base
+ priv
->rx_ring_size
- 1)
1696 lstatus
|= BD_LFLAG(RXBD_WRAP
);
1700 bdp
->lstatus
= lstatus
;
1704 struct sk_buff
* gfar_new_skb(struct net_device
*dev
)
1706 unsigned int alignamount
;
1707 struct gfar_private
*priv
= netdev_priv(dev
);
1708 struct sk_buff
*skb
= NULL
;
1710 skb
= __skb_dequeue(&priv
->rx_recycle
);
1712 skb
= netdev_alloc_skb(dev
,
1713 priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
1718 alignamount
= RXBUF_ALIGNMENT
-
1719 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
1721 /* We need the data buffer to be aligned properly. We will reserve
1722 * as many bytes as needed to align the data properly
1724 skb_reserve(skb
, alignamount
);
1729 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
1731 struct gfar_private
*priv
= netdev_priv(dev
);
1732 struct net_device_stats
*stats
= &dev
->stats
;
1733 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
1735 /* If the packet was truncated, none of the other errors
1737 if (status
& RXBD_TRUNCATED
) {
1738 stats
->rx_length_errors
++;
1744 /* Count the errors, if there were any */
1745 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
1746 stats
->rx_length_errors
++;
1748 if (status
& RXBD_LARGE
)
1753 if (status
& RXBD_NONOCTET
) {
1754 stats
->rx_frame_errors
++;
1755 estats
->rx_nonoctet
++;
1757 if (status
& RXBD_CRCERR
) {
1758 estats
->rx_crcerr
++;
1759 stats
->rx_crc_errors
++;
1761 if (status
& RXBD_OVERRUN
) {
1762 estats
->rx_overrun
++;
1763 stats
->rx_crc_errors
++;
1767 irqreturn_t
gfar_receive(int irq
, void *dev_id
)
1769 gfar_schedule_cleanup((struct net_device
*)dev_id
);
1773 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
1775 /* If valid headers were found, and valid sums
1776 * were verified, then we tell the kernel that no
1777 * checksumming is necessary. Otherwise, it is */
1778 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
1779 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1781 skb
->ip_summed
= CHECKSUM_NONE
;
1785 /* gfar_process_frame() -- handle one incoming packet if skb
1787 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
1790 struct gfar_private
*priv
= netdev_priv(dev
);
1791 struct rxfcb
*fcb
= NULL
;
1795 /* fcb is at the beginning if exists */
1796 fcb
= (struct rxfcb
*)skb
->data
;
1798 /* Remove the FCB from the skb */
1799 /* Remove the padded bytes, if there are any */
1801 skb_pull(skb
, amount_pull
);
1803 if (priv
->rx_csum_enable
)
1804 gfar_rx_checksum(skb
, fcb
);
1806 /* Tell the skb what kind of packet this is */
1807 skb
->protocol
= eth_type_trans(skb
, dev
);
1809 /* Send the packet up the stack */
1810 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
)))
1811 ret
= vlan_hwaccel_receive_skb(skb
, priv
->vlgrp
, fcb
->vlctl
);
1813 ret
= netif_receive_skb(skb
);
1815 if (NET_RX_DROP
== ret
)
1816 priv
->extra_stats
.kernel_dropped
++;
1821 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1822 * until the budget/quota has been reached. Returns the number
1825 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
)
1827 struct rxbd8
*bdp
, *base
;
1828 struct sk_buff
*skb
;
1832 struct gfar_private
*priv
= netdev_priv(dev
);
1834 /* Get the first full descriptor */
1836 base
= priv
->rx_bd_base
;
1838 amount_pull
= (gfar_uses_fcb(priv
) ? GMAC_FCB_LEN
: 0) +
1841 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
1842 struct sk_buff
*newskb
;
1845 /* Add another skb for the future */
1846 newskb
= gfar_new_skb(dev
);
1848 skb
= priv
->rx_skbuff
[priv
->skb_currx
];
1850 dma_unmap_single(&priv
->dev
->dev
, bdp
->bufPtr
,
1851 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1853 /* We drop the frame if we failed to allocate a new buffer */
1854 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
1855 bdp
->status
& RXBD_ERR
)) {
1856 count_errors(bdp
->status
, dev
);
1858 if (unlikely(!newskb
))
1861 __skb_queue_head(&priv
->rx_recycle
, skb
);
1863 /* Increment the number of packets */
1864 dev
->stats
.rx_packets
++;
1868 pkt_len
= bdp
->length
- ETH_FCS_LEN
;
1869 /* Remove the FCS from the packet length */
1870 skb_put(skb
, pkt_len
);
1871 dev
->stats
.rx_bytes
+= pkt_len
;
1873 if (in_irq() || irqs_disabled())
1874 printk("Interrupt problem!\n");
1875 gfar_process_frame(dev
, skb
, amount_pull
);
1878 if (netif_msg_rx_err(priv
))
1880 "%s: Missing skb!\n", dev
->name
);
1881 dev
->stats
.rx_dropped
++;
1882 priv
->extra_stats
.rx_skbmissing
++;
1887 priv
->rx_skbuff
[priv
->skb_currx
] = newskb
;
1889 /* Setup the new bdp */
1890 gfar_new_rxbdp(dev
, bdp
, newskb
);
1892 /* Update to the next pointer */
1893 bdp
= next_bd(bdp
, base
, priv
->rx_ring_size
);
1895 /* update to point at the next skb */
1897 (priv
->skb_currx
+ 1) &
1898 RX_RING_MOD_MASK(priv
->rx_ring_size
);
1901 /* Update the current rxbd pointer to be the next one */
1907 static int gfar_poll(struct napi_struct
*napi
, int budget
)
1909 struct gfar_private
*priv
= container_of(napi
, struct gfar_private
, napi
);
1910 struct net_device
*dev
= priv
->dev
;
1913 unsigned long flags
;
1915 /* Clear IEVENT, so interrupts aren't called again
1916 * because of the packets that have already arrived */
1917 gfar_write(&priv
->regs
->ievent
, IEVENT_RTX_MASK
);
1919 /* If we fail to get the lock, don't bother with the TX BDs */
1920 if (spin_trylock_irqsave(&priv
->txlock
, flags
)) {
1921 tx_cleaned
= gfar_clean_tx_ring(dev
);
1922 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1925 rx_cleaned
= gfar_clean_rx_ring(dev
, budget
);
1930 if (rx_cleaned
< budget
) {
1931 napi_complete(napi
);
1933 /* Clear the halt bit in RSTAT */
1934 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1936 gfar_write(&priv
->regs
->imask
, IMASK_DEFAULT
);
1938 /* If we are coalescing interrupts, update the timer */
1939 /* Otherwise, clear it */
1940 if (likely(priv
->rxcoalescing
)) {
1941 gfar_write(&priv
->regs
->rxic
, 0);
1942 gfar_write(&priv
->regs
->rxic
, priv
->rxic
);
1944 if (likely(priv
->txcoalescing
)) {
1945 gfar_write(&priv
->regs
->txic
, 0);
1946 gfar_write(&priv
->regs
->txic
, priv
->txic
);
1953 #ifdef CONFIG_NET_POLL_CONTROLLER
1955 * Polling 'interrupt' - used by things like netconsole to send skbs
1956 * without having to re-enable interrupts. It's not called while
1957 * the interrupt routine is executing.
1959 static void gfar_netpoll(struct net_device
*dev
)
1961 struct gfar_private
*priv
= netdev_priv(dev
);
1963 /* If the device has multiple interrupts, run tx/rx */
1964 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1965 disable_irq(priv
->interruptTransmit
);
1966 disable_irq(priv
->interruptReceive
);
1967 disable_irq(priv
->interruptError
);
1968 gfar_interrupt(priv
->interruptTransmit
, dev
);
1969 enable_irq(priv
->interruptError
);
1970 enable_irq(priv
->interruptReceive
);
1971 enable_irq(priv
->interruptTransmit
);
1973 disable_irq(priv
->interruptTransmit
);
1974 gfar_interrupt(priv
->interruptTransmit
, dev
);
1975 enable_irq(priv
->interruptTransmit
);
1980 /* The interrupt handler for devices with one interrupt */
1981 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
)
1983 struct net_device
*dev
= dev_id
;
1984 struct gfar_private
*priv
= netdev_priv(dev
);
1986 /* Save ievent for future reference */
1987 u32 events
= gfar_read(&priv
->regs
->ievent
);
1989 /* Check for reception */
1990 if (events
& IEVENT_RX_MASK
)
1991 gfar_receive(irq
, dev_id
);
1993 /* Check for transmit completion */
1994 if (events
& IEVENT_TX_MASK
)
1995 gfar_transmit(irq
, dev_id
);
1997 /* Check for errors */
1998 if (events
& IEVENT_ERR_MASK
)
1999 gfar_error(irq
, dev_id
);
2004 /* Called every time the controller might need to be made
2005 * aware of new link state. The PHY code conveys this
2006 * information through variables in the phydev structure, and this
2007 * function converts those variables into the appropriate
2008 * register values, and can bring down the device if needed.
2010 static void adjust_link(struct net_device
*dev
)
2012 struct gfar_private
*priv
= netdev_priv(dev
);
2013 struct gfar __iomem
*regs
= priv
->regs
;
2014 unsigned long flags
;
2015 struct phy_device
*phydev
= priv
->phydev
;
2018 spin_lock_irqsave(&priv
->txlock
, flags
);
2020 u32 tempval
= gfar_read(®s
->maccfg2
);
2021 u32 ecntrl
= gfar_read(®s
->ecntrl
);
2023 /* Now we make sure that we can be in full duplex mode.
2024 * If not, we operate in half-duplex mode. */
2025 if (phydev
->duplex
!= priv
->oldduplex
) {
2027 if (!(phydev
->duplex
))
2028 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
2030 tempval
|= MACCFG2_FULL_DUPLEX
;
2032 priv
->oldduplex
= phydev
->duplex
;
2035 if (phydev
->speed
!= priv
->oldspeed
) {
2037 switch (phydev
->speed
) {
2040 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
2042 ecntrl
&= ~(ECNTRL_R100
);
2047 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
2049 /* Reduced mode distinguishes
2050 * between 10 and 100 */
2051 if (phydev
->speed
== SPEED_100
)
2052 ecntrl
|= ECNTRL_R100
;
2054 ecntrl
&= ~(ECNTRL_R100
);
2057 if (netif_msg_link(priv
))
2059 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2060 dev
->name
, phydev
->speed
);
2064 priv
->oldspeed
= phydev
->speed
;
2067 gfar_write(®s
->maccfg2
, tempval
);
2068 gfar_write(®s
->ecntrl
, ecntrl
);
2070 if (!priv
->oldlink
) {
2074 } else if (priv
->oldlink
) {
2078 priv
->oldduplex
= -1;
2081 if (new_state
&& netif_msg_link(priv
))
2082 phy_print_status(phydev
);
2084 spin_unlock_irqrestore(&priv
->txlock
, flags
);
2087 /* Update the hash table based on the current list of multicast
2088 * addresses we subscribe to. Also, change the promiscuity of
2089 * the device based on the flags (this function is called
2090 * whenever dev->flags is changed */
2091 static void gfar_set_multi(struct net_device
*dev
)
2093 struct dev_mc_list
*mc_ptr
;
2094 struct gfar_private
*priv
= netdev_priv(dev
);
2095 struct gfar __iomem
*regs
= priv
->regs
;
2098 if(dev
->flags
& IFF_PROMISC
) {
2099 /* Set RCTRL to PROM */
2100 tempval
= gfar_read(®s
->rctrl
);
2101 tempval
|= RCTRL_PROM
;
2102 gfar_write(®s
->rctrl
, tempval
);
2104 /* Set RCTRL to not PROM */
2105 tempval
= gfar_read(®s
->rctrl
);
2106 tempval
&= ~(RCTRL_PROM
);
2107 gfar_write(®s
->rctrl
, tempval
);
2110 if(dev
->flags
& IFF_ALLMULTI
) {
2111 /* Set the hash to rx all multicast frames */
2112 gfar_write(®s
->igaddr0
, 0xffffffff);
2113 gfar_write(®s
->igaddr1
, 0xffffffff);
2114 gfar_write(®s
->igaddr2
, 0xffffffff);
2115 gfar_write(®s
->igaddr3
, 0xffffffff);
2116 gfar_write(®s
->igaddr4
, 0xffffffff);
2117 gfar_write(®s
->igaddr5
, 0xffffffff);
2118 gfar_write(®s
->igaddr6
, 0xffffffff);
2119 gfar_write(®s
->igaddr7
, 0xffffffff);
2120 gfar_write(®s
->gaddr0
, 0xffffffff);
2121 gfar_write(®s
->gaddr1
, 0xffffffff);
2122 gfar_write(®s
->gaddr2
, 0xffffffff);
2123 gfar_write(®s
->gaddr3
, 0xffffffff);
2124 gfar_write(®s
->gaddr4
, 0xffffffff);
2125 gfar_write(®s
->gaddr5
, 0xffffffff);
2126 gfar_write(®s
->gaddr6
, 0xffffffff);
2127 gfar_write(®s
->gaddr7
, 0xffffffff);
2132 /* zero out the hash */
2133 gfar_write(®s
->igaddr0
, 0x0);
2134 gfar_write(®s
->igaddr1
, 0x0);
2135 gfar_write(®s
->igaddr2
, 0x0);
2136 gfar_write(®s
->igaddr3
, 0x0);
2137 gfar_write(®s
->igaddr4
, 0x0);
2138 gfar_write(®s
->igaddr5
, 0x0);
2139 gfar_write(®s
->igaddr6
, 0x0);
2140 gfar_write(®s
->igaddr7
, 0x0);
2141 gfar_write(®s
->gaddr0
, 0x0);
2142 gfar_write(®s
->gaddr1
, 0x0);
2143 gfar_write(®s
->gaddr2
, 0x0);
2144 gfar_write(®s
->gaddr3
, 0x0);
2145 gfar_write(®s
->gaddr4
, 0x0);
2146 gfar_write(®s
->gaddr5
, 0x0);
2147 gfar_write(®s
->gaddr6
, 0x0);
2148 gfar_write(®s
->gaddr7
, 0x0);
2150 /* If we have extended hash tables, we need to
2151 * clear the exact match registers to prepare for
2153 if (priv
->extended_hash
) {
2154 em_num
= GFAR_EM_NUM
+ 1;
2155 gfar_clear_exact_match(dev
);
2162 if(dev
->mc_count
== 0)
2165 /* Parse the list, and set the appropriate bits */
2166 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
2168 gfar_set_mac_for_addr(dev
, idx
,
2172 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
2180 /* Clears each of the exact match registers to zero, so they
2181 * don't interfere with normal reception */
2182 static void gfar_clear_exact_match(struct net_device
*dev
)
2185 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
2187 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
2188 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
2191 /* Set the appropriate hash bit for the given addr */
2192 /* The algorithm works like so:
2193 * 1) Take the Destination Address (ie the multicast address), and
2194 * do a CRC on it (little endian), and reverse the bits of the
2196 * 2) Use the 8 most significant bits as a hash into a 256-entry
2197 * table. The table is controlled through 8 32-bit registers:
2198 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2199 * gaddr7. This means that the 3 most significant bits in the
2200 * hash index which gaddr register to use, and the 5 other bits
2201 * indicate which bit (assuming an IBM numbering scheme, which
2202 * for PowerPC (tm) is usually the case) in the register holds
2204 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
2207 struct gfar_private
*priv
= netdev_priv(dev
);
2208 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
2209 int width
= priv
->hash_width
;
2210 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
2211 u8 whichreg
= result
>> (32 - width
+ 5);
2212 u32 value
= (1 << (31-whichbit
));
2214 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
2216 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
2222 /* There are multiple MAC Address register pairs on some controllers
2223 * This function sets the numth pair to a given address
2225 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
2227 struct gfar_private
*priv
= netdev_priv(dev
);
2229 char tmpbuf
[MAC_ADDR_LEN
];
2231 u32 __iomem
*macptr
= &priv
->regs
->macstnaddr1
;
2235 /* Now copy it into the mac registers backwards, cuz */
2236 /* little endian is silly */
2237 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
2238 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
2240 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
2242 tempval
= *((u32
*) (tmpbuf
+ 4));
2244 gfar_write(macptr
+1, tempval
);
2247 /* GFAR error interrupt handler */
2248 static irqreturn_t
gfar_error(int irq
, void *dev_id
)
2250 struct net_device
*dev
= dev_id
;
2251 struct gfar_private
*priv
= netdev_priv(dev
);
2253 /* Save ievent for future reference */
2254 u32 events
= gfar_read(&priv
->regs
->ievent
);
2257 gfar_write(&priv
->regs
->ievent
, events
& IEVENT_ERR_MASK
);
2259 /* Magic Packet is not an error. */
2260 if ((priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
) &&
2261 (events
& IEVENT_MAG
))
2262 events
&= ~IEVENT_MAG
;
2265 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
2266 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2267 dev
->name
, events
, gfar_read(&priv
->regs
->imask
));
2269 /* Update the error counters */
2270 if (events
& IEVENT_TXE
) {
2271 dev
->stats
.tx_errors
++;
2273 if (events
& IEVENT_LC
)
2274 dev
->stats
.tx_window_errors
++;
2275 if (events
& IEVENT_CRL
)
2276 dev
->stats
.tx_aborted_errors
++;
2277 if (events
& IEVENT_XFUN
) {
2278 if (netif_msg_tx_err(priv
))
2279 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
2280 "packet dropped.\n", dev
->name
);
2281 dev
->stats
.tx_dropped
++;
2282 priv
->extra_stats
.tx_underrun
++;
2284 /* Reactivate the Tx Queues */
2285 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
2287 if (netif_msg_tx_err(priv
))
2288 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
2290 if (events
& IEVENT_BSY
) {
2291 dev
->stats
.rx_errors
++;
2292 priv
->extra_stats
.rx_bsy
++;
2294 gfar_receive(irq
, dev_id
);
2296 if (netif_msg_rx_err(priv
))
2297 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
2298 dev
->name
, gfar_read(&priv
->regs
->rstat
));
2300 if (events
& IEVENT_BABR
) {
2301 dev
->stats
.rx_errors
++;
2302 priv
->extra_stats
.rx_babr
++;
2304 if (netif_msg_rx_err(priv
))
2305 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
2307 if (events
& IEVENT_EBERR
) {
2308 priv
->extra_stats
.eberr
++;
2309 if (netif_msg_rx_err(priv
))
2310 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
2312 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
2313 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
2315 if (events
& IEVENT_BABT
) {
2316 priv
->extra_stats
.tx_babt
++;
2317 if (netif_msg_tx_err(priv
))
2318 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
2323 /* work with hotplug and coldplug */
2324 MODULE_ALIAS("platform:fsl-gianfar");
2326 static struct of_device_id gfar_match
[] =
2330 .compatible
= "gianfar",
2335 /* Structure for a device driver */
2336 static struct of_platform_driver gfar_driver
= {
2337 .name
= "fsl-gianfar",
2338 .match_table
= gfar_match
,
2340 .probe
= gfar_probe
,
2341 .remove
= gfar_remove
,
2342 .suspend
= gfar_suspend
,
2343 .resume
= gfar_resume
,
2346 static int __init
gfar_init(void)
2348 return of_register_platform_driver(&gfar_driver
);
2351 static void __exit
gfar_exit(void)
2353 of_unregister_platform_driver(&gfar_driver
);
2356 module_init(gfar_init
);
2357 module_exit(gfar_exit
);