2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
13 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
21 * Gianfar: AKA Lambda Draconis, "Dragon"
29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
36 * last descriptor of the ring.
38 * When a packet is received, the RXF bit in the
39 * IEVENT register is set, triggering an interrupt when the
40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
43 * of frames or amount of time have passed). In NAPI, the
44 * interrupt handler will signal there is work to be done, and
45 * exit. This method will start at the last known empty
46 * descriptor, and process every subsequent descriptor until there
47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
65 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
68 #include <linux/kernel.h>
69 #include <linux/string.h>
70 #include <linux/errno.h>
71 #include <linux/unistd.h>
72 #include <linux/slab.h>
73 #include <linux/interrupt.h>
74 #include <linux/init.h>
75 #include <linux/delay.h>
76 #include <linux/netdevice.h>
77 #include <linux/etherdevice.h>
78 #include <linux/skbuff.h>
79 #include <linux/if_vlan.h>
80 #include <linux/spinlock.h>
82 #include <linux/of_mdio.h>
83 #include <linux/of_platform.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
88 #include <linux/net_tstamp.h>
93 #include <asm/uaccess.h>
94 #include <linux/module.h>
95 #include <linux/dma-mapping.h>
96 #include <linux/crc32.h>
97 #include <linux/mii.h>
98 #include <linux/phy.h>
99 #include <linux/phy_fixed.h>
100 #include <linux/of.h>
101 #include <linux/of_net.h>
104 #include "fsl_pq_mdio.h"
106 #define TX_TIMEOUT (1*HZ)
107 #undef BRIEF_GFAR_ERRORS
108 #undef VERBOSE_GFAR_ERRORS
110 const char gfar_driver_name
[] = "Gianfar Ethernet";
111 const char gfar_driver_version
[] = "1.3";
113 static int gfar_enet_open(struct net_device
*dev
);
114 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
115 static void gfar_reset_task(struct work_struct
*work
);
116 static void gfar_timeout(struct net_device
*dev
);
117 static int gfar_close(struct net_device
*dev
);
118 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
119 static void gfar_new_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
120 struct sk_buff
*skb
);
121 static int gfar_set_mac_address(struct net_device
*dev
);
122 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
123 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
124 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
125 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
126 static void adjust_link(struct net_device
*dev
);
127 static void init_registers(struct net_device
*dev
);
128 static int init_phy(struct net_device
*dev
);
129 static int gfar_probe(struct platform_device
*ofdev
);
130 static int gfar_remove(struct platform_device
*ofdev
);
131 static void free_skb_resources(struct gfar_private
*priv
);
132 static void gfar_set_multi(struct net_device
*dev
);
133 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
134 static void gfar_configure_serdes(struct net_device
*dev
);
135 static int gfar_poll(struct napi_struct
*napi
, int budget
);
136 #ifdef CONFIG_NET_POLL_CONTROLLER
137 static void gfar_netpoll(struct net_device
*dev
);
139 int gfar_clean_rx_ring(struct gfar_priv_rx_q
*rx_queue
, int rx_work_limit
);
140 static int gfar_clean_tx_ring(struct gfar_priv_tx_q
*tx_queue
);
141 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
143 void gfar_halt(struct net_device
*dev
);
144 static void gfar_halt_nodisable(struct net_device
*dev
);
145 void gfar_start(struct net_device
*dev
);
146 static void gfar_clear_exact_match(struct net_device
*dev
);
147 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
,
149 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
153 MODULE_LICENSE("GPL");
155 static void gfar_init_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
162 lstatus
= BD_LFLAG(RXBD_EMPTY
| RXBD_INTERRUPT
);
163 if (bdp
== rx_queue
->rx_bd_base
+ rx_queue
->rx_ring_size
- 1)
164 lstatus
|= BD_LFLAG(RXBD_WRAP
);
168 bdp
->lstatus
= lstatus
;
171 static int gfar_init_bds(struct net_device
*ndev
)
173 struct gfar_private
*priv
= netdev_priv(ndev
);
174 struct gfar_priv_tx_q
*tx_queue
= NULL
;
175 struct gfar_priv_rx_q
*rx_queue
= NULL
;
180 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
181 tx_queue
= priv
->tx_queue
[i
];
182 /* Initialize some variables in our dev structure */
183 tx_queue
->num_txbdfree
= tx_queue
->tx_ring_size
;
184 tx_queue
->dirty_tx
= tx_queue
->tx_bd_base
;
185 tx_queue
->cur_tx
= tx_queue
->tx_bd_base
;
186 tx_queue
->skb_curtx
= 0;
187 tx_queue
->skb_dirtytx
= 0;
189 /* Initialize Transmit Descriptor Ring */
190 txbdp
= tx_queue
->tx_bd_base
;
191 for (j
= 0; j
< tx_queue
->tx_ring_size
; j
++) {
197 /* Set the last descriptor in the ring to indicate wrap */
199 txbdp
->status
|= TXBD_WRAP
;
202 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
203 rx_queue
= priv
->rx_queue
[i
];
204 rx_queue
->cur_rx
= rx_queue
->rx_bd_base
;
205 rx_queue
->skb_currx
= 0;
206 rxbdp
= rx_queue
->rx_bd_base
;
208 for (j
= 0; j
< rx_queue
->rx_ring_size
; j
++) {
209 struct sk_buff
*skb
= rx_queue
->rx_skbuff
[j
];
212 gfar_init_rxbdp(rx_queue
, rxbdp
,
215 skb
= gfar_new_skb(ndev
);
217 netdev_err(ndev
, "Can't allocate RX buffers\n");
218 goto err_rxalloc_fail
;
220 rx_queue
->rx_skbuff
[j
] = skb
;
222 gfar_new_rxbdp(rx_queue
, rxbdp
, skb
);
233 free_skb_resources(priv
);
237 static int gfar_alloc_skb_resources(struct net_device
*ndev
)
242 struct gfar_private
*priv
= netdev_priv(ndev
);
243 struct device
*dev
= &priv
->ofdev
->dev
;
244 struct gfar_priv_tx_q
*tx_queue
= NULL
;
245 struct gfar_priv_rx_q
*rx_queue
= NULL
;
247 priv
->total_tx_ring_size
= 0;
248 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
249 priv
->total_tx_ring_size
+= priv
->tx_queue
[i
]->tx_ring_size
;
251 priv
->total_rx_ring_size
= 0;
252 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
253 priv
->total_rx_ring_size
+= priv
->rx_queue
[i
]->rx_ring_size
;
255 /* Allocate memory for the buffer descriptors */
256 vaddr
= dma_alloc_coherent(dev
,
257 sizeof(struct txbd8
) * priv
->total_tx_ring_size
+
258 sizeof(struct rxbd8
) * priv
->total_rx_ring_size
,
261 netif_err(priv
, ifup
, ndev
,
262 "Could not allocate buffer descriptors!\n");
266 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
267 tx_queue
= priv
->tx_queue
[i
];
268 tx_queue
->tx_bd_base
= vaddr
;
269 tx_queue
->tx_bd_dma_base
= addr
;
270 tx_queue
->dev
= ndev
;
271 /* enet DMA only understands physical addresses */
272 addr
+= sizeof(struct txbd8
) *tx_queue
->tx_ring_size
;
273 vaddr
+= sizeof(struct txbd8
) *tx_queue
->tx_ring_size
;
276 /* Start the rx descriptor ring where the tx ring leaves off */
277 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
278 rx_queue
= priv
->rx_queue
[i
];
279 rx_queue
->rx_bd_base
= vaddr
;
280 rx_queue
->rx_bd_dma_base
= addr
;
281 rx_queue
->dev
= ndev
;
282 addr
+= sizeof (struct rxbd8
) * rx_queue
->rx_ring_size
;
283 vaddr
+= sizeof (struct rxbd8
) * rx_queue
->rx_ring_size
;
286 /* Setup the skbuff rings */
287 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
288 tx_queue
= priv
->tx_queue
[i
];
289 tx_queue
->tx_skbuff
= kmalloc(sizeof(*tx_queue
->tx_skbuff
) *
290 tx_queue
->tx_ring_size
, GFP_KERNEL
);
291 if (!tx_queue
->tx_skbuff
) {
292 netif_err(priv
, ifup
, ndev
,
293 "Could not allocate tx_skbuff\n");
297 for (k
= 0; k
< tx_queue
->tx_ring_size
; k
++)
298 tx_queue
->tx_skbuff
[k
] = NULL
;
301 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
302 rx_queue
= priv
->rx_queue
[i
];
303 rx_queue
->rx_skbuff
= kmalloc(sizeof(*rx_queue
->rx_skbuff
) *
304 rx_queue
->rx_ring_size
, GFP_KERNEL
);
306 if (!rx_queue
->rx_skbuff
) {
307 netif_err(priv
, ifup
, ndev
,
308 "Could not allocate rx_skbuff\n");
312 for (j
= 0; j
< rx_queue
->rx_ring_size
; j
++)
313 rx_queue
->rx_skbuff
[j
] = NULL
;
316 if (gfar_init_bds(ndev
))
322 free_skb_resources(priv
);
326 static void gfar_init_tx_rx_base(struct gfar_private
*priv
)
328 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
332 baddr
= ®s
->tbase0
;
333 for(i
= 0; i
< priv
->num_tx_queues
; i
++) {
334 gfar_write(baddr
, priv
->tx_queue
[i
]->tx_bd_dma_base
);
338 baddr
= ®s
->rbase0
;
339 for(i
= 0; i
< priv
->num_rx_queues
; i
++) {
340 gfar_write(baddr
, priv
->rx_queue
[i
]->rx_bd_dma_base
);
345 static void gfar_init_mac(struct net_device
*ndev
)
347 struct gfar_private
*priv
= netdev_priv(ndev
);
348 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
353 /* write the tx/rx base registers */
354 gfar_init_tx_rx_base(priv
);
356 /* Configure the coalescing support */
357 gfar_configure_coalescing(priv
, 0xFF, 0xFF);
359 if (priv
->rx_filer_enable
) {
360 rctrl
|= RCTRL_FILREN
;
361 /* Program the RIR0 reg with the required distribution */
362 gfar_write(®s
->rir0
, DEFAULT_RIR0
);
365 if (ndev
->features
& NETIF_F_RXCSUM
)
366 rctrl
|= RCTRL_CHECKSUMMING
;
368 if (priv
->extended_hash
) {
369 rctrl
|= RCTRL_EXTHASH
;
371 gfar_clear_exact_match(ndev
);
376 rctrl
&= ~RCTRL_PAL_MASK
;
377 rctrl
|= RCTRL_PADDING(priv
->padding
);
380 /* Insert receive time stamps into padding alignment bytes */
381 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
) {
382 rctrl
&= ~RCTRL_PAL_MASK
;
383 rctrl
|= RCTRL_PADDING(8);
387 /* Enable HW time stamping if requested from user space */
388 if (priv
->hwts_rx_en
)
389 rctrl
|= RCTRL_PRSDEP_INIT
| RCTRL_TS_ENABLE
;
391 /* keep vlan related bits if it's enabled */
392 if (ndev
->features
& NETIF_F_HW_VLAN_TX
)
393 rctrl
|= RCTRL_VLEX
| RCTRL_PRSDEP_INIT
;
395 if (ndev
->features
& NETIF_F_HW_VLAN_RX
)
396 tctrl
|= TCTRL_VLINS
;
398 /* Init rctrl based on our settings */
399 gfar_write(®s
->rctrl
, rctrl
);
401 if (ndev
->features
& NETIF_F_IP_CSUM
)
402 tctrl
|= TCTRL_INIT_CSUM
;
404 tctrl
|= TCTRL_TXSCHED_PRIO
;
406 gfar_write(®s
->tctrl
, tctrl
);
408 /* Set the extraction length and index */
409 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
410 ATTRELI_EI(priv
->rx_stash_index
);
412 gfar_write(®s
->attreli
, attrs
);
414 /* Start with defaults, and add stashing or locking
415 * depending on the approprate variables */
416 attrs
= ATTR_INIT_SETTINGS
;
418 if (priv
->bd_stash_en
)
419 attrs
|= ATTR_BDSTASH
;
421 if (priv
->rx_stash_size
!= 0)
422 attrs
|= ATTR_BUFSTASH
;
424 gfar_write(®s
->attr
, attrs
);
426 gfar_write(®s
->fifo_tx_thr
, priv
->fifo_threshold
);
427 gfar_write(®s
->fifo_tx_starve
, priv
->fifo_starve
);
428 gfar_write(®s
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
431 static struct net_device_stats
*gfar_get_stats(struct net_device
*dev
)
433 struct gfar_private
*priv
= netdev_priv(dev
);
434 unsigned long rx_packets
= 0, rx_bytes
= 0, rx_dropped
= 0;
435 unsigned long tx_packets
= 0, tx_bytes
= 0;
438 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
439 rx_packets
+= priv
->rx_queue
[i
]->stats
.rx_packets
;
440 rx_bytes
+= priv
->rx_queue
[i
]->stats
.rx_bytes
;
441 rx_dropped
+= priv
->rx_queue
[i
]->stats
.rx_dropped
;
444 dev
->stats
.rx_packets
= rx_packets
;
445 dev
->stats
.rx_bytes
= rx_bytes
;
446 dev
->stats
.rx_dropped
= rx_dropped
;
448 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
449 tx_bytes
+= priv
->tx_queue
[i
]->stats
.tx_bytes
;
450 tx_packets
+= priv
->tx_queue
[i
]->stats
.tx_packets
;
453 dev
->stats
.tx_bytes
= tx_bytes
;
454 dev
->stats
.tx_packets
= tx_packets
;
459 static const struct net_device_ops gfar_netdev_ops
= {
460 .ndo_open
= gfar_enet_open
,
461 .ndo_start_xmit
= gfar_start_xmit
,
462 .ndo_stop
= gfar_close
,
463 .ndo_change_mtu
= gfar_change_mtu
,
464 .ndo_set_features
= gfar_set_features
,
465 .ndo_set_multicast_list
= gfar_set_multi
,
466 .ndo_tx_timeout
= gfar_timeout
,
467 .ndo_do_ioctl
= gfar_ioctl
,
468 .ndo_get_stats
= gfar_get_stats
,
469 .ndo_set_mac_address
= eth_mac_addr
,
470 .ndo_validate_addr
= eth_validate_addr
,
471 #ifdef CONFIG_NET_POLL_CONTROLLER
472 .ndo_poll_controller
= gfar_netpoll
,
476 void lock_rx_qs(struct gfar_private
*priv
)
480 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
481 spin_lock(&priv
->rx_queue
[i
]->rxlock
);
484 void lock_tx_qs(struct gfar_private
*priv
)
488 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
489 spin_lock(&priv
->tx_queue
[i
]->txlock
);
492 void unlock_rx_qs(struct gfar_private
*priv
)
496 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
497 spin_unlock(&priv
->rx_queue
[i
]->rxlock
);
500 void unlock_tx_qs(struct gfar_private
*priv
)
504 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
505 spin_unlock(&priv
->tx_queue
[i
]->txlock
);
508 static bool gfar_is_vlan_on(struct gfar_private
*priv
)
510 return (priv
->ndev
->features
& NETIF_F_HW_VLAN_RX
) ||
511 (priv
->ndev
->features
& NETIF_F_HW_VLAN_TX
);
514 /* Returns 1 if incoming frames use an FCB */
515 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
517 return gfar_is_vlan_on(priv
) ||
518 (priv
->ndev
->features
& NETIF_F_RXCSUM
) ||
519 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
);
522 static void free_tx_pointers(struct gfar_private
*priv
)
526 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
527 kfree(priv
->tx_queue
[i
]);
530 static void free_rx_pointers(struct gfar_private
*priv
)
534 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
535 kfree(priv
->rx_queue
[i
]);
538 static void unmap_group_regs(struct gfar_private
*priv
)
542 for (i
= 0; i
< MAXGROUPS
; i
++)
543 if (priv
->gfargrp
[i
].regs
)
544 iounmap(priv
->gfargrp
[i
].regs
);
547 static void disable_napi(struct gfar_private
*priv
)
551 for (i
= 0; i
< priv
->num_grps
; i
++)
552 napi_disable(&priv
->gfargrp
[i
].napi
);
555 static void enable_napi(struct gfar_private
*priv
)
559 for (i
= 0; i
< priv
->num_grps
; i
++)
560 napi_enable(&priv
->gfargrp
[i
].napi
);
563 static int gfar_parse_group(struct device_node
*np
,
564 struct gfar_private
*priv
, const char *model
)
568 priv
->gfargrp
[priv
->num_grps
].regs
= of_iomap(np
, 0);
569 if (!priv
->gfargrp
[priv
->num_grps
].regs
)
572 priv
->gfargrp
[priv
->num_grps
].interruptTransmit
=
573 irq_of_parse_and_map(np
, 0);
575 /* If we aren't the FEC we have multiple interrupts */
576 if (model
&& strcasecmp(model
, "FEC")) {
577 priv
->gfargrp
[priv
->num_grps
].interruptReceive
=
578 irq_of_parse_and_map(np
, 1);
579 priv
->gfargrp
[priv
->num_grps
].interruptError
=
580 irq_of_parse_and_map(np
,2);
581 if (priv
->gfargrp
[priv
->num_grps
].interruptTransmit
== NO_IRQ
||
582 priv
->gfargrp
[priv
->num_grps
].interruptReceive
== NO_IRQ
||
583 priv
->gfargrp
[priv
->num_grps
].interruptError
== NO_IRQ
)
587 priv
->gfargrp
[priv
->num_grps
].grp_id
= priv
->num_grps
;
588 priv
->gfargrp
[priv
->num_grps
].priv
= priv
;
589 spin_lock_init(&priv
->gfargrp
[priv
->num_grps
].grplock
);
590 if(priv
->mode
== MQ_MG_MODE
) {
591 queue_mask
= (u32
*)of_get_property(np
,
592 "fsl,rx-bit-map", NULL
);
593 priv
->gfargrp
[priv
->num_grps
].rx_bit_map
=
594 queue_mask
? *queue_mask
:(DEFAULT_MAPPING
>> priv
->num_grps
);
595 queue_mask
= (u32
*)of_get_property(np
,
596 "fsl,tx-bit-map", NULL
);
597 priv
->gfargrp
[priv
->num_grps
].tx_bit_map
=
598 queue_mask
? *queue_mask
: (DEFAULT_MAPPING
>> priv
->num_grps
);
600 priv
->gfargrp
[priv
->num_grps
].rx_bit_map
= 0xFF;
601 priv
->gfargrp
[priv
->num_grps
].tx_bit_map
= 0xFF;
608 static int gfar_of_init(struct platform_device
*ofdev
, struct net_device
**pdev
)
612 const void *mac_addr
;
614 struct net_device
*dev
= NULL
;
615 struct gfar_private
*priv
= NULL
;
616 struct device_node
*np
= ofdev
->dev
.of_node
;
617 struct device_node
*child
= NULL
;
619 const u32
*stash_len
;
620 const u32
*stash_idx
;
621 unsigned int num_tx_qs
, num_rx_qs
;
622 u32
*tx_queues
, *rx_queues
;
624 if (!np
|| !of_device_is_available(np
))
627 /* parse the num of tx and rx queues */
628 tx_queues
= (u32
*)of_get_property(np
, "fsl,num_tx_queues", NULL
);
629 num_tx_qs
= tx_queues
? *tx_queues
: 1;
631 if (num_tx_qs
> MAX_TX_QS
) {
632 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
633 num_tx_qs
, MAX_TX_QS
);
634 pr_err("Cannot do alloc_etherdev, aborting\n");
638 rx_queues
= (u32
*)of_get_property(np
, "fsl,num_rx_queues", NULL
);
639 num_rx_qs
= rx_queues
? *rx_queues
: 1;
641 if (num_rx_qs
> MAX_RX_QS
) {
642 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
643 num_rx_qs
, MAX_RX_QS
);
644 pr_err("Cannot do alloc_etherdev, aborting\n");
648 *pdev
= alloc_etherdev_mq(sizeof(*priv
), num_tx_qs
);
653 priv
= netdev_priv(dev
);
654 priv
->node
= ofdev
->dev
.of_node
;
657 priv
->num_tx_queues
= num_tx_qs
;
658 netif_set_real_num_rx_queues(dev
, num_rx_qs
);
659 priv
->num_rx_queues
= num_rx_qs
;
660 priv
->num_grps
= 0x0;
662 /* Init Rx queue filer rule set linked list*/
663 INIT_LIST_HEAD(&priv
->rx_list
.list
);
664 priv
->rx_list
.count
= 0;
665 mutex_init(&priv
->rx_queue_access
);
667 model
= of_get_property(np
, "model", NULL
);
669 for (i
= 0; i
< MAXGROUPS
; i
++)
670 priv
->gfargrp
[i
].regs
= NULL
;
672 /* Parse and initialize group specific information */
673 if (of_device_is_compatible(np
, "fsl,etsec2")) {
674 priv
->mode
= MQ_MG_MODE
;
675 for_each_child_of_node(np
, child
) {
676 err
= gfar_parse_group(child
, priv
, model
);
681 priv
->mode
= SQ_SG_MODE
;
682 err
= gfar_parse_group(np
, priv
, model
);
687 for (i
= 0; i
< priv
->num_tx_queues
; i
++)
688 priv
->tx_queue
[i
] = NULL
;
689 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
690 priv
->rx_queue
[i
] = NULL
;
692 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
693 priv
->tx_queue
[i
] = kzalloc(sizeof(struct gfar_priv_tx_q
),
695 if (!priv
->tx_queue
[i
]) {
697 goto tx_alloc_failed
;
699 priv
->tx_queue
[i
]->tx_skbuff
= NULL
;
700 priv
->tx_queue
[i
]->qindex
= i
;
701 priv
->tx_queue
[i
]->dev
= dev
;
702 spin_lock_init(&(priv
->tx_queue
[i
]->txlock
));
705 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
706 priv
->rx_queue
[i
] = kzalloc(sizeof(struct gfar_priv_rx_q
),
708 if (!priv
->rx_queue
[i
]) {
710 goto rx_alloc_failed
;
712 priv
->rx_queue
[i
]->rx_skbuff
= NULL
;
713 priv
->rx_queue
[i
]->qindex
= i
;
714 priv
->rx_queue
[i
]->dev
= dev
;
715 spin_lock_init(&(priv
->rx_queue
[i
]->rxlock
));
719 stash
= of_get_property(np
, "bd-stash", NULL
);
722 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BD_STASHING
;
723 priv
->bd_stash_en
= 1;
726 stash_len
= of_get_property(np
, "rx-stash-len", NULL
);
729 priv
->rx_stash_size
= *stash_len
;
731 stash_idx
= of_get_property(np
, "rx-stash-idx", NULL
);
734 priv
->rx_stash_index
= *stash_idx
;
736 if (stash_len
|| stash_idx
)
737 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_BUF_STASHING
;
739 mac_addr
= of_get_mac_address(np
);
741 memcpy(dev
->dev_addr
, mac_addr
, MAC_ADDR_LEN
);
743 if (model
&& !strcasecmp(model
, "TSEC"))
745 FSL_GIANFAR_DEV_HAS_GIGABIT
|
746 FSL_GIANFAR_DEV_HAS_COALESCE
|
747 FSL_GIANFAR_DEV_HAS_RMON
|
748 FSL_GIANFAR_DEV_HAS_MULTI_INTR
;
749 if (model
&& !strcasecmp(model
, "eTSEC"))
751 FSL_GIANFAR_DEV_HAS_GIGABIT
|
752 FSL_GIANFAR_DEV_HAS_COALESCE
|
753 FSL_GIANFAR_DEV_HAS_RMON
|
754 FSL_GIANFAR_DEV_HAS_MULTI_INTR
|
755 FSL_GIANFAR_DEV_HAS_PADDING
|
756 FSL_GIANFAR_DEV_HAS_CSUM
|
757 FSL_GIANFAR_DEV_HAS_VLAN
|
758 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
|
759 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
|
760 FSL_GIANFAR_DEV_HAS_TIMER
;
762 ctype
= of_get_property(np
, "phy-connection-type", NULL
);
764 /* We only care about rgmii-id. The rest are autodetected */
765 if (ctype
&& !strcmp(ctype
, "rgmii-id"))
766 priv
->interface
= PHY_INTERFACE_MODE_RGMII_ID
;
768 priv
->interface
= PHY_INTERFACE_MODE_MII
;
770 if (of_get_property(np
, "fsl,magic-packet", NULL
))
771 priv
->device_flags
|= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
;
773 priv
->phy_node
= of_parse_phandle(np
, "phy-handle", 0);
775 /* Find the TBI PHY. If it's not there, we don't support SGMII */
776 priv
->tbi_node
= of_parse_phandle(np
, "tbi-handle", 0);
781 free_rx_pointers(priv
);
783 free_tx_pointers(priv
);
785 unmap_group_regs(priv
);
790 static int gfar_hwtstamp_ioctl(struct net_device
*netdev
,
791 struct ifreq
*ifr
, int cmd
)
793 struct hwtstamp_config config
;
794 struct gfar_private
*priv
= netdev_priv(netdev
);
796 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
799 /* reserved for future extensions */
803 switch (config
.tx_type
) {
804 case HWTSTAMP_TX_OFF
:
805 priv
->hwts_tx_en
= 0;
808 if (!(priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
))
810 priv
->hwts_tx_en
= 1;
816 switch (config
.rx_filter
) {
817 case HWTSTAMP_FILTER_NONE
:
818 if (priv
->hwts_rx_en
) {
820 priv
->hwts_rx_en
= 0;
821 startup_gfar(netdev
);
825 if (!(priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
))
827 if (!priv
->hwts_rx_en
) {
829 priv
->hwts_rx_en
= 1;
830 startup_gfar(netdev
);
832 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
836 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
840 /* Ioctl MII Interface */
841 static int gfar_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
843 struct gfar_private
*priv
= netdev_priv(dev
);
845 if (!netif_running(dev
))
848 if (cmd
== SIOCSHWTSTAMP
)
849 return gfar_hwtstamp_ioctl(dev
, rq
, cmd
);
854 return phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
857 static unsigned int reverse_bitmap(unsigned int bit_map
, unsigned int max_qs
)
859 unsigned int new_bit_map
= 0x0;
860 int mask
= 0x1 << (max_qs
- 1), i
;
861 for (i
= 0; i
< max_qs
; i
++) {
863 new_bit_map
= new_bit_map
+ (1 << i
);
869 static u32
cluster_entry_per_class(struct gfar_private
*priv
, u32 rqfar
,
872 u32 rqfpr
= FPR_FILER_MASK
;
876 rqfcr
= RQFCR_CLE
| RQFCR_PID_MASK
| RQFCR_CMP_EXACT
;
877 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
878 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
879 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
882 rqfcr
= RQFCR_CMP_NOMATCH
;
883 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
884 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
885 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
888 rqfcr
= RQFCR_CMP_EXACT
| RQFCR_PID_PARSE
| RQFCR_CLE
| RQFCR_AND
;
890 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
891 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
892 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
895 rqfcr
= RQFCR_CMP_EXACT
| RQFCR_PID_MASK
| RQFCR_AND
;
897 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
898 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
899 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
904 static void gfar_init_filer_table(struct gfar_private
*priv
)
907 u32 rqfar
= MAX_FILER_IDX
;
909 u32 rqfpr
= FPR_FILER_MASK
;
912 rqfcr
= RQFCR_CMP_MATCH
;
913 priv
->ftp_rqfcr
[rqfar
] = rqfcr
;
914 priv
->ftp_rqfpr
[rqfar
] = rqfpr
;
915 gfar_write_filer(priv
, rqfar
, rqfcr
, rqfpr
);
917 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
);
918 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
| RQFPR_UDP
);
919 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV6
| RQFPR_TCP
);
920 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
);
921 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
| RQFPR_UDP
);
922 rqfar
= cluster_entry_per_class(priv
, rqfar
, RQFPR_IPV4
| RQFPR_TCP
);
924 /* cur_filer_idx indicated the first non-masked rule */
925 priv
->cur_filer_idx
= rqfar
;
927 /* Rest are masked rules */
928 rqfcr
= RQFCR_CMP_NOMATCH
;
929 for (i
= 0; i
< rqfar
; i
++) {
930 priv
->ftp_rqfcr
[i
] = rqfcr
;
931 priv
->ftp_rqfpr
[i
] = rqfpr
;
932 gfar_write_filer(priv
, i
, rqfcr
, rqfpr
);
936 static void gfar_detect_errata(struct gfar_private
*priv
)
938 struct device
*dev
= &priv
->ofdev
->dev
;
939 unsigned int pvr
= mfspr(SPRN_PVR
);
940 unsigned int svr
= mfspr(SPRN_SVR
);
941 unsigned int mod
= (svr
>> 16) & 0xfff6; /* w/o E suffix */
942 unsigned int rev
= svr
& 0xffff;
944 /* MPC8313 Rev 2.0 and higher; All MPC837x */
945 if ((pvr
== 0x80850010 && mod
== 0x80b0 && rev
>= 0x0020) ||
946 (pvr
== 0x80861010 && (mod
& 0xfff9) == 0x80c0))
947 priv
->errata
|= GFAR_ERRATA_74
;
949 /* MPC8313 and MPC837x all rev */
950 if ((pvr
== 0x80850010 && mod
== 0x80b0) ||
951 (pvr
== 0x80861010 && (mod
& 0xfff9) == 0x80c0))
952 priv
->errata
|= GFAR_ERRATA_76
;
954 /* MPC8313 and MPC837x all rev */
955 if ((pvr
== 0x80850010 && mod
== 0x80b0) ||
956 (pvr
== 0x80861010 && (mod
& 0xfff9) == 0x80c0))
957 priv
->errata
|= GFAR_ERRATA_A002
;
959 /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
960 if ((pvr
== 0x80850010 && mod
== 0x80b0 && rev
< 0x0020) ||
961 (pvr
== 0x80210020 && mod
== 0x8030 && rev
== 0x0020))
962 priv
->errata
|= GFAR_ERRATA_12
;
965 dev_info(dev
, "enabled errata workarounds, flags: 0x%x\n",
969 /* Set up the ethernet device structure, private data,
970 * and anything else we need before we start */
971 static int gfar_probe(struct platform_device
*ofdev
)
974 struct net_device
*dev
= NULL
;
975 struct gfar_private
*priv
= NULL
;
976 struct gfar __iomem
*regs
= NULL
;
977 int err
= 0, i
, grp_idx
= 0;
979 u32 rstat
= 0, tstat
= 0, rqueue
= 0, tqueue
= 0;
983 err
= gfar_of_init(ofdev
, &dev
);
988 priv
= netdev_priv(dev
);
991 priv
->node
= ofdev
->dev
.of_node
;
992 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
994 spin_lock_init(&priv
->bflock
);
995 INIT_WORK(&priv
->reset_task
, gfar_reset_task
);
997 dev_set_drvdata(&ofdev
->dev
, priv
);
998 regs
= priv
->gfargrp
[0].regs
;
1000 gfar_detect_errata(priv
);
1002 /* Stop the DMA engine now, in case it was running before */
1003 /* (The firmware could have used it, and left it running). */
1006 /* Reset MAC layer */
1007 gfar_write(®s
->maccfg1
, MACCFG1_SOFT_RESET
);
1009 /* We need to delay at least 3 TX clocks */
1012 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
1013 gfar_write(®s
->maccfg1
, tempval
);
1015 /* Initialize MACCFG2. */
1016 tempval
= MACCFG2_INIT_SETTINGS
;
1017 if (gfar_has_errata(priv
, GFAR_ERRATA_74
))
1018 tempval
|= MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
;
1019 gfar_write(®s
->maccfg2
, tempval
);
1021 /* Initialize ECNTRL */
1022 gfar_write(®s
->ecntrl
, ECNTRL_INIT_SETTINGS
);
1024 /* Set the dev->base_addr to the gfar reg region */
1025 dev
->base_addr
= (unsigned long) regs
;
1027 SET_NETDEV_DEV(dev
, &ofdev
->dev
);
1029 /* Fill in the dev structure */
1030 dev
->watchdog_timeo
= TX_TIMEOUT
;
1032 dev
->netdev_ops
= &gfar_netdev_ops
;
1033 dev
->ethtool_ops
= &gfar_ethtool_ops
;
1035 /* Register for napi ...We are registering NAPI for each grp */
1036 for (i
= 0; i
< priv
->num_grps
; i
++)
1037 netif_napi_add(dev
, &priv
->gfargrp
[i
].napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
1039 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
1040 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_SG
|
1042 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
|
1043 NETIF_F_RXCSUM
| NETIF_F_HIGHDMA
;
1046 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
1047 dev
->hw_features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
1048 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
1051 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
1052 priv
->extended_hash
= 1;
1053 priv
->hash_width
= 9;
1055 priv
->hash_regs
[0] = ®s
->igaddr0
;
1056 priv
->hash_regs
[1] = ®s
->igaddr1
;
1057 priv
->hash_regs
[2] = ®s
->igaddr2
;
1058 priv
->hash_regs
[3] = ®s
->igaddr3
;
1059 priv
->hash_regs
[4] = ®s
->igaddr4
;
1060 priv
->hash_regs
[5] = ®s
->igaddr5
;
1061 priv
->hash_regs
[6] = ®s
->igaddr6
;
1062 priv
->hash_regs
[7] = ®s
->igaddr7
;
1063 priv
->hash_regs
[8] = ®s
->gaddr0
;
1064 priv
->hash_regs
[9] = ®s
->gaddr1
;
1065 priv
->hash_regs
[10] = ®s
->gaddr2
;
1066 priv
->hash_regs
[11] = ®s
->gaddr3
;
1067 priv
->hash_regs
[12] = ®s
->gaddr4
;
1068 priv
->hash_regs
[13] = ®s
->gaddr5
;
1069 priv
->hash_regs
[14] = ®s
->gaddr6
;
1070 priv
->hash_regs
[15] = ®s
->gaddr7
;
1073 priv
->extended_hash
= 0;
1074 priv
->hash_width
= 8;
1076 priv
->hash_regs
[0] = ®s
->gaddr0
;
1077 priv
->hash_regs
[1] = ®s
->gaddr1
;
1078 priv
->hash_regs
[2] = ®s
->gaddr2
;
1079 priv
->hash_regs
[3] = ®s
->gaddr3
;
1080 priv
->hash_regs
[4] = ®s
->gaddr4
;
1081 priv
->hash_regs
[5] = ®s
->gaddr5
;
1082 priv
->hash_regs
[6] = ®s
->gaddr6
;
1083 priv
->hash_regs
[7] = ®s
->gaddr7
;
1086 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
1087 priv
->padding
= DEFAULT_PADDING
;
1091 if (dev
->features
& NETIF_F_IP_CSUM
||
1092 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_TIMER
)
1093 dev
->hard_header_len
+= GMAC_FCB_LEN
;
1095 /* Program the isrg regs only if number of grps > 1 */
1096 if (priv
->num_grps
> 1) {
1097 baddr
= ®s
->isrg0
;
1098 for (i
= 0; i
< priv
->num_grps
; i
++) {
1099 isrg
|= (priv
->gfargrp
[i
].rx_bit_map
<< ISRG_SHIFT_RX
);
1100 isrg
|= (priv
->gfargrp
[i
].tx_bit_map
<< ISRG_SHIFT_TX
);
1101 gfar_write(baddr
, isrg
);
1107 /* Need to reverse the bit maps as bit_map's MSB is q0
1108 * but, for_each_set_bit parses from right to left, which
1109 * basically reverses the queue numbers */
1110 for (i
= 0; i
< priv
->num_grps
; i
++) {
1111 priv
->gfargrp
[i
].tx_bit_map
= reverse_bitmap(
1112 priv
->gfargrp
[i
].tx_bit_map
, MAX_TX_QS
);
1113 priv
->gfargrp
[i
].rx_bit_map
= reverse_bitmap(
1114 priv
->gfargrp
[i
].rx_bit_map
, MAX_RX_QS
);
1117 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1118 * also assign queues to groups */
1119 for (grp_idx
= 0; grp_idx
< priv
->num_grps
; grp_idx
++) {
1120 priv
->gfargrp
[grp_idx
].num_rx_queues
= 0x0;
1121 for_each_set_bit(i
, &priv
->gfargrp
[grp_idx
].rx_bit_map
,
1122 priv
->num_rx_queues
) {
1123 priv
->gfargrp
[grp_idx
].num_rx_queues
++;
1124 priv
->rx_queue
[i
]->grp
= &priv
->gfargrp
[grp_idx
];
1125 rstat
= rstat
| (RSTAT_CLEAR_RHALT
>> i
);
1126 rqueue
= rqueue
| ((RQUEUE_EN0
| RQUEUE_EX0
) >> i
);
1128 priv
->gfargrp
[grp_idx
].num_tx_queues
= 0x0;
1129 for_each_set_bit(i
, &priv
->gfargrp
[grp_idx
].tx_bit_map
,
1130 priv
->num_tx_queues
) {
1131 priv
->gfargrp
[grp_idx
].num_tx_queues
++;
1132 priv
->tx_queue
[i
]->grp
= &priv
->gfargrp
[grp_idx
];
1133 tstat
= tstat
| (TSTAT_CLEAR_THALT
>> i
);
1134 tqueue
= tqueue
| (TQUEUE_EN0
>> i
);
1136 priv
->gfargrp
[grp_idx
].rstat
= rstat
;
1137 priv
->gfargrp
[grp_idx
].tstat
= tstat
;
1141 gfar_write(®s
->rqueue
, rqueue
);
1142 gfar_write(®s
->tqueue
, tqueue
);
1144 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
1146 /* Initializing some of the rx/tx queue level parameters */
1147 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
1148 priv
->tx_queue
[i
]->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
1149 priv
->tx_queue
[i
]->num_txbdfree
= DEFAULT_TX_RING_SIZE
;
1150 priv
->tx_queue
[i
]->txcoalescing
= DEFAULT_TX_COALESCE
;
1151 priv
->tx_queue
[i
]->txic
= DEFAULT_TXIC
;
1154 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
1155 priv
->rx_queue
[i
]->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
1156 priv
->rx_queue
[i
]->rxcoalescing
= DEFAULT_RX_COALESCE
;
1157 priv
->rx_queue
[i
]->rxic
= DEFAULT_RXIC
;
1160 /* always enable rx filer*/
1161 priv
->rx_filer_enable
= 1;
1162 /* Enable most messages by default */
1163 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
1165 /* Carrier starts down, phylib will bring it up */
1166 netif_carrier_off(dev
);
1168 err
= register_netdev(dev
);
1171 pr_err("%s: Cannot register net device, aborting\n", dev
->name
);
1175 device_init_wakeup(&dev
->dev
,
1176 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1178 /* fill out IRQ number and name fields */
1179 len_devname
= strlen(dev
->name
);
1180 for (i
= 0; i
< priv
->num_grps
; i
++) {
1181 strncpy(&priv
->gfargrp
[i
].int_name_tx
[0], dev
->name
,
1183 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1184 strncpy(&priv
->gfargrp
[i
].int_name_tx
[len_devname
],
1185 "_g", sizeof("_g"));
1186 priv
->gfargrp
[i
].int_name_tx
[
1187 strlen(priv
->gfargrp
[i
].int_name_tx
)] = i
+48;
1188 strncpy(&priv
->gfargrp
[i
].int_name_tx
[strlen(
1189 priv
->gfargrp
[i
].int_name_tx
)],
1190 "_tx", sizeof("_tx") + 1);
1192 strncpy(&priv
->gfargrp
[i
].int_name_rx
[0], dev
->name
,
1194 strncpy(&priv
->gfargrp
[i
].int_name_rx
[len_devname
],
1195 "_g", sizeof("_g"));
1196 priv
->gfargrp
[i
].int_name_rx
[
1197 strlen(priv
->gfargrp
[i
].int_name_rx
)] = i
+48;
1198 strncpy(&priv
->gfargrp
[i
].int_name_rx
[strlen(
1199 priv
->gfargrp
[i
].int_name_rx
)],
1200 "_rx", sizeof("_rx") + 1);
1202 strncpy(&priv
->gfargrp
[i
].int_name_er
[0], dev
->name
,
1204 strncpy(&priv
->gfargrp
[i
].int_name_er
[len_devname
],
1205 "_g", sizeof("_g"));
1206 priv
->gfargrp
[i
].int_name_er
[strlen(
1207 priv
->gfargrp
[i
].int_name_er
)] = i
+48;
1208 strncpy(&priv
->gfargrp
[i
].int_name_er
[strlen(\
1209 priv
->gfargrp
[i
].int_name_er
)],
1210 "_er", sizeof("_er") + 1);
1212 priv
->gfargrp
[i
].int_name_tx
[len_devname
] = '\0';
1215 /* Initialize the filer table */
1216 gfar_init_filer_table(priv
);
1218 /* Create all the sysfs files */
1219 gfar_init_sysfs(dev
);
1221 /* Print out the device info */
1222 netdev_info(dev
, "mac: %pM\n", dev
->dev_addr
);
1224 /* Even more device info helps when determining which kernel */
1225 /* provided which set of benchmarks. */
1226 netdev_info(dev
, "Running with NAPI enabled\n");
1227 for (i
= 0; i
< priv
->num_rx_queues
; i
++)
1228 netdev_info(dev
, "RX BD ring size for Q[%d]: %d\n",
1229 i
, priv
->rx_queue
[i
]->rx_ring_size
);
1230 for(i
= 0; i
< priv
->num_tx_queues
; i
++)
1231 netdev_info(dev
, "TX BD ring size for Q[%d]: %d\n",
1232 i
, priv
->tx_queue
[i
]->tx_ring_size
);
1237 unmap_group_regs(priv
);
1238 free_tx_pointers(priv
);
1239 free_rx_pointers(priv
);
1241 of_node_put(priv
->phy_node
);
1243 of_node_put(priv
->tbi_node
);
1248 static int gfar_remove(struct platform_device
*ofdev
)
1250 struct gfar_private
*priv
= dev_get_drvdata(&ofdev
->dev
);
1253 of_node_put(priv
->phy_node
);
1255 of_node_put(priv
->tbi_node
);
1257 dev_set_drvdata(&ofdev
->dev
, NULL
);
1259 unregister_netdev(priv
->ndev
);
1260 unmap_group_regs(priv
);
1261 free_netdev(priv
->ndev
);
1268 static int gfar_suspend(struct device
*dev
)
1270 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1271 struct net_device
*ndev
= priv
->ndev
;
1272 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1273 unsigned long flags
;
1276 int magic_packet
= priv
->wol_en
&&
1277 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1279 netif_device_detach(ndev
);
1281 if (netif_running(ndev
)) {
1283 local_irq_save(flags
);
1287 gfar_halt_nodisable(ndev
);
1289 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1290 tempval
= gfar_read(®s
->maccfg1
);
1292 tempval
&= ~MACCFG1_TX_EN
;
1295 tempval
&= ~MACCFG1_RX_EN
;
1297 gfar_write(®s
->maccfg1
, tempval
);
1301 local_irq_restore(flags
);
1306 /* Enable interrupt on Magic Packet */
1307 gfar_write(®s
->imask
, IMASK_MAG
);
1309 /* Enable Magic Packet mode */
1310 tempval
= gfar_read(®s
->maccfg2
);
1311 tempval
|= MACCFG2_MPEN
;
1312 gfar_write(®s
->maccfg2
, tempval
);
1314 phy_stop(priv
->phydev
);
1321 static int gfar_resume(struct device
*dev
)
1323 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1324 struct net_device
*ndev
= priv
->ndev
;
1325 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1326 unsigned long flags
;
1328 int magic_packet
= priv
->wol_en
&&
1329 (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
1331 if (!netif_running(ndev
)) {
1332 netif_device_attach(ndev
);
1336 if (!magic_packet
&& priv
->phydev
)
1337 phy_start(priv
->phydev
);
1339 /* Disable Magic Packet mode, in case something
1342 local_irq_save(flags
);
1346 tempval
= gfar_read(®s
->maccfg2
);
1347 tempval
&= ~MACCFG2_MPEN
;
1348 gfar_write(®s
->maccfg2
, tempval
);
1354 local_irq_restore(flags
);
1356 netif_device_attach(ndev
);
1363 static int gfar_restore(struct device
*dev
)
1365 struct gfar_private
*priv
= dev_get_drvdata(dev
);
1366 struct net_device
*ndev
= priv
->ndev
;
1368 if (!netif_running(ndev
))
1371 gfar_init_bds(ndev
);
1372 init_registers(ndev
);
1373 gfar_set_mac_address(ndev
);
1374 gfar_init_mac(ndev
);
1379 priv
->oldduplex
= -1;
1382 phy_start(priv
->phydev
);
1384 netif_device_attach(ndev
);
1390 static struct dev_pm_ops gfar_pm_ops
= {
1391 .suspend
= gfar_suspend
,
1392 .resume
= gfar_resume
,
1393 .freeze
= gfar_suspend
,
1394 .thaw
= gfar_resume
,
1395 .restore
= gfar_restore
,
1398 #define GFAR_PM_OPS (&gfar_pm_ops)
1402 #define GFAR_PM_OPS NULL
1406 /* Reads the controller's registers to determine what interface
1407 * connects it to the PHY.
1409 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
1411 struct gfar_private
*priv
= netdev_priv(dev
);
1412 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1415 ecntrl
= gfar_read(®s
->ecntrl
);
1417 if (ecntrl
& ECNTRL_SGMII_MODE
)
1418 return PHY_INTERFACE_MODE_SGMII
;
1420 if (ecntrl
& ECNTRL_TBI_MODE
) {
1421 if (ecntrl
& ECNTRL_REDUCED_MODE
)
1422 return PHY_INTERFACE_MODE_RTBI
;
1424 return PHY_INTERFACE_MODE_TBI
;
1427 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
1428 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
1429 return PHY_INTERFACE_MODE_RMII
;
1431 phy_interface_t interface
= priv
->interface
;
1434 * This isn't autodetected right now, so it must
1435 * be set by the device tree or platform code.
1437 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
1438 return PHY_INTERFACE_MODE_RGMII_ID
;
1440 return PHY_INTERFACE_MODE_RGMII
;
1444 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
1445 return PHY_INTERFACE_MODE_GMII
;
1447 return PHY_INTERFACE_MODE_MII
;
1451 /* Initializes driver's PHY state, and attaches to the PHY.
1452 * Returns 0 on success.
1454 static int init_phy(struct net_device
*dev
)
1456 struct gfar_private
*priv
= netdev_priv(dev
);
1457 uint gigabit_support
=
1458 priv
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
1459 SUPPORTED_1000baseT_Full
: 0;
1460 phy_interface_t interface
;
1464 priv
->oldduplex
= -1;
1466 interface
= gfar_get_interface(dev
);
1468 priv
->phydev
= of_phy_connect(dev
, priv
->phy_node
, &adjust_link
, 0,
1471 priv
->phydev
= of_phy_connect_fixed_link(dev
, &adjust_link
,
1473 if (!priv
->phydev
) {
1474 dev_err(&dev
->dev
, "could not attach to PHY\n");
1478 if (interface
== PHY_INTERFACE_MODE_SGMII
)
1479 gfar_configure_serdes(dev
);
1481 /* Remove any features not supported by the controller */
1482 priv
->phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
1483 priv
->phydev
->advertising
= priv
->phydev
->supported
;
1489 * Initialize TBI PHY interface for communicating with the
1490 * SERDES lynx PHY on the chip. We communicate with this PHY
1491 * through the MDIO bus on each controller, treating it as a
1492 * "normal" PHY at the address found in the TBIPA register. We assume
1493 * that the TBIPA register is valid. Either the MDIO bus code will set
1494 * it to a value that doesn't conflict with other PHYs on the bus, or the
1495 * value doesn't matter, as there are no other PHYs on the bus.
1497 static void gfar_configure_serdes(struct net_device
*dev
)
1499 struct gfar_private
*priv
= netdev_priv(dev
);
1500 struct phy_device
*tbiphy
;
1502 if (!priv
->tbi_node
) {
1503 dev_warn(&dev
->dev
, "error: SGMII mode requires that the "
1504 "device tree specify a tbi-handle\n");
1508 tbiphy
= of_phy_find_device(priv
->tbi_node
);
1510 dev_err(&dev
->dev
, "error: Could not get TBI device\n");
1515 * If the link is already up, we must already be ok, and don't need to
1516 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1517 * everything for us? Resetting it takes the link down and requires
1518 * several seconds for it to come back.
1520 if (phy_read(tbiphy
, MII_BMSR
) & BMSR_LSTATUS
)
1523 /* Single clk mode, mii mode off(for serdes communication) */
1524 phy_write(tbiphy
, MII_TBICON
, TBICON_CLK_SELECT
);
1526 phy_write(tbiphy
, MII_ADVERTISE
,
1527 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
1528 ADVERTISE_1000XPSE_ASYM
);
1530 phy_write(tbiphy
, MII_BMCR
, BMCR_ANENABLE
|
1531 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
1534 static void init_registers(struct net_device
*dev
)
1536 struct gfar_private
*priv
= netdev_priv(dev
);
1537 struct gfar __iomem
*regs
= NULL
;
1540 for (i
= 0; i
< priv
->num_grps
; i
++) {
1541 regs
= priv
->gfargrp
[i
].regs
;
1543 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
1545 /* Initialize IMASK */
1546 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1549 regs
= priv
->gfargrp
[0].regs
;
1550 /* Init hash registers to zero */
1551 gfar_write(®s
->igaddr0
, 0);
1552 gfar_write(®s
->igaddr1
, 0);
1553 gfar_write(®s
->igaddr2
, 0);
1554 gfar_write(®s
->igaddr3
, 0);
1555 gfar_write(®s
->igaddr4
, 0);
1556 gfar_write(®s
->igaddr5
, 0);
1557 gfar_write(®s
->igaddr6
, 0);
1558 gfar_write(®s
->igaddr7
, 0);
1560 gfar_write(®s
->gaddr0
, 0);
1561 gfar_write(®s
->gaddr1
, 0);
1562 gfar_write(®s
->gaddr2
, 0);
1563 gfar_write(®s
->gaddr3
, 0);
1564 gfar_write(®s
->gaddr4
, 0);
1565 gfar_write(®s
->gaddr5
, 0);
1566 gfar_write(®s
->gaddr6
, 0);
1567 gfar_write(®s
->gaddr7
, 0);
1569 /* Zero out the rmon mib registers if it has them */
1570 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
1571 memset_io(&(regs
->rmon
), 0, sizeof (struct rmon_mib
));
1573 /* Mask off the CAM interrupts */
1574 gfar_write(®s
->rmon
.cam1
, 0xffffffff);
1575 gfar_write(®s
->rmon
.cam2
, 0xffffffff);
1578 /* Initialize the max receive buffer length */
1579 gfar_write(®s
->mrblr
, priv
->rx_buffer_size
);
1581 /* Initialize the Minimum Frame Length Register */
1582 gfar_write(®s
->minflr
, MINFLR_INIT_SETTINGS
);
1585 static int __gfar_is_rx_idle(struct gfar_private
*priv
)
1590 * Normaly TSEC should not hang on GRS commands, so we should
1591 * actually wait for IEVENT_GRSC flag.
1593 if (likely(!gfar_has_errata(priv
, GFAR_ERRATA_A002
)))
1597 * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1598 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1599 * and the Rx can be safely reset.
1601 res
= gfar_read((void __iomem
*)priv
->gfargrp
[0].regs
+ 0xd1c);
1603 if ((res
& 0xffff) == (res
>> 16))
1609 /* Halt the receive and transmit queues */
1610 static void gfar_halt_nodisable(struct net_device
*dev
)
1612 struct gfar_private
*priv
= netdev_priv(dev
);
1613 struct gfar __iomem
*regs
= NULL
;
1617 for (i
= 0; i
< priv
->num_grps
; i
++) {
1618 regs
= priv
->gfargrp
[i
].regs
;
1619 /* Mask all interrupts */
1620 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1622 /* Clear all interrupts */
1623 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
1626 regs
= priv
->gfargrp
[0].regs
;
1627 /* Stop the DMA, and wait for it to stop */
1628 tempval
= gfar_read(®s
->dmactrl
);
1629 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
1630 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
1633 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
1634 gfar_write(®s
->dmactrl
, tempval
);
1637 ret
= spin_event_timeout(((gfar_read(®s
->ievent
) &
1638 (IEVENT_GRSC
| IEVENT_GTSC
)) ==
1639 (IEVENT_GRSC
| IEVENT_GTSC
)), 1000000, 0);
1640 if (!ret
&& !(gfar_read(®s
->ievent
) & IEVENT_GRSC
))
1641 ret
= __gfar_is_rx_idle(priv
);
1646 /* Halt the receive and transmit queues */
1647 void gfar_halt(struct net_device
*dev
)
1649 struct gfar_private
*priv
= netdev_priv(dev
);
1650 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1653 gfar_halt_nodisable(dev
);
1655 /* Disable Rx and Tx */
1656 tempval
= gfar_read(®s
->maccfg1
);
1657 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
1658 gfar_write(®s
->maccfg1
, tempval
);
1661 static void free_grp_irqs(struct gfar_priv_grp
*grp
)
1663 free_irq(grp
->interruptError
, grp
);
1664 free_irq(grp
->interruptTransmit
, grp
);
1665 free_irq(grp
->interruptReceive
, grp
);
1668 void stop_gfar(struct net_device
*dev
)
1670 struct gfar_private
*priv
= netdev_priv(dev
);
1671 unsigned long flags
;
1674 phy_stop(priv
->phydev
);
1678 local_irq_save(flags
);
1686 local_irq_restore(flags
);
1689 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1690 for (i
= 0; i
< priv
->num_grps
; i
++)
1691 free_grp_irqs(&priv
->gfargrp
[i
]);
1693 for (i
= 0; i
< priv
->num_grps
; i
++)
1694 free_irq(priv
->gfargrp
[i
].interruptTransmit
,
1698 free_skb_resources(priv
);
1701 static void free_skb_tx_queue(struct gfar_priv_tx_q
*tx_queue
)
1703 struct txbd8
*txbdp
;
1704 struct gfar_private
*priv
= netdev_priv(tx_queue
->dev
);
1707 txbdp
= tx_queue
->tx_bd_base
;
1709 for (i
= 0; i
< tx_queue
->tx_ring_size
; i
++) {
1710 if (!tx_queue
->tx_skbuff
[i
])
1713 dma_unmap_single(&priv
->ofdev
->dev
, txbdp
->bufPtr
,
1714 txbdp
->length
, DMA_TO_DEVICE
);
1716 for (j
= 0; j
< skb_shinfo(tx_queue
->tx_skbuff
[i
])->nr_frags
;
1719 dma_unmap_page(&priv
->ofdev
->dev
, txbdp
->bufPtr
,
1720 txbdp
->length
, DMA_TO_DEVICE
);
1723 dev_kfree_skb_any(tx_queue
->tx_skbuff
[i
]);
1724 tx_queue
->tx_skbuff
[i
] = NULL
;
1726 kfree(tx_queue
->tx_skbuff
);
1729 static void free_skb_rx_queue(struct gfar_priv_rx_q
*rx_queue
)
1731 struct rxbd8
*rxbdp
;
1732 struct gfar_private
*priv
= netdev_priv(rx_queue
->dev
);
1735 rxbdp
= rx_queue
->rx_bd_base
;
1737 for (i
= 0; i
< rx_queue
->rx_ring_size
; i
++) {
1738 if (rx_queue
->rx_skbuff
[i
]) {
1739 dma_unmap_single(&priv
->ofdev
->dev
,
1740 rxbdp
->bufPtr
, priv
->rx_buffer_size
,
1742 dev_kfree_skb_any(rx_queue
->rx_skbuff
[i
]);
1743 rx_queue
->rx_skbuff
[i
] = NULL
;
1749 kfree(rx_queue
->rx_skbuff
);
1752 /* If there are any tx skbs or rx skbs still around, free them.
1753 * Then free tx_skbuff and rx_skbuff */
1754 static void free_skb_resources(struct gfar_private
*priv
)
1756 struct gfar_priv_tx_q
*tx_queue
= NULL
;
1757 struct gfar_priv_rx_q
*rx_queue
= NULL
;
1760 /* Go through all the buffer descriptors and free their data buffers */
1761 for (i
= 0; i
< priv
->num_tx_queues
; i
++) {
1762 tx_queue
= priv
->tx_queue
[i
];
1763 if(tx_queue
->tx_skbuff
)
1764 free_skb_tx_queue(tx_queue
);
1767 for (i
= 0; i
< priv
->num_rx_queues
; i
++) {
1768 rx_queue
= priv
->rx_queue
[i
];
1769 if(rx_queue
->rx_skbuff
)
1770 free_skb_rx_queue(rx_queue
);
1773 dma_free_coherent(&priv
->ofdev
->dev
,
1774 sizeof(struct txbd8
) * priv
->total_tx_ring_size
+
1775 sizeof(struct rxbd8
) * priv
->total_rx_ring_size
,
1776 priv
->tx_queue
[0]->tx_bd_base
,
1777 priv
->tx_queue
[0]->tx_bd_dma_base
);
1778 skb_queue_purge(&priv
->rx_recycle
);
1781 void gfar_start(struct net_device
*dev
)
1783 struct gfar_private
*priv
= netdev_priv(dev
);
1784 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1788 /* Enable Rx and Tx in MACCFG1 */
1789 tempval
= gfar_read(®s
->maccfg1
);
1790 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
1791 gfar_write(®s
->maccfg1
, tempval
);
1793 /* Initialize DMACTRL to have WWR and WOP */
1794 tempval
= gfar_read(®s
->dmactrl
);
1795 tempval
|= DMACTRL_INIT_SETTINGS
;
1796 gfar_write(®s
->dmactrl
, tempval
);
1798 /* Make sure we aren't stopped */
1799 tempval
= gfar_read(®s
->dmactrl
);
1800 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
1801 gfar_write(®s
->dmactrl
, tempval
);
1803 for (i
= 0; i
< priv
->num_grps
; i
++) {
1804 regs
= priv
->gfargrp
[i
].regs
;
1805 /* Clear THLT/RHLT, so that the DMA starts polling now */
1806 gfar_write(®s
->tstat
, priv
->gfargrp
[i
].tstat
);
1807 gfar_write(®s
->rstat
, priv
->gfargrp
[i
].rstat
);
1808 /* Unmask the interrupts we look for */
1809 gfar_write(®s
->imask
, IMASK_DEFAULT
);
1812 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1815 void gfar_configure_coalescing(struct gfar_private
*priv
,
1816 unsigned long tx_mask
, unsigned long rx_mask
)
1818 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
1822 /* Backward compatible case ---- even if we enable
1823 * multiple queues, there's only single reg to program
1825 gfar_write(®s
->txic
, 0);
1826 if(likely(priv
->tx_queue
[0]->txcoalescing
))
1827 gfar_write(®s
->txic
, priv
->tx_queue
[0]->txic
);
1829 gfar_write(®s
->rxic
, 0);
1830 if(unlikely(priv
->rx_queue
[0]->rxcoalescing
))
1831 gfar_write(®s
->rxic
, priv
->rx_queue
[0]->rxic
);
1833 if (priv
->mode
== MQ_MG_MODE
) {
1834 baddr
= ®s
->txic0
;
1835 for_each_set_bit(i
, &tx_mask
, priv
->num_tx_queues
) {
1836 if (likely(priv
->tx_queue
[i
]->txcoalescing
)) {
1837 gfar_write(baddr
+ i
, 0);
1838 gfar_write(baddr
+ i
, priv
->tx_queue
[i
]->txic
);
1842 baddr
= ®s
->rxic0
;
1843 for_each_set_bit(i
, &rx_mask
, priv
->num_rx_queues
) {
1844 if (likely(priv
->rx_queue
[i
]->rxcoalescing
)) {
1845 gfar_write(baddr
+ i
, 0);
1846 gfar_write(baddr
+ i
, priv
->rx_queue
[i
]->rxic
);
1852 static int register_grp_irqs(struct gfar_priv_grp
*grp
)
1854 struct gfar_private
*priv
= grp
->priv
;
1855 struct net_device
*dev
= priv
->ndev
;
1858 /* If the device has multiple interrupts, register for
1859 * them. Otherwise, only register for the one */
1860 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1861 /* Install our interrupt handlers for Error,
1862 * Transmit, and Receive */
1863 if ((err
= request_irq(grp
->interruptError
, gfar_error
, 0,
1864 grp
->int_name_er
,grp
)) < 0) {
1865 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1866 grp
->interruptError
);
1871 if ((err
= request_irq(grp
->interruptTransmit
, gfar_transmit
,
1872 0, grp
->int_name_tx
, grp
)) < 0) {
1873 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1874 grp
->interruptTransmit
);
1878 if ((err
= request_irq(grp
->interruptReceive
, gfar_receive
, 0,
1879 grp
->int_name_rx
, grp
)) < 0) {
1880 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1881 grp
->interruptReceive
);
1885 if ((err
= request_irq(grp
->interruptTransmit
, gfar_interrupt
, 0,
1886 grp
->int_name_tx
, grp
)) < 0) {
1887 netif_err(priv
, intr
, dev
, "Can't get IRQ %d\n",
1888 grp
->interruptTransmit
);
1896 free_irq(grp
->interruptTransmit
, grp
);
1898 free_irq(grp
->interruptError
, grp
);
1904 /* Bring the controller up and running */
1905 int startup_gfar(struct net_device
*ndev
)
1907 struct gfar_private
*priv
= netdev_priv(ndev
);
1908 struct gfar __iomem
*regs
= NULL
;
1911 for (i
= 0; i
< priv
->num_grps
; i
++) {
1912 regs
= priv
->gfargrp
[i
].regs
;
1913 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
1916 regs
= priv
->gfargrp
[0].regs
;
1917 err
= gfar_alloc_skb_resources(ndev
);
1921 gfar_init_mac(ndev
);
1923 for (i
= 0; i
< priv
->num_grps
; i
++) {
1924 err
= register_grp_irqs(&priv
->gfargrp
[i
]);
1926 for (j
= 0; j
< i
; j
++)
1927 free_grp_irqs(&priv
->gfargrp
[j
]);
1932 /* Start the controller */
1935 phy_start(priv
->phydev
);
1937 gfar_configure_coalescing(priv
, 0xFF, 0xFF);
1942 free_skb_resources(priv
);
1946 /* Called when something needs to use the ethernet device */
1947 /* Returns 0 for success. */
1948 static int gfar_enet_open(struct net_device
*dev
)
1950 struct gfar_private
*priv
= netdev_priv(dev
);
1955 skb_queue_head_init(&priv
->rx_recycle
);
1957 /* Initialize a bunch of registers */
1958 init_registers(dev
);
1960 gfar_set_mac_address(dev
);
1962 err
= init_phy(dev
);
1969 err
= startup_gfar(dev
);
1975 netif_tx_start_all_queues(dev
);
1977 device_set_wakeup_enable(&dev
->dev
, priv
->wol_en
);
1982 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
)
1984 struct txfcb
*fcb
= (struct txfcb
*)skb_push(skb
, GMAC_FCB_LEN
);
1986 memset(fcb
, 0, GMAC_FCB_LEN
);
1991 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
1995 /* If we're here, it's a IP packet with a TCP or UDP
1996 * payload. We set it to checksum, using a pseudo-header
1999 flags
= TXFCB_DEFAULT
;
2001 /* Tell the controller what the protocol is */
2002 /* And provide the already calculated phcs */
2003 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
2005 fcb
->phcs
= udp_hdr(skb
)->check
;
2007 fcb
->phcs
= tcp_hdr(skb
)->check
;
2009 /* l3os is the distance between the start of the
2010 * frame (skb->data) and the start of the IP hdr.
2011 * l4os is the distance between the start of the
2012 * l3 hdr and the l4 hdr */
2013 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
2014 fcb
->l4os
= skb_network_header_len(skb
);
2019 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
2021 fcb
->flags
|= TXFCB_VLN
;
2022 fcb
->vlctl
= vlan_tx_tag_get(skb
);
2025 static inline struct txbd8
*skip_txbd(struct txbd8
*bdp
, int stride
,
2026 struct txbd8
*base
, int ring_size
)
2028 struct txbd8
*new_bd
= bdp
+ stride
;
2030 return (new_bd
>= (base
+ ring_size
)) ? (new_bd
- ring_size
) : new_bd
;
2033 static inline struct txbd8
*next_txbd(struct txbd8
*bdp
, struct txbd8
*base
,
2036 return skip_txbd(bdp
, 1, base
, ring_size
);
2039 /* This is called by the kernel when a frame is ready for transmission. */
2040 /* It is pointed to by the dev->hard_start_xmit function pointer */
2041 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
2043 struct gfar_private
*priv
= netdev_priv(dev
);
2044 struct gfar_priv_tx_q
*tx_queue
= NULL
;
2045 struct netdev_queue
*txq
;
2046 struct gfar __iomem
*regs
= NULL
;
2047 struct txfcb
*fcb
= NULL
;
2048 struct txbd8
*txbdp
, *txbdp_start
, *base
, *txbdp_tstamp
= NULL
;
2050 int i
, rq
= 0, do_tstamp
= 0;
2052 unsigned long flags
;
2053 unsigned int nr_frags
, nr_txbds
, length
;
2056 * TOE=1 frames larger than 2500 bytes may see excess delays
2057 * before start of transmission.
2059 if (unlikely(gfar_has_errata(priv
, GFAR_ERRATA_76
) &&
2060 skb
->ip_summed
== CHECKSUM_PARTIAL
&&
2064 ret
= skb_checksum_help(skb
);
2069 rq
= skb
->queue_mapping
;
2070 tx_queue
= priv
->tx_queue
[rq
];
2071 txq
= netdev_get_tx_queue(dev
, rq
);
2072 base
= tx_queue
->tx_bd_base
;
2073 regs
= tx_queue
->grp
->regs
;
2075 /* check if time stamp should be generated */
2076 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
&&
2080 /* make space for additional header when fcb is needed */
2081 if (((skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
2082 vlan_tx_tag_present(skb
) ||
2083 unlikely(do_tstamp
)) &&
2084 (skb_headroom(skb
) < GMAC_FCB_LEN
)) {
2085 struct sk_buff
*skb_new
;
2087 skb_new
= skb_realloc_headroom(skb
, GMAC_FCB_LEN
);
2089 dev
->stats
.tx_errors
++;
2091 return NETDEV_TX_OK
;
2097 /* total number of fragments in the SKB */
2098 nr_frags
= skb_shinfo(skb
)->nr_frags
;
2100 /* calculate the required number of TxBDs for this skb */
2101 if (unlikely(do_tstamp
))
2102 nr_txbds
= nr_frags
+ 2;
2104 nr_txbds
= nr_frags
+ 1;
2106 /* check if there is space to queue this packet */
2107 if (nr_txbds
> tx_queue
->num_txbdfree
) {
2108 /* no space, stop the queue */
2109 netif_tx_stop_queue(txq
);
2110 dev
->stats
.tx_fifo_errors
++;
2111 return NETDEV_TX_BUSY
;
2114 /* Update transmit stats */
2115 tx_queue
->stats
.tx_bytes
+= skb
->len
;
2116 tx_queue
->stats
.tx_packets
++;
2118 txbdp
= txbdp_start
= tx_queue
->cur_tx
;
2119 lstatus
= txbdp
->lstatus
;
2121 /* Time stamp insertion requires one additional TxBD */
2122 if (unlikely(do_tstamp
))
2123 txbdp_tstamp
= txbdp
= next_txbd(txbdp
, base
,
2124 tx_queue
->tx_ring_size
);
2126 if (nr_frags
== 0) {
2127 if (unlikely(do_tstamp
))
2128 txbdp_tstamp
->lstatus
|= BD_LFLAG(TXBD_LAST
|
2131 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
2133 /* Place the fragment addresses and lengths into the TxBDs */
2134 for (i
= 0; i
< nr_frags
; i
++) {
2135 /* Point at the next BD, wrapping as needed */
2136 txbdp
= next_txbd(txbdp
, base
, tx_queue
->tx_ring_size
);
2138 length
= skb_shinfo(skb
)->frags
[i
].size
;
2140 lstatus
= txbdp
->lstatus
| length
|
2141 BD_LFLAG(TXBD_READY
);
2143 /* Handle the last BD specially */
2144 if (i
== nr_frags
- 1)
2145 lstatus
|= BD_LFLAG(TXBD_LAST
| TXBD_INTERRUPT
);
2147 bufaddr
= dma_map_page(&priv
->ofdev
->dev
,
2148 skb_shinfo(skb
)->frags
[i
].page
,
2149 skb_shinfo(skb
)->frags
[i
].page_offset
,
2153 /* set the TxBD length and buffer pointer */
2154 txbdp
->bufPtr
= bufaddr
;
2155 txbdp
->lstatus
= lstatus
;
2158 lstatus
= txbdp_start
->lstatus
;
2161 /* Set up checksumming */
2162 if (CHECKSUM_PARTIAL
== skb
->ip_summed
) {
2163 fcb
= gfar_add_fcb(skb
);
2164 /* as specified by errata */
2165 if (unlikely(gfar_has_errata(priv
, GFAR_ERRATA_12
)
2166 && ((unsigned long)fcb
% 0x20) > 0x18)) {
2167 __skb_pull(skb
, GMAC_FCB_LEN
);
2168 skb_checksum_help(skb
);
2170 lstatus
|= BD_LFLAG(TXBD_TOE
);
2171 gfar_tx_checksum(skb
, fcb
);
2175 if (vlan_tx_tag_present(skb
)) {
2176 if (unlikely(NULL
== fcb
)) {
2177 fcb
= gfar_add_fcb(skb
);
2178 lstatus
|= BD_LFLAG(TXBD_TOE
);
2181 gfar_tx_vlan(skb
, fcb
);
2184 /* Setup tx hardware time stamping if requested */
2185 if (unlikely(do_tstamp
)) {
2186 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
2188 fcb
= gfar_add_fcb(skb
);
2190 lstatus
|= BD_LFLAG(TXBD_TOE
);
2193 txbdp_start
->bufPtr
= dma_map_single(&priv
->ofdev
->dev
, skb
->data
,
2194 skb_headlen(skb
), DMA_TO_DEVICE
);
2197 * If time stamping is requested one additional TxBD must be set up. The
2198 * first TxBD points to the FCB and must have a data length of
2199 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2200 * the full frame length.
2202 if (unlikely(do_tstamp
)) {
2203 txbdp_tstamp
->bufPtr
= txbdp_start
->bufPtr
+ GMAC_FCB_LEN
;
2204 txbdp_tstamp
->lstatus
|= BD_LFLAG(TXBD_READY
) |
2205 (skb_headlen(skb
) - GMAC_FCB_LEN
);
2206 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | GMAC_FCB_LEN
;
2208 lstatus
|= BD_LFLAG(TXBD_CRC
| TXBD_READY
) | skb_headlen(skb
);
2212 * We can work in parallel with gfar_clean_tx_ring(), except
2213 * when modifying num_txbdfree. Note that we didn't grab the lock
2214 * when we were reading the num_txbdfree and checking for available
2215 * space, that's because outside of this function it can only grow,
2216 * and once we've got needed space, it cannot suddenly disappear.
2218 * The lock also protects us from gfar_error(), which can modify
2219 * regs->tstat and thus retrigger the transfers, which is why we
2220 * also must grab the lock before setting ready bit for the first
2221 * to be transmitted BD.
2223 spin_lock_irqsave(&tx_queue
->txlock
, flags
);
2226 * The powerpc-specific eieio() is used, as wmb() has too strong
2227 * semantics (it requires synchronization between cacheable and
2228 * uncacheable mappings, which eieio doesn't provide and which we
2229 * don't need), thus requiring a more expensive sync instruction. At
2230 * some point, the set of architecture-independent barrier functions
2231 * should be expanded to include weaker barriers.
2235 txbdp_start
->lstatus
= lstatus
;
2237 eieio(); /* force lstatus write before tx_skbuff */
2239 tx_queue
->tx_skbuff
[tx_queue
->skb_curtx
] = skb
;
2241 /* Update the current skb pointer to the next entry we will use
2242 * (wrapping if necessary) */
2243 tx_queue
->skb_curtx
= (tx_queue
->skb_curtx
+ 1) &
2244 TX_RING_MOD_MASK(tx_queue
->tx_ring_size
);
2246 tx_queue
->cur_tx
= next_txbd(txbdp
, base
, tx_queue
->tx_ring_size
);
2248 /* reduce TxBD free count */
2249 tx_queue
->num_txbdfree
-= (nr_txbds
);
2251 /* If the next BD still needs to be cleaned up, then the bds
2252 are full. We need to tell the kernel to stop sending us stuff. */
2253 if (!tx_queue
->num_txbdfree
) {
2254 netif_tx_stop_queue(txq
);
2256 dev
->stats
.tx_fifo_errors
++;
2259 /* Tell the DMA to go go go */
2260 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
>> tx_queue
->qindex
);
2263 spin_unlock_irqrestore(&tx_queue
->txlock
, flags
);
2265 return NETDEV_TX_OK
;
2268 /* Stops the kernel queue, and halts the controller */
2269 static int gfar_close(struct net_device
*dev
)
2271 struct gfar_private
*priv
= netdev_priv(dev
);
2275 cancel_work_sync(&priv
->reset_task
);
2278 /* Disconnect from the PHY */
2279 phy_disconnect(priv
->phydev
);
2280 priv
->phydev
= NULL
;
2282 netif_tx_stop_all_queues(dev
);
2287 /* Changes the mac address if the controller is not running. */
2288 static int gfar_set_mac_address(struct net_device
*dev
)
2290 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
2295 /* Check if rx parser should be activated */
2296 void gfar_check_rx_parser_mode(struct gfar_private
*priv
)
2298 struct gfar __iomem
*regs
;
2301 regs
= priv
->gfargrp
[0].regs
;
2303 tempval
= gfar_read(®s
->rctrl
);
2304 /* If parse is no longer required, then disable parser */
2305 if (tempval
& RCTRL_REQ_PARSER
)
2306 tempval
|= RCTRL_PRSDEP_INIT
;
2308 tempval
&= ~RCTRL_PRSDEP_INIT
;
2309 gfar_write(®s
->rctrl
, tempval
);
2312 /* Enables and disables VLAN insertion/extraction */
2313 void gfar_vlan_mode(struct net_device
*dev
, u32 features
)
2315 struct gfar_private
*priv
= netdev_priv(dev
);
2316 struct gfar __iomem
*regs
= NULL
;
2317 unsigned long flags
;
2320 regs
= priv
->gfargrp
[0].regs
;
2321 local_irq_save(flags
);
2324 if (features
& NETIF_F_HW_VLAN_TX
) {
2325 /* Enable VLAN tag insertion */
2326 tempval
= gfar_read(®s
->tctrl
);
2327 tempval
|= TCTRL_VLINS
;
2328 gfar_write(®s
->tctrl
, tempval
);
2330 /* Disable VLAN tag insertion */
2331 tempval
= gfar_read(®s
->tctrl
);
2332 tempval
&= ~TCTRL_VLINS
;
2333 gfar_write(®s
->tctrl
, tempval
);
2336 if (features
& NETIF_F_HW_VLAN_RX
) {
2337 /* Enable VLAN tag extraction */
2338 tempval
= gfar_read(®s
->rctrl
);
2339 tempval
|= (RCTRL_VLEX
| RCTRL_PRSDEP_INIT
);
2340 gfar_write(®s
->rctrl
, tempval
);
2342 /* Disable VLAN tag extraction */
2343 tempval
= gfar_read(®s
->rctrl
);
2344 tempval
&= ~RCTRL_VLEX
;
2345 gfar_write(®s
->rctrl
, tempval
);
2347 gfar_check_rx_parser_mode(priv
);
2350 gfar_change_mtu(dev
, dev
->mtu
);
2353 local_irq_restore(flags
);
2356 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
2358 int tempsize
, tempval
;
2359 struct gfar_private
*priv
= netdev_priv(dev
);
2360 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
2361 int oldsize
= priv
->rx_buffer_size
;
2362 int frame_size
= new_mtu
+ ETH_HLEN
;
2364 if (gfar_is_vlan_on(priv
))
2365 frame_size
+= VLAN_HLEN
;
2367 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
2368 netif_err(priv
, drv
, dev
, "Invalid MTU setting\n");
2372 if (gfar_uses_fcb(priv
))
2373 frame_size
+= GMAC_FCB_LEN
;
2375 frame_size
+= priv
->padding
;
2378 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
2379 INCREMENTAL_BUFFER_SIZE
;
2381 /* Only stop and start the controller if it isn't already
2382 * stopped, and we changed something */
2383 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
2386 priv
->rx_buffer_size
= tempsize
;
2390 gfar_write(®s
->mrblr
, priv
->rx_buffer_size
);
2391 gfar_write(®s
->maxfrm
, priv
->rx_buffer_size
);
2393 /* If the mtu is larger than the max size for standard
2394 * ethernet frames (ie, a jumbo frame), then set maccfg2
2395 * to allow huge frames, and to check the length */
2396 tempval
= gfar_read(®s
->maccfg2
);
2398 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
||
2399 gfar_has_errata(priv
, GFAR_ERRATA_74
))
2400 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
2402 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
2404 gfar_write(®s
->maccfg2
, tempval
);
2406 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
2412 /* gfar_reset_task gets scheduled when a packet has not been
2413 * transmitted after a set amount of time.
2414 * For now, assume that clearing out all the structures, and
2415 * starting over will fix the problem.
2417 static void gfar_reset_task(struct work_struct
*work
)
2419 struct gfar_private
*priv
= container_of(work
, struct gfar_private
,
2421 struct net_device
*dev
= priv
->ndev
;
2423 if (dev
->flags
& IFF_UP
) {
2424 netif_tx_stop_all_queues(dev
);
2427 netif_tx_start_all_queues(dev
);
2430 netif_tx_schedule_all(dev
);
2433 static void gfar_timeout(struct net_device
*dev
)
2435 struct gfar_private
*priv
= netdev_priv(dev
);
2437 dev
->stats
.tx_errors
++;
2438 schedule_work(&priv
->reset_task
);
2441 static void gfar_align_skb(struct sk_buff
*skb
)
2443 /* We need the data buffer to be aligned properly. We will reserve
2444 * as many bytes as needed to align the data properly
2446 skb_reserve(skb
, RXBUF_ALIGNMENT
-
2447 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1)));
2450 /* Interrupt Handler for Transmit complete */
2451 static int gfar_clean_tx_ring(struct gfar_priv_tx_q
*tx_queue
)
2453 struct net_device
*dev
= tx_queue
->dev
;
2454 struct gfar_private
*priv
= netdev_priv(dev
);
2455 struct gfar_priv_rx_q
*rx_queue
= NULL
;
2456 struct txbd8
*bdp
, *next
= NULL
;
2457 struct txbd8
*lbdp
= NULL
;
2458 struct txbd8
*base
= tx_queue
->tx_bd_base
;
2459 struct sk_buff
*skb
;
2461 int tx_ring_size
= tx_queue
->tx_ring_size
;
2462 int frags
= 0, nr_txbds
= 0;
2468 rx_queue
= priv
->rx_queue
[tx_queue
->qindex
];
2469 bdp
= tx_queue
->dirty_tx
;
2470 skb_dirtytx
= tx_queue
->skb_dirtytx
;
2472 while ((skb
= tx_queue
->tx_skbuff
[skb_dirtytx
])) {
2473 unsigned long flags
;
2475 frags
= skb_shinfo(skb
)->nr_frags
;
2478 * When time stamping, one additional TxBD must be freed.
2479 * Also, we need to dma_unmap_single() the TxPAL.
2481 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
))
2482 nr_txbds
= frags
+ 2;
2484 nr_txbds
= frags
+ 1;
2486 lbdp
= skip_txbd(bdp
, nr_txbds
- 1, base
, tx_ring_size
);
2488 lstatus
= lbdp
->lstatus
;
2490 /* Only clean completed frames */
2491 if ((lstatus
& BD_LFLAG(TXBD_READY
)) &&
2492 (lstatus
& BD_LENGTH_MASK
))
2495 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)) {
2496 next
= next_txbd(bdp
, base
, tx_ring_size
);
2497 buflen
= next
->length
+ GMAC_FCB_LEN
;
2499 buflen
= bdp
->length
;
2501 dma_unmap_single(&priv
->ofdev
->dev
, bdp
->bufPtr
,
2502 buflen
, DMA_TO_DEVICE
);
2504 if (unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_IN_PROGRESS
)) {
2505 struct skb_shared_hwtstamps shhwtstamps
;
2506 u64
*ns
= (u64
*) (((u32
)skb
->data
+ 0x10) & ~0x7);
2507 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
2508 shhwtstamps
.hwtstamp
= ns_to_ktime(*ns
);
2509 skb_tstamp_tx(skb
, &shhwtstamps
);
2510 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2514 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2515 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
2517 for (i
= 0; i
< frags
; i
++) {
2518 dma_unmap_page(&priv
->ofdev
->dev
,
2522 bdp
->lstatus
&= BD_LFLAG(TXBD_WRAP
);
2523 bdp
= next_txbd(bdp
, base
, tx_ring_size
);
2527 * If there's room in the queue (limit it to rx_buffer_size)
2528 * we add this skb back into the pool, if it's the right size
2530 if (skb_queue_len(&priv
->rx_recycle
) < rx_queue
->rx_ring_size
&&
2531 skb_recycle_check(skb
, priv
->rx_buffer_size
+
2533 gfar_align_skb(skb
);
2534 skb_queue_head(&priv
->rx_recycle
, skb
);
2536 dev_kfree_skb_any(skb
);
2538 tx_queue
->tx_skbuff
[skb_dirtytx
] = NULL
;
2540 skb_dirtytx
= (skb_dirtytx
+ 1) &
2541 TX_RING_MOD_MASK(tx_ring_size
);
2544 spin_lock_irqsave(&tx_queue
->txlock
, flags
);
2545 tx_queue
->num_txbdfree
+= nr_txbds
;
2546 spin_unlock_irqrestore(&tx_queue
->txlock
, flags
);
2549 /* If we freed a buffer, we can restart transmission, if necessary */
2550 if (__netif_subqueue_stopped(dev
, tx_queue
->qindex
) && tx_queue
->num_txbdfree
)
2551 netif_wake_subqueue(dev
, tx_queue
->qindex
);
2553 /* Update dirty indicators */
2554 tx_queue
->skb_dirtytx
= skb_dirtytx
;
2555 tx_queue
->dirty_tx
= bdp
;
2560 static void gfar_schedule_cleanup(struct gfar_priv_grp
*gfargrp
)
2562 unsigned long flags
;
2564 spin_lock_irqsave(&gfargrp
->grplock
, flags
);
2565 if (napi_schedule_prep(&gfargrp
->napi
)) {
2566 gfar_write(&gfargrp
->regs
->imask
, IMASK_RTX_DISABLED
);
2567 __napi_schedule(&gfargrp
->napi
);
2570 * Clear IEVENT, so interrupts aren't called again
2571 * because of the packets that have already arrived.
2573 gfar_write(&gfargrp
->regs
->ievent
, IEVENT_RTX_MASK
);
2575 spin_unlock_irqrestore(&gfargrp
->grplock
, flags
);
2579 /* Interrupt Handler for Transmit complete */
2580 static irqreturn_t
gfar_transmit(int irq
, void *grp_id
)
2582 gfar_schedule_cleanup((struct gfar_priv_grp
*)grp_id
);
2586 static void gfar_new_rxbdp(struct gfar_priv_rx_q
*rx_queue
, struct rxbd8
*bdp
,
2587 struct sk_buff
*skb
)
2589 struct net_device
*dev
= rx_queue
->dev
;
2590 struct gfar_private
*priv
= netdev_priv(dev
);
2593 buf
= dma_map_single(&priv
->ofdev
->dev
, skb
->data
,
2594 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
2595 gfar_init_rxbdp(rx_queue
, bdp
, buf
);
2598 static struct sk_buff
* gfar_alloc_skb(struct net_device
*dev
)
2600 struct gfar_private
*priv
= netdev_priv(dev
);
2601 struct sk_buff
*skb
= NULL
;
2603 skb
= netdev_alloc_skb(dev
, priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
2607 gfar_align_skb(skb
);
2612 struct sk_buff
* gfar_new_skb(struct net_device
*dev
)
2614 struct gfar_private
*priv
= netdev_priv(dev
);
2615 struct sk_buff
*skb
= NULL
;
2617 skb
= skb_dequeue(&priv
->rx_recycle
);
2619 skb
= gfar_alloc_skb(dev
);
2624 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
2626 struct gfar_private
*priv
= netdev_priv(dev
);
2627 struct net_device_stats
*stats
= &dev
->stats
;
2628 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
2630 /* If the packet was truncated, none of the other errors
2632 if (status
& RXBD_TRUNCATED
) {
2633 stats
->rx_length_errors
++;
2639 /* Count the errors, if there were any */
2640 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
2641 stats
->rx_length_errors
++;
2643 if (status
& RXBD_LARGE
)
2648 if (status
& RXBD_NONOCTET
) {
2649 stats
->rx_frame_errors
++;
2650 estats
->rx_nonoctet
++;
2652 if (status
& RXBD_CRCERR
) {
2653 estats
->rx_crcerr
++;
2654 stats
->rx_crc_errors
++;
2656 if (status
& RXBD_OVERRUN
) {
2657 estats
->rx_overrun
++;
2658 stats
->rx_crc_errors
++;
2662 irqreturn_t
gfar_receive(int irq
, void *grp_id
)
2664 gfar_schedule_cleanup((struct gfar_priv_grp
*)grp_id
);
2668 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
2670 /* If valid headers were found, and valid sums
2671 * were verified, then we tell the kernel that no
2672 * checksumming is necessary. Otherwise, it is */
2673 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
2674 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2676 skb_checksum_none_assert(skb
);
2680 /* gfar_process_frame() -- handle one incoming packet if skb
2682 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
2685 struct gfar_private
*priv
= netdev_priv(dev
);
2686 struct rxfcb
*fcb
= NULL
;
2690 /* fcb is at the beginning if exists */
2691 fcb
= (struct rxfcb
*)skb
->data
;
2693 /* Remove the FCB from the skb */
2694 /* Remove the padded bytes, if there are any */
2696 skb_record_rx_queue(skb
, fcb
->rq
);
2697 skb_pull(skb
, amount_pull
);
2700 /* Get receive timestamp from the skb */
2701 if (priv
->hwts_rx_en
) {
2702 struct skb_shared_hwtstamps
*shhwtstamps
= skb_hwtstamps(skb
);
2703 u64
*ns
= (u64
*) skb
->data
;
2704 memset(shhwtstamps
, 0, sizeof(*shhwtstamps
));
2705 shhwtstamps
->hwtstamp
= ns_to_ktime(*ns
);
2709 skb_pull(skb
, priv
->padding
);
2711 if (dev
->features
& NETIF_F_RXCSUM
)
2712 gfar_rx_checksum(skb
, fcb
);
2714 /* Tell the skb what kind of packet this is */
2715 skb
->protocol
= eth_type_trans(skb
, dev
);
2718 if (fcb
->flags
& RXFCB_VLN
)
2719 __vlan_hwaccel_put_tag(skb
, fcb
->vlctl
);
2721 /* Send the packet up the stack */
2722 ret
= netif_receive_skb(skb
);
2724 if (NET_RX_DROP
== ret
)
2725 priv
->extra_stats
.kernel_dropped
++;
2730 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2731 * until the budget/quota has been reached. Returns the number
2734 int gfar_clean_rx_ring(struct gfar_priv_rx_q
*rx_queue
, int rx_work_limit
)
2736 struct net_device
*dev
= rx_queue
->dev
;
2737 struct rxbd8
*bdp
, *base
;
2738 struct sk_buff
*skb
;
2742 struct gfar_private
*priv
= netdev_priv(dev
);
2744 /* Get the first full descriptor */
2745 bdp
= rx_queue
->cur_rx
;
2746 base
= rx_queue
->rx_bd_base
;
2748 amount_pull
= (gfar_uses_fcb(priv
) ? GMAC_FCB_LEN
: 0);
2750 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
2751 struct sk_buff
*newskb
;
2754 /* Add another skb for the future */
2755 newskb
= gfar_new_skb(dev
);
2757 skb
= rx_queue
->rx_skbuff
[rx_queue
->skb_currx
];
2759 dma_unmap_single(&priv
->ofdev
->dev
, bdp
->bufPtr
,
2760 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
2762 if (unlikely(!(bdp
->status
& RXBD_ERR
) &&
2763 bdp
->length
> priv
->rx_buffer_size
))
2764 bdp
->status
= RXBD_LARGE
;
2766 /* We drop the frame if we failed to allocate a new buffer */
2767 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
2768 bdp
->status
& RXBD_ERR
)) {
2769 count_errors(bdp
->status
, dev
);
2771 if (unlikely(!newskb
))
2774 skb_queue_head(&priv
->rx_recycle
, skb
);
2776 /* Increment the number of packets */
2777 rx_queue
->stats
.rx_packets
++;
2781 pkt_len
= bdp
->length
- ETH_FCS_LEN
;
2782 /* Remove the FCS from the packet length */
2783 skb_put(skb
, pkt_len
);
2784 rx_queue
->stats
.rx_bytes
+= pkt_len
;
2785 skb_record_rx_queue(skb
, rx_queue
->qindex
);
2786 gfar_process_frame(dev
, skb
, amount_pull
);
2789 netif_warn(priv
, rx_err
, dev
, "Missing skb!\n");
2790 rx_queue
->stats
.rx_dropped
++;
2791 priv
->extra_stats
.rx_skbmissing
++;
2796 rx_queue
->rx_skbuff
[rx_queue
->skb_currx
] = newskb
;
2798 /* Setup the new bdp */
2799 gfar_new_rxbdp(rx_queue
, bdp
, newskb
);
2801 /* Update to the next pointer */
2802 bdp
= next_bd(bdp
, base
, rx_queue
->rx_ring_size
);
2804 /* update to point at the next skb */
2805 rx_queue
->skb_currx
=
2806 (rx_queue
->skb_currx
+ 1) &
2807 RX_RING_MOD_MASK(rx_queue
->rx_ring_size
);
2810 /* Update the current rxbd pointer to be the next one */
2811 rx_queue
->cur_rx
= bdp
;
2816 static int gfar_poll(struct napi_struct
*napi
, int budget
)
2818 struct gfar_priv_grp
*gfargrp
= container_of(napi
,
2819 struct gfar_priv_grp
, napi
);
2820 struct gfar_private
*priv
= gfargrp
->priv
;
2821 struct gfar __iomem
*regs
= gfargrp
->regs
;
2822 struct gfar_priv_tx_q
*tx_queue
= NULL
;
2823 struct gfar_priv_rx_q
*rx_queue
= NULL
;
2824 int rx_cleaned
= 0, budget_per_queue
= 0, rx_cleaned_per_queue
= 0;
2825 int tx_cleaned
= 0, i
, left_over_budget
= budget
;
2826 unsigned long serviced_queues
= 0;
2829 num_queues
= gfargrp
->num_rx_queues
;
2830 budget_per_queue
= budget
/num_queues
;
2832 /* Clear IEVENT, so interrupts aren't called again
2833 * because of the packets that have already arrived */
2834 gfar_write(®s
->ievent
, IEVENT_RTX_MASK
);
2836 while (num_queues
&& left_over_budget
) {
2838 budget_per_queue
= left_over_budget
/num_queues
;
2839 left_over_budget
= 0;
2841 for_each_set_bit(i
, &gfargrp
->rx_bit_map
, priv
->num_rx_queues
) {
2842 if (test_bit(i
, &serviced_queues
))
2844 rx_queue
= priv
->rx_queue
[i
];
2845 tx_queue
= priv
->tx_queue
[rx_queue
->qindex
];
2847 tx_cleaned
+= gfar_clean_tx_ring(tx_queue
);
2848 rx_cleaned_per_queue
= gfar_clean_rx_ring(rx_queue
,
2850 rx_cleaned
+= rx_cleaned_per_queue
;
2851 if(rx_cleaned_per_queue
< budget_per_queue
) {
2852 left_over_budget
= left_over_budget
+
2853 (budget_per_queue
- rx_cleaned_per_queue
);
2854 set_bit(i
, &serviced_queues
);
2863 if (rx_cleaned
< budget
) {
2864 napi_complete(napi
);
2866 /* Clear the halt bit in RSTAT */
2867 gfar_write(®s
->rstat
, gfargrp
->rstat
);
2869 gfar_write(®s
->imask
, IMASK_DEFAULT
);
2871 /* If we are coalescing interrupts, update the timer */
2872 /* Otherwise, clear it */
2873 gfar_configure_coalescing(priv
,
2874 gfargrp
->rx_bit_map
, gfargrp
->tx_bit_map
);
2880 #ifdef CONFIG_NET_POLL_CONTROLLER
2882 * Polling 'interrupt' - used by things like netconsole to send skbs
2883 * without having to re-enable interrupts. It's not called while
2884 * the interrupt routine is executing.
2886 static void gfar_netpoll(struct net_device
*dev
)
2888 struct gfar_private
*priv
= netdev_priv(dev
);
2891 /* If the device has multiple interrupts, run tx/rx */
2892 if (priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
2893 for (i
= 0; i
< priv
->num_grps
; i
++) {
2894 disable_irq(priv
->gfargrp
[i
].interruptTransmit
);
2895 disable_irq(priv
->gfargrp
[i
].interruptReceive
);
2896 disable_irq(priv
->gfargrp
[i
].interruptError
);
2897 gfar_interrupt(priv
->gfargrp
[i
].interruptTransmit
,
2899 enable_irq(priv
->gfargrp
[i
].interruptError
);
2900 enable_irq(priv
->gfargrp
[i
].interruptReceive
);
2901 enable_irq(priv
->gfargrp
[i
].interruptTransmit
);
2904 for (i
= 0; i
< priv
->num_grps
; i
++) {
2905 disable_irq(priv
->gfargrp
[i
].interruptTransmit
);
2906 gfar_interrupt(priv
->gfargrp
[i
].interruptTransmit
,
2908 enable_irq(priv
->gfargrp
[i
].interruptTransmit
);
2914 /* The interrupt handler for devices with one interrupt */
2915 static irqreturn_t
gfar_interrupt(int irq
, void *grp_id
)
2917 struct gfar_priv_grp
*gfargrp
= grp_id
;
2919 /* Save ievent for future reference */
2920 u32 events
= gfar_read(&gfargrp
->regs
->ievent
);
2922 /* Check for reception */
2923 if (events
& IEVENT_RX_MASK
)
2924 gfar_receive(irq
, grp_id
);
2926 /* Check for transmit completion */
2927 if (events
& IEVENT_TX_MASK
)
2928 gfar_transmit(irq
, grp_id
);
2930 /* Check for errors */
2931 if (events
& IEVENT_ERR_MASK
)
2932 gfar_error(irq
, grp_id
);
2937 /* Called every time the controller might need to be made
2938 * aware of new link state. The PHY code conveys this
2939 * information through variables in the phydev structure, and this
2940 * function converts those variables into the appropriate
2941 * register values, and can bring down the device if needed.
2943 static void adjust_link(struct net_device
*dev
)
2945 struct gfar_private
*priv
= netdev_priv(dev
);
2946 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
2947 unsigned long flags
;
2948 struct phy_device
*phydev
= priv
->phydev
;
2951 local_irq_save(flags
);
2955 u32 tempval
= gfar_read(®s
->maccfg2
);
2956 u32 ecntrl
= gfar_read(®s
->ecntrl
);
2958 /* Now we make sure that we can be in full duplex mode.
2959 * If not, we operate in half-duplex mode. */
2960 if (phydev
->duplex
!= priv
->oldduplex
) {
2962 if (!(phydev
->duplex
))
2963 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
2965 tempval
|= MACCFG2_FULL_DUPLEX
;
2967 priv
->oldduplex
= phydev
->duplex
;
2970 if (phydev
->speed
!= priv
->oldspeed
) {
2972 switch (phydev
->speed
) {
2975 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
2977 ecntrl
&= ~(ECNTRL_R100
);
2982 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
2984 /* Reduced mode distinguishes
2985 * between 10 and 100 */
2986 if (phydev
->speed
== SPEED_100
)
2987 ecntrl
|= ECNTRL_R100
;
2989 ecntrl
&= ~(ECNTRL_R100
);
2992 netif_warn(priv
, link
, dev
,
2993 "Ack! Speed (%d) is not 10/100/1000!\n",
2998 priv
->oldspeed
= phydev
->speed
;
3001 gfar_write(®s
->maccfg2
, tempval
);
3002 gfar_write(®s
->ecntrl
, ecntrl
);
3004 if (!priv
->oldlink
) {
3008 } else if (priv
->oldlink
) {
3012 priv
->oldduplex
= -1;
3015 if (new_state
&& netif_msg_link(priv
))
3016 phy_print_status(phydev
);
3018 local_irq_restore(flags
);
3021 /* Update the hash table based on the current list of multicast
3022 * addresses we subscribe to. Also, change the promiscuity of
3023 * the device based on the flags (this function is called
3024 * whenever dev->flags is changed */
3025 static void gfar_set_multi(struct net_device
*dev
)
3027 struct netdev_hw_addr
*ha
;
3028 struct gfar_private
*priv
= netdev_priv(dev
);
3029 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
3032 if (dev
->flags
& IFF_PROMISC
) {
3033 /* Set RCTRL to PROM */
3034 tempval
= gfar_read(®s
->rctrl
);
3035 tempval
|= RCTRL_PROM
;
3036 gfar_write(®s
->rctrl
, tempval
);
3038 /* Set RCTRL to not PROM */
3039 tempval
= gfar_read(®s
->rctrl
);
3040 tempval
&= ~(RCTRL_PROM
);
3041 gfar_write(®s
->rctrl
, tempval
);
3044 if (dev
->flags
& IFF_ALLMULTI
) {
3045 /* Set the hash to rx all multicast frames */
3046 gfar_write(®s
->igaddr0
, 0xffffffff);
3047 gfar_write(®s
->igaddr1
, 0xffffffff);
3048 gfar_write(®s
->igaddr2
, 0xffffffff);
3049 gfar_write(®s
->igaddr3
, 0xffffffff);
3050 gfar_write(®s
->igaddr4
, 0xffffffff);
3051 gfar_write(®s
->igaddr5
, 0xffffffff);
3052 gfar_write(®s
->igaddr6
, 0xffffffff);
3053 gfar_write(®s
->igaddr7
, 0xffffffff);
3054 gfar_write(®s
->gaddr0
, 0xffffffff);
3055 gfar_write(®s
->gaddr1
, 0xffffffff);
3056 gfar_write(®s
->gaddr2
, 0xffffffff);
3057 gfar_write(®s
->gaddr3
, 0xffffffff);
3058 gfar_write(®s
->gaddr4
, 0xffffffff);
3059 gfar_write(®s
->gaddr5
, 0xffffffff);
3060 gfar_write(®s
->gaddr6
, 0xffffffff);
3061 gfar_write(®s
->gaddr7
, 0xffffffff);
3066 /* zero out the hash */
3067 gfar_write(®s
->igaddr0
, 0x0);
3068 gfar_write(®s
->igaddr1
, 0x0);
3069 gfar_write(®s
->igaddr2
, 0x0);
3070 gfar_write(®s
->igaddr3
, 0x0);
3071 gfar_write(®s
->igaddr4
, 0x0);
3072 gfar_write(®s
->igaddr5
, 0x0);
3073 gfar_write(®s
->igaddr6
, 0x0);
3074 gfar_write(®s
->igaddr7
, 0x0);
3075 gfar_write(®s
->gaddr0
, 0x0);
3076 gfar_write(®s
->gaddr1
, 0x0);
3077 gfar_write(®s
->gaddr2
, 0x0);
3078 gfar_write(®s
->gaddr3
, 0x0);
3079 gfar_write(®s
->gaddr4
, 0x0);
3080 gfar_write(®s
->gaddr5
, 0x0);
3081 gfar_write(®s
->gaddr6
, 0x0);
3082 gfar_write(®s
->gaddr7
, 0x0);
3084 /* If we have extended hash tables, we need to
3085 * clear the exact match registers to prepare for
3087 if (priv
->extended_hash
) {
3088 em_num
= GFAR_EM_NUM
+ 1;
3089 gfar_clear_exact_match(dev
);
3096 if (netdev_mc_empty(dev
))
3099 /* Parse the list, and set the appropriate bits */
3100 netdev_for_each_mc_addr(ha
, dev
) {
3102 gfar_set_mac_for_addr(dev
, idx
, ha
->addr
);
3105 gfar_set_hash_for_addr(dev
, ha
->addr
);
3111 /* Clears each of the exact match registers to zero, so they
3112 * don't interfere with normal reception */
3113 static void gfar_clear_exact_match(struct net_device
*dev
)
3116 static const u8 zero_arr
[MAC_ADDR_LEN
] = {0, 0, 0, 0, 0, 0};
3118 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
3119 gfar_set_mac_for_addr(dev
, idx
, zero_arr
);
3122 /* Set the appropriate hash bit for the given addr */
3123 /* The algorithm works like so:
3124 * 1) Take the Destination Address (ie the multicast address), and
3125 * do a CRC on it (little endian), and reverse the bits of the
3127 * 2) Use the 8 most significant bits as a hash into a 256-entry
3128 * table. The table is controlled through 8 32-bit registers:
3129 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3130 * gaddr7. This means that the 3 most significant bits in the
3131 * hash index which gaddr register to use, and the 5 other bits
3132 * indicate which bit (assuming an IBM numbering scheme, which
3133 * for PowerPC (tm) is usually the case) in the register holds
3135 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
3138 struct gfar_private
*priv
= netdev_priv(dev
);
3139 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
3140 int width
= priv
->hash_width
;
3141 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
3142 u8 whichreg
= result
>> (32 - width
+ 5);
3143 u32 value
= (1 << (31-whichbit
));
3145 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
3147 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
3151 /* There are multiple MAC Address register pairs on some controllers
3152 * This function sets the numth pair to a given address
3154 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
,
3157 struct gfar_private
*priv
= netdev_priv(dev
);
3158 struct gfar __iomem
*regs
= priv
->gfargrp
[0].regs
;
3160 char tmpbuf
[MAC_ADDR_LEN
];
3162 u32 __iomem
*macptr
= ®s
->macstnaddr1
;
3166 /* Now copy it into the mac registers backwards, cuz */
3167 /* little endian is silly */
3168 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
3169 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
3171 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
3173 tempval
= *((u32
*) (tmpbuf
+ 4));
3175 gfar_write(macptr
+1, tempval
);
3178 /* GFAR error interrupt handler */
3179 static irqreturn_t
gfar_error(int irq
, void *grp_id
)
3181 struct gfar_priv_grp
*gfargrp
= grp_id
;
3182 struct gfar __iomem
*regs
= gfargrp
->regs
;
3183 struct gfar_private
*priv
= gfargrp
->priv
;
3184 struct net_device
*dev
= priv
->ndev
;
3186 /* Save ievent for future reference */
3187 u32 events
= gfar_read(®s
->ievent
);
3190 gfar_write(®s
->ievent
, events
& IEVENT_ERR_MASK
);
3192 /* Magic Packet is not an error. */
3193 if ((priv
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
) &&
3194 (events
& IEVENT_MAG
))
3195 events
&= ~IEVENT_MAG
;
3198 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
3199 netdev_dbg(dev
, "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3200 events
, gfar_read(®s
->imask
));
3202 /* Update the error counters */
3203 if (events
& IEVENT_TXE
) {
3204 dev
->stats
.tx_errors
++;
3206 if (events
& IEVENT_LC
)
3207 dev
->stats
.tx_window_errors
++;
3208 if (events
& IEVENT_CRL
)
3209 dev
->stats
.tx_aborted_errors
++;
3210 if (events
& IEVENT_XFUN
) {
3211 unsigned long flags
;
3213 netif_dbg(priv
, tx_err
, dev
,
3214 "TX FIFO underrun, packet dropped\n");
3215 dev
->stats
.tx_dropped
++;
3216 priv
->extra_stats
.tx_underrun
++;
3218 local_irq_save(flags
);
3221 /* Reactivate the Tx Queues */
3222 gfar_write(®s
->tstat
, gfargrp
->tstat
);
3225 local_irq_restore(flags
);
3227 netif_dbg(priv
, tx_err
, dev
, "Transmit Error\n");
3229 if (events
& IEVENT_BSY
) {
3230 dev
->stats
.rx_errors
++;
3231 priv
->extra_stats
.rx_bsy
++;
3233 gfar_receive(irq
, grp_id
);
3235 netif_dbg(priv
, rx_err
, dev
, "busy error (rstat: %x)\n",
3236 gfar_read(®s
->rstat
));
3238 if (events
& IEVENT_BABR
) {
3239 dev
->stats
.rx_errors
++;
3240 priv
->extra_stats
.rx_babr
++;
3242 netif_dbg(priv
, rx_err
, dev
, "babbling RX error\n");
3244 if (events
& IEVENT_EBERR
) {
3245 priv
->extra_stats
.eberr
++;
3246 netif_dbg(priv
, rx_err
, dev
, "bus error\n");
3248 if (events
& IEVENT_RXC
)
3249 netif_dbg(priv
, rx_status
, dev
, "control frame\n");
3251 if (events
& IEVENT_BABT
) {
3252 priv
->extra_stats
.tx_babt
++;
3253 netif_dbg(priv
, tx_err
, dev
, "babbling TX error\n");
3258 static struct of_device_id gfar_match
[] =
3262 .compatible
= "gianfar",
3265 .compatible
= "fsl,etsec2",
3269 MODULE_DEVICE_TABLE(of
, gfar_match
);
3271 /* Structure for a device driver */
3272 static struct platform_driver gfar_driver
= {
3274 .name
= "fsl-gianfar",
3275 .owner
= THIS_MODULE
,
3277 .of_match_table
= gfar_match
,
3279 .probe
= gfar_probe
,
3280 .remove
= gfar_remove
,
3283 static int __init
gfar_init(void)
3285 return platform_driver_register(&gfar_driver
);
3288 static void __exit
gfar_exit(void)
3290 platform_driver_unregister(&gfar_driver
);
3293 module_init(gfar_init
);
3294 module_exit(gfar_exit
);