2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
19 * Gianfar: AKA Lambda Draconis, "Dragon"
27 * The driver is initialized through platform_device. Structures which
28 * define the configuration needed by the board are defined in a
29 * board structure in arch/ppc/platforms (though I do not
30 * discount the possibility that other architectures could one
33 * The Gianfar Ethernet Controller uses a ring of buffer
34 * descriptors. The beginning is indicated by a register
35 * pointing to the physical address of the start of the ring.
36 * The end is determined by a "wrap" bit being set in the
37 * last descriptor of the ring.
39 * When a packet is received, the RXF bit in the
40 * IEVENT register is set, triggering an interrupt when the
41 * corresponding bit in the IMASK register is also set (if
42 * interrupt coalescing is active, then the interrupt may not
43 * happen immediately, but will wait until either a set number
44 * of frames or amount of time have passed). In NAPI, the
45 * interrupt handler will signal there is work to be done, and
46 * exit. Without NAPI, the packet(s) will be handled
47 * immediately. Both methods will start at the last known empty
48 * descriptor, and process every subsequent descriptor until there
49 * are none left with data (NAPI will stop after a set number of
50 * packets to give time to other tasks, but will eventually
51 * process all the packets). The data arrives inside a
52 * pre-allocated skb, and so after the skb is passed up to the
53 * stack, a new skb must be allocated, and the address field in
54 * the buffer descriptor must be updated to indicate this new
57 * When the kernel requests that a packet be transmitted, the
58 * driver starts where it left off last time, and points the
59 * descriptor at the buffer which was passed in. The driver
60 * then informs the DMA engine that there are packets ready to
61 * be transmitted. Once the controller is finished transmitting
62 * the packet, an interrupt may be triggered (under the same
63 * conditions as for reception, but depending on the TXF bit).
64 * The driver then cleans up the buffer.
67 #include <linux/config.h>
68 #include <linux/kernel.h>
69 #include <linux/sched.h>
70 #include <linux/string.h>
71 #include <linux/errno.h>
72 #include <linux/unistd.h>
73 #include <linux/slab.h>
74 #include <linux/interrupt.h>
75 #include <linux/init.h>
76 #include <linux/delay.h>
77 #include <linux/netdevice.h>
78 #include <linux/etherdevice.h>
79 #include <linux/skbuff.h>
80 #include <linux/if_vlan.h>
81 #include <linux/spinlock.h>
83 #include <linux/platform_device.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
91 #include <asm/uaccess.h>
92 #include <linux/module.h>
93 #include <linux/dma-mapping.h>
94 #include <linux/crc32.h>
95 #include <linux/mii.h>
96 #include <linux/phy.h>
99 #include "gianfar_mii.h"
101 #define TX_TIMEOUT (1*HZ)
102 #define SKB_ALLOC_TIMEOUT 1000000
103 #undef BRIEF_GFAR_ERRORS
104 #undef VERBOSE_GFAR_ERRORS
106 #ifdef CONFIG_GFAR_NAPI
107 #define RECEIVE(x) netif_receive_skb(x)
109 #define RECEIVE(x) netif_rx(x)
112 const char gfar_driver_name
[] = "Gianfar Ethernet";
113 const char gfar_driver_version
[] = "1.3";
115 static int gfar_enet_open(struct net_device
*dev
);
116 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
117 static void gfar_timeout(struct net_device
*dev
);
118 static int gfar_close(struct net_device
*dev
);
119 struct sk_buff
*gfar_new_skb(struct net_device
*dev
, struct rxbd8
*bdp
);
120 static struct net_device_stats
*gfar_get_stats(struct net_device
*dev
);
121 static int gfar_set_mac_address(struct net_device
*dev
);
122 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
123 static irqreturn_t
gfar_error(int irq
, void *dev_id
, struct pt_regs
*regs
);
124 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
, struct pt_regs
*regs
);
125 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
);
126 static void adjust_link(struct net_device
*dev
);
127 static void init_registers(struct net_device
*dev
);
128 static int init_phy(struct net_device
*dev
);
129 static int gfar_probe(struct platform_device
*pdev
);
130 static int gfar_remove(struct platform_device
*pdev
);
131 static void free_skb_resources(struct gfar_private
*priv
);
132 static void gfar_set_multi(struct net_device
*dev
);
133 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
134 #ifdef CONFIG_GFAR_NAPI
135 static int gfar_poll(struct net_device
*dev
, int *budget
);
137 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
);
138 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
, int length
);
139 static void gfar_vlan_rx_register(struct net_device
*netdev
,
140 struct vlan_group
*grp
);
141 static void gfar_vlan_rx_kill_vid(struct net_device
*netdev
, uint16_t vid
);
142 void gfar_halt(struct net_device
*dev
);
143 void gfar_start(struct net_device
*dev
);
144 static void gfar_clear_exact_match(struct net_device
*dev
);
145 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
147 extern struct ethtool_ops gfar_ethtool_ops
;
149 MODULE_AUTHOR("Freescale Semiconductor, Inc");
150 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
151 MODULE_LICENSE("GPL");
153 /* Returns 1 if incoming frames use an FCB */
154 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
156 return (priv
->vlan_enable
|| priv
->rx_csum_enable
);
159 /* Set up the ethernet device structure, private data,
160 * and anything else we need before we start */
161 static int gfar_probe(struct platform_device
*pdev
)
164 struct net_device
*dev
= NULL
;
165 struct gfar_private
*priv
= NULL
;
166 struct gianfar_platform_data
*einfo
;
171 einfo
= (struct gianfar_platform_data
*) pdev
->dev
.platform_data
;
174 printk(KERN_ERR
"gfar %d: Missing additional data!\n",
180 /* Create an ethernet device instance */
181 dev
= alloc_etherdev(sizeof (*priv
));
186 priv
= netdev_priv(dev
);
188 /* Set the info in the priv to the current info */
191 /* fill out IRQ fields */
192 if (einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
193 priv
->interruptTransmit
= platform_get_irq_byname(pdev
, "tx");
194 priv
->interruptReceive
= platform_get_irq_byname(pdev
, "rx");
195 priv
->interruptError
= platform_get_irq_byname(pdev
, "error");
196 if (priv
->interruptTransmit
< 0 || priv
->interruptReceive
< 0 || priv
->interruptError
< 0)
199 priv
->interruptTransmit
= platform_get_irq(pdev
, 0);
200 if (priv
->interruptTransmit
< 0)
204 /* get a pointer to the register memory */
205 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
206 priv
->regs
= ioremap(r
->start
, sizeof (struct gfar
));
208 if (NULL
== priv
->regs
) {
213 spin_lock_init(&priv
->lock
);
215 platform_set_drvdata(pdev
, dev
);
217 /* Stop the DMA engine now, in case it was running before */
218 /* (The firmware could have used it, and left it running). */
219 /* To do this, we write Graceful Receive Stop and Graceful */
220 /* Transmit Stop, and then wait until the corresponding bits */
221 /* in IEVENT indicate the stops have completed. */
222 tempval
= gfar_read(&priv
->regs
->dmactrl
);
223 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
224 gfar_write(&priv
->regs
->dmactrl
, tempval
);
226 tempval
= gfar_read(&priv
->regs
->dmactrl
);
227 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
228 gfar_write(&priv
->regs
->dmactrl
, tempval
);
230 while (!(gfar_read(&priv
->regs
->ievent
) & (IEVENT_GRSC
| IEVENT_GTSC
)))
233 /* Reset MAC layer */
234 gfar_write(&priv
->regs
->maccfg1
, MACCFG1_SOFT_RESET
);
236 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
237 gfar_write(&priv
->regs
->maccfg1
, tempval
);
239 /* Initialize MACCFG2. */
240 gfar_write(&priv
->regs
->maccfg2
, MACCFG2_INIT_SETTINGS
);
242 /* Initialize ECNTRL */
243 gfar_write(&priv
->regs
->ecntrl
, ECNTRL_INIT_SETTINGS
);
245 /* Copy the station address into the dev structure, */
246 memcpy(dev
->dev_addr
, einfo
->mac_addr
, MAC_ADDR_LEN
);
248 /* Set the dev->base_addr to the gfar reg region */
249 dev
->base_addr
= (unsigned long) (priv
->regs
);
251 SET_MODULE_OWNER(dev
);
252 SET_NETDEV_DEV(dev
, &pdev
->dev
);
254 /* Fill in the dev structure */
255 dev
->open
= gfar_enet_open
;
256 dev
->hard_start_xmit
= gfar_start_xmit
;
257 dev
->tx_timeout
= gfar_timeout
;
258 dev
->watchdog_timeo
= TX_TIMEOUT
;
259 #ifdef CONFIG_GFAR_NAPI
260 dev
->poll
= gfar_poll
;
261 dev
->weight
= GFAR_DEV_WEIGHT
;
263 dev
->stop
= gfar_close
;
264 dev
->get_stats
= gfar_get_stats
;
265 dev
->change_mtu
= gfar_change_mtu
;
267 dev
->set_multicast_list
= gfar_set_multi
;
269 dev
->ethtool_ops
= &gfar_ethtool_ops
;
271 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
272 priv
->rx_csum_enable
= 1;
273 dev
->features
|= NETIF_F_IP_CSUM
;
275 priv
->rx_csum_enable
= 0;
279 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
280 dev
->vlan_rx_register
= gfar_vlan_rx_register
;
281 dev
->vlan_rx_kill_vid
= gfar_vlan_rx_kill_vid
;
283 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
285 priv
->vlan_enable
= 1;
288 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
289 priv
->extended_hash
= 1;
290 priv
->hash_width
= 9;
292 priv
->hash_regs
[0] = &priv
->regs
->igaddr0
;
293 priv
->hash_regs
[1] = &priv
->regs
->igaddr1
;
294 priv
->hash_regs
[2] = &priv
->regs
->igaddr2
;
295 priv
->hash_regs
[3] = &priv
->regs
->igaddr3
;
296 priv
->hash_regs
[4] = &priv
->regs
->igaddr4
;
297 priv
->hash_regs
[5] = &priv
->regs
->igaddr5
;
298 priv
->hash_regs
[6] = &priv
->regs
->igaddr6
;
299 priv
->hash_regs
[7] = &priv
->regs
->igaddr7
;
300 priv
->hash_regs
[8] = &priv
->regs
->gaddr0
;
301 priv
->hash_regs
[9] = &priv
->regs
->gaddr1
;
302 priv
->hash_regs
[10] = &priv
->regs
->gaddr2
;
303 priv
->hash_regs
[11] = &priv
->regs
->gaddr3
;
304 priv
->hash_regs
[12] = &priv
->regs
->gaddr4
;
305 priv
->hash_regs
[13] = &priv
->regs
->gaddr5
;
306 priv
->hash_regs
[14] = &priv
->regs
->gaddr6
;
307 priv
->hash_regs
[15] = &priv
->regs
->gaddr7
;
310 priv
->extended_hash
= 0;
311 priv
->hash_width
= 8;
313 priv
->hash_regs
[0] = &priv
->regs
->gaddr0
;
314 priv
->hash_regs
[1] = &priv
->regs
->gaddr1
;
315 priv
->hash_regs
[2] = &priv
->regs
->gaddr2
;
316 priv
->hash_regs
[3] = &priv
->regs
->gaddr3
;
317 priv
->hash_regs
[4] = &priv
->regs
->gaddr4
;
318 priv
->hash_regs
[5] = &priv
->regs
->gaddr5
;
319 priv
->hash_regs
[6] = &priv
->regs
->gaddr6
;
320 priv
->hash_regs
[7] = &priv
->regs
->gaddr7
;
323 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
324 priv
->padding
= DEFAULT_PADDING
;
328 if (dev
->features
& NETIF_F_IP_CSUM
)
329 dev
->hard_header_len
+= GMAC_FCB_LEN
;
331 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
332 priv
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
333 priv
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
335 priv
->txcoalescing
= DEFAULT_TX_COALESCE
;
336 priv
->txcount
= DEFAULT_TXCOUNT
;
337 priv
->txtime
= DEFAULT_TXTIME
;
338 priv
->rxcoalescing
= DEFAULT_RX_COALESCE
;
339 priv
->rxcount
= DEFAULT_RXCOUNT
;
340 priv
->rxtime
= DEFAULT_RXTIME
;
342 /* Enable most messages by default */
343 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
345 err
= register_netdev(dev
);
348 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
353 /* Create all the sysfs files */
354 gfar_init_sysfs(dev
);
356 /* Print out the device info */
357 printk(KERN_INFO DEVICE_NAME
, dev
->name
);
358 for (idx
= 0; idx
< 6; idx
++)
359 printk("%2.2x%c", dev
->dev_addr
[idx
], idx
== 5 ? ' ' : ':');
362 /* Even more device info helps when determining which kernel */
363 /* provided which set of benchmarks. */
364 #ifdef CONFIG_GFAR_NAPI
365 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
367 printk(KERN_INFO
"%s: Running with NAPI disabled\n", dev
->name
);
369 printk(KERN_INFO
"%s: %d/%d RX/TX BD ring size\n",
370 dev
->name
, priv
->rx_ring_size
, priv
->tx_ring_size
);
381 static int gfar_remove(struct platform_device
*pdev
)
383 struct net_device
*dev
= platform_get_drvdata(pdev
);
384 struct gfar_private
*priv
= netdev_priv(dev
);
386 platform_set_drvdata(pdev
, NULL
);
395 /* Initializes driver's PHY state, and attaches to the PHY.
396 * Returns 0 on success.
398 static int init_phy(struct net_device
*dev
)
400 struct gfar_private
*priv
= netdev_priv(dev
);
401 uint gigabit_support
=
402 priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
403 SUPPORTED_1000baseT_Full
: 0;
404 struct phy_device
*phydev
;
405 char phy_id
[BUS_ID_SIZE
];
409 priv
->oldduplex
= -1;
411 snprintf(phy_id
, BUS_ID_SIZE
, PHY_ID_FMT
, priv
->einfo
->bus_id
, priv
->einfo
->phy_id
);
413 phydev
= phy_connect(dev
, phy_id
, &adjust_link
, 0);
415 if (IS_ERR(phydev
)) {
416 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
417 return PTR_ERR(phydev
);
420 /* Remove any features not supported by the controller */
421 phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
422 phydev
->advertising
= phydev
->supported
;
424 priv
->phydev
= phydev
;
429 static void init_registers(struct net_device
*dev
)
431 struct gfar_private
*priv
= netdev_priv(dev
);
434 gfar_write(&priv
->regs
->ievent
, IEVENT_INIT_CLEAR
);
436 /* Initialize IMASK */
437 gfar_write(&priv
->regs
->imask
, IMASK_INIT_CLEAR
);
439 /* Init hash registers to zero */
440 gfar_write(&priv
->regs
->igaddr0
, 0);
441 gfar_write(&priv
->regs
->igaddr1
, 0);
442 gfar_write(&priv
->regs
->igaddr2
, 0);
443 gfar_write(&priv
->regs
->igaddr3
, 0);
444 gfar_write(&priv
->regs
->igaddr4
, 0);
445 gfar_write(&priv
->regs
->igaddr5
, 0);
446 gfar_write(&priv
->regs
->igaddr6
, 0);
447 gfar_write(&priv
->regs
->igaddr7
, 0);
449 gfar_write(&priv
->regs
->gaddr0
, 0);
450 gfar_write(&priv
->regs
->gaddr1
, 0);
451 gfar_write(&priv
->regs
->gaddr2
, 0);
452 gfar_write(&priv
->regs
->gaddr3
, 0);
453 gfar_write(&priv
->regs
->gaddr4
, 0);
454 gfar_write(&priv
->regs
->gaddr5
, 0);
455 gfar_write(&priv
->regs
->gaddr6
, 0);
456 gfar_write(&priv
->regs
->gaddr7
, 0);
458 /* Zero out the rmon mib registers if it has them */
459 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
460 memset_io(&(priv
->regs
->rmon
), 0, sizeof (struct rmon_mib
));
462 /* Mask off the CAM interrupts */
463 gfar_write(&priv
->regs
->rmon
.cam1
, 0xffffffff);
464 gfar_write(&priv
->regs
->rmon
.cam2
, 0xffffffff);
467 /* Initialize the max receive buffer length */
468 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
470 /* Initialize the Minimum Frame Length Register */
471 gfar_write(&priv
->regs
->minflr
, MINFLR_INIT_SETTINGS
);
473 /* Assign the TBI an address which won't conflict with the PHYs */
474 gfar_write(&priv
->regs
->tbipa
, TBIPA_VALUE
);
478 /* Halt the receive and transmit queues */
479 void gfar_halt(struct net_device
*dev
)
481 struct gfar_private
*priv
= netdev_priv(dev
);
482 struct gfar __iomem
*regs
= priv
->regs
;
485 /* Mask all interrupts */
486 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
488 /* Clear all interrupts */
489 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
491 /* Stop the DMA, and wait for it to stop */
492 tempval
= gfar_read(&priv
->regs
->dmactrl
);
493 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
494 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
495 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
496 gfar_write(&priv
->regs
->dmactrl
, tempval
);
498 while (!(gfar_read(&priv
->regs
->ievent
) &
499 (IEVENT_GRSC
| IEVENT_GTSC
)))
503 /* Disable Rx and Tx */
504 tempval
= gfar_read(®s
->maccfg1
);
505 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
506 gfar_write(®s
->maccfg1
, tempval
);
509 void stop_gfar(struct net_device
*dev
)
511 struct gfar_private
*priv
= netdev_priv(dev
);
512 struct gfar __iomem
*regs
= priv
->regs
;
515 phy_stop(priv
->phydev
);
518 spin_lock_irqsave(&priv
->lock
, flags
);
522 spin_unlock_irqrestore(&priv
->lock
, flags
);
525 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
526 free_irq(priv
->interruptError
, dev
);
527 free_irq(priv
->interruptTransmit
, dev
);
528 free_irq(priv
->interruptReceive
, dev
);
530 free_irq(priv
->interruptTransmit
, dev
);
533 free_skb_resources(priv
);
535 dma_free_coherent(NULL
,
536 sizeof(struct txbd8
)*priv
->tx_ring_size
537 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
539 gfar_read(®s
->tbase0
));
542 /* If there are any tx skbs or rx skbs still around, free them.
543 * Then free tx_skbuff and rx_skbuff */
544 static void free_skb_resources(struct gfar_private
*priv
)
550 /* Go through all the buffer descriptors and free their data buffers */
551 txbdp
= priv
->tx_bd_base
;
553 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
555 if (priv
->tx_skbuff
[i
]) {
556 dma_unmap_single(NULL
, txbdp
->bufPtr
,
559 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
560 priv
->tx_skbuff
[i
] = NULL
;
564 kfree(priv
->tx_skbuff
);
566 rxbdp
= priv
->rx_bd_base
;
568 /* rx_skbuff is not guaranteed to be allocated, so only
569 * free it and its contents if it is allocated */
570 if(priv
->rx_skbuff
!= NULL
) {
571 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
572 if (priv
->rx_skbuff
[i
]) {
573 dma_unmap_single(NULL
, rxbdp
->bufPtr
,
574 priv
->rx_buffer_size
,
577 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
578 priv
->rx_skbuff
[i
] = NULL
;
588 kfree(priv
->rx_skbuff
);
592 void gfar_start(struct net_device
*dev
)
594 struct gfar_private
*priv
= netdev_priv(dev
);
595 struct gfar __iomem
*regs
= priv
->regs
;
598 /* Enable Rx and Tx in MACCFG1 */
599 tempval
= gfar_read(®s
->maccfg1
);
600 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
601 gfar_write(®s
->maccfg1
, tempval
);
603 /* Initialize DMACTRL to have WWR and WOP */
604 tempval
= gfar_read(&priv
->regs
->dmactrl
);
605 tempval
|= DMACTRL_INIT_SETTINGS
;
606 gfar_write(&priv
->regs
->dmactrl
, tempval
);
608 /* Clear THLT, so that the DMA starts polling now */
609 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
);
611 /* Make sure we aren't stopped */
612 tempval
= gfar_read(&priv
->regs
->dmactrl
);
613 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
614 gfar_write(&priv
->regs
->dmactrl
, tempval
);
616 /* Unmask the interrupts we look for */
617 gfar_write(®s
->imask
, IMASK_DEFAULT
);
620 /* Bring the controller up and running */
621 int startup_gfar(struct net_device
*dev
)
628 struct gfar_private
*priv
= netdev_priv(dev
);
629 struct gfar __iomem
*regs
= priv
->regs
;
634 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
636 /* Allocate memory for the buffer descriptors */
637 vaddr
= (unsigned long) dma_alloc_coherent(NULL
,
638 sizeof (struct txbd8
) * priv
->tx_ring_size
+
639 sizeof (struct rxbd8
) * priv
->rx_ring_size
,
643 if (netif_msg_ifup(priv
))
644 printk(KERN_ERR
"%s: Could not allocate buffer descriptors!\n",
649 priv
->tx_bd_base
= (struct txbd8
*) vaddr
;
651 /* enet DMA only understands physical addresses */
652 gfar_write(®s
->tbase0
, addr
);
654 /* Start the rx descriptor ring where the tx ring leaves off */
655 addr
= addr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
656 vaddr
= vaddr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
657 priv
->rx_bd_base
= (struct rxbd8
*) vaddr
;
658 gfar_write(®s
->rbase0
, addr
);
660 /* Setup the skbuff rings */
662 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
663 priv
->tx_ring_size
, GFP_KERNEL
);
665 if (NULL
== priv
->tx_skbuff
) {
666 if (netif_msg_ifup(priv
))
667 printk(KERN_ERR
"%s: Could not allocate tx_skbuff\n",
673 for (i
= 0; i
< priv
->tx_ring_size
; i
++)
674 priv
->tx_skbuff
[i
] = NULL
;
677 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
678 priv
->rx_ring_size
, GFP_KERNEL
);
680 if (NULL
== priv
->rx_skbuff
) {
681 if (netif_msg_ifup(priv
))
682 printk(KERN_ERR
"%s: Could not allocate rx_skbuff\n",
688 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
689 priv
->rx_skbuff
[i
] = NULL
;
691 /* Initialize some variables in our dev structure */
692 priv
->dirty_tx
= priv
->cur_tx
= priv
->tx_bd_base
;
693 priv
->cur_rx
= priv
->rx_bd_base
;
694 priv
->skb_curtx
= priv
->skb_dirtytx
= 0;
697 /* Initialize Transmit Descriptor Ring */
698 txbdp
= priv
->tx_bd_base
;
699 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
706 /* Set the last descriptor in the ring to indicate wrap */
708 txbdp
->status
|= TXBD_WRAP
;
710 rxbdp
= priv
->rx_bd_base
;
711 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
712 struct sk_buff
*skb
= NULL
;
716 skb
= gfar_new_skb(dev
, rxbdp
);
718 priv
->rx_skbuff
[i
] = skb
;
723 /* Set the last descriptor in the ring to wrap */
725 rxbdp
->status
|= RXBD_WRAP
;
727 /* If the device has multiple interrupts, register for
728 * them. Otherwise, only register for the one */
729 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
730 /* Install our interrupt handlers for Error,
731 * Transmit, and Receive */
732 if (request_irq(priv
->interruptError
, gfar_error
,
733 0, "enet_error", dev
) < 0) {
734 if (netif_msg_intr(priv
))
735 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
736 dev
->name
, priv
->interruptError
);
742 if (request_irq(priv
->interruptTransmit
, gfar_transmit
,
743 0, "enet_tx", dev
) < 0) {
744 if (netif_msg_intr(priv
))
745 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
746 dev
->name
, priv
->interruptTransmit
);
753 if (request_irq(priv
->interruptReceive
, gfar_receive
,
754 0, "enet_rx", dev
) < 0) {
755 if (netif_msg_intr(priv
))
756 printk(KERN_ERR
"%s: Can't get IRQ %d (receive0)\n",
757 dev
->name
, priv
->interruptReceive
);
763 if (request_irq(priv
->interruptTransmit
, gfar_interrupt
,
764 0, "gfar_interrupt", dev
) < 0) {
765 if (netif_msg_intr(priv
))
766 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
767 dev
->name
, priv
->interruptError
);
774 phy_start(priv
->phydev
);
776 /* Configure the coalescing support */
777 if (priv
->txcoalescing
)
778 gfar_write(®s
->txic
,
779 mk_ic_value(priv
->txcount
, priv
->txtime
));
781 gfar_write(®s
->txic
, 0);
783 if (priv
->rxcoalescing
)
784 gfar_write(®s
->rxic
,
785 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
787 gfar_write(®s
->rxic
, 0);
789 if (priv
->rx_csum_enable
)
790 rctrl
|= RCTRL_CHECKSUMMING
;
792 if (priv
->extended_hash
) {
793 rctrl
|= RCTRL_EXTHASH
;
795 gfar_clear_exact_match(dev
);
799 if (priv
->vlan_enable
)
803 rctrl
&= ~RCTRL_PAL_MASK
;
804 rctrl
|= RCTRL_PADDING(priv
->padding
);
807 /* Init rctrl based on our settings */
808 gfar_write(&priv
->regs
->rctrl
, rctrl
);
810 if (dev
->features
& NETIF_F_IP_CSUM
)
811 gfar_write(&priv
->regs
->tctrl
, TCTRL_INIT_CSUM
);
813 /* Set the extraction length and index */
814 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
815 ATTRELI_EI(priv
->rx_stash_index
);
817 gfar_write(&priv
->regs
->attreli
, attrs
);
819 /* Start with defaults, and add stashing or locking
820 * depending on the approprate variables */
821 attrs
= ATTR_INIT_SETTINGS
;
823 if (priv
->bd_stash_en
)
824 attrs
|= ATTR_BDSTASH
;
826 if (priv
->rx_stash_size
!= 0)
827 attrs
|= ATTR_BUFSTASH
;
829 gfar_write(&priv
->regs
->attr
, attrs
);
831 gfar_write(&priv
->regs
->fifo_tx_thr
, priv
->fifo_threshold
);
832 gfar_write(&priv
->regs
->fifo_tx_starve
, priv
->fifo_starve
);
833 gfar_write(&priv
->regs
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
835 /* Start the controller */
841 free_irq(priv
->interruptTransmit
, dev
);
843 free_irq(priv
->interruptError
, dev
);
846 free_skb_resources(priv
);
848 dma_free_coherent(NULL
,
849 sizeof(struct txbd8
)*priv
->tx_ring_size
850 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
852 gfar_read(®s
->tbase0
));
857 /* Called when something needs to use the ethernet device */
858 /* Returns 0 for success. */
859 static int gfar_enet_open(struct net_device
*dev
)
863 /* Initialize a bunch of registers */
866 gfar_set_mac_address(dev
);
873 err
= startup_gfar(dev
);
875 netif_start_queue(dev
);
880 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
, struct txbd8
*bdp
)
882 struct txfcb
*fcb
= (struct txfcb
*)skb_push (skb
, GMAC_FCB_LEN
);
884 memset(fcb
, 0, GMAC_FCB_LEN
);
889 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
893 /* If we're here, it's a IP packet with a TCP or UDP
894 * payload. We set it to checksum, using a pseudo-header
897 flags
= TXFCB_DEFAULT
;
899 /* Tell the controller what the protocol is */
900 /* And provide the already calculated phcs */
901 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
) {
903 fcb
->phcs
= skb
->h
.uh
->check
;
905 fcb
->phcs
= skb
->h
.th
->check
;
907 /* l3os is the distance between the start of the
908 * frame (skb->data) and the start of the IP hdr.
909 * l4os is the distance between the start of the
910 * l3 hdr and the l4 hdr */
911 fcb
->l3os
= (u16
)(skb
->nh
.raw
- skb
->data
- GMAC_FCB_LEN
);
912 fcb
->l4os
= (u16
)(skb
->h
.raw
- skb
->nh
.raw
);
917 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
919 fcb
->flags
|= TXFCB_VLN
;
920 fcb
->vlctl
= vlan_tx_tag_get(skb
);
923 /* This is called by the kernel when a frame is ready for transmission. */
924 /* It is pointed to by the dev->hard_start_xmit function pointer */
925 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
927 struct gfar_private
*priv
= netdev_priv(dev
);
928 struct txfcb
*fcb
= NULL
;
932 /* Update transmit stats */
933 priv
->stats
.tx_bytes
+= skb
->len
;
936 spin_lock_irq(&priv
->lock
);
938 /* Point at the first free tx descriptor */
939 txbdp
= priv
->cur_tx
;
941 /* Clear all but the WRAP status flags */
942 status
= txbdp
->status
& TXBD_WRAP
;
944 /* Set up checksumming */
945 if (likely((dev
->features
& NETIF_F_IP_CSUM
)
946 && (CHECKSUM_HW
== skb
->ip_summed
))) {
947 fcb
= gfar_add_fcb(skb
, txbdp
);
949 gfar_tx_checksum(skb
, fcb
);
952 if (priv
->vlan_enable
&&
953 unlikely(priv
->vlgrp
&& vlan_tx_tag_present(skb
))) {
954 if (unlikely(NULL
== fcb
)) {
955 fcb
= gfar_add_fcb(skb
, txbdp
);
959 gfar_tx_vlan(skb
, fcb
);
962 /* Set buffer length and pointer */
963 txbdp
->length
= skb
->len
;
964 txbdp
->bufPtr
= dma_map_single(NULL
, skb
->data
,
965 skb
->len
, DMA_TO_DEVICE
);
967 /* Save the skb pointer so we can free it later */
968 priv
->tx_skbuff
[priv
->skb_curtx
] = skb
;
970 /* Update the current skb pointer (wrapping if this was the last) */
972 (priv
->skb_curtx
+ 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
974 /* Flag the BD as interrupt-causing */
975 status
|= TXBD_INTERRUPT
;
977 /* Flag the BD as ready to go, last in frame, and */
979 status
|= (TXBD_READY
| TXBD_LAST
| TXBD_CRC
);
981 dev
->trans_start
= jiffies
;
983 txbdp
->status
= status
;
985 /* If this was the last BD in the ring, the next one */
986 /* is at the beginning of the ring */
987 if (txbdp
->status
& TXBD_WRAP
)
988 txbdp
= priv
->tx_bd_base
;
992 /* If the next BD still needs to be cleaned up, then the bds
993 are full. We need to tell the kernel to stop sending us stuff. */
994 if (txbdp
== priv
->dirty_tx
) {
995 netif_stop_queue(dev
);
997 priv
->stats
.tx_fifo_errors
++;
1000 /* Update the current txbd to the next one */
1001 priv
->cur_tx
= txbdp
;
1003 /* Tell the DMA to go go go */
1004 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1007 spin_unlock_irq(&priv
->lock
);
1012 /* Stops the kernel queue, and halts the controller */
1013 static int gfar_close(struct net_device
*dev
)
1015 struct gfar_private
*priv
= netdev_priv(dev
);
1018 /* Disconnect from the PHY */
1019 phy_disconnect(priv
->phydev
);
1020 priv
->phydev
= NULL
;
1022 netif_stop_queue(dev
);
1027 /* returns a net_device_stats structure pointer */
1028 static struct net_device_stats
* gfar_get_stats(struct net_device
*dev
)
1030 struct gfar_private
*priv
= netdev_priv(dev
);
1032 return &(priv
->stats
);
1035 /* Changes the mac address if the controller is not running. */
1036 int gfar_set_mac_address(struct net_device
*dev
)
1038 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
1044 /* Enables and disables VLAN insertion/extraction */
1045 static void gfar_vlan_rx_register(struct net_device
*dev
,
1046 struct vlan_group
*grp
)
1048 struct gfar_private
*priv
= netdev_priv(dev
);
1049 unsigned long flags
;
1052 spin_lock_irqsave(&priv
->lock
, flags
);
1057 /* Enable VLAN tag insertion */
1058 tempval
= gfar_read(&priv
->regs
->tctrl
);
1059 tempval
|= TCTRL_VLINS
;
1061 gfar_write(&priv
->regs
->tctrl
, tempval
);
1063 /* Enable VLAN tag extraction */
1064 tempval
= gfar_read(&priv
->regs
->rctrl
);
1065 tempval
|= RCTRL_VLEX
;
1066 gfar_write(&priv
->regs
->rctrl
, tempval
);
1068 /* Disable VLAN tag insertion */
1069 tempval
= gfar_read(&priv
->regs
->tctrl
);
1070 tempval
&= ~TCTRL_VLINS
;
1071 gfar_write(&priv
->regs
->tctrl
, tempval
);
1073 /* Disable VLAN tag extraction */
1074 tempval
= gfar_read(&priv
->regs
->rctrl
);
1075 tempval
&= ~RCTRL_VLEX
;
1076 gfar_write(&priv
->regs
->rctrl
, tempval
);
1079 spin_unlock_irqrestore(&priv
->lock
, flags
);
1083 static void gfar_vlan_rx_kill_vid(struct net_device
*dev
, uint16_t vid
)
1085 struct gfar_private
*priv
= netdev_priv(dev
);
1086 unsigned long flags
;
1088 spin_lock_irqsave(&priv
->lock
, flags
);
1091 priv
->vlgrp
->vlan_devices
[vid
] = NULL
;
1093 spin_unlock_irqrestore(&priv
->lock
, flags
);
1097 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
1099 int tempsize
, tempval
;
1100 struct gfar_private
*priv
= netdev_priv(dev
);
1101 int oldsize
= priv
->rx_buffer_size
;
1102 int frame_size
= new_mtu
+ ETH_HLEN
;
1104 if (priv
->vlan_enable
)
1105 frame_size
+= VLAN_ETH_HLEN
;
1107 if (gfar_uses_fcb(priv
))
1108 frame_size
+= GMAC_FCB_LEN
;
1110 frame_size
+= priv
->padding
;
1112 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
1113 if (netif_msg_drv(priv
))
1114 printk(KERN_ERR
"%s: Invalid MTU setting\n",
1120 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
1121 INCREMENTAL_BUFFER_SIZE
;
1123 /* Only stop and start the controller if it isn't already
1124 * stopped, and we changed something */
1125 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1128 priv
->rx_buffer_size
= tempsize
;
1132 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
1133 gfar_write(&priv
->regs
->maxfrm
, priv
->rx_buffer_size
);
1135 /* If the mtu is larger than the max size for standard
1136 * ethernet frames (ie, a jumbo frame), then set maccfg2
1137 * to allow huge frames, and to check the length */
1138 tempval
= gfar_read(&priv
->regs
->maccfg2
);
1140 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
1141 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1143 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1145 gfar_write(&priv
->regs
->maccfg2
, tempval
);
1147 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1153 /* gfar_timeout gets called when a packet has not been
1154 * transmitted after a set amount of time.
1155 * For now, assume that clearing out all the structures, and
1156 * starting over will fix the problem. */
1157 static void gfar_timeout(struct net_device
*dev
)
1159 struct gfar_private
*priv
= netdev_priv(dev
);
1161 priv
->stats
.tx_errors
++;
1163 if (dev
->flags
& IFF_UP
) {
1168 netif_schedule(dev
);
1171 /* Interrupt Handler for Transmit complete */
1172 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
, struct pt_regs
*regs
)
1174 struct net_device
*dev
= (struct net_device
*) dev_id
;
1175 struct gfar_private
*priv
= netdev_priv(dev
);
1179 gfar_write(&priv
->regs
->ievent
, IEVENT_TX_MASK
);
1182 spin_lock(&priv
->lock
);
1183 bdp
= priv
->dirty_tx
;
1184 while ((bdp
->status
& TXBD_READY
) == 0) {
1185 /* If dirty_tx and cur_tx are the same, then either the */
1186 /* ring is empty or full now (it could only be full in the beginning, */
1187 /* obviously). If it is empty, we are done. */
1188 if ((bdp
== priv
->cur_tx
) && (netif_queue_stopped(dev
) == 0))
1191 priv
->stats
.tx_packets
++;
1193 /* Deferred means some collisions occurred during transmit, */
1194 /* but we eventually sent the packet. */
1195 if (bdp
->status
& TXBD_DEF
)
1196 priv
->stats
.collisions
++;
1198 /* Free the sk buffer associated with this TxBD */
1199 dev_kfree_skb_irq(priv
->tx_skbuff
[priv
->skb_dirtytx
]);
1200 priv
->tx_skbuff
[priv
->skb_dirtytx
] = NULL
;
1202 (priv
->skb_dirtytx
+
1203 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1205 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1206 if (bdp
->status
& TXBD_WRAP
)
1207 bdp
= priv
->tx_bd_base
;
1211 /* Move dirty_tx to be the next bd */
1212 priv
->dirty_tx
= bdp
;
1214 /* We freed a buffer, so now we can restart transmission */
1215 if (netif_queue_stopped(dev
))
1216 netif_wake_queue(dev
);
1217 } /* while ((bdp->status & TXBD_READY) == 0) */
1219 /* If we are coalescing the interrupts, reset the timer */
1220 /* Otherwise, clear it */
1221 if (priv
->txcoalescing
)
1222 gfar_write(&priv
->regs
->txic
,
1223 mk_ic_value(priv
->txcount
, priv
->txtime
));
1225 gfar_write(&priv
->regs
->txic
, 0);
1227 spin_unlock(&priv
->lock
);
1232 struct sk_buff
* gfar_new_skb(struct net_device
*dev
, struct rxbd8
*bdp
)
1234 unsigned int alignamount
;
1235 struct gfar_private
*priv
= netdev_priv(dev
);
1236 struct sk_buff
*skb
= NULL
;
1237 unsigned int timeout
= SKB_ALLOC_TIMEOUT
;
1239 /* We have to allocate the skb, so keep trying till we succeed */
1240 while ((!skb
) && timeout
--)
1241 skb
= dev_alloc_skb(priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
1246 alignamount
= RXBUF_ALIGNMENT
-
1247 (((unsigned) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
1249 /* We need the data buffer to be aligned properly. We will reserve
1250 * as many bytes as needed to align the data properly
1252 skb_reserve(skb
, alignamount
);
1256 bdp
->bufPtr
= dma_map_single(NULL
, skb
->data
,
1257 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1261 /* Mark the buffer empty */
1262 bdp
->status
|= (RXBD_EMPTY
| RXBD_INTERRUPT
);
1267 static inline void count_errors(unsigned short status
, struct gfar_private
*priv
)
1269 struct net_device_stats
*stats
= &priv
->stats
;
1270 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
1272 /* If the packet was truncated, none of the other errors
1274 if (status
& RXBD_TRUNCATED
) {
1275 stats
->rx_length_errors
++;
1281 /* Count the errors, if there were any */
1282 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
1283 stats
->rx_length_errors
++;
1285 if (status
& RXBD_LARGE
)
1290 if (status
& RXBD_NONOCTET
) {
1291 stats
->rx_frame_errors
++;
1292 estats
->rx_nonoctet
++;
1294 if (status
& RXBD_CRCERR
) {
1295 estats
->rx_crcerr
++;
1296 stats
->rx_crc_errors
++;
1298 if (status
& RXBD_OVERRUN
) {
1299 estats
->rx_overrun
++;
1300 stats
->rx_crc_errors
++;
1304 irqreturn_t
gfar_receive(int irq
, void *dev_id
, struct pt_regs
*regs
)
1306 struct net_device
*dev
= (struct net_device
*) dev_id
;
1307 struct gfar_private
*priv
= netdev_priv(dev
);
1309 #ifdef CONFIG_GFAR_NAPI
1313 /* Clear IEVENT, so rx interrupt isn't called again
1314 * because of this interrupt */
1315 gfar_write(&priv
->regs
->ievent
, IEVENT_RX_MASK
);
1318 #ifdef CONFIG_GFAR_NAPI
1319 if (netif_rx_schedule_prep(dev
)) {
1320 tempval
= gfar_read(&priv
->regs
->imask
);
1321 tempval
&= IMASK_RX_DISABLED
;
1322 gfar_write(&priv
->regs
->imask
, tempval
);
1324 __netif_rx_schedule(dev
);
1326 if (netif_msg_rx_err(priv
))
1327 printk(KERN_DEBUG
"%s: receive called twice (%x)[%x]\n",
1328 dev
->name
, gfar_read(&priv
->regs
->ievent
),
1329 gfar_read(&priv
->regs
->imask
));
1333 spin_lock(&priv
->lock
);
1334 gfar_clean_rx_ring(dev
, priv
->rx_ring_size
);
1336 /* If we are coalescing interrupts, update the timer */
1337 /* Otherwise, clear it */
1338 if (priv
->rxcoalescing
)
1339 gfar_write(&priv
->regs
->rxic
,
1340 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
1342 gfar_write(&priv
->regs
->rxic
, 0);
1344 spin_unlock(&priv
->lock
);
1350 static inline int gfar_rx_vlan(struct sk_buff
*skb
,
1351 struct vlan_group
*vlgrp
, unsigned short vlctl
)
1353 #ifdef CONFIG_GFAR_NAPI
1354 return vlan_hwaccel_receive_skb(skb
, vlgrp
, vlctl
);
1356 return vlan_hwaccel_rx(skb
, vlgrp
, vlctl
);
1360 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
1362 /* If valid headers were found, and valid sums
1363 * were verified, then we tell the kernel that no
1364 * checksumming is necessary. Otherwise, it is */
1365 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
1366 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1368 skb
->ip_summed
= CHECKSUM_NONE
;
1372 static inline struct rxfcb
*gfar_get_fcb(struct sk_buff
*skb
)
1374 struct rxfcb
*fcb
= (struct rxfcb
*)skb
->data
;
1376 /* Remove the FCB from the skb */
1377 skb_pull(skb
, GMAC_FCB_LEN
);
1382 /* gfar_process_frame() -- handle one incoming packet if skb
1384 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
1387 struct gfar_private
*priv
= netdev_priv(dev
);
1388 struct rxfcb
*fcb
= NULL
;
1391 if (netif_msg_rx_err(priv
))
1392 printk(KERN_WARNING
"%s: Missing skb!!.\n", dev
->name
);
1393 priv
->stats
.rx_dropped
++;
1394 priv
->extra_stats
.rx_skbmissing
++;
1398 /* Prep the skb for the packet */
1399 skb_put(skb
, length
);
1401 /* Grab the FCB if there is one */
1402 if (gfar_uses_fcb(priv
))
1403 fcb
= gfar_get_fcb(skb
);
1405 /* Remove the padded bytes, if there are any */
1407 skb_pull(skb
, priv
->padding
);
1409 if (priv
->rx_csum_enable
)
1410 gfar_rx_checksum(skb
, fcb
);
1412 /* Tell the skb what kind of packet this is */
1413 skb
->protocol
= eth_type_trans(skb
, dev
);
1415 /* Send the packet up the stack */
1416 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
)))
1417 ret
= gfar_rx_vlan(skb
, priv
->vlgrp
, fcb
->vlctl
);
1421 if (NET_RX_DROP
== ret
)
1422 priv
->extra_stats
.kernel_dropped
++;
1428 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1429 * until the budget/quota has been reached. Returns the number
1432 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
)
1435 struct sk_buff
*skb
;
1438 struct gfar_private
*priv
= netdev_priv(dev
);
1440 /* Get the first full descriptor */
1443 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
1444 skb
= priv
->rx_skbuff
[priv
->skb_currx
];
1447 (RXBD_LARGE
| RXBD_SHORT
| RXBD_NONOCTET
1448 | RXBD_CRCERR
| RXBD_OVERRUN
| RXBD_TRUNCATED
))) {
1449 /* Increment the number of packets */
1450 priv
->stats
.rx_packets
++;
1453 /* Remove the FCS from the packet length */
1454 pkt_len
= bdp
->length
- 4;
1456 gfar_process_frame(dev
, skb
, pkt_len
);
1458 priv
->stats
.rx_bytes
+= pkt_len
;
1460 count_errors(bdp
->status
, priv
);
1463 dev_kfree_skb_any(skb
);
1465 priv
->rx_skbuff
[priv
->skb_currx
] = NULL
;
1468 dev
->last_rx
= jiffies
;
1470 /* Clear the status flags for this buffer */
1471 bdp
->status
&= ~RXBD_STATS
;
1473 /* Add another skb for the future */
1474 skb
= gfar_new_skb(dev
, bdp
);
1475 priv
->rx_skbuff
[priv
->skb_currx
] = skb
;
1477 /* Update to the next pointer */
1478 if (bdp
->status
& RXBD_WRAP
)
1479 bdp
= priv
->rx_bd_base
;
1483 /* update to point at the next skb */
1486 1) & RX_RING_MOD_MASK(priv
->rx_ring_size
);
1490 /* Update the current rxbd pointer to be the next one */
1493 /* If no packets have arrived since the
1494 * last one we processed, clear the IEVENT RX and
1495 * BSY bits so that another interrupt won't be
1496 * generated when we set IMASK */
1497 if (bdp
->status
& RXBD_EMPTY
)
1498 gfar_write(&priv
->regs
->ievent
, IEVENT_RX_MASK
);
1503 #ifdef CONFIG_GFAR_NAPI
1504 static int gfar_poll(struct net_device
*dev
, int *budget
)
1507 struct gfar_private
*priv
= netdev_priv(dev
);
1508 int rx_work_limit
= *budget
;
1510 if (rx_work_limit
> dev
->quota
)
1511 rx_work_limit
= dev
->quota
;
1513 howmany
= gfar_clean_rx_ring(dev
, rx_work_limit
);
1515 dev
->quota
-= howmany
;
1516 rx_work_limit
-= howmany
;
1519 if (rx_work_limit
>= 0) {
1520 netif_rx_complete(dev
);
1522 /* Clear the halt bit in RSTAT */
1523 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1525 gfar_write(&priv
->regs
->imask
, IMASK_DEFAULT
);
1527 /* If we are coalescing interrupts, update the timer */
1528 /* Otherwise, clear it */
1529 if (priv
->rxcoalescing
)
1530 gfar_write(&priv
->regs
->rxic
,
1531 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
1533 gfar_write(&priv
->regs
->rxic
, 0);
1536 return (rx_work_limit
< 0) ? 1 : 0;
1540 /* The interrupt handler for devices with one interrupt */
1541 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
1543 struct net_device
*dev
= dev_id
;
1544 struct gfar_private
*priv
= netdev_priv(dev
);
1546 /* Save ievent for future reference */
1547 u32 events
= gfar_read(&priv
->regs
->ievent
);
1550 gfar_write(&priv
->regs
->ievent
, events
);
1552 /* Check for reception */
1553 if ((events
& IEVENT_RXF0
) || (events
& IEVENT_RXB0
))
1554 gfar_receive(irq
, dev_id
, regs
);
1556 /* Check for transmit completion */
1557 if ((events
& IEVENT_TXF
) || (events
& IEVENT_TXB
))
1558 gfar_transmit(irq
, dev_id
, regs
);
1560 /* Update error statistics */
1561 if (events
& IEVENT_TXE
) {
1562 priv
->stats
.tx_errors
++;
1564 if (events
& IEVENT_LC
)
1565 priv
->stats
.tx_window_errors
++;
1566 if (events
& IEVENT_CRL
)
1567 priv
->stats
.tx_aborted_errors
++;
1568 if (events
& IEVENT_XFUN
) {
1569 if (netif_msg_tx_err(priv
))
1570 printk(KERN_WARNING
"%s: tx underrun. dropped packet\n", dev
->name
);
1571 priv
->stats
.tx_dropped
++;
1572 priv
->extra_stats
.tx_underrun
++;
1574 /* Reactivate the Tx Queues */
1575 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1578 if (events
& IEVENT_BSY
) {
1579 priv
->stats
.rx_errors
++;
1580 priv
->extra_stats
.rx_bsy
++;
1582 gfar_receive(irq
, dev_id
, regs
);
1584 #ifndef CONFIG_GFAR_NAPI
1585 /* Clear the halt bit in RSTAT */
1586 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1589 if (netif_msg_rx_err(priv
))
1590 printk(KERN_DEBUG
"%s: busy error (rhalt: %x)\n",
1592 gfar_read(&priv
->regs
->rstat
));
1594 if (events
& IEVENT_BABR
) {
1595 priv
->stats
.rx_errors
++;
1596 priv
->extra_stats
.rx_babr
++;
1598 if (netif_msg_rx_err(priv
))
1599 printk(KERN_DEBUG
"%s: babbling error\n", dev
->name
);
1601 if (events
& IEVENT_EBERR
) {
1602 priv
->extra_stats
.eberr
++;
1603 if (netif_msg_rx_err(priv
))
1604 printk(KERN_DEBUG
"%s: EBERR\n", dev
->name
);
1606 if ((events
& IEVENT_RXC
) && (netif_msg_rx_err(priv
)))
1607 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
1609 if (events
& IEVENT_BABT
) {
1610 priv
->extra_stats
.tx_babt
++;
1611 if (netif_msg_rx_err(priv
))
1612 printk(KERN_DEBUG
"%s: babt error\n", dev
->name
);
1618 /* Called every time the controller might need to be made
1619 * aware of new link state. The PHY code conveys this
1620 * information through variables in the phydev structure, and this
1621 * function converts those variables into the appropriate
1622 * register values, and can bring down the device if needed.
1624 static void adjust_link(struct net_device
*dev
)
1626 struct gfar_private
*priv
= netdev_priv(dev
);
1627 struct gfar __iomem
*regs
= priv
->regs
;
1628 unsigned long flags
;
1629 struct phy_device
*phydev
= priv
->phydev
;
1632 spin_lock_irqsave(&priv
->lock
, flags
);
1634 u32 tempval
= gfar_read(®s
->maccfg2
);
1635 u32 ecntrl
= gfar_read(®s
->ecntrl
);
1637 /* Now we make sure that we can be in full duplex mode.
1638 * If not, we operate in half-duplex mode. */
1639 if (phydev
->duplex
!= priv
->oldduplex
) {
1641 if (!(phydev
->duplex
))
1642 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
1644 tempval
|= MACCFG2_FULL_DUPLEX
;
1646 priv
->oldduplex
= phydev
->duplex
;
1649 if (phydev
->speed
!= priv
->oldspeed
) {
1651 switch (phydev
->speed
) {
1654 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
1659 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
1661 /* Reduced mode distinguishes
1662 * between 10 and 100 */
1663 if (phydev
->speed
== SPEED_100
)
1664 ecntrl
|= ECNTRL_R100
;
1666 ecntrl
&= ~(ECNTRL_R100
);
1669 if (netif_msg_link(priv
))
1671 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1672 dev
->name
, phydev
->speed
);
1676 priv
->oldspeed
= phydev
->speed
;
1679 gfar_write(®s
->maccfg2
, tempval
);
1680 gfar_write(®s
->ecntrl
, ecntrl
);
1682 if (!priv
->oldlink
) {
1685 netif_schedule(dev
);
1687 } else if (priv
->oldlink
) {
1691 priv
->oldduplex
= -1;
1694 if (new_state
&& netif_msg_link(priv
))
1695 phy_print_status(phydev
);
1697 spin_unlock_irqrestore(&priv
->lock
, flags
);
1700 /* Update the hash table based on the current list of multicast
1701 * addresses we subscribe to. Also, change the promiscuity of
1702 * the device based on the flags (this function is called
1703 * whenever dev->flags is changed */
1704 static void gfar_set_multi(struct net_device
*dev
)
1706 struct dev_mc_list
*mc_ptr
;
1707 struct gfar_private
*priv
= netdev_priv(dev
);
1708 struct gfar __iomem
*regs
= priv
->regs
;
1711 if(dev
->flags
& IFF_PROMISC
) {
1712 if (netif_msg_drv(priv
))
1713 printk(KERN_INFO
"%s: Entering promiscuous mode.\n",
1715 /* Set RCTRL to PROM */
1716 tempval
= gfar_read(®s
->rctrl
);
1717 tempval
|= RCTRL_PROM
;
1718 gfar_write(®s
->rctrl
, tempval
);
1720 /* Set RCTRL to not PROM */
1721 tempval
= gfar_read(®s
->rctrl
);
1722 tempval
&= ~(RCTRL_PROM
);
1723 gfar_write(®s
->rctrl
, tempval
);
1726 if(dev
->flags
& IFF_ALLMULTI
) {
1727 /* Set the hash to rx all multicast frames */
1728 gfar_write(®s
->igaddr0
, 0xffffffff);
1729 gfar_write(®s
->igaddr1
, 0xffffffff);
1730 gfar_write(®s
->igaddr2
, 0xffffffff);
1731 gfar_write(®s
->igaddr3
, 0xffffffff);
1732 gfar_write(®s
->igaddr4
, 0xffffffff);
1733 gfar_write(®s
->igaddr5
, 0xffffffff);
1734 gfar_write(®s
->igaddr6
, 0xffffffff);
1735 gfar_write(®s
->igaddr7
, 0xffffffff);
1736 gfar_write(®s
->gaddr0
, 0xffffffff);
1737 gfar_write(®s
->gaddr1
, 0xffffffff);
1738 gfar_write(®s
->gaddr2
, 0xffffffff);
1739 gfar_write(®s
->gaddr3
, 0xffffffff);
1740 gfar_write(®s
->gaddr4
, 0xffffffff);
1741 gfar_write(®s
->gaddr5
, 0xffffffff);
1742 gfar_write(®s
->gaddr6
, 0xffffffff);
1743 gfar_write(®s
->gaddr7
, 0xffffffff);
1748 /* zero out the hash */
1749 gfar_write(®s
->igaddr0
, 0x0);
1750 gfar_write(®s
->igaddr1
, 0x0);
1751 gfar_write(®s
->igaddr2
, 0x0);
1752 gfar_write(®s
->igaddr3
, 0x0);
1753 gfar_write(®s
->igaddr4
, 0x0);
1754 gfar_write(®s
->igaddr5
, 0x0);
1755 gfar_write(®s
->igaddr6
, 0x0);
1756 gfar_write(®s
->igaddr7
, 0x0);
1757 gfar_write(®s
->gaddr0
, 0x0);
1758 gfar_write(®s
->gaddr1
, 0x0);
1759 gfar_write(®s
->gaddr2
, 0x0);
1760 gfar_write(®s
->gaddr3
, 0x0);
1761 gfar_write(®s
->gaddr4
, 0x0);
1762 gfar_write(®s
->gaddr5
, 0x0);
1763 gfar_write(®s
->gaddr6
, 0x0);
1764 gfar_write(®s
->gaddr7
, 0x0);
1766 /* If we have extended hash tables, we need to
1767 * clear the exact match registers to prepare for
1769 if (priv
->extended_hash
) {
1770 em_num
= GFAR_EM_NUM
+ 1;
1771 gfar_clear_exact_match(dev
);
1778 if(dev
->mc_count
== 0)
1781 /* Parse the list, and set the appropriate bits */
1782 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
1784 gfar_set_mac_for_addr(dev
, idx
,
1788 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
1796 /* Clears each of the exact match registers to zero, so they
1797 * don't interfere with normal reception */
1798 static void gfar_clear_exact_match(struct net_device
*dev
)
1801 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
1803 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
1804 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
1807 /* Set the appropriate hash bit for the given addr */
1808 /* The algorithm works like so:
1809 * 1) Take the Destination Address (ie the multicast address), and
1810 * do a CRC on it (little endian), and reverse the bits of the
1812 * 2) Use the 8 most significant bits as a hash into a 256-entry
1813 * table. The table is controlled through 8 32-bit registers:
1814 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1815 * gaddr7. This means that the 3 most significant bits in the
1816 * hash index which gaddr register to use, and the 5 other bits
1817 * indicate which bit (assuming an IBM numbering scheme, which
1818 * for PowerPC (tm) is usually the case) in the register holds
1820 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
1823 struct gfar_private
*priv
= netdev_priv(dev
);
1824 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
1825 int width
= priv
->hash_width
;
1826 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
1827 u8 whichreg
= result
>> (32 - width
+ 5);
1828 u32 value
= (1 << (31-whichbit
));
1830 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
1832 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
1838 /* There are multiple MAC Address register pairs on some controllers
1839 * This function sets the numth pair to a given address
1841 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
1843 struct gfar_private
*priv
= netdev_priv(dev
);
1845 char tmpbuf
[MAC_ADDR_LEN
];
1847 u32 __iomem
*macptr
= &priv
->regs
->macstnaddr1
;
1851 /* Now copy it into the mac registers backwards, cuz */
1852 /* little endian is silly */
1853 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
1854 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
1856 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
1858 tempval
= *((u32
*) (tmpbuf
+ 4));
1860 gfar_write(macptr
+1, tempval
);
1863 /* GFAR error interrupt handler */
1864 static irqreturn_t
gfar_error(int irq
, void *dev_id
, struct pt_regs
*regs
)
1866 struct net_device
*dev
= dev_id
;
1867 struct gfar_private
*priv
= netdev_priv(dev
);
1869 /* Save ievent for future reference */
1870 u32 events
= gfar_read(&priv
->regs
->ievent
);
1873 gfar_write(&priv
->regs
->ievent
, IEVENT_ERR_MASK
);
1876 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
1877 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1878 dev
->name
, events
, gfar_read(&priv
->regs
->imask
));
1880 /* Update the error counters */
1881 if (events
& IEVENT_TXE
) {
1882 priv
->stats
.tx_errors
++;
1884 if (events
& IEVENT_LC
)
1885 priv
->stats
.tx_window_errors
++;
1886 if (events
& IEVENT_CRL
)
1887 priv
->stats
.tx_aborted_errors
++;
1888 if (events
& IEVENT_XFUN
) {
1889 if (netif_msg_tx_err(priv
))
1890 printk(KERN_DEBUG
"%s: underrun. packet dropped.\n",
1892 priv
->stats
.tx_dropped
++;
1893 priv
->extra_stats
.tx_underrun
++;
1895 /* Reactivate the Tx Queues */
1896 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1898 if (netif_msg_tx_err(priv
))
1899 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
1901 if (events
& IEVENT_BSY
) {
1902 priv
->stats
.rx_errors
++;
1903 priv
->extra_stats
.rx_bsy
++;
1905 gfar_receive(irq
, dev_id
, regs
);
1907 #ifndef CONFIG_GFAR_NAPI
1908 /* Clear the halt bit in RSTAT */
1909 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1912 if (netif_msg_rx_err(priv
))
1913 printk(KERN_DEBUG
"%s: busy error (rhalt: %x)\n",
1915 gfar_read(&priv
->regs
->rstat
));
1917 if (events
& IEVENT_BABR
) {
1918 priv
->stats
.rx_errors
++;
1919 priv
->extra_stats
.rx_babr
++;
1921 if (netif_msg_rx_err(priv
))
1922 printk(KERN_DEBUG
"%s: babbling error\n", dev
->name
);
1924 if (events
& IEVENT_EBERR
) {
1925 priv
->extra_stats
.eberr
++;
1926 if (netif_msg_rx_err(priv
))
1927 printk(KERN_DEBUG
"%s: EBERR\n", dev
->name
);
1929 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
1930 if (netif_msg_rx_status(priv
))
1931 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
1933 if (events
& IEVENT_BABT
) {
1934 priv
->extra_stats
.tx_babt
++;
1935 if (netif_msg_tx_err(priv
))
1936 printk(KERN_DEBUG
"%s: babt error\n", dev
->name
);
1941 /* Structure for a device driver */
1942 static struct platform_driver gfar_driver
= {
1943 .probe
= gfar_probe
,
1944 .remove
= gfar_remove
,
1946 .name
= "fsl-gianfar",
1950 static int __init
gfar_init(void)
1952 int err
= gfar_mdio_init();
1957 err
= platform_driver_register(&gfar_driver
);
1965 static void __exit
gfar_exit(void)
1967 platform_driver_unregister(&gfar_driver
);
1971 module_init(gfar_init
);
1972 module_exit(gfar_exit
);