2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through platform_device. Structures which
29 * define the configuration needed by the board are defined in a
30 * board structure in arch/ppc/platforms (though I do not
31 * discount the possibility that other architectures could one
34 * The Gianfar Ethernet Controller uses a ring of buffer
35 * descriptors. The beginning is indicated by a register
36 * pointing to the physical address of the start of the ring.
37 * The end is determined by a "wrap" bit being set in the
38 * last descriptor of the ring.
40 * When a packet is received, the RXF bit in the
41 * IEVENT register is set, triggering an interrupt when the
42 * corresponding bit in the IMASK register is also set (if
43 * interrupt coalescing is active, then the interrupt may not
44 * happen immediately, but will wait until either a set number
45 * of frames or amount of time have passed). In NAPI, the
46 * interrupt handler will signal there is work to be done, and
47 * exit. This method will start at the last known empty
48 * descriptor, and process every subsequent descriptor until there
49 * are none left with data (NAPI will stop after a set number of
50 * packets to give time to other tasks, but will eventually
51 * process all the packets). The data arrives inside a
52 * pre-allocated skb, and so after the skb is passed up to the
53 * stack, a new skb must be allocated, and the address field in
54 * the buffer descriptor must be updated to indicate this new
57 * When the kernel requests that a packet be transmitted, the
58 * driver starts where it left off last time, and points the
59 * descriptor at the buffer which was passed in. The driver
60 * then informs the DMA engine that there are packets ready to
61 * be transmitted. Once the controller is finished transmitting
62 * the packet, an interrupt may be triggered (under the same
63 * conditions as for reception, but depending on the TXF bit).
64 * The driver then cleans up the buffer.
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
81 #include <linux/platform_device.h>
83 #include <linux/tcp.h>
84 #include <linux/udp.h>
89 #include <asm/uaccess.h>
90 #include <linux/module.h>
91 #include <linux/dma-mapping.h>
92 #include <linux/crc32.h>
93 #include <linux/mii.h>
94 #include <linux/phy.h>
97 #include "gianfar_mii.h"
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
103 const char gfar_driver_name
[] = "Gianfar Ethernet";
104 const char gfar_driver_version
[] = "1.3";
106 static int gfar_enet_open(struct net_device
*dev
);
107 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
108 static void gfar_timeout(struct net_device
*dev
);
109 static int gfar_close(struct net_device
*dev
);
110 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
111 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
112 struct sk_buff
*skb
);
113 static int gfar_set_mac_address(struct net_device
*dev
);
114 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
115 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
116 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
117 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
118 static void adjust_link(struct net_device
*dev
);
119 static void init_registers(struct net_device
*dev
);
120 static int init_phy(struct net_device
*dev
);
121 static int gfar_probe(struct platform_device
*pdev
);
122 static int gfar_remove(struct platform_device
*pdev
);
123 static void free_skb_resources(struct gfar_private
*priv
);
124 static void gfar_set_multi(struct net_device
*dev
);
125 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
126 static void gfar_configure_serdes(struct net_device
*dev
);
127 static int gfar_poll(struct napi_struct
*napi
, int budget
);
128 #ifdef CONFIG_NET_POLL_CONTROLLER
129 static void gfar_netpoll(struct net_device
*dev
);
131 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
);
132 static int gfar_clean_tx_ring(struct net_device
*dev
);
133 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
, int length
);
134 static void gfar_vlan_rx_register(struct net_device
*netdev
,
135 struct vlan_group
*grp
);
136 void gfar_halt(struct net_device
*dev
);
138 static void gfar_halt_nodisable(struct net_device
*dev
);
140 void gfar_start(struct net_device
*dev
);
141 static void gfar_clear_exact_match(struct net_device
*dev
);
142 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
144 extern const struct ethtool_ops gfar_ethtool_ops
;
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 /* Returns 1 if incoming frames use an FCB */
151 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
153 return (priv
->vlan_enable
|| priv
->rx_csum_enable
);
156 /* Set up the ethernet device structure, private data,
157 * and anything else we need before we start */
158 static int gfar_probe(struct platform_device
*pdev
)
161 struct net_device
*dev
= NULL
;
162 struct gfar_private
*priv
= NULL
;
163 struct gianfar_platform_data
*einfo
;
166 DECLARE_MAC_BUF(mac
);
168 einfo
= (struct gianfar_platform_data
*) pdev
->dev
.platform_data
;
171 printk(KERN_ERR
"gfar %d: Missing additional data!\n",
177 /* Create an ethernet device instance */
178 dev
= alloc_etherdev(sizeof (*priv
));
183 priv
= netdev_priv(dev
);
186 /* Set the info in the priv to the current info */
189 /* fill out IRQ fields */
190 if (einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
191 priv
->interruptTransmit
= platform_get_irq_byname(pdev
, "tx");
192 priv
->interruptReceive
= platform_get_irq_byname(pdev
, "rx");
193 priv
->interruptError
= platform_get_irq_byname(pdev
, "error");
194 if (priv
->interruptTransmit
< 0 || priv
->interruptReceive
< 0 || priv
->interruptError
< 0)
197 priv
->interruptTransmit
= platform_get_irq(pdev
, 0);
198 if (priv
->interruptTransmit
< 0)
202 /* get a pointer to the register memory */
203 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
204 priv
->regs
= ioremap(r
->start
, sizeof (struct gfar
));
206 if (NULL
== priv
->regs
) {
211 spin_lock_init(&priv
->txlock
);
212 spin_lock_init(&priv
->rxlock
);
213 spin_lock_init(&priv
->bflock
);
215 platform_set_drvdata(pdev
, dev
);
217 /* Stop the DMA engine now, in case it was running before */
218 /* (The firmware could have used it, and left it running). */
219 /* To do this, we write Graceful Receive Stop and Graceful */
220 /* Transmit Stop, and then wait until the corresponding bits */
221 /* in IEVENT indicate the stops have completed. */
222 tempval
= gfar_read(&priv
->regs
->dmactrl
);
223 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
224 gfar_write(&priv
->regs
->dmactrl
, tempval
);
226 tempval
= gfar_read(&priv
->regs
->dmactrl
);
227 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
228 gfar_write(&priv
->regs
->dmactrl
, tempval
);
230 while (!(gfar_read(&priv
->regs
->ievent
) & (IEVENT_GRSC
| IEVENT_GTSC
)))
233 /* Reset MAC layer */
234 gfar_write(&priv
->regs
->maccfg1
, MACCFG1_SOFT_RESET
);
236 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
237 gfar_write(&priv
->regs
->maccfg1
, tempval
);
239 /* Initialize MACCFG2. */
240 gfar_write(&priv
->regs
->maccfg2
, MACCFG2_INIT_SETTINGS
);
242 /* Initialize ECNTRL */
243 gfar_write(&priv
->regs
->ecntrl
, ECNTRL_INIT_SETTINGS
);
245 /* Copy the station address into the dev structure, */
246 memcpy(dev
->dev_addr
, einfo
->mac_addr
, MAC_ADDR_LEN
);
248 /* Set the dev->base_addr to the gfar reg region */
249 dev
->base_addr
= (unsigned long) (priv
->regs
);
251 SET_NETDEV_DEV(dev
, &pdev
->dev
);
253 /* Fill in the dev structure */
254 dev
->open
= gfar_enet_open
;
255 dev
->hard_start_xmit
= gfar_start_xmit
;
256 dev
->tx_timeout
= gfar_timeout
;
257 dev
->watchdog_timeo
= TX_TIMEOUT
;
258 netif_napi_add(dev
, &priv
->napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
259 #ifdef CONFIG_NET_POLL_CONTROLLER
260 dev
->poll_controller
= gfar_netpoll
;
262 dev
->stop
= gfar_close
;
263 dev
->change_mtu
= gfar_change_mtu
;
265 dev
->set_multicast_list
= gfar_set_multi
;
267 dev
->ethtool_ops
= &gfar_ethtool_ops
;
269 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
270 priv
->rx_csum_enable
= 1;
271 dev
->features
|= NETIF_F_IP_CSUM
;
273 priv
->rx_csum_enable
= 0;
277 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
278 dev
->vlan_rx_register
= gfar_vlan_rx_register
;
280 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
282 priv
->vlan_enable
= 1;
285 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
286 priv
->extended_hash
= 1;
287 priv
->hash_width
= 9;
289 priv
->hash_regs
[0] = &priv
->regs
->igaddr0
;
290 priv
->hash_regs
[1] = &priv
->regs
->igaddr1
;
291 priv
->hash_regs
[2] = &priv
->regs
->igaddr2
;
292 priv
->hash_regs
[3] = &priv
->regs
->igaddr3
;
293 priv
->hash_regs
[4] = &priv
->regs
->igaddr4
;
294 priv
->hash_regs
[5] = &priv
->regs
->igaddr5
;
295 priv
->hash_regs
[6] = &priv
->regs
->igaddr6
;
296 priv
->hash_regs
[7] = &priv
->regs
->igaddr7
;
297 priv
->hash_regs
[8] = &priv
->regs
->gaddr0
;
298 priv
->hash_regs
[9] = &priv
->regs
->gaddr1
;
299 priv
->hash_regs
[10] = &priv
->regs
->gaddr2
;
300 priv
->hash_regs
[11] = &priv
->regs
->gaddr3
;
301 priv
->hash_regs
[12] = &priv
->regs
->gaddr4
;
302 priv
->hash_regs
[13] = &priv
->regs
->gaddr5
;
303 priv
->hash_regs
[14] = &priv
->regs
->gaddr6
;
304 priv
->hash_regs
[15] = &priv
->regs
->gaddr7
;
307 priv
->extended_hash
= 0;
308 priv
->hash_width
= 8;
310 priv
->hash_regs
[0] = &priv
->regs
->gaddr0
;
311 priv
->hash_regs
[1] = &priv
->regs
->gaddr1
;
312 priv
->hash_regs
[2] = &priv
->regs
->gaddr2
;
313 priv
->hash_regs
[3] = &priv
->regs
->gaddr3
;
314 priv
->hash_regs
[4] = &priv
->regs
->gaddr4
;
315 priv
->hash_regs
[5] = &priv
->regs
->gaddr5
;
316 priv
->hash_regs
[6] = &priv
->regs
->gaddr6
;
317 priv
->hash_regs
[7] = &priv
->regs
->gaddr7
;
320 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
321 priv
->padding
= DEFAULT_PADDING
;
325 if (dev
->features
& NETIF_F_IP_CSUM
)
326 dev
->hard_header_len
+= GMAC_FCB_LEN
;
328 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
329 priv
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
330 priv
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
332 priv
->txcoalescing
= DEFAULT_TX_COALESCE
;
333 priv
->txcount
= DEFAULT_TXCOUNT
;
334 priv
->txtime
= DEFAULT_TXTIME
;
335 priv
->rxcoalescing
= DEFAULT_RX_COALESCE
;
336 priv
->rxcount
= DEFAULT_RXCOUNT
;
337 priv
->rxtime
= DEFAULT_RXTIME
;
339 /* Enable most messages by default */
340 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
342 err
= register_netdev(dev
);
345 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
350 /* Create all the sysfs files */
351 gfar_init_sysfs(dev
);
353 /* Print out the device info */
354 printk(KERN_INFO DEVICE_NAME
"%s\n",
355 dev
->name
, print_mac(mac
, dev
->dev_addr
));
357 /* Even more device info helps when determining which kernel */
358 /* provided which set of benchmarks. */
359 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
360 printk(KERN_INFO
"%s: %d/%d RX/TX BD ring size\n",
361 dev
->name
, priv
->rx_ring_size
, priv
->tx_ring_size
);
372 static int gfar_remove(struct platform_device
*pdev
)
374 struct net_device
*dev
= platform_get_drvdata(pdev
);
375 struct gfar_private
*priv
= netdev_priv(dev
);
377 platform_set_drvdata(pdev
, NULL
);
386 static int gfar_suspend(struct platform_device
*pdev
, pm_message_t state
)
388 struct net_device
*dev
= platform_get_drvdata(pdev
);
389 struct gfar_private
*priv
= netdev_priv(dev
);
393 int magic_packet
= priv
->wol_en
&&
394 (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
396 netif_device_detach(dev
);
398 if (netif_running(dev
)) {
399 spin_lock_irqsave(&priv
->txlock
, flags
);
400 spin_lock(&priv
->rxlock
);
402 gfar_halt_nodisable(dev
);
404 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
405 tempval
= gfar_read(&priv
->regs
->maccfg1
);
407 tempval
&= ~MACCFG1_TX_EN
;
410 tempval
&= ~MACCFG1_RX_EN
;
412 gfar_write(&priv
->regs
->maccfg1
, tempval
);
414 spin_unlock(&priv
->rxlock
);
415 spin_unlock_irqrestore(&priv
->txlock
, flags
);
417 napi_disable(&priv
->napi
);
420 /* Enable interrupt on Magic Packet */
421 gfar_write(&priv
->regs
->imask
, IMASK_MAG
);
423 /* Enable Magic Packet mode */
424 tempval
= gfar_read(&priv
->regs
->maccfg2
);
425 tempval
|= MACCFG2_MPEN
;
426 gfar_write(&priv
->regs
->maccfg2
, tempval
);
428 phy_stop(priv
->phydev
);
435 static int gfar_resume(struct platform_device
*pdev
)
437 struct net_device
*dev
= platform_get_drvdata(pdev
);
438 struct gfar_private
*priv
= netdev_priv(dev
);
441 int magic_packet
= priv
->wol_en
&&
442 (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
);
444 if (!netif_running(dev
)) {
445 netif_device_attach(dev
);
449 if (!magic_packet
&& priv
->phydev
)
450 phy_start(priv
->phydev
);
452 /* Disable Magic Packet mode, in case something
456 spin_lock_irqsave(&priv
->txlock
, flags
);
457 spin_lock(&priv
->rxlock
);
459 tempval
= gfar_read(&priv
->regs
->maccfg2
);
460 tempval
&= ~MACCFG2_MPEN
;
461 gfar_write(&priv
->regs
->maccfg2
, tempval
);
465 spin_unlock(&priv
->rxlock
);
466 spin_unlock_irqrestore(&priv
->txlock
, flags
);
468 netif_device_attach(dev
);
470 napi_enable(&priv
->napi
);
475 #define gfar_suspend NULL
476 #define gfar_resume NULL
479 /* Reads the controller's registers to determine what interface
480 * connects it to the PHY.
482 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
484 struct gfar_private
*priv
= netdev_priv(dev
);
485 u32 ecntrl
= gfar_read(&priv
->regs
->ecntrl
);
487 if (ecntrl
& ECNTRL_SGMII_MODE
)
488 return PHY_INTERFACE_MODE_SGMII
;
490 if (ecntrl
& ECNTRL_TBI_MODE
) {
491 if (ecntrl
& ECNTRL_REDUCED_MODE
)
492 return PHY_INTERFACE_MODE_RTBI
;
494 return PHY_INTERFACE_MODE_TBI
;
497 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
498 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
499 return PHY_INTERFACE_MODE_RMII
;
501 phy_interface_t interface
= priv
->einfo
->interface
;
504 * This isn't autodetected right now, so it must
505 * be set by the device tree or platform code.
507 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
508 return PHY_INTERFACE_MODE_RGMII_ID
;
510 return PHY_INTERFACE_MODE_RGMII
;
514 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
515 return PHY_INTERFACE_MODE_GMII
;
517 return PHY_INTERFACE_MODE_MII
;
521 /* Initializes driver's PHY state, and attaches to the PHY.
522 * Returns 0 on success.
524 static int init_phy(struct net_device
*dev
)
526 struct gfar_private
*priv
= netdev_priv(dev
);
527 uint gigabit_support
=
528 priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
529 SUPPORTED_1000baseT_Full
: 0;
530 struct phy_device
*phydev
;
531 char phy_id
[BUS_ID_SIZE
];
532 phy_interface_t interface
;
536 priv
->oldduplex
= -1;
538 snprintf(phy_id
, BUS_ID_SIZE
, PHY_ID_FMT
, priv
->einfo
->bus_id
, priv
->einfo
->phy_id
);
540 interface
= gfar_get_interface(dev
);
542 phydev
= phy_connect(dev
, phy_id
, &adjust_link
, 0, interface
);
544 if (interface
== PHY_INTERFACE_MODE_SGMII
)
545 gfar_configure_serdes(dev
);
547 if (IS_ERR(phydev
)) {
548 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
549 return PTR_ERR(phydev
);
552 /* Remove any features not supported by the controller */
553 phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
554 phydev
->advertising
= phydev
->supported
;
556 priv
->phydev
= phydev
;
562 * Initialize TBI PHY interface for communicating with the
563 * SERDES lynx PHY on the chip. We communicate with this PHY
564 * through the MDIO bus on each controller, treating it as a
565 * "normal" PHY at the address found in the TBIPA register. We assume
566 * that the TBIPA register is valid. Either the MDIO bus code will set
567 * it to a value that doesn't conflict with other PHYs on the bus, or the
568 * value doesn't matter, as there are no other PHYs on the bus.
570 static void gfar_configure_serdes(struct net_device
*dev
)
572 struct gfar_private
*priv
= netdev_priv(dev
);
573 struct gfar_mii __iomem
*regs
=
574 (void __iomem
*)&priv
->regs
->gfar_mii_regs
;
575 int tbipa
= gfar_read(&priv
->regs
->tbipa
);
577 /* Single clk mode, mii mode off(for serdes communication) */
578 gfar_local_mdio_write(regs
, tbipa
, MII_TBICON
, TBICON_CLK_SELECT
);
580 gfar_local_mdio_write(regs
, tbipa
, MII_ADVERTISE
,
581 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
582 ADVERTISE_1000XPSE_ASYM
);
584 gfar_local_mdio_write(regs
, tbipa
, MII_BMCR
, BMCR_ANENABLE
|
585 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
588 static void init_registers(struct net_device
*dev
)
590 struct gfar_private
*priv
= netdev_priv(dev
);
593 gfar_write(&priv
->regs
->ievent
, IEVENT_INIT_CLEAR
);
595 /* Initialize IMASK */
596 gfar_write(&priv
->regs
->imask
, IMASK_INIT_CLEAR
);
598 /* Init hash registers to zero */
599 gfar_write(&priv
->regs
->igaddr0
, 0);
600 gfar_write(&priv
->regs
->igaddr1
, 0);
601 gfar_write(&priv
->regs
->igaddr2
, 0);
602 gfar_write(&priv
->regs
->igaddr3
, 0);
603 gfar_write(&priv
->regs
->igaddr4
, 0);
604 gfar_write(&priv
->regs
->igaddr5
, 0);
605 gfar_write(&priv
->regs
->igaddr6
, 0);
606 gfar_write(&priv
->regs
->igaddr7
, 0);
608 gfar_write(&priv
->regs
->gaddr0
, 0);
609 gfar_write(&priv
->regs
->gaddr1
, 0);
610 gfar_write(&priv
->regs
->gaddr2
, 0);
611 gfar_write(&priv
->regs
->gaddr3
, 0);
612 gfar_write(&priv
->regs
->gaddr4
, 0);
613 gfar_write(&priv
->regs
->gaddr5
, 0);
614 gfar_write(&priv
->regs
->gaddr6
, 0);
615 gfar_write(&priv
->regs
->gaddr7
, 0);
617 /* Zero out the rmon mib registers if it has them */
618 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
619 memset_io(&(priv
->regs
->rmon
), 0, sizeof (struct rmon_mib
));
621 /* Mask off the CAM interrupts */
622 gfar_write(&priv
->regs
->rmon
.cam1
, 0xffffffff);
623 gfar_write(&priv
->regs
->rmon
.cam2
, 0xffffffff);
626 /* Initialize the max receive buffer length */
627 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
629 /* Initialize the Minimum Frame Length Register */
630 gfar_write(&priv
->regs
->minflr
, MINFLR_INIT_SETTINGS
);
635 /* Halt the receive and transmit queues */
636 static void gfar_halt_nodisable(struct net_device
*dev
)
638 struct gfar_private
*priv
= netdev_priv(dev
);
639 struct gfar __iomem
*regs
= priv
->regs
;
642 /* Mask all interrupts */
643 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
645 /* Clear all interrupts */
646 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
648 /* Stop the DMA, and wait for it to stop */
649 tempval
= gfar_read(&priv
->regs
->dmactrl
);
650 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
651 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
652 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
653 gfar_write(&priv
->regs
->dmactrl
, tempval
);
655 while (!(gfar_read(&priv
->regs
->ievent
) &
656 (IEVENT_GRSC
| IEVENT_GTSC
)))
662 /* Halt the receive and transmit queues */
663 void gfar_halt(struct net_device
*dev
)
665 struct gfar_private
*priv
= netdev_priv(dev
);
666 struct gfar __iomem
*regs
= priv
->regs
;
669 /* Disable Rx and Tx */
670 tempval
= gfar_read(®s
->maccfg1
);
671 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
672 gfar_write(®s
->maccfg1
, tempval
);
675 void stop_gfar(struct net_device
*dev
)
677 struct gfar_private
*priv
= netdev_priv(dev
);
678 struct gfar __iomem
*regs
= priv
->regs
;
681 phy_stop(priv
->phydev
);
684 spin_lock_irqsave(&priv
->txlock
, flags
);
685 spin_lock(&priv
->rxlock
);
689 spin_unlock(&priv
->rxlock
);
690 spin_unlock_irqrestore(&priv
->txlock
, flags
);
693 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
694 free_irq(priv
->interruptError
, dev
);
695 free_irq(priv
->interruptTransmit
, dev
);
696 free_irq(priv
->interruptReceive
, dev
);
698 free_irq(priv
->interruptTransmit
, dev
);
701 free_skb_resources(priv
);
703 dma_free_coherent(&dev
->dev
,
704 sizeof(struct txbd8
)*priv
->tx_ring_size
705 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
707 gfar_read(®s
->tbase0
));
710 /* If there are any tx skbs or rx skbs still around, free them.
711 * Then free tx_skbuff and rx_skbuff */
712 static void free_skb_resources(struct gfar_private
*priv
)
718 /* Go through all the buffer descriptors and free their data buffers */
719 txbdp
= priv
->tx_bd_base
;
721 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
723 if (priv
->tx_skbuff
[i
]) {
724 dma_unmap_single(&priv
->dev
->dev
, txbdp
->bufPtr
,
727 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
728 priv
->tx_skbuff
[i
] = NULL
;
734 kfree(priv
->tx_skbuff
);
736 rxbdp
= priv
->rx_bd_base
;
738 /* rx_skbuff is not guaranteed to be allocated, so only
739 * free it and its contents if it is allocated */
740 if(priv
->rx_skbuff
!= NULL
) {
741 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
742 if (priv
->rx_skbuff
[i
]) {
743 dma_unmap_single(&priv
->dev
->dev
, rxbdp
->bufPtr
,
744 priv
->rx_buffer_size
,
747 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
748 priv
->rx_skbuff
[i
] = NULL
;
758 kfree(priv
->rx_skbuff
);
762 void gfar_start(struct net_device
*dev
)
764 struct gfar_private
*priv
= netdev_priv(dev
);
765 struct gfar __iomem
*regs
= priv
->regs
;
768 /* Enable Rx and Tx in MACCFG1 */
769 tempval
= gfar_read(®s
->maccfg1
);
770 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
771 gfar_write(®s
->maccfg1
, tempval
);
773 /* Initialize DMACTRL to have WWR and WOP */
774 tempval
= gfar_read(&priv
->regs
->dmactrl
);
775 tempval
|= DMACTRL_INIT_SETTINGS
;
776 gfar_write(&priv
->regs
->dmactrl
, tempval
);
778 /* Make sure we aren't stopped */
779 tempval
= gfar_read(&priv
->regs
->dmactrl
);
780 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
781 gfar_write(&priv
->regs
->dmactrl
, tempval
);
783 /* Clear THLT/RHLT, so that the DMA starts polling now */
784 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
);
785 gfar_write(®s
->rstat
, RSTAT_CLEAR_RHALT
);
787 /* Unmask the interrupts we look for */
788 gfar_write(®s
->imask
, IMASK_DEFAULT
);
791 /* Bring the controller up and running */
792 int startup_gfar(struct net_device
*dev
)
799 struct gfar_private
*priv
= netdev_priv(dev
);
800 struct gfar __iomem
*regs
= priv
->regs
;
805 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
807 /* Allocate memory for the buffer descriptors */
808 vaddr
= (unsigned long) dma_alloc_coherent(&dev
->dev
,
809 sizeof (struct txbd8
) * priv
->tx_ring_size
+
810 sizeof (struct rxbd8
) * priv
->rx_ring_size
,
814 if (netif_msg_ifup(priv
))
815 printk(KERN_ERR
"%s: Could not allocate buffer descriptors!\n",
820 priv
->tx_bd_base
= (struct txbd8
*) vaddr
;
822 /* enet DMA only understands physical addresses */
823 gfar_write(®s
->tbase0
, addr
);
825 /* Start the rx descriptor ring where the tx ring leaves off */
826 addr
= addr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
827 vaddr
= vaddr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
828 priv
->rx_bd_base
= (struct rxbd8
*) vaddr
;
829 gfar_write(®s
->rbase0
, addr
);
831 /* Setup the skbuff rings */
833 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
834 priv
->tx_ring_size
, GFP_KERNEL
);
836 if (NULL
== priv
->tx_skbuff
) {
837 if (netif_msg_ifup(priv
))
838 printk(KERN_ERR
"%s: Could not allocate tx_skbuff\n",
844 for (i
= 0; i
< priv
->tx_ring_size
; i
++)
845 priv
->tx_skbuff
[i
] = NULL
;
848 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
849 priv
->rx_ring_size
, GFP_KERNEL
);
851 if (NULL
== priv
->rx_skbuff
) {
852 if (netif_msg_ifup(priv
))
853 printk(KERN_ERR
"%s: Could not allocate rx_skbuff\n",
859 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
860 priv
->rx_skbuff
[i
] = NULL
;
862 /* Initialize some variables in our dev structure */
863 priv
->dirty_tx
= priv
->cur_tx
= priv
->tx_bd_base
;
864 priv
->cur_rx
= priv
->rx_bd_base
;
865 priv
->skb_curtx
= priv
->skb_dirtytx
= 0;
868 /* Initialize Transmit Descriptor Ring */
869 txbdp
= priv
->tx_bd_base
;
870 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
877 /* Set the last descriptor in the ring to indicate wrap */
879 txbdp
->status
|= TXBD_WRAP
;
881 rxbdp
= priv
->rx_bd_base
;
882 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
885 skb
= gfar_new_skb(dev
);
888 printk(KERN_ERR
"%s: Can't allocate RX buffers\n",
891 goto err_rxalloc_fail
;
894 priv
->rx_skbuff
[i
] = skb
;
896 gfar_new_rxbdp(dev
, rxbdp
, skb
);
901 /* Set the last descriptor in the ring to wrap */
903 rxbdp
->status
|= RXBD_WRAP
;
905 /* If the device has multiple interrupts, register for
906 * them. Otherwise, only register for the one */
907 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
908 /* Install our interrupt handlers for Error,
909 * Transmit, and Receive */
910 if (request_irq(priv
->interruptError
, gfar_error
,
911 0, "enet_error", dev
) < 0) {
912 if (netif_msg_intr(priv
))
913 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
914 dev
->name
, priv
->interruptError
);
920 if (request_irq(priv
->interruptTransmit
, gfar_transmit
,
921 0, "enet_tx", dev
) < 0) {
922 if (netif_msg_intr(priv
))
923 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
924 dev
->name
, priv
->interruptTransmit
);
931 if (request_irq(priv
->interruptReceive
, gfar_receive
,
932 0, "enet_rx", dev
) < 0) {
933 if (netif_msg_intr(priv
))
934 printk(KERN_ERR
"%s: Can't get IRQ %d (receive0)\n",
935 dev
->name
, priv
->interruptReceive
);
941 if (request_irq(priv
->interruptTransmit
, gfar_interrupt
,
942 0, "gfar_interrupt", dev
) < 0) {
943 if (netif_msg_intr(priv
))
944 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
945 dev
->name
, priv
->interruptError
);
952 phy_start(priv
->phydev
);
954 /* Configure the coalescing support */
955 if (priv
->txcoalescing
)
956 gfar_write(®s
->txic
,
957 mk_ic_value(priv
->txcount
, priv
->txtime
));
959 gfar_write(®s
->txic
, 0);
961 if (priv
->rxcoalescing
)
962 gfar_write(®s
->rxic
,
963 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
965 gfar_write(®s
->rxic
, 0);
967 if (priv
->rx_csum_enable
)
968 rctrl
|= RCTRL_CHECKSUMMING
;
970 if (priv
->extended_hash
) {
971 rctrl
|= RCTRL_EXTHASH
;
973 gfar_clear_exact_match(dev
);
977 if (priv
->vlan_enable
)
981 rctrl
&= ~RCTRL_PAL_MASK
;
982 rctrl
|= RCTRL_PADDING(priv
->padding
);
985 /* Init rctrl based on our settings */
986 gfar_write(&priv
->regs
->rctrl
, rctrl
);
988 if (dev
->features
& NETIF_F_IP_CSUM
)
989 gfar_write(&priv
->regs
->tctrl
, TCTRL_INIT_CSUM
);
991 /* Set the extraction length and index */
992 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
993 ATTRELI_EI(priv
->rx_stash_index
);
995 gfar_write(&priv
->regs
->attreli
, attrs
);
997 /* Start with defaults, and add stashing or locking
998 * depending on the approprate variables */
999 attrs
= ATTR_INIT_SETTINGS
;
1001 if (priv
->bd_stash_en
)
1002 attrs
|= ATTR_BDSTASH
;
1004 if (priv
->rx_stash_size
!= 0)
1005 attrs
|= ATTR_BUFSTASH
;
1007 gfar_write(&priv
->regs
->attr
, attrs
);
1009 gfar_write(&priv
->regs
->fifo_tx_thr
, priv
->fifo_threshold
);
1010 gfar_write(&priv
->regs
->fifo_tx_starve
, priv
->fifo_starve
);
1011 gfar_write(&priv
->regs
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
1013 /* Start the controller */
1019 free_irq(priv
->interruptTransmit
, dev
);
1021 free_irq(priv
->interruptError
, dev
);
1025 free_skb_resources(priv
);
1027 dma_free_coherent(&dev
->dev
,
1028 sizeof(struct txbd8
)*priv
->tx_ring_size
1029 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
1031 gfar_read(®s
->tbase0
));
1036 /* Called when something needs to use the ethernet device */
1037 /* Returns 0 for success. */
1038 static int gfar_enet_open(struct net_device
*dev
)
1040 struct gfar_private
*priv
= netdev_priv(dev
);
1043 napi_enable(&priv
->napi
);
1045 /* Initialize a bunch of registers */
1046 init_registers(dev
);
1048 gfar_set_mac_address(dev
);
1050 err
= init_phy(dev
);
1053 napi_disable(&priv
->napi
);
1057 err
= startup_gfar(dev
);
1059 napi_disable(&priv
->napi
);
1063 netif_start_queue(dev
);
1068 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
, struct txbd8
*bdp
)
1070 struct txfcb
*fcb
= (struct txfcb
*)skb_push (skb
, GMAC_FCB_LEN
);
1072 memset(fcb
, 0, GMAC_FCB_LEN
);
1077 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
1081 /* If we're here, it's a IP packet with a TCP or UDP
1082 * payload. We set it to checksum, using a pseudo-header
1085 flags
= TXFCB_DEFAULT
;
1087 /* Tell the controller what the protocol is */
1088 /* And provide the already calculated phcs */
1089 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
1091 fcb
->phcs
= udp_hdr(skb
)->check
;
1093 fcb
->phcs
= tcp_hdr(skb
)->check
;
1095 /* l3os is the distance between the start of the
1096 * frame (skb->data) and the start of the IP hdr.
1097 * l4os is the distance between the start of the
1098 * l3 hdr and the l4 hdr */
1099 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
1100 fcb
->l4os
= skb_network_header_len(skb
);
1105 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
1107 fcb
->flags
|= TXFCB_VLN
;
1108 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1111 /* This is called by the kernel when a frame is ready for transmission. */
1112 /* It is pointed to by the dev->hard_start_xmit function pointer */
1113 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1115 struct gfar_private
*priv
= netdev_priv(dev
);
1116 struct txfcb
*fcb
= NULL
;
1117 struct txbd8
*txbdp
;
1119 unsigned long flags
;
1121 /* Update transmit stats */
1122 dev
->stats
.tx_bytes
+= skb
->len
;
1125 spin_lock_irqsave(&priv
->txlock
, flags
);
1127 /* Point at the first free tx descriptor */
1128 txbdp
= priv
->cur_tx
;
1130 /* Clear all but the WRAP status flags */
1131 status
= txbdp
->status
& TXBD_WRAP
;
1133 /* Set up checksumming */
1134 if (likely((dev
->features
& NETIF_F_IP_CSUM
)
1135 && (CHECKSUM_PARTIAL
== skb
->ip_summed
))) {
1136 fcb
= gfar_add_fcb(skb
, txbdp
);
1138 gfar_tx_checksum(skb
, fcb
);
1141 if (priv
->vlan_enable
&&
1142 unlikely(priv
->vlgrp
&& vlan_tx_tag_present(skb
))) {
1143 if (unlikely(NULL
== fcb
)) {
1144 fcb
= gfar_add_fcb(skb
, txbdp
);
1148 gfar_tx_vlan(skb
, fcb
);
1151 /* Set buffer length and pointer */
1152 txbdp
->length
= skb
->len
;
1153 txbdp
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1154 skb
->len
, DMA_TO_DEVICE
);
1156 /* Save the skb pointer so we can free it later */
1157 priv
->tx_skbuff
[priv
->skb_curtx
] = skb
;
1159 /* Update the current skb pointer (wrapping if this was the last) */
1161 (priv
->skb_curtx
+ 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1163 /* Flag the BD as interrupt-causing */
1164 status
|= TXBD_INTERRUPT
;
1166 /* Flag the BD as ready to go, last in frame, and */
1167 /* in need of CRC */
1168 status
|= (TXBD_READY
| TXBD_LAST
| TXBD_CRC
);
1170 dev
->trans_start
= jiffies
;
1172 /* The powerpc-specific eieio() is used, as wmb() has too strong
1173 * semantics (it requires synchronization between cacheable and
1174 * uncacheable mappings, which eieio doesn't provide and which we
1175 * don't need), thus requiring a more expensive sync instruction. At
1176 * some point, the set of architecture-independent barrier functions
1177 * should be expanded to include weaker barriers.
1181 txbdp
->status
= status
;
1183 /* If this was the last BD in the ring, the next one */
1184 /* is at the beginning of the ring */
1185 if (txbdp
->status
& TXBD_WRAP
)
1186 txbdp
= priv
->tx_bd_base
;
1190 /* If the next BD still needs to be cleaned up, then the bds
1191 are full. We need to tell the kernel to stop sending us stuff. */
1192 if (txbdp
== priv
->dirty_tx
) {
1193 netif_stop_queue(dev
);
1195 dev
->stats
.tx_fifo_errors
++;
1198 /* Update the current txbd to the next one */
1199 priv
->cur_tx
= txbdp
;
1201 /* Tell the DMA to go go go */
1202 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1205 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1210 /* Stops the kernel queue, and halts the controller */
1211 static int gfar_close(struct net_device
*dev
)
1213 struct gfar_private
*priv
= netdev_priv(dev
);
1215 napi_disable(&priv
->napi
);
1219 /* Disconnect from the PHY */
1220 phy_disconnect(priv
->phydev
);
1221 priv
->phydev
= NULL
;
1223 netif_stop_queue(dev
);
1228 /* Changes the mac address if the controller is not running. */
1229 static int gfar_set_mac_address(struct net_device
*dev
)
1231 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
1237 /* Enables and disables VLAN insertion/extraction */
1238 static void gfar_vlan_rx_register(struct net_device
*dev
,
1239 struct vlan_group
*grp
)
1241 struct gfar_private
*priv
= netdev_priv(dev
);
1242 unsigned long flags
;
1245 spin_lock_irqsave(&priv
->rxlock
, flags
);
1250 /* Enable VLAN tag insertion */
1251 tempval
= gfar_read(&priv
->regs
->tctrl
);
1252 tempval
|= TCTRL_VLINS
;
1254 gfar_write(&priv
->regs
->tctrl
, tempval
);
1256 /* Enable VLAN tag extraction */
1257 tempval
= gfar_read(&priv
->regs
->rctrl
);
1258 tempval
|= RCTRL_VLEX
;
1259 gfar_write(&priv
->regs
->rctrl
, tempval
);
1261 /* Disable VLAN tag insertion */
1262 tempval
= gfar_read(&priv
->regs
->tctrl
);
1263 tempval
&= ~TCTRL_VLINS
;
1264 gfar_write(&priv
->regs
->tctrl
, tempval
);
1266 /* Disable VLAN tag extraction */
1267 tempval
= gfar_read(&priv
->regs
->rctrl
);
1268 tempval
&= ~RCTRL_VLEX
;
1269 gfar_write(&priv
->regs
->rctrl
, tempval
);
1272 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1275 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
1277 int tempsize
, tempval
;
1278 struct gfar_private
*priv
= netdev_priv(dev
);
1279 int oldsize
= priv
->rx_buffer_size
;
1280 int frame_size
= new_mtu
+ ETH_HLEN
;
1282 if (priv
->vlan_enable
)
1283 frame_size
+= VLAN_HLEN
;
1285 if (gfar_uses_fcb(priv
))
1286 frame_size
+= GMAC_FCB_LEN
;
1288 frame_size
+= priv
->padding
;
1290 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
1291 if (netif_msg_drv(priv
))
1292 printk(KERN_ERR
"%s: Invalid MTU setting\n",
1298 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
1299 INCREMENTAL_BUFFER_SIZE
;
1301 /* Only stop and start the controller if it isn't already
1302 * stopped, and we changed something */
1303 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1306 priv
->rx_buffer_size
= tempsize
;
1310 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
1311 gfar_write(&priv
->regs
->maxfrm
, priv
->rx_buffer_size
);
1313 /* If the mtu is larger than the max size for standard
1314 * ethernet frames (ie, a jumbo frame), then set maccfg2
1315 * to allow huge frames, and to check the length */
1316 tempval
= gfar_read(&priv
->regs
->maccfg2
);
1318 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
1319 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1321 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1323 gfar_write(&priv
->regs
->maccfg2
, tempval
);
1325 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1331 /* gfar_timeout gets called when a packet has not been
1332 * transmitted after a set amount of time.
1333 * For now, assume that clearing out all the structures, and
1334 * starting over will fix the problem. */
1335 static void gfar_timeout(struct net_device
*dev
)
1337 dev
->stats
.tx_errors
++;
1339 if (dev
->flags
& IFF_UP
) {
1344 netif_tx_schedule_all(dev
);
1347 /* Interrupt Handler for Transmit complete */
1348 static int gfar_clean_tx_ring(struct net_device
*dev
)
1351 struct gfar_private
*priv
= netdev_priv(dev
);
1354 bdp
= priv
->dirty_tx
;
1355 while ((bdp
->status
& TXBD_READY
) == 0) {
1356 /* If dirty_tx and cur_tx are the same, then either the */
1357 /* ring is empty or full now (it could only be full in the beginning, */
1358 /* obviously). If it is empty, we are done. */
1359 if ((bdp
== priv
->cur_tx
) && (netif_queue_stopped(dev
) == 0))
1364 /* Deferred means some collisions occurred during transmit, */
1365 /* but we eventually sent the packet. */
1366 if (bdp
->status
& TXBD_DEF
)
1367 dev
->stats
.collisions
++;
1369 /* Free the sk buffer associated with this TxBD */
1370 dev_kfree_skb_irq(priv
->tx_skbuff
[priv
->skb_dirtytx
]);
1372 priv
->tx_skbuff
[priv
->skb_dirtytx
] = NULL
;
1374 (priv
->skb_dirtytx
+
1375 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1377 /* Clean BD length for empty detection */
1380 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1381 if (bdp
->status
& TXBD_WRAP
)
1382 bdp
= priv
->tx_bd_base
;
1386 /* Move dirty_tx to be the next bd */
1387 priv
->dirty_tx
= bdp
;
1389 /* We freed a buffer, so now we can restart transmission */
1390 if (netif_queue_stopped(dev
))
1391 netif_wake_queue(dev
);
1392 } /* while ((bdp->status & TXBD_READY) == 0) */
1394 dev
->stats
.tx_packets
+= howmany
;
1399 /* Interrupt Handler for Transmit complete */
1400 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
)
1402 struct net_device
*dev
= (struct net_device
*) dev_id
;
1403 struct gfar_private
*priv
= netdev_priv(dev
);
1406 gfar_write(&priv
->regs
->ievent
, IEVENT_TX_MASK
);
1409 spin_lock(&priv
->txlock
);
1411 gfar_clean_tx_ring(dev
);
1413 /* If we are coalescing the interrupts, reset the timer */
1414 /* Otherwise, clear it */
1415 if (likely(priv
->txcoalescing
)) {
1416 gfar_write(&priv
->regs
->txic
, 0);
1417 gfar_write(&priv
->regs
->txic
,
1418 mk_ic_value(priv
->txcount
, priv
->txtime
));
1421 spin_unlock(&priv
->txlock
);
1426 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
1427 struct sk_buff
*skb
)
1429 struct gfar_private
*priv
= netdev_priv(dev
);
1430 u32
* status_len
= (u32
*)bdp
;
1433 bdp
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1434 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1436 flags
= RXBD_EMPTY
| RXBD_INTERRUPT
;
1438 if (bdp
== priv
->rx_bd_base
+ priv
->rx_ring_size
- 1)
1443 *status_len
= (u32
)flags
<< 16;
1447 struct sk_buff
* gfar_new_skb(struct net_device
*dev
)
1449 unsigned int alignamount
;
1450 struct gfar_private
*priv
= netdev_priv(dev
);
1451 struct sk_buff
*skb
= NULL
;
1453 /* We have to allocate the skb, so keep trying till we succeed */
1454 skb
= netdev_alloc_skb(dev
, priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
1459 alignamount
= RXBUF_ALIGNMENT
-
1460 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
1462 /* We need the data buffer to be aligned properly. We will reserve
1463 * as many bytes as needed to align the data properly
1465 skb_reserve(skb
, alignamount
);
1470 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
1472 struct gfar_private
*priv
= netdev_priv(dev
);
1473 struct net_device_stats
*stats
= &dev
->stats
;
1474 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
1476 /* If the packet was truncated, none of the other errors
1478 if (status
& RXBD_TRUNCATED
) {
1479 stats
->rx_length_errors
++;
1485 /* Count the errors, if there were any */
1486 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
1487 stats
->rx_length_errors
++;
1489 if (status
& RXBD_LARGE
)
1494 if (status
& RXBD_NONOCTET
) {
1495 stats
->rx_frame_errors
++;
1496 estats
->rx_nonoctet
++;
1498 if (status
& RXBD_CRCERR
) {
1499 estats
->rx_crcerr
++;
1500 stats
->rx_crc_errors
++;
1502 if (status
& RXBD_OVERRUN
) {
1503 estats
->rx_overrun
++;
1504 stats
->rx_crc_errors
++;
1508 irqreturn_t
gfar_receive(int irq
, void *dev_id
)
1510 struct net_device
*dev
= (struct net_device
*) dev_id
;
1511 struct gfar_private
*priv
= netdev_priv(dev
);
1515 /* Clear IEVENT, so interrupts aren't called again
1516 * because of the packets that have already arrived */
1517 gfar_write(&priv
->regs
->ievent
, IEVENT_RTX_MASK
);
1519 if (netif_rx_schedule_prep(dev
, &priv
->napi
)) {
1520 tempval
= gfar_read(&priv
->regs
->imask
);
1521 tempval
&= IMASK_RTX_DISABLED
;
1522 gfar_write(&priv
->regs
->imask
, tempval
);
1524 __netif_rx_schedule(dev
, &priv
->napi
);
1526 if (netif_msg_rx_err(priv
))
1527 printk(KERN_DEBUG
"%s: receive called twice (%x)[%x]\n",
1528 dev
->name
, gfar_read(&priv
->regs
->ievent
),
1529 gfar_read(&priv
->regs
->imask
));
1535 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
1537 /* If valid headers were found, and valid sums
1538 * were verified, then we tell the kernel that no
1539 * checksumming is necessary. Otherwise, it is */
1540 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
1541 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1543 skb
->ip_summed
= CHECKSUM_NONE
;
1547 static inline struct rxfcb
*gfar_get_fcb(struct sk_buff
*skb
)
1549 struct rxfcb
*fcb
= (struct rxfcb
*)skb
->data
;
1551 /* Remove the FCB from the skb */
1552 skb_pull(skb
, GMAC_FCB_LEN
);
1557 /* gfar_process_frame() -- handle one incoming packet if skb
1559 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
1562 struct gfar_private
*priv
= netdev_priv(dev
);
1563 struct rxfcb
*fcb
= NULL
;
1566 if (netif_msg_rx_err(priv
))
1567 printk(KERN_WARNING
"%s: Missing skb!!.\n", dev
->name
);
1568 dev
->stats
.rx_dropped
++;
1569 priv
->extra_stats
.rx_skbmissing
++;
1573 /* Prep the skb for the packet */
1574 skb_put(skb
, length
);
1576 /* Grab the FCB if there is one */
1577 if (gfar_uses_fcb(priv
))
1578 fcb
= gfar_get_fcb(skb
);
1580 /* Remove the padded bytes, if there are any */
1582 skb_pull(skb
, priv
->padding
);
1584 if (priv
->rx_csum_enable
)
1585 gfar_rx_checksum(skb
, fcb
);
1587 /* Tell the skb what kind of packet this is */
1588 skb
->protocol
= eth_type_trans(skb
, dev
);
1590 /* Send the packet up the stack */
1591 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
))) {
1592 ret
= vlan_hwaccel_receive_skb(skb
, priv
->vlgrp
,
1595 ret
= netif_receive_skb(skb
);
1597 if (NET_RX_DROP
== ret
)
1598 priv
->extra_stats
.kernel_dropped
++;
1604 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1605 * until the budget/quota has been reached. Returns the number
1608 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
)
1611 struct sk_buff
*skb
;
1614 struct gfar_private
*priv
= netdev_priv(dev
);
1616 /* Get the first full descriptor */
1619 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
1620 struct sk_buff
*newskb
;
1623 /* Add another skb for the future */
1624 newskb
= gfar_new_skb(dev
);
1626 skb
= priv
->rx_skbuff
[priv
->skb_currx
];
1628 /* We drop the frame if we failed to allocate a new buffer */
1629 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
1630 bdp
->status
& RXBD_ERR
)) {
1631 count_errors(bdp
->status
, dev
);
1633 if (unlikely(!newskb
))
1637 dma_unmap_single(&priv
->dev
->dev
,
1639 priv
->rx_buffer_size
,
1642 dev_kfree_skb_any(skb
);
1645 /* Increment the number of packets */
1646 dev
->stats
.rx_packets
++;
1649 /* Remove the FCS from the packet length */
1650 pkt_len
= bdp
->length
- 4;
1652 gfar_process_frame(dev
, skb
, pkt_len
);
1654 dev
->stats
.rx_bytes
+= pkt_len
;
1657 dev
->last_rx
= jiffies
;
1659 priv
->rx_skbuff
[priv
->skb_currx
] = newskb
;
1661 /* Setup the new bdp */
1662 gfar_new_rxbdp(dev
, bdp
, newskb
);
1664 /* Update to the next pointer */
1665 if (bdp
->status
& RXBD_WRAP
)
1666 bdp
= priv
->rx_bd_base
;
1670 /* update to point at the next skb */
1672 (priv
->skb_currx
+ 1) &
1673 RX_RING_MOD_MASK(priv
->rx_ring_size
);
1676 /* Update the current rxbd pointer to be the next one */
1682 static int gfar_poll(struct napi_struct
*napi
, int budget
)
1684 struct gfar_private
*priv
= container_of(napi
, struct gfar_private
, napi
);
1685 struct net_device
*dev
= priv
->dev
;
1687 unsigned long flags
;
1689 /* If we fail to get the lock, don't bother with the TX BDs */
1690 if (spin_trylock_irqsave(&priv
->txlock
, flags
)) {
1691 gfar_clean_tx_ring(dev
);
1692 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1695 howmany
= gfar_clean_rx_ring(dev
, budget
);
1697 if (howmany
< budget
) {
1698 netif_rx_complete(dev
, napi
);
1700 /* Clear the halt bit in RSTAT */
1701 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1703 gfar_write(&priv
->regs
->imask
, IMASK_DEFAULT
);
1705 /* If we are coalescing interrupts, update the timer */
1706 /* Otherwise, clear it */
1707 if (likely(priv
->rxcoalescing
)) {
1708 gfar_write(&priv
->regs
->rxic
, 0);
1709 gfar_write(&priv
->regs
->rxic
,
1710 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
1717 #ifdef CONFIG_NET_POLL_CONTROLLER
1719 * Polling 'interrupt' - used by things like netconsole to send skbs
1720 * without having to re-enable interrupts. It's not called while
1721 * the interrupt routine is executing.
1723 static void gfar_netpoll(struct net_device
*dev
)
1725 struct gfar_private
*priv
= netdev_priv(dev
);
1727 /* If the device has multiple interrupts, run tx/rx */
1728 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1729 disable_irq(priv
->interruptTransmit
);
1730 disable_irq(priv
->interruptReceive
);
1731 disable_irq(priv
->interruptError
);
1732 gfar_interrupt(priv
->interruptTransmit
, dev
);
1733 enable_irq(priv
->interruptError
);
1734 enable_irq(priv
->interruptReceive
);
1735 enable_irq(priv
->interruptTransmit
);
1737 disable_irq(priv
->interruptTransmit
);
1738 gfar_interrupt(priv
->interruptTransmit
, dev
);
1739 enable_irq(priv
->interruptTransmit
);
1744 /* The interrupt handler for devices with one interrupt */
1745 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
)
1747 struct net_device
*dev
= dev_id
;
1748 struct gfar_private
*priv
= netdev_priv(dev
);
1750 /* Save ievent for future reference */
1751 u32 events
= gfar_read(&priv
->regs
->ievent
);
1753 /* Check for reception */
1754 if (events
& IEVENT_RX_MASK
)
1755 gfar_receive(irq
, dev_id
);
1757 /* Check for transmit completion */
1758 if (events
& IEVENT_TX_MASK
)
1759 gfar_transmit(irq
, dev_id
);
1761 /* Check for errors */
1762 if (events
& IEVENT_ERR_MASK
)
1763 gfar_error(irq
, dev_id
);
1768 /* Called every time the controller might need to be made
1769 * aware of new link state. The PHY code conveys this
1770 * information through variables in the phydev structure, and this
1771 * function converts those variables into the appropriate
1772 * register values, and can bring down the device if needed.
1774 static void adjust_link(struct net_device
*dev
)
1776 struct gfar_private
*priv
= netdev_priv(dev
);
1777 struct gfar __iomem
*regs
= priv
->regs
;
1778 unsigned long flags
;
1779 struct phy_device
*phydev
= priv
->phydev
;
1782 spin_lock_irqsave(&priv
->txlock
, flags
);
1784 u32 tempval
= gfar_read(®s
->maccfg2
);
1785 u32 ecntrl
= gfar_read(®s
->ecntrl
);
1787 /* Now we make sure that we can be in full duplex mode.
1788 * If not, we operate in half-duplex mode. */
1789 if (phydev
->duplex
!= priv
->oldduplex
) {
1791 if (!(phydev
->duplex
))
1792 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
1794 tempval
|= MACCFG2_FULL_DUPLEX
;
1796 priv
->oldduplex
= phydev
->duplex
;
1799 if (phydev
->speed
!= priv
->oldspeed
) {
1801 switch (phydev
->speed
) {
1804 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
1809 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
1811 /* Reduced mode distinguishes
1812 * between 10 and 100 */
1813 if (phydev
->speed
== SPEED_100
)
1814 ecntrl
|= ECNTRL_R100
;
1816 ecntrl
&= ~(ECNTRL_R100
);
1819 if (netif_msg_link(priv
))
1821 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1822 dev
->name
, phydev
->speed
);
1826 priv
->oldspeed
= phydev
->speed
;
1829 gfar_write(®s
->maccfg2
, tempval
);
1830 gfar_write(®s
->ecntrl
, ecntrl
);
1832 if (!priv
->oldlink
) {
1836 } else if (priv
->oldlink
) {
1840 priv
->oldduplex
= -1;
1843 if (new_state
&& netif_msg_link(priv
))
1844 phy_print_status(phydev
);
1846 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1849 /* Update the hash table based on the current list of multicast
1850 * addresses we subscribe to. Also, change the promiscuity of
1851 * the device based on the flags (this function is called
1852 * whenever dev->flags is changed */
1853 static void gfar_set_multi(struct net_device
*dev
)
1855 struct dev_mc_list
*mc_ptr
;
1856 struct gfar_private
*priv
= netdev_priv(dev
);
1857 struct gfar __iomem
*regs
= priv
->regs
;
1860 if(dev
->flags
& IFF_PROMISC
) {
1861 /* Set RCTRL to PROM */
1862 tempval
= gfar_read(®s
->rctrl
);
1863 tempval
|= RCTRL_PROM
;
1864 gfar_write(®s
->rctrl
, tempval
);
1866 /* Set RCTRL to not PROM */
1867 tempval
= gfar_read(®s
->rctrl
);
1868 tempval
&= ~(RCTRL_PROM
);
1869 gfar_write(®s
->rctrl
, tempval
);
1872 if(dev
->flags
& IFF_ALLMULTI
) {
1873 /* Set the hash to rx all multicast frames */
1874 gfar_write(®s
->igaddr0
, 0xffffffff);
1875 gfar_write(®s
->igaddr1
, 0xffffffff);
1876 gfar_write(®s
->igaddr2
, 0xffffffff);
1877 gfar_write(®s
->igaddr3
, 0xffffffff);
1878 gfar_write(®s
->igaddr4
, 0xffffffff);
1879 gfar_write(®s
->igaddr5
, 0xffffffff);
1880 gfar_write(®s
->igaddr6
, 0xffffffff);
1881 gfar_write(®s
->igaddr7
, 0xffffffff);
1882 gfar_write(®s
->gaddr0
, 0xffffffff);
1883 gfar_write(®s
->gaddr1
, 0xffffffff);
1884 gfar_write(®s
->gaddr2
, 0xffffffff);
1885 gfar_write(®s
->gaddr3
, 0xffffffff);
1886 gfar_write(®s
->gaddr4
, 0xffffffff);
1887 gfar_write(®s
->gaddr5
, 0xffffffff);
1888 gfar_write(®s
->gaddr6
, 0xffffffff);
1889 gfar_write(®s
->gaddr7
, 0xffffffff);
1894 /* zero out the hash */
1895 gfar_write(®s
->igaddr0
, 0x0);
1896 gfar_write(®s
->igaddr1
, 0x0);
1897 gfar_write(®s
->igaddr2
, 0x0);
1898 gfar_write(®s
->igaddr3
, 0x0);
1899 gfar_write(®s
->igaddr4
, 0x0);
1900 gfar_write(®s
->igaddr5
, 0x0);
1901 gfar_write(®s
->igaddr6
, 0x0);
1902 gfar_write(®s
->igaddr7
, 0x0);
1903 gfar_write(®s
->gaddr0
, 0x0);
1904 gfar_write(®s
->gaddr1
, 0x0);
1905 gfar_write(®s
->gaddr2
, 0x0);
1906 gfar_write(®s
->gaddr3
, 0x0);
1907 gfar_write(®s
->gaddr4
, 0x0);
1908 gfar_write(®s
->gaddr5
, 0x0);
1909 gfar_write(®s
->gaddr6
, 0x0);
1910 gfar_write(®s
->gaddr7
, 0x0);
1912 /* If we have extended hash tables, we need to
1913 * clear the exact match registers to prepare for
1915 if (priv
->extended_hash
) {
1916 em_num
= GFAR_EM_NUM
+ 1;
1917 gfar_clear_exact_match(dev
);
1924 if(dev
->mc_count
== 0)
1927 /* Parse the list, and set the appropriate bits */
1928 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
1930 gfar_set_mac_for_addr(dev
, idx
,
1934 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
1942 /* Clears each of the exact match registers to zero, so they
1943 * don't interfere with normal reception */
1944 static void gfar_clear_exact_match(struct net_device
*dev
)
1947 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
1949 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
1950 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
1953 /* Set the appropriate hash bit for the given addr */
1954 /* The algorithm works like so:
1955 * 1) Take the Destination Address (ie the multicast address), and
1956 * do a CRC on it (little endian), and reverse the bits of the
1958 * 2) Use the 8 most significant bits as a hash into a 256-entry
1959 * table. The table is controlled through 8 32-bit registers:
1960 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1961 * gaddr7. This means that the 3 most significant bits in the
1962 * hash index which gaddr register to use, and the 5 other bits
1963 * indicate which bit (assuming an IBM numbering scheme, which
1964 * for PowerPC (tm) is usually the case) in the register holds
1966 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
1969 struct gfar_private
*priv
= netdev_priv(dev
);
1970 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
1971 int width
= priv
->hash_width
;
1972 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
1973 u8 whichreg
= result
>> (32 - width
+ 5);
1974 u32 value
= (1 << (31-whichbit
));
1976 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
1978 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
1984 /* There are multiple MAC Address register pairs on some controllers
1985 * This function sets the numth pair to a given address
1987 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
1989 struct gfar_private
*priv
= netdev_priv(dev
);
1991 char tmpbuf
[MAC_ADDR_LEN
];
1993 u32 __iomem
*macptr
= &priv
->regs
->macstnaddr1
;
1997 /* Now copy it into the mac registers backwards, cuz */
1998 /* little endian is silly */
1999 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
2000 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
2002 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
2004 tempval
= *((u32
*) (tmpbuf
+ 4));
2006 gfar_write(macptr
+1, tempval
);
2009 /* GFAR error interrupt handler */
2010 static irqreturn_t
gfar_error(int irq
, void *dev_id
)
2012 struct net_device
*dev
= dev_id
;
2013 struct gfar_private
*priv
= netdev_priv(dev
);
2015 /* Save ievent for future reference */
2016 u32 events
= gfar_read(&priv
->regs
->ievent
);
2019 gfar_write(&priv
->regs
->ievent
, events
& IEVENT_ERR_MASK
);
2021 /* Magic Packet is not an error. */
2022 if ((priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MAGIC_PACKET
) &&
2023 (events
& IEVENT_MAG
))
2024 events
&= ~IEVENT_MAG
;
2027 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
2028 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2029 dev
->name
, events
, gfar_read(&priv
->regs
->imask
));
2031 /* Update the error counters */
2032 if (events
& IEVENT_TXE
) {
2033 dev
->stats
.tx_errors
++;
2035 if (events
& IEVENT_LC
)
2036 dev
->stats
.tx_window_errors
++;
2037 if (events
& IEVENT_CRL
)
2038 dev
->stats
.tx_aborted_errors
++;
2039 if (events
& IEVENT_XFUN
) {
2040 if (netif_msg_tx_err(priv
))
2041 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
2042 "packet dropped.\n", dev
->name
);
2043 dev
->stats
.tx_dropped
++;
2044 priv
->extra_stats
.tx_underrun
++;
2046 /* Reactivate the Tx Queues */
2047 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
2049 if (netif_msg_tx_err(priv
))
2050 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
2052 if (events
& IEVENT_BSY
) {
2053 dev
->stats
.rx_errors
++;
2054 priv
->extra_stats
.rx_bsy
++;
2056 gfar_receive(irq
, dev_id
);
2058 if (netif_msg_rx_err(priv
))
2059 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
2060 dev
->name
, gfar_read(&priv
->regs
->rstat
));
2062 if (events
& IEVENT_BABR
) {
2063 dev
->stats
.rx_errors
++;
2064 priv
->extra_stats
.rx_babr
++;
2066 if (netif_msg_rx_err(priv
))
2067 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
2069 if (events
& IEVENT_EBERR
) {
2070 priv
->extra_stats
.eberr
++;
2071 if (netif_msg_rx_err(priv
))
2072 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
2074 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
2075 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
2077 if (events
& IEVENT_BABT
) {
2078 priv
->extra_stats
.tx_babt
++;
2079 if (netif_msg_tx_err(priv
))
2080 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
2085 /* work with hotplug and coldplug */
2086 MODULE_ALIAS("platform:fsl-gianfar");
2088 /* Structure for a device driver */
2089 static struct platform_driver gfar_driver
= {
2090 .probe
= gfar_probe
,
2091 .remove
= gfar_remove
,
2092 .suspend
= gfar_suspend
,
2093 .resume
= gfar_resume
,
2095 .name
= "fsl-gianfar",
2096 .owner
= THIS_MODULE
,
2100 static int __init
gfar_init(void)
2102 int err
= gfar_mdio_init();
2107 err
= platform_driver_register(&gfar_driver
);
2115 static void __exit
gfar_exit(void)
2117 platform_driver_unregister(&gfar_driver
);
2121 module_init(gfar_init
);
2122 module_exit(gfar_exit
);