projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branches 'topic/fix/misc' and 'topic/fix/asoc' into for-linus
[deliverable/linux.git] / drivers / net / ibm_newemac / mal.c
1 /*
2 * drivers/net/ibm_newemac/mal.c
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
7 * <benh@kernel.crashing.org>
8 *
9 * Based on the arch/ppc version of the driver:
10 *
11 * Copyright (c) 2004, 2005 Zultys Technologies.
12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
13 *
14 * Based on original work by
15 * Benjamin Herrenschmidt <benh@kernel.crashing.org>,
16 * David Gibson <hermes@gibson.dropbear.id.au>,
17 *
18 * Armin Kuster <akuster@mvista.com>
19 * Copyright 2002 MontaVista Softare Inc.
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2 of the License, or (at your
24 * option) any later version.
25 *
26 */
27
28 #include <linux/delay.h>
29
30 #include "core.h"
31 #include <asm/dcr-regs.h>
32
33 static int mal_count;
34
35 int __devinit mal_register_commac(struct mal_instance *mal,
36 struct mal_commac *commac)
37 {
38 unsigned long flags;
39
40 spin_lock_irqsave(&mal->lock, flags);
41
42 MAL_DBG(mal, "reg(%08x, %08x)" NL,
43 commac->tx_chan_mask, commac->rx_chan_mask);
44
45 /* Don't let multiple commacs claim the same channel(s) */
46 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
47 (mal->rx_chan_mask & commac->rx_chan_mask)) {
48 spin_unlock_irqrestore(&mal->lock, flags);
49 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
50 mal->index);
51 return -EBUSY;
52 }
53
54 if (list_empty(&mal->list))
55 napi_enable(&mal->napi);
56 mal->tx_chan_mask |= commac->tx_chan_mask;
57 mal->rx_chan_mask |= commac->rx_chan_mask;
58 list_add(&commac->list, &mal->list);
59
60 spin_unlock_irqrestore(&mal->lock, flags);
61
62 return 0;
63 }
64
65 void mal_unregister_commac(struct mal_instance *mal,
66 struct mal_commac *commac)
67 {
68 unsigned long flags;
69
70 spin_lock_irqsave(&mal->lock, flags);
71
72 MAL_DBG(mal, "unreg(%08x, %08x)" NL,
73 commac->tx_chan_mask, commac->rx_chan_mask);
74
75 mal->tx_chan_mask &= ~commac->tx_chan_mask;
76 mal->rx_chan_mask &= ~commac->rx_chan_mask;
77 list_del_init(&commac->list);
78 if (list_empty(&mal->list))
79 napi_disable(&mal->napi);
80
81 spin_unlock_irqrestore(&mal->lock, flags);
82 }
83
84 int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size)
85 {
86 BUG_ON(channel < 0 || channel >= mal->num_rx_chans ||
87 size > MAL_MAX_RX_SIZE);
88
89 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size);
90
91 if (size & 0xf) {
92 printk(KERN_WARNING
93 "mal%d: incorrect RX size %lu for the channel %d\n",
94 mal->index, size, channel);
95 return -EINVAL;
96 }
97
98 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
99 return 0;
100 }
101
102 int mal_tx_bd_offset(struct mal_instance *mal, int channel)
103 {
104 BUG_ON(channel < 0 || channel >= mal->num_tx_chans);
105
106 return channel * NUM_TX_BUFF;
107 }
108
109 int mal_rx_bd_offset(struct mal_instance *mal, int channel)
110 {
111 BUG_ON(channel < 0 || channel >= mal->num_rx_chans);
112 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
113 }
114
115 void mal_enable_tx_channel(struct mal_instance *mal, int channel)
116 {
117 unsigned long flags;
118
119 spin_lock_irqsave(&mal->lock, flags);
120
121 MAL_DBG(mal, "enable_tx(%d)" NL, channel);
122
123 set_mal_dcrn(mal, MAL_TXCASR,
124 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
125
126 spin_unlock_irqrestore(&mal->lock, flags);
127 }
128
129 void mal_disable_tx_channel(struct mal_instance *mal, int channel)
130 {
131 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
132
133 MAL_DBG(mal, "disable_tx(%d)" NL, channel);
134 }
135
136 void mal_enable_rx_channel(struct mal_instance *mal, int channel)
137 {
138 unsigned long flags;
139
140 /*
141 * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple
142 * of 8, but enabling in MAL_RXCASR needs the divided by 8 value
143 * for the bitmask
144 */
145 if (!(channel % 8))
146 channel >>= 3;
147
148 spin_lock_irqsave(&mal->lock, flags);
149
150 MAL_DBG(mal, "enable_rx(%d)" NL, channel);
151
152 set_mal_dcrn(mal, MAL_RXCASR,
153 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
154
155 spin_unlock_irqrestore(&mal->lock, flags);
156 }
157
158 void mal_disable_rx_channel(struct mal_instance *mal, int channel)
159 {
160 /*
161 * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple
162 * of 8, but enabling in MAL_RXCASR needs the divided by 8 value
163 * for the bitmask
164 */
165 if (!(channel % 8))
166 channel >>= 3;
167
168 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
169
170 MAL_DBG(mal, "disable_rx(%d)" NL, channel);
171 }
172
173 void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac)
174 {
175 unsigned long flags;
176
177 spin_lock_irqsave(&mal->lock, flags);
178
179 MAL_DBG(mal, "poll_add(%p)" NL, commac);
180
181 /* starts disabled */
182 set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
183
184 list_add_tail(&commac->poll_list, &mal->poll_list);
185
186 spin_unlock_irqrestore(&mal->lock, flags);
187 }
188
189 void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac)
190 {
191 unsigned long flags;
192
193 spin_lock_irqsave(&mal->lock, flags);
194
195 MAL_DBG(mal, "poll_del(%p)" NL, commac);
196
197 list_del(&commac->poll_list);
198
199 spin_unlock_irqrestore(&mal->lock, flags);
200 }
201
202 /* synchronized by mal_poll() */
203 static inline void mal_enable_eob_irq(struct mal_instance *mal)
204 {
205 MAL_DBG2(mal, "enable_irq" NL);
206
207 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
208 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
209 }
210
211 /* synchronized by NAPI state */
212 static inline void mal_disable_eob_irq(struct mal_instance *mal)
213 {
214 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
215 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
216
217 MAL_DBG2(mal, "disable_irq" NL);
218 }
219
220 static irqreturn_t mal_serr(int irq, void *dev_instance)
221 {
222 struct mal_instance *mal = dev_instance;
223
224 u32 esr = get_mal_dcrn(mal, MAL_ESR);
225
226 /* Clear the error status register */
227 set_mal_dcrn(mal, MAL_ESR, esr);
228
229 MAL_DBG(mal, "SERR %08x" NL, esr);
230
231 if (esr & MAL_ESR_EVB) {
232 if (esr & MAL_ESR_DE) {
233 /* We ignore Descriptor error,
234 * TXDE or RXDE interrupt will be generated anyway.
235 */
236 return IRQ_HANDLED;
237 }
238
239 if (esr & MAL_ESR_PEIN) {
240 /* PLB error, it's probably buggy hardware or
241 * incorrect physical address in BD (i.e. bug)
242 */
243 if (net_ratelimit())
244 printk(KERN_ERR
245 "mal%d: system error, "
246 "PLB (ESR = 0x%08x)\n",
247 mal->index, esr);
248 return IRQ_HANDLED;
249 }
250
251 /* OPB error, it's probably buggy hardware or incorrect
252 * EBC setup
253 */
254 if (net_ratelimit())
255 printk(KERN_ERR
256 "mal%d: system error, OPB (ESR = 0x%08x)\n",
257 mal->index, esr);
258 }
259 return IRQ_HANDLED;
260 }
261
262 static inline void mal_schedule_poll(struct mal_instance *mal)
263 {
264 if (likely(napi_schedule_prep(&mal->napi))) {
265 MAL_DBG2(mal, "schedule_poll" NL);
266 mal_disable_eob_irq(mal);
267 __napi_schedule(&mal->napi);
268 } else
269 MAL_DBG2(mal, "already in poll" NL);
270 }
271
272 static irqreturn_t mal_txeob(int irq, void *dev_instance)
273 {
274 struct mal_instance *mal = dev_instance;
275
276 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
277
278 MAL_DBG2(mal, "txeob %08x" NL, r);
279
280 mal_schedule_poll(mal);
281 set_mal_dcrn(mal, MAL_TXEOBISR, r);
282
283 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))
284 mtdcri(SDR0, DCRN_SDR_ICINTSTAT,
285 (mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICTX));
286
287 return IRQ_HANDLED;
288 }
289
290 static irqreturn_t mal_rxeob(int irq, void *dev_instance)
291 {
292 struct mal_instance *mal = dev_instance;
293
294 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
295
296 MAL_DBG2(mal, "rxeob %08x" NL, r);
297
298 mal_schedule_poll(mal);
299 set_mal_dcrn(mal, MAL_RXEOBISR, r);
300
301 if (mal_has_feature(mal, MAL_FTR_CLEAR_ICINTSTAT))
302 mtdcri(SDR0, DCRN_SDR_ICINTSTAT,
303 (mfdcri(SDR0, DCRN_SDR_ICINTSTAT) | ICINTSTAT_ICRX));
304
305 return IRQ_HANDLED;
306 }
307
308 static irqreturn_t mal_txde(int irq, void *dev_instance)
309 {
310 struct mal_instance *mal = dev_instance;
311
312 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
313 set_mal_dcrn(mal, MAL_TXDEIR, deir);
314
315 MAL_DBG(mal, "txde %08x" NL, deir);
316
317 if (net_ratelimit())
318 printk(KERN_ERR
319 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
320 mal->index, deir);
321
322 return IRQ_HANDLED;
323 }
324
325 static irqreturn_t mal_rxde(int irq, void *dev_instance)
326 {
327 struct mal_instance *mal = dev_instance;
328 struct list_head *l;
329
330 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
331
332 MAL_DBG(mal, "rxde %08x" NL, deir);
333
334 list_for_each(l, &mal->list) {
335 struct mal_commac *mc = list_entry(l, struct mal_commac, list);
336 if (deir & mc->rx_chan_mask) {
337 set_bit(MAL_COMMAC_RX_STOPPED, &mc->flags);
338 mc->ops->rxde(mc->dev);
339 }
340 }
341
342 mal_schedule_poll(mal);
343 set_mal_dcrn(mal, MAL_RXDEIR, deir);
344
345 return IRQ_HANDLED;
346 }
347
348 static irqreturn_t mal_int(int irq, void *dev_instance)
349 {
350 struct mal_instance *mal = dev_instance;
351 u32 esr = get_mal_dcrn(mal, MAL_ESR);
352
353 if (esr & MAL_ESR_EVB) {
354 /* descriptor error */
355 if (esr & MAL_ESR_DE) {
356 if (esr & MAL_ESR_CIDT)
357 return mal_rxde(irq, dev_instance);
358 else
359 return mal_txde(irq, dev_instance);
360 } else { /* SERR */
361 return mal_serr(irq, dev_instance);
362 }
363 }
364 return IRQ_HANDLED;
365 }
366
367 void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac)
368 {
369 /* Spinlock-type semantics: only one caller disable poll at a time */
370 while (test_and_set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags))
371 msleep(1);
372
373 /* Synchronize with the MAL NAPI poller */
374 napi_synchronize(&mal->napi);
375 }
376
377 void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac)
378 {
379 smp_wmb();
380 clear_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
381
382 /* Feels better to trigger a poll here to catch up with events that
383 * may have happened on this channel while disabled. It will most
384 * probably be delayed until the next interrupt but that's mostly a
385 * non-issue in the context where this is called.
386 */
387 napi_schedule(&mal->napi);
388 }
389
390 static int mal_poll(struct napi_struct *napi, int budget)
391 {
392 struct mal_instance *mal = container_of(napi, struct mal_instance, napi);
393 struct list_head *l;
394 int received = 0;
395 unsigned long flags;
396
397 MAL_DBG2(mal, "poll(%d)" NL, budget);
398 again:
399 /* Process TX skbs */
400 list_for_each(l, &mal->poll_list) {
401 struct mal_commac *mc =
402 list_entry(l, struct mal_commac, poll_list);
403 mc->ops->poll_tx(mc->dev);
404 }
405
406 /* Process RX skbs.
407 *
408 * We _might_ need something more smart here to enforce polling
409 * fairness.
410 */
411 list_for_each(l, &mal->poll_list) {
412 struct mal_commac *mc =
413 list_entry(l, struct mal_commac, poll_list);
414 int n;
415 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
416 continue;
417 n = mc->ops->poll_rx(mc->dev, budget);
418 if (n) {
419 received += n;
420 budget -= n;
421 if (budget <= 0)
422 goto more_work; // XXX What if this is the last one ?
423 }
424 }
425
426 /* We need to disable IRQs to protect from RXDE IRQ here */
427 spin_lock_irqsave(&mal->lock, flags);
428 __napi_complete(napi);
429 mal_enable_eob_irq(mal);
430 spin_unlock_irqrestore(&mal->lock, flags);
431
432 /* Check for "rotting" packet(s) */
433 list_for_each(l, &mal->poll_list) {
434 struct mal_commac *mc =
435 list_entry(l, struct mal_commac, poll_list);
436 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
437 continue;
438 if (unlikely(mc->ops->peek_rx(mc->dev) ||
439 test_bit(MAL_COMMAC_RX_STOPPED, &mc->flags))) {
440 MAL_DBG2(mal, "rotting packet" NL);
441 if (napi_reschedule(napi))
442 mal_disable_eob_irq(mal);
443 else
444 MAL_DBG2(mal, "already in poll list" NL);
445
446 if (budget > 0)
447 goto again;
448 else
449 goto more_work;
450 }
451 mc->ops->poll_tx(mc->dev);
452 }
453
454 more_work:
455 MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received);
456 return received;
457 }
458
459 static void mal_reset(struct mal_instance *mal)
460 {
461 int n = 10;
462
463 MAL_DBG(mal, "reset" NL);
464
465 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
466
467 /* Wait for reset to complete (1 system clock) */
468 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
469 --n;
470
471 if (unlikely(!n))
472 printk(KERN_ERR "mal%d: reset timeout\n", mal->index);
473 }
474
475 int mal_get_regs_len(struct mal_instance *mal)
476 {
477 return sizeof(struct emac_ethtool_regs_subhdr) +
478 sizeof(struct mal_regs);
479 }
480
481 void *mal_dump_regs(struct mal_instance *mal, void *buf)
482 {
483 struct emac_ethtool_regs_subhdr *hdr = buf;
484 struct mal_regs *regs = (struct mal_regs *)(hdr + 1);
485 int i;
486
487 hdr->version = mal->version;
488 hdr->index = mal->index;
489
490 regs->tx_count = mal->num_tx_chans;
491 regs->rx_count = mal->num_rx_chans;
492
493 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
494 regs->esr = get_mal_dcrn(mal, MAL_ESR);
495 regs->ier = get_mal_dcrn(mal, MAL_IER);
496 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
497 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
498 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
499 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
500 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
501 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
502 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
503 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
504
505 for (i = 0; i < regs->tx_count; ++i)
506 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
507
508 for (i = 0; i < regs->rx_count; ++i) {
509 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
510 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
511 }
512 return regs + 1;
513 }
514
515 static int __devinit mal_probe(struct of_device *ofdev,
516 const struct of_device_id *match)
517 {
518 struct mal_instance *mal;
519 int err = 0, i, bd_size;
520 int index = mal_count++;
521 unsigned int dcr_base;
522 const u32 *prop;
523 u32 cfg;
524 unsigned long irqflags;
525 irq_handler_t hdlr_serr, hdlr_txde, hdlr_rxde;
526
527 mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL);
528 if (!mal) {
529 printk(KERN_ERR
530 "mal%d: out of memory allocating MAL structure!\n",
531 index);
532 return -ENOMEM;
533 }
534 mal->index = index;
535 mal->ofdev = ofdev;
536 mal->version = of_device_is_compatible(ofdev->node, "ibm,mcmal2") ? 2 : 1;
537
538 MAL_DBG(mal, "probe" NL);
539
540 prop = of_get_property(ofdev->node, "num-tx-chans", NULL);
541 if (prop == NULL) {
542 printk(KERN_ERR
543 "mal%d: can't find MAL num-tx-chans property!\n",
544 index);
545 err = -ENODEV;
546 goto fail;
547 }
548 mal->num_tx_chans = prop[0];
549
550 prop = of_get_property(ofdev->node, "num-rx-chans", NULL);
551 if (prop == NULL) {
552 printk(KERN_ERR
553 "mal%d: can't find MAL num-rx-chans property!\n",
554 index);
555 err = -ENODEV;
556 goto fail;
557 }
558 mal->num_rx_chans = prop[0];
559
560 dcr_base = dcr_resource_start(ofdev->node, 0);
561 if (dcr_base == 0) {
562 printk(KERN_ERR
563 "mal%d: can't find DCR resource!\n", index);
564 err = -ENODEV;
565 goto fail;
566 }
567 mal->dcr_host = dcr_map(ofdev->node, dcr_base, 0x100);
568 if (!DCR_MAP_OK(mal->dcr_host)) {
569 printk(KERN_ERR
570 "mal%d: failed to map DCRs !\n", index);
571 err = -ENODEV;
572 goto fail;
573 }
574
575 if (of_device_is_compatible(ofdev->node, "ibm,mcmal-405ez"))
576 mal->features |= (MAL_FTR_CLEAR_ICINTSTAT |
577 MAL_FTR_COMMON_ERR_INT);
578
579 mal->txeob_irq = irq_of_parse_and_map(ofdev->node, 0);
580 mal->rxeob_irq = irq_of_parse_and_map(ofdev->node, 1);
581 mal->serr_irq = irq_of_parse_and_map(ofdev->node, 2);
582
583 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {
584 mal->txde_irq = mal->rxde_irq = mal->serr_irq;
585 } else {
586 mal->txde_irq = irq_of_parse_and_map(ofdev->node, 3);
587 mal->rxde_irq = irq_of_parse_and_map(ofdev->node, 4);
588 }
589
590 if (mal->txeob_irq == NO_IRQ || mal->rxeob_irq == NO_IRQ ||
591 mal->serr_irq == NO_IRQ || mal->txde_irq == NO_IRQ ||
592 mal->rxde_irq == NO_IRQ) {
593 printk(KERN_ERR
594 "mal%d: failed to map interrupts !\n", index);
595 err = -ENODEV;
596 goto fail_unmap;
597 }
598
599 INIT_LIST_HEAD(&mal->poll_list);
600 INIT_LIST_HEAD(&mal->list);
601 spin_lock_init(&mal->lock);
602
603 netif_napi_add(NULL, &mal->napi, mal_poll,
604 CONFIG_IBM_NEW_EMAC_POLL_WEIGHT);
605
606 /* Load power-on reset defaults */
607 mal_reset(mal);
608
609 /* Set the MAL configuration register */
610 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT;
611 cfg |= MAL_CFG_PLBB | MAL_CFG_OPBBL | MAL_CFG_LEA;
612
613 /* Current Axon is not happy with priority being non-0, it can
614 * deadlock, fix it up here
615 */
616 if (of_device_is_compatible(ofdev->node, "ibm,mcmal-axon"))
617 cfg &= ~(MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10);
618
619 /* Apply configuration */
620 set_mal_dcrn(mal, MAL_CFG, cfg);
621
622 /* Allocate space for BD rings */
623 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32);
624 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32);
625
626 bd_size = sizeof(struct mal_descriptor) *
627 (NUM_TX_BUFF * mal->num_tx_chans +
628 NUM_RX_BUFF * mal->num_rx_chans);
629 mal->bd_virt =
630 dma_alloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma,
631 GFP_KERNEL);
632 if (mal->bd_virt == NULL) {
633 printk(KERN_ERR
634 "mal%d: out of memory allocating RX/TX descriptors!\n",
635 index);
636 err = -ENOMEM;
637 goto fail_unmap;
638 }
639 memset(mal->bd_virt, 0, bd_size);
640
641 for (i = 0; i < mal->num_tx_chans; ++i)
642 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
643 sizeof(struct mal_descriptor) *
644 mal_tx_bd_offset(mal, i));
645
646 for (i = 0; i < mal->num_rx_chans; ++i)
647 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
648 sizeof(struct mal_descriptor) *
649 mal_rx_bd_offset(mal, i));
650
651 if (mal_has_feature(mal, MAL_FTR_COMMON_ERR_INT)) {
652 irqflags = IRQF_SHARED;
653 hdlr_serr = hdlr_txde = hdlr_rxde = mal_int;
654 } else {
655 irqflags = 0;
656 hdlr_serr = mal_serr;
657 hdlr_txde = mal_txde;
658 hdlr_rxde = mal_rxde;
659 }
660
661 err = request_irq(mal->serr_irq, hdlr_serr, irqflags, "MAL SERR", mal);
662 if (err)
663 goto fail2;
664 err = request_irq(mal->txde_irq, hdlr_txde, irqflags, "MAL TX DE", mal);
665 if (err)
666 goto fail3;
667 err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
668 if (err)
669 goto fail4;
670 err = request_irq(mal->rxde_irq, hdlr_rxde, irqflags, "MAL RX DE", mal);
671 if (err)
672 goto fail5;
673 err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
674 if (err)
675 goto fail6;
676
677 /* Enable all MAL SERR interrupt sources */
678 if (mal->version == 2)
679 set_mal_dcrn(mal, MAL_IER, MAL2_IER_EVENTS);
680 else
681 set_mal_dcrn(mal, MAL_IER, MAL1_IER_EVENTS);
682
683 /* Enable EOB interrupt */
684 mal_enable_eob_irq(mal);
685
686 printk(KERN_INFO
687 "MAL v%d %s, %d TX channels, %d RX channels\n",
688 mal->version, ofdev->node->full_name,
689 mal->num_tx_chans, mal->num_rx_chans);
690
691 /* Advertise this instance to the rest of the world */
692 wmb();
693 dev_set_drvdata(&ofdev->dev, mal);
694
695 mal_dbg_register(mal);
696
697 return 0;
698
699 fail6:
700 free_irq(mal->rxde_irq, mal);
701 fail5:
702 free_irq(mal->txeob_irq, mal);
703 fail4:
704 free_irq(mal->txde_irq, mal);
705 fail3:
706 free_irq(mal->serr_irq, mal);
707 fail2:
708 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
709 fail_unmap:
710 dcr_unmap(mal->dcr_host, 0x100);
711 fail:
712 kfree(mal);
713
714 return err;
715 }
716
717 static int __devexit mal_remove(struct of_device *ofdev)
718 {
719 struct mal_instance *mal = dev_get_drvdata(&ofdev->dev);
720
721 MAL_DBG(mal, "remove" NL);
722
723 /* Synchronize with scheduled polling */
724 napi_disable(&mal->napi);
725
726 if (!list_empty(&mal->list)) {
727 /* This is *very* bad */
728 printk(KERN_EMERG
729 "mal%d: commac list is not empty on remove!\n",
730 mal->index);
731 WARN_ON(1);
732 }
733
734 dev_set_drvdata(&ofdev->dev, NULL);
735
736 free_irq(mal->serr_irq, mal);
737 free_irq(mal->txde_irq, mal);
738 free_irq(mal->txeob_irq, mal);
739 free_irq(mal->rxde_irq, mal);
740 free_irq(mal->rxeob_irq, mal);
741
742 mal_reset(mal);
743
744 mal_dbg_unregister(mal);
745
746 dma_free_coherent(&ofdev->dev,
747 sizeof(struct mal_descriptor) *
748 (NUM_TX_BUFF * mal->num_tx_chans +
749 NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt,
750 mal->bd_dma);
751 kfree(mal);
752
753 return 0;
754 }
755
756 static struct of_device_id mal_platform_match[] =
757 {
758 {
759 .compatible = "ibm,mcmal",
760 },
761 {
762 .compatible = "ibm,mcmal2",
763 },
764 /* Backward compat */
765 {
766 .type = "mcmal-dma",
767 .compatible = "ibm,mcmal",
768 },
769 {
770 .type = "mcmal-dma",
771 .compatible = "ibm,mcmal2",
772 },
773 {},
774 };
775
776 static struct of_platform_driver mal_of_driver = {
777 .name = "mcmal",
778 .match_table = mal_platform_match,
779
780 .probe = mal_probe,
781 .remove = mal_remove,
782 };
783
784 int __init mal_init(void)
785 {
786 return of_register_platform_driver(&mal_of_driver);
787 }
788
789 void mal_exit(void)
790 {
791 of_unregister_platform_driver(&mal_of_driver);
792 }
Linux kernel - Deliverables
This page took 0.04754 seconds and 6 git commands to generate.