2 * AT86RF230/RF231 driver
4 * Copyright (C) 2009-2012 Siemens AG
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
21 * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/interrupt.h>
26 #include <linux/gpio.h>
27 #include <linux/delay.h>
28 #include <linux/mutex.h>
29 #include <linux/workqueue.h>
30 #include <linux/spinlock.h>
31 #include <linux/spi/spi.h>
32 #include <linux/spi/at86rf230.h>
33 #include <linux/skbuff.h>
34 #include <linux/of_gpio.h>
36 #include <net/mac802154.h>
37 #include <net/wpan-phy.h>
39 struct at86rf230_local
{
40 struct spi_device
*spi
;
48 struct work_struct irqwork
;
49 struct completion tx_complete
;
51 struct ieee802154_dev
*dev
;
61 static bool is_rf212(struct at86rf230_local
*local
)
63 return local
->part
== 7;
66 #define RG_TRX_STATUS (0x01)
67 #define SR_TRX_STATUS 0x01, 0x1f, 0
68 #define SR_RESERVED_01_3 0x01, 0x20, 5
69 #define SR_CCA_STATUS 0x01, 0x40, 6
70 #define SR_CCA_DONE 0x01, 0x80, 7
71 #define RG_TRX_STATE (0x02)
72 #define SR_TRX_CMD 0x02, 0x1f, 0
73 #define SR_TRAC_STATUS 0x02, 0xe0, 5
74 #define RG_TRX_CTRL_0 (0x03)
75 #define SR_CLKM_CTRL 0x03, 0x07, 0
76 #define SR_CLKM_SHA_SEL 0x03, 0x08, 3
77 #define SR_PAD_IO_CLKM 0x03, 0x30, 4
78 #define SR_PAD_IO 0x03, 0xc0, 6
79 #define RG_TRX_CTRL_1 (0x04)
80 #define SR_IRQ_POLARITY 0x04, 0x01, 0
81 #define SR_IRQ_MASK_MODE 0x04, 0x02, 1
82 #define SR_SPI_CMD_MODE 0x04, 0x0c, 2
83 #define SR_RX_BL_CTRL 0x04, 0x10, 4
84 #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
85 #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6
86 #define SR_PA_EXT_EN 0x04, 0x80, 7
87 #define RG_PHY_TX_PWR (0x05)
88 #define SR_TX_PWR 0x05, 0x0f, 0
89 #define SR_PA_LT 0x05, 0x30, 4
90 #define SR_PA_BUF_LT 0x05, 0xc0, 6
91 #define RG_PHY_RSSI (0x06)
92 #define SR_RSSI 0x06, 0x1f, 0
93 #define SR_RND_VALUE 0x06, 0x60, 5
94 #define SR_RX_CRC_VALID 0x06, 0x80, 7
95 #define RG_PHY_ED_LEVEL (0x07)
96 #define SR_ED_LEVEL 0x07, 0xff, 0
97 #define RG_PHY_CC_CCA (0x08)
98 #define SR_CHANNEL 0x08, 0x1f, 0
99 #define SR_CCA_MODE 0x08, 0x60, 5
100 #define SR_CCA_REQUEST 0x08, 0x80, 7
101 #define RG_CCA_THRES (0x09)
102 #define SR_CCA_ED_THRES 0x09, 0x0f, 0
103 #define SR_RESERVED_09_1 0x09, 0xf0, 4
104 #define RG_RX_CTRL (0x0a)
105 #define SR_PDT_THRES 0x0a, 0x0f, 0
106 #define SR_RESERVED_0a_1 0x0a, 0xf0, 4
107 #define RG_SFD_VALUE (0x0b)
108 #define SR_SFD_VALUE 0x0b, 0xff, 0
109 #define RG_TRX_CTRL_2 (0x0c)
110 #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
111 #define SR_SUB_MODE 0x0c, 0x04, 2
112 #define SR_BPSK_QPSK 0x0c, 0x08, 3
113 #define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4
114 #define SR_RESERVED_0c_5 0x0c, 0x60, 5
115 #define SR_RX_SAFE_MODE 0x0c, 0x80, 7
116 #define RG_ANT_DIV (0x0d)
117 #define SR_ANT_CTRL 0x0d, 0x03, 0
118 #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
119 #define SR_ANT_DIV_EN 0x0d, 0x08, 3
120 #define SR_RESERVED_0d_2 0x0d, 0x70, 4
121 #define SR_ANT_SEL 0x0d, 0x80, 7
122 #define RG_IRQ_MASK (0x0e)
123 #define SR_IRQ_MASK 0x0e, 0xff, 0
124 #define RG_IRQ_STATUS (0x0f)
125 #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
126 #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
127 #define SR_IRQ_2_RX_START 0x0f, 0x04, 2
128 #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
129 #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4
130 #define SR_IRQ_5_AMI 0x0f, 0x20, 5
131 #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
132 #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
133 #define RG_VREG_CTRL (0x10)
134 #define SR_RESERVED_10_6 0x10, 0x03, 0
135 #define SR_DVDD_OK 0x10, 0x04, 2
136 #define SR_DVREG_EXT 0x10, 0x08, 3
137 #define SR_RESERVED_10_3 0x10, 0x30, 4
138 #define SR_AVDD_OK 0x10, 0x40, 6
139 #define SR_AVREG_EXT 0x10, 0x80, 7
140 #define RG_BATMON (0x11)
141 #define SR_BATMON_VTH 0x11, 0x0f, 0
142 #define SR_BATMON_HR 0x11, 0x10, 4
143 #define SR_BATMON_OK 0x11, 0x20, 5
144 #define SR_RESERVED_11_1 0x11, 0xc0, 6
145 #define RG_XOSC_CTRL (0x12)
146 #define SR_XTAL_TRIM 0x12, 0x0f, 0
147 #define SR_XTAL_MODE 0x12, 0xf0, 4
148 #define RG_RX_SYN (0x15)
149 #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0
150 #define SR_RESERVED_15_2 0x15, 0x70, 4
151 #define SR_RX_PDT_DIS 0x15, 0x80, 7
152 #define RG_XAH_CTRL_1 (0x17)
153 #define SR_RESERVED_17_8 0x17, 0x01, 0
154 #define SR_AACK_PROM_MODE 0x17, 0x02, 1
155 #define SR_AACK_ACK_TIME 0x17, 0x04, 2
156 #define SR_RESERVED_17_5 0x17, 0x08, 3
157 #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
158 #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
159 #define SR_CSMA_LBT_MODE 0x17, 0x40, 6
160 #define SR_RESERVED_17_1 0x17, 0x80, 7
161 #define RG_FTN_CTRL (0x18)
162 #define SR_RESERVED_18_2 0x18, 0x7f, 0
163 #define SR_FTN_START 0x18, 0x80, 7
164 #define RG_PLL_CF (0x1a)
165 #define SR_RESERVED_1a_2 0x1a, 0x7f, 0
166 #define SR_PLL_CF_START 0x1a, 0x80, 7
167 #define RG_PLL_DCU (0x1b)
168 #define SR_RESERVED_1b_3 0x1b, 0x3f, 0
169 #define SR_RESERVED_1b_2 0x1b, 0x40, 6
170 #define SR_PLL_DCU_START 0x1b, 0x80, 7
171 #define RG_PART_NUM (0x1c)
172 #define SR_PART_NUM 0x1c, 0xff, 0
173 #define RG_VERSION_NUM (0x1d)
174 #define SR_VERSION_NUM 0x1d, 0xff, 0
175 #define RG_MAN_ID_0 (0x1e)
176 #define SR_MAN_ID_0 0x1e, 0xff, 0
177 #define RG_MAN_ID_1 (0x1f)
178 #define SR_MAN_ID_1 0x1f, 0xff, 0
179 #define RG_SHORT_ADDR_0 (0x20)
180 #define SR_SHORT_ADDR_0 0x20, 0xff, 0
181 #define RG_SHORT_ADDR_1 (0x21)
182 #define SR_SHORT_ADDR_1 0x21, 0xff, 0
183 #define RG_PAN_ID_0 (0x22)
184 #define SR_PAN_ID_0 0x22, 0xff, 0
185 #define RG_PAN_ID_1 (0x23)
186 #define SR_PAN_ID_1 0x23, 0xff, 0
187 #define RG_IEEE_ADDR_0 (0x24)
188 #define SR_IEEE_ADDR_0 0x24, 0xff, 0
189 #define RG_IEEE_ADDR_1 (0x25)
190 #define SR_IEEE_ADDR_1 0x25, 0xff, 0
191 #define RG_IEEE_ADDR_2 (0x26)
192 #define SR_IEEE_ADDR_2 0x26, 0xff, 0
193 #define RG_IEEE_ADDR_3 (0x27)
194 #define SR_IEEE_ADDR_3 0x27, 0xff, 0
195 #define RG_IEEE_ADDR_4 (0x28)
196 #define SR_IEEE_ADDR_4 0x28, 0xff, 0
197 #define RG_IEEE_ADDR_5 (0x29)
198 #define SR_IEEE_ADDR_5 0x29, 0xff, 0
199 #define RG_IEEE_ADDR_6 (0x2a)
200 #define SR_IEEE_ADDR_6 0x2a, 0xff, 0
201 #define RG_IEEE_ADDR_7 (0x2b)
202 #define SR_IEEE_ADDR_7 0x2b, 0xff, 0
203 #define RG_XAH_CTRL_0 (0x2c)
204 #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0
205 #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
206 #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
207 #define RG_CSMA_SEED_0 (0x2d)
208 #define SR_CSMA_SEED_0 0x2d, 0xff, 0
209 #define RG_CSMA_SEED_1 (0x2e)
210 #define SR_CSMA_SEED_1 0x2e, 0x07, 0
211 #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3
212 #define SR_AACK_DIS_ACK 0x2e, 0x10, 4
213 #define SR_AACK_SET_PD 0x2e, 0x20, 5
214 #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6
215 #define RG_CSMA_BE (0x2f)
216 #define SR_MIN_BE 0x2f, 0x0f, 0
217 #define SR_MAX_BE 0x2f, 0xf0, 4
220 #define CMD_REG_MASK 0x3f
221 #define CMD_WRITE 0x40
224 #define IRQ_BAT_LOW (1 << 7)
225 #define IRQ_TRX_UR (1 << 6)
226 #define IRQ_AMI (1 << 5)
227 #define IRQ_CCA_ED (1 << 4)
228 #define IRQ_TRX_END (1 << 3)
229 #define IRQ_RX_START (1 << 2)
230 #define IRQ_PLL_UNL (1 << 1)
231 #define IRQ_PLL_LOCK (1 << 0)
233 #define IRQ_ACTIVE_HIGH 0
234 #define IRQ_ACTIVE_LOW 1
236 #define STATE_P_ON 0x00 /* BUSY */
237 #define STATE_BUSY_RX 0x01
238 #define STATE_BUSY_TX 0x02
239 #define STATE_FORCE_TRX_OFF 0x03
240 #define STATE_FORCE_TX_ON 0x04 /* IDLE */
241 /* 0x05 */ /* INVALID_PARAMETER */
242 #define STATE_RX_ON 0x06
243 /* 0x07 */ /* SUCCESS */
244 #define STATE_TRX_OFF 0x08
245 #define STATE_TX_ON 0x09
246 /* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */
247 #define STATE_SLEEP 0x0F
248 #define STATE_PREP_DEEP_SLEEP 0x10
249 #define STATE_BUSY_RX_AACK 0x11
250 #define STATE_BUSY_TX_ARET 0x12
251 #define STATE_RX_AACK_ON 0x16
252 #define STATE_TX_ARET_ON 0x19
253 #define STATE_RX_ON_NOCLK 0x1C
254 #define STATE_RX_AACK_ON_NOCLK 0x1D
255 #define STATE_BUSY_RX_AACK_NOCLK 0x1E
256 #define STATE_TRANSITION_IN_PROGRESS 0x1F
259 __at86rf230_detect_device(struct spi_device
*spi
, u16
*man_id
, u8
*part
,
263 u8
*buf
= kmalloc(2, GFP_KERNEL
);
265 struct spi_message msg
;
266 struct spi_transfer xfer
= {
276 for (reg
= RG_PART_NUM
; reg
<= RG_MAN_ID_1
; reg
++) {
277 buf
[0] = (reg
& CMD_REG_MASK
) | CMD_REG
;
279 dev_vdbg(&spi
->dev
, "buf[0] = %02x\n", buf
[0]);
280 spi_message_init(&msg
);
281 spi_message_add_tail(&xfer
, &msg
);
283 status
= spi_sync(spi
, &msg
);
284 dev_vdbg(&spi
->dev
, "status = %d\n", status
);
288 dev_vdbg(&spi
->dev
, "status = %d\n", status
);
289 dev_vdbg(&spi
->dev
, "buf[0] = %02x\n", buf
[0]);
290 dev_vdbg(&spi
->dev
, "buf[1] = %02x\n", buf
[1]);
293 data
[reg
- RG_PART_NUM
] = buf
[1];
301 *man_id
= (data
[3] << 8) | data
[2];
310 __at86rf230_write(struct at86rf230_local
*lp
, u8 addr
, u8 data
)
314 struct spi_message msg
;
315 struct spi_transfer xfer
= {
320 buf
[0] = (addr
& CMD_REG_MASK
) | CMD_REG
| CMD_WRITE
;
322 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
323 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
324 spi_message_init(&msg
);
325 spi_message_add_tail(&xfer
, &msg
);
327 status
= spi_sync(lp
->spi
, &msg
);
328 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
332 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
333 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
334 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
340 __at86rf230_read_subreg(struct at86rf230_local
*lp
,
341 u8 addr
, u8 mask
, int shift
, u8
*data
)
345 struct spi_message msg
;
346 struct spi_transfer xfer
= {
352 buf
[0] = (addr
& CMD_REG_MASK
) | CMD_REG
;
354 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
355 spi_message_init(&msg
);
356 spi_message_add_tail(&xfer
, &msg
);
358 status
= spi_sync(lp
->spi
, &msg
);
359 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
363 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
364 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
365 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
374 at86rf230_read_subreg(struct at86rf230_local
*lp
,
375 u8 addr
, u8 mask
, int shift
, u8
*data
)
379 mutex_lock(&lp
->bmux
);
380 status
= __at86rf230_read_subreg(lp
, addr
, mask
, shift
, data
);
381 mutex_unlock(&lp
->bmux
);
387 at86rf230_write_subreg(struct at86rf230_local
*lp
,
388 u8 addr
, u8 mask
, int shift
, u8 data
)
393 mutex_lock(&lp
->bmux
);
394 status
= __at86rf230_read_subreg(lp
, addr
, 0xff, 0, &val
);
399 val
|= (data
<< shift
) & mask
;
401 status
= __at86rf230_write(lp
, addr
, val
);
403 mutex_unlock(&lp
->bmux
);
409 at86rf230_write_fbuf(struct at86rf230_local
*lp
, u8
*data
, u8 len
)
413 struct spi_message msg
;
414 struct spi_transfer xfer_head
= {
419 struct spi_transfer xfer_buf
= {
424 mutex_lock(&lp
->bmux
);
425 buf
[0] = CMD_WRITE
| CMD_FB
;
426 buf
[1] = len
+ 2; /* 2 bytes for CRC that isn't written */
428 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
429 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
431 spi_message_init(&msg
);
432 spi_message_add_tail(&xfer_head
, &msg
);
433 spi_message_add_tail(&xfer_buf
, &msg
);
435 status
= spi_sync(lp
->spi
, &msg
);
436 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
440 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
441 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
442 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
444 mutex_unlock(&lp
->bmux
);
449 at86rf230_read_fbuf(struct at86rf230_local
*lp
, u8
*data
, u8
*len
, u8
*lqi
)
453 struct spi_message msg
;
454 struct spi_transfer xfer_head
= {
459 struct spi_transfer xfer_head1
= {
464 struct spi_transfer xfer_buf
= {
469 mutex_lock(&lp
->bmux
);
474 spi_message_init(&msg
);
475 spi_message_add_tail(&xfer_head
, &msg
);
477 status
= spi_sync(lp
->spi
, &msg
);
478 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
480 xfer_buf
.len
= *(buf
+ 1) + 1;
486 spi_message_init(&msg
);
487 spi_message_add_tail(&xfer_head1
, &msg
);
488 spi_message_add_tail(&xfer_buf
, &msg
);
490 status
= spi_sync(lp
->spi
, &msg
);
495 dev_vdbg(&lp
->spi
->dev
, "status = %d\n", status
);
496 dev_vdbg(&lp
->spi
->dev
, "buf[0] = %02x\n", buf
[0]);
497 dev_vdbg(&lp
->spi
->dev
, "buf[1] = %02x\n", buf
[1]);
500 if (lqi
&& (*len
> lp
->buf
[1]))
501 *lqi
= data
[lp
->buf
[1]];
503 mutex_unlock(&lp
->bmux
);
509 at86rf230_ed(struct ieee802154_dev
*dev
, u8
*level
)
518 at86rf230_state(struct ieee802154_dev
*dev
, int state
)
520 struct at86rf230_local
*lp
= dev
->priv
;
527 if (state
== STATE_FORCE_TX_ON
)
528 desired_status
= STATE_TX_ON
;
529 else if (state
== STATE_FORCE_TRX_OFF
)
530 desired_status
= STATE_TRX_OFF
;
532 desired_status
= state
;
535 rc
= at86rf230_read_subreg(lp
, SR_TRX_STATUS
, &val
);
538 } while (val
== STATE_TRANSITION_IN_PROGRESS
);
540 if (val
== desired_status
)
543 /* state is equal to phy states */
544 rc
= at86rf230_write_subreg(lp
, SR_TRX_CMD
, state
);
549 rc
= at86rf230_read_subreg(lp
, SR_TRX_STATUS
, &val
);
552 } while (val
== STATE_TRANSITION_IN_PROGRESS
);
555 if (val
== desired_status
||
556 (desired_status
== STATE_RX_ON
&& val
== STATE_BUSY_RX
) ||
557 (desired_status
== STATE_RX_AACK_ON
&& val
== STATE_BUSY_RX_AACK
))
560 pr_err("unexpected state change: %d, asked for %d\n", val
, state
);
564 pr_err("error: %d\n", rc
);
569 at86rf230_start(struct ieee802154_dev
*dev
)
571 struct at86rf230_local
*lp
= dev
->priv
;
574 rc
= at86rf230_write_subreg(lp
, SR_RX_SAFE_MODE
, 1);
578 rc
= at86rf230_state(dev
, STATE_TX_ON
);
582 return at86rf230_state(dev
, STATE_RX_AACK_ON
);
586 at86rf230_stop(struct ieee802154_dev
*dev
)
588 at86rf230_state(dev
, STATE_FORCE_TRX_OFF
);
592 at86rf230_set_channel(struct at86rf230_local
*lp
, int page
, int channel
)
594 lp
->rssi_base_val
= -91;
596 return at86rf230_write_subreg(lp
, SR_CHANNEL
, channel
);
600 at86rf212_set_channel(struct at86rf230_local
*lp
, int page
, int channel
)
605 rc
= at86rf230_write_subreg(lp
, SR_SUB_MODE
, 0);
607 rc
= at86rf230_write_subreg(lp
, SR_SUB_MODE
, 1);
612 rc
= at86rf230_write_subreg(lp
, SR_BPSK_QPSK
, 0);
613 lp
->rssi_base_val
= -100;
615 rc
= at86rf230_write_subreg(lp
, SR_BPSK_QPSK
, 1);
616 lp
->rssi_base_val
= -98;
621 return at86rf230_write_subreg(lp
, SR_CHANNEL
, channel
);
625 at86rf230_channel(struct ieee802154_dev
*dev
, int page
, int channel
)
627 struct at86rf230_local
*lp
= dev
->priv
;
632 if (page
< 0 || page
> 31 ||
633 !(lp
->dev
->phy
->channels_supported
[page
] & BIT(channel
))) {
639 rc
= at86rf212_set_channel(lp
, page
, channel
);
641 rc
= at86rf230_set_channel(lp
, page
, channel
);
645 msleep(1); /* Wait for PLL */
646 dev
->phy
->current_channel
= channel
;
647 dev
->phy
->current_page
= page
;
653 at86rf230_xmit(struct ieee802154_dev
*dev
, struct sk_buff
*skb
)
655 struct at86rf230_local
*lp
= dev
->priv
;
659 spin_lock_irqsave(&lp
->lock
, flags
);
661 spin_unlock_irqrestore(&lp
->lock
, flags
);
664 spin_unlock_irqrestore(&lp
->lock
, flags
);
668 rc
= at86rf230_state(dev
, STATE_FORCE_TX_ON
);
672 spin_lock_irqsave(&lp
->lock
, flags
);
674 reinit_completion(&lp
->tx_complete
);
675 spin_unlock_irqrestore(&lp
->lock
, flags
);
677 rc
= at86rf230_write_fbuf(lp
, skb
->data
, skb
->len
);
682 rc
= at86rf230_write_subreg(lp
, SR_TRX_CMD
, STATE_TX_ARET_ON
);
687 rc
= at86rf230_write_subreg(lp
, SR_TRX_CMD
, STATE_BUSY_TX
);
691 rc
= wait_for_completion_interruptible(&lp
->tx_complete
);
695 rc
= at86rf230_start(dev
);
700 at86rf230_start(dev
);
702 pr_err("error: %d\n", rc
);
704 spin_lock_irqsave(&lp
->lock
, flags
);
706 spin_unlock_irqrestore(&lp
->lock
, flags
);
711 static int at86rf230_rx(struct at86rf230_local
*lp
)
713 u8 len
= 128, lqi
= 0;
716 skb
= alloc_skb(len
, GFP_KERNEL
);
721 if (at86rf230_read_fbuf(lp
, skb_put(skb
, len
), &len
, &lqi
))
727 skb_trim(skb
, len
- 2); /* We do not put CRC into the frame */
729 ieee802154_rx_irqsafe(lp
->dev
, skb
, lqi
);
731 dev_dbg(&lp
->spi
->dev
, "READ_FBUF: %d %x\n", len
, lqi
);
735 pr_debug("received frame is too small\n");
742 at86rf230_set_hw_addr_filt(struct ieee802154_dev
*dev
,
743 struct ieee802154_hw_addr_filt
*filt
,
744 unsigned long changed
)
746 struct at86rf230_local
*lp
= dev
->priv
;
748 if (changed
& IEEE802515_AFILT_SADDR_CHANGED
) {
749 u16 addr
= le16_to_cpu(filt
->short_addr
);
751 dev_vdbg(&lp
->spi
->dev
,
752 "at86rf230_set_hw_addr_filt called for saddr\n");
753 __at86rf230_write(lp
, RG_SHORT_ADDR_0
, addr
);
754 __at86rf230_write(lp
, RG_SHORT_ADDR_1
, addr
>> 8);
757 if (changed
& IEEE802515_AFILT_PANID_CHANGED
) {
758 u16 pan
= le16_to_cpu(filt
->pan_id
);
760 dev_vdbg(&lp
->spi
->dev
,
761 "at86rf230_set_hw_addr_filt called for pan id\n");
762 __at86rf230_write(lp
, RG_PAN_ID_0
, pan
);
763 __at86rf230_write(lp
, RG_PAN_ID_1
, pan
>> 8);
766 if (changed
& IEEE802515_AFILT_IEEEADDR_CHANGED
) {
769 memcpy(addr
, &filt
->ieee_addr
, 8);
770 dev_vdbg(&lp
->spi
->dev
,
771 "at86rf230_set_hw_addr_filt called for IEEE addr\n");
772 for (i
= 0; i
< 8; i
++)
773 __at86rf230_write(lp
, RG_IEEE_ADDR_0
+ i
, addr
[i
]);
776 if (changed
& IEEE802515_AFILT_PANC_CHANGED
) {
777 dev_vdbg(&lp
->spi
->dev
,
778 "at86rf230_set_hw_addr_filt called for panc change\n");
780 at86rf230_write_subreg(lp
, SR_AACK_I_AM_COORD
, 1);
782 at86rf230_write_subreg(lp
, SR_AACK_I_AM_COORD
, 0);
789 at86rf212_set_txpower(struct ieee802154_dev
*dev
, int db
)
791 struct at86rf230_local
*lp
= dev
->priv
;
793 /* typical maximum output is 5dBm with RG_PHY_TX_PWR 0x60, lower five
794 * bits decrease power in 1dB steps. 0x60 represents extra PA gain of
796 * thus, supported values for db range from -26 to 5, for 31dB of
797 * reduction to 0dB of reduction.
799 if (db
> 5 || db
< -26)
804 return __at86rf230_write(lp
, RG_PHY_TX_PWR
, 0x60 | db
);
808 at86rf212_set_lbt(struct ieee802154_dev
*dev
, bool on
)
810 struct at86rf230_local
*lp
= dev
->priv
;
812 return at86rf230_write_subreg(lp
, SR_CSMA_LBT_MODE
, on
);
816 at86rf212_set_cca_mode(struct ieee802154_dev
*dev
, u8 mode
)
818 struct at86rf230_local
*lp
= dev
->priv
;
820 return at86rf230_write_subreg(lp
, SR_CCA_MODE
, mode
);
824 at86rf212_set_cca_ed_level(struct ieee802154_dev
*dev
, s32 level
)
826 struct at86rf230_local
*lp
= dev
->priv
;
829 if (level
< lp
->rssi_base_val
|| level
> 30)
832 desens_steps
= (level
- lp
->rssi_base_val
) * 100 / 207;
834 return at86rf230_write_subreg(lp
, SR_CCA_ED_THRES
, desens_steps
);
838 at86rf212_set_csma_params(struct ieee802154_dev
*dev
, u8 min_be
, u8 max_be
,
841 struct at86rf230_local
*lp
= dev
->priv
;
844 if (min_be
> max_be
|| max_be
> 8 || retries
> 5)
847 rc
= at86rf230_write_subreg(lp
, SR_MIN_BE
, min_be
);
851 rc
= at86rf230_write_subreg(lp
, SR_MAX_BE
, max_be
);
855 return at86rf230_write_subreg(lp
, SR_MAX_CSMA_RETRIES
, retries
);
859 at86rf212_set_frame_retries(struct ieee802154_dev
*dev
, s8 retries
)
861 struct at86rf230_local
*lp
= dev
->priv
;
864 if (retries
< -1 || retries
> 15)
867 lp
->tx_aret
= retries
>= 0;
870 rc
= at86rf230_write_subreg(lp
, SR_MAX_FRAME_RETRIES
, retries
);
875 static struct ieee802154_ops at86rf230_ops
= {
876 .owner
= THIS_MODULE
,
877 .xmit
= at86rf230_xmit
,
879 .set_channel
= at86rf230_channel
,
880 .start
= at86rf230_start
,
881 .stop
= at86rf230_stop
,
882 .set_hw_addr_filt
= at86rf230_set_hw_addr_filt
,
885 static struct ieee802154_ops at86rf212_ops
= {
886 .owner
= THIS_MODULE
,
887 .xmit
= at86rf230_xmit
,
889 .set_channel
= at86rf230_channel
,
890 .start
= at86rf230_start
,
891 .stop
= at86rf230_stop
,
892 .set_hw_addr_filt
= at86rf230_set_hw_addr_filt
,
893 .set_txpower
= at86rf212_set_txpower
,
894 .set_lbt
= at86rf212_set_lbt
,
895 .set_cca_mode
= at86rf212_set_cca_mode
,
896 .set_cca_ed_level
= at86rf212_set_cca_ed_level
,
897 .set_csma_params
= at86rf212_set_csma_params
,
898 .set_frame_retries
= at86rf212_set_frame_retries
,
901 static void at86rf230_irqwork(struct work_struct
*work
)
903 struct at86rf230_local
*lp
=
904 container_of(work
, struct at86rf230_local
, irqwork
);
909 rc
= at86rf230_read_subreg(lp
, RG_IRQ_STATUS
, 0xff, 0, &val
);
912 status
&= ~IRQ_PLL_LOCK
; /* ignore */
913 status
&= ~IRQ_RX_START
; /* ignore */
914 status
&= ~IRQ_AMI
; /* ignore */
915 status
&= ~IRQ_TRX_UR
; /* FIXME: possibly handle ???*/
917 if (status
& IRQ_TRX_END
) {
918 status
&= ~IRQ_TRX_END
;
919 spin_lock_irqsave(&lp
->lock
, flags
);
922 spin_unlock_irqrestore(&lp
->lock
, flags
);
923 complete(&lp
->tx_complete
);
925 spin_unlock_irqrestore(&lp
->lock
, flags
);
930 spin_lock_irqsave(&lp
->lock
, flags
);
932 spin_unlock_irqrestore(&lp
->lock
, flags
);
935 static void at86rf230_irqwork_level(struct work_struct
*work
)
937 struct at86rf230_local
*lp
=
938 container_of(work
, struct at86rf230_local
, irqwork
);
940 at86rf230_irqwork(work
);
942 enable_irq(lp
->spi
->irq
);
945 static irqreturn_t
at86rf230_isr(int irq
, void *data
)
947 struct at86rf230_local
*lp
= data
;
950 spin_lock_irqsave(&lp
->lock
, flags
);
952 spin_unlock_irqrestore(&lp
->lock
, flags
);
954 schedule_work(&lp
->irqwork
);
959 static irqreturn_t
at86rf230_isr_level(int irq
, void *data
)
961 disable_irq_nosync(irq
);
963 return at86rf230_isr(irq
, data
);
966 static int at86rf230_irq_polarity(struct at86rf230_local
*lp
, int pol
)
968 return at86rf230_write_subreg(lp
, SR_IRQ_POLARITY
, pol
);
971 static int at86rf230_hw_init(struct at86rf230_local
*lp
)
973 struct at86rf230_platform_data
*pdata
= lp
->spi
->dev
.platform_data
;
978 rc
= at86rf230_read_subreg(lp
, SR_TRX_STATUS
, &status
);
982 rc
= at86rf230_write_subreg(lp
, SR_TRX_CMD
, STATE_FORCE_TRX_OFF
);
986 /* configure irq polarity, defaults to high active */
987 if (pdata
->irq_type
& (IRQF_TRIGGER_FALLING
| IRQF_TRIGGER_LOW
))
988 irq_pol
= IRQ_ACTIVE_LOW
;
990 irq_pol
= IRQ_ACTIVE_HIGH
;
992 rc
= at86rf230_irq_polarity(lp
, irq_pol
);
996 rc
= at86rf230_write_subreg(lp
, SR_IRQ_MASK
, IRQ_TRX_END
);
1000 get_random_bytes(csma_seed
, ARRAY_SIZE(csma_seed
));
1001 rc
= at86rf230_write_subreg(lp
, SR_CSMA_SEED_0
, csma_seed
[0]);
1004 rc
= at86rf230_write_subreg(lp
, SR_CSMA_SEED_1
, csma_seed
[1]);
1008 /* CLKM changes are applied immediately */
1009 rc
= at86rf230_write_subreg(lp
, SR_CLKM_SHA_SEL
, 0x00);
1014 rc
= at86rf230_write_subreg(lp
, SR_CLKM_CTRL
, 0x00);
1017 /* Wait the next SLEEP cycle */
1020 rc
= at86rf230_read_subreg(lp
, SR_DVDD_OK
, &status
);
1024 dev_err(&lp
->spi
->dev
, "DVDD error\n");
1031 static struct at86rf230_platform_data
*
1032 at86rf230_get_pdata(struct spi_device
*spi
)
1034 struct at86rf230_platform_data
*pdata
;
1035 const char *irq_type
;
1037 if (!IS_ENABLED(CONFIG_OF
) || !spi
->dev
.of_node
)
1038 return spi
->dev
.platform_data
;
1040 pdata
= devm_kzalloc(&spi
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1044 pdata
->rstn
= of_get_named_gpio(spi
->dev
.of_node
, "reset-gpio", 0);
1045 pdata
->slp_tr
= of_get_named_gpio(spi
->dev
.of_node
, "sleep-gpio", 0);
1047 pdata
->irq_type
= IRQF_TRIGGER_RISING
;
1048 of_property_read_string(spi
->dev
.of_node
, "irq-type", &irq_type
);
1049 if (!strcmp(irq_type
, "level-high"))
1050 pdata
->irq_type
= IRQF_TRIGGER_HIGH
;
1051 else if (!strcmp(irq_type
, "level-low"))
1052 pdata
->irq_type
= IRQF_TRIGGER_LOW
;
1053 else if (!strcmp(irq_type
, "edge-rising"))
1054 pdata
->irq_type
= IRQF_TRIGGER_RISING
;
1055 else if (!strcmp(irq_type
, "edge-falling"))
1056 pdata
->irq_type
= IRQF_TRIGGER_FALLING
;
1058 dev_warn(&spi
->dev
, "wrong irq-type specified using edge-rising\n");
1060 spi
->dev
.platform_data
= pdata
;
1065 static int at86rf230_probe(struct spi_device
*spi
)
1067 struct at86rf230_platform_data
*pdata
;
1068 struct ieee802154_dev
*dev
;
1069 struct at86rf230_local
*lp
;
1071 u8 part
= 0, version
= 0, status
;
1072 irq_handler_t irq_handler
;
1073 work_func_t irq_worker
;
1076 struct ieee802154_ops
*ops
= NULL
;
1079 dev_err(&spi
->dev
, "no IRQ specified\n");
1083 pdata
= at86rf230_get_pdata(spi
);
1085 dev_err(&spi
->dev
, "no platform_data\n");
1089 if (gpio_is_valid(pdata
->rstn
)) {
1090 rc
= gpio_request(pdata
->rstn
, "rstn");
1095 if (gpio_is_valid(pdata
->slp_tr
)) {
1096 rc
= gpio_request(pdata
->slp_tr
, "slp_tr");
1101 if (gpio_is_valid(pdata
->rstn
)) {
1102 rc
= gpio_direction_output(pdata
->rstn
, 1);
1107 if (gpio_is_valid(pdata
->slp_tr
)) {
1108 rc
= gpio_direction_output(pdata
->slp_tr
, 0);
1114 if (gpio_is_valid(pdata
->rstn
)) {
1116 gpio_set_value(pdata
->rstn
, 0);
1118 gpio_set_value(pdata
->rstn
, 1);
1119 usleep_range(120, 240);
1122 rc
= __at86rf230_detect_device(spi
, &man_id
, &part
, &version
);
1126 if (man_id
!= 0x001f) {
1127 dev_err(&spi
->dev
, "Non-Atmel dev found (MAN_ID %02x %02x)\n",
1128 man_id
>> 8, man_id
& 0xFF);
1136 /* FIXME: should be easy to support; */
1140 ops
= &at86rf230_ops
;
1145 ops
= &at86rf212_ops
;
1149 ops
= &at86rf230_ops
;
1156 dev_info(&spi
->dev
, "Detected %s chip version %d\n", chip
, version
);
1162 dev
= ieee802154_alloc_device(sizeof(*lp
), ops
);
1175 dev
->parent
= &spi
->dev
;
1176 dev
->extra_tx_headroom
= 0;
1177 dev
->flags
= IEEE802154_HW_OMIT_CKSUM
| IEEE802154_HW_AACK
;
1179 if (pdata
->irq_type
& (IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
)) {
1180 irq_worker
= at86rf230_irqwork
;
1181 irq_handler
= at86rf230_isr
;
1183 irq_worker
= at86rf230_irqwork_level
;
1184 irq_handler
= at86rf230_isr_level
;
1187 mutex_init(&lp
->bmux
);
1188 INIT_WORK(&lp
->irqwork
, irq_worker
);
1189 spin_lock_init(&lp
->lock
);
1190 init_completion(&lp
->tx_complete
);
1192 spi_set_drvdata(spi
, lp
);
1195 dev
->phy
->channels_supported
[0] = 0x00007FF;
1196 dev
->phy
->channels_supported
[2] = 0x00007FF;
1198 dev
->phy
->channels_supported
[0] = 0x7FFF800;
1201 rc
= at86rf230_hw_init(lp
);
1205 rc
= request_irq(spi
->irq
, irq_handler
,
1206 IRQF_SHARED
| pdata
->irq_type
,
1207 dev_name(&spi
->dev
), lp
);
1211 /* Read irq status register to reset irq line */
1212 rc
= at86rf230_read_subreg(lp
, RG_IRQ_STATUS
, 0xff, 0, &status
);
1216 rc
= ieee802154_register_device(lp
->dev
);
1223 free_irq(spi
->irq
, lp
);
1225 flush_work(&lp
->irqwork
);
1226 spi_set_drvdata(spi
, NULL
);
1227 mutex_destroy(&lp
->bmux
);
1228 ieee802154_free_device(lp
->dev
);
1231 if (gpio_is_valid(pdata
->slp_tr
))
1232 gpio_free(pdata
->slp_tr
);
1234 if (gpio_is_valid(pdata
->rstn
))
1235 gpio_free(pdata
->rstn
);
1239 static int at86rf230_remove(struct spi_device
*spi
)
1241 struct at86rf230_local
*lp
= spi_get_drvdata(spi
);
1242 struct at86rf230_platform_data
*pdata
= spi
->dev
.platform_data
;
1244 /* mask all at86rf230 irq's */
1245 at86rf230_write_subreg(lp
, SR_IRQ_MASK
, 0);
1246 ieee802154_unregister_device(lp
->dev
);
1248 free_irq(spi
->irq
, lp
);
1249 flush_work(&lp
->irqwork
);
1251 if (gpio_is_valid(pdata
->slp_tr
))
1252 gpio_free(pdata
->slp_tr
);
1253 if (gpio_is_valid(pdata
->rstn
))
1254 gpio_free(pdata
->rstn
);
1256 mutex_destroy(&lp
->bmux
);
1257 ieee802154_free_device(lp
->dev
);
1259 dev_dbg(&spi
->dev
, "unregistered at86rf230\n");
1263 #if IS_ENABLED(CONFIG_OF)
1264 static struct of_device_id at86rf230_of_match
[] = {
1265 { .compatible
= "atmel,at86rf230", },
1266 { .compatible
= "atmel,at86rf231", },
1267 { .compatible
= "atmel,at86rf233", },
1268 { .compatible
= "atmel,at86rf212", },
1273 static struct spi_driver at86rf230_driver
= {
1275 .of_match_table
= of_match_ptr(at86rf230_of_match
),
1276 .name
= "at86rf230",
1277 .owner
= THIS_MODULE
,
1279 .probe
= at86rf230_probe
,
1280 .remove
= at86rf230_remove
,
1283 module_spi_driver(at86rf230_driver
);
1285 MODULE_DESCRIPTION("AT86RF230 Transceiver Driver");
1286 MODULE_LICENSE("GPL v2");