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Merge branch 'for-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetoot...
[deliverable/linux.git] / drivers / net / ieee802154 / at86rf230.c
1 /*
2 * AT86RF230/RF231 driver
3 *
4 * Copyright (C) 2009-2012 Siemens AG
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * Written by:
16 * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
17 * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
18 * Alexander Aring <aar@pengutronix.de>
19 */
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/hrtimer.h>
23 #include <linux/jiffies.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/gpio.h>
27 #include <linux/delay.h>
28 #include <linux/spinlock.h>
29 #include <linux/spi/spi.h>
30 #include <linux/spi/at86rf230.h>
31 #include <linux/regmap.h>
32 #include <linux/skbuff.h>
33 #include <linux/of_gpio.h>
34 #include <linux/ieee802154.h>
35
36 #include <net/mac802154.h>
37 #include <net/cfg802154.h>
38
39 struct at86rf230_local;
40 /* at86rf2xx chip depend data.
41 * All timings are in us.
42 */
43 struct at86rf2xx_chip_data {
44 u16 t_sleep_cycle;
45 u16 t_channel_switch;
46 u16 t_reset_to_off;
47 u16 t_off_to_aack;
48 u16 t_off_to_tx_on;
49 u16 t_frame;
50 u16 t_p_ack;
51 int rssi_base_val;
52
53 int (*set_channel)(struct at86rf230_local *, u8, u8);
54 int (*get_desense_steps)(struct at86rf230_local *, s32);
55 };
56
57 #define AT86RF2XX_MAX_BUF (127 + 3)
58 /* tx retries to access the TX_ON state
59 * if it's above then force change will be started.
60 *
61 * We assume the max_frame_retries (7) value of 802.15.4 here.
62 */
63 #define AT86RF2XX_MAX_TX_RETRIES 7
64 /* We use the recommended 5 minutes timeout to recalibrate */
65 #define AT86RF2XX_CAL_LOOP_TIMEOUT (5 * 60 * HZ)
66
67 struct at86rf230_state_change {
68 struct at86rf230_local *lp;
69 int irq;
70
71 struct hrtimer timer;
72 struct spi_message msg;
73 struct spi_transfer trx;
74 u8 buf[AT86RF2XX_MAX_BUF];
75
76 void (*complete)(void *context);
77 u8 from_state;
78 u8 to_state;
79
80 bool irq_enable;
81 };
82
83 struct at86rf230_local {
84 struct spi_device *spi;
85
86 struct ieee802154_hw *hw;
87 struct at86rf2xx_chip_data *data;
88 struct regmap *regmap;
89
90 struct completion state_complete;
91 struct at86rf230_state_change state;
92
93 struct at86rf230_state_change irq;
94
95 bool tx_aret;
96 unsigned long cal_timeout;
97 s8 max_frame_retries;
98 bool is_tx;
99 /* spinlock for is_tx protection */
100 spinlock_t lock;
101 u8 tx_retry;
102 struct sk_buff *tx_skb;
103 struct at86rf230_state_change tx;
104 };
105
106 #define RG_TRX_STATUS (0x01)
107 #define SR_TRX_STATUS 0x01, 0x1f, 0
108 #define SR_RESERVED_01_3 0x01, 0x20, 5
109 #define SR_CCA_STATUS 0x01, 0x40, 6
110 #define SR_CCA_DONE 0x01, 0x80, 7
111 #define RG_TRX_STATE (0x02)
112 #define SR_TRX_CMD 0x02, 0x1f, 0
113 #define SR_TRAC_STATUS 0x02, 0xe0, 5
114 #define RG_TRX_CTRL_0 (0x03)
115 #define SR_CLKM_CTRL 0x03, 0x07, 0
116 #define SR_CLKM_SHA_SEL 0x03, 0x08, 3
117 #define SR_PAD_IO_CLKM 0x03, 0x30, 4
118 #define SR_PAD_IO 0x03, 0xc0, 6
119 #define RG_TRX_CTRL_1 (0x04)
120 #define SR_IRQ_POLARITY 0x04, 0x01, 0
121 #define SR_IRQ_MASK_MODE 0x04, 0x02, 1
122 #define SR_SPI_CMD_MODE 0x04, 0x0c, 2
123 #define SR_RX_BL_CTRL 0x04, 0x10, 4
124 #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
125 #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6
126 #define SR_PA_EXT_EN 0x04, 0x80, 7
127 #define RG_PHY_TX_PWR (0x05)
128 #define SR_TX_PWR 0x05, 0x0f, 0
129 #define SR_PA_LT 0x05, 0x30, 4
130 #define SR_PA_BUF_LT 0x05, 0xc0, 6
131 #define RG_PHY_RSSI (0x06)
132 #define SR_RSSI 0x06, 0x1f, 0
133 #define SR_RND_VALUE 0x06, 0x60, 5
134 #define SR_RX_CRC_VALID 0x06, 0x80, 7
135 #define RG_PHY_ED_LEVEL (0x07)
136 #define SR_ED_LEVEL 0x07, 0xff, 0
137 #define RG_PHY_CC_CCA (0x08)
138 #define SR_CHANNEL 0x08, 0x1f, 0
139 #define SR_CCA_MODE 0x08, 0x60, 5
140 #define SR_CCA_REQUEST 0x08, 0x80, 7
141 #define RG_CCA_THRES (0x09)
142 #define SR_CCA_ED_THRES 0x09, 0x0f, 0
143 #define SR_RESERVED_09_1 0x09, 0xf0, 4
144 #define RG_RX_CTRL (0x0a)
145 #define SR_PDT_THRES 0x0a, 0x0f, 0
146 #define SR_RESERVED_0a_1 0x0a, 0xf0, 4
147 #define RG_SFD_VALUE (0x0b)
148 #define SR_SFD_VALUE 0x0b, 0xff, 0
149 #define RG_TRX_CTRL_2 (0x0c)
150 #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
151 #define SR_SUB_MODE 0x0c, 0x04, 2
152 #define SR_BPSK_QPSK 0x0c, 0x08, 3
153 #define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4
154 #define SR_RESERVED_0c_5 0x0c, 0x60, 5
155 #define SR_RX_SAFE_MODE 0x0c, 0x80, 7
156 #define RG_ANT_DIV (0x0d)
157 #define SR_ANT_CTRL 0x0d, 0x03, 0
158 #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
159 #define SR_ANT_DIV_EN 0x0d, 0x08, 3
160 #define SR_RESERVED_0d_2 0x0d, 0x70, 4
161 #define SR_ANT_SEL 0x0d, 0x80, 7
162 #define RG_IRQ_MASK (0x0e)
163 #define SR_IRQ_MASK 0x0e, 0xff, 0
164 #define RG_IRQ_STATUS (0x0f)
165 #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
166 #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
167 #define SR_IRQ_2_RX_START 0x0f, 0x04, 2
168 #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
169 #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4
170 #define SR_IRQ_5_AMI 0x0f, 0x20, 5
171 #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
172 #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
173 #define RG_VREG_CTRL (0x10)
174 #define SR_RESERVED_10_6 0x10, 0x03, 0
175 #define SR_DVDD_OK 0x10, 0x04, 2
176 #define SR_DVREG_EXT 0x10, 0x08, 3
177 #define SR_RESERVED_10_3 0x10, 0x30, 4
178 #define SR_AVDD_OK 0x10, 0x40, 6
179 #define SR_AVREG_EXT 0x10, 0x80, 7
180 #define RG_BATMON (0x11)
181 #define SR_BATMON_VTH 0x11, 0x0f, 0
182 #define SR_BATMON_HR 0x11, 0x10, 4
183 #define SR_BATMON_OK 0x11, 0x20, 5
184 #define SR_RESERVED_11_1 0x11, 0xc0, 6
185 #define RG_XOSC_CTRL (0x12)
186 #define SR_XTAL_TRIM 0x12, 0x0f, 0
187 #define SR_XTAL_MODE 0x12, 0xf0, 4
188 #define RG_RX_SYN (0x15)
189 #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0
190 #define SR_RESERVED_15_2 0x15, 0x70, 4
191 #define SR_RX_PDT_DIS 0x15, 0x80, 7
192 #define RG_XAH_CTRL_1 (0x17)
193 #define SR_RESERVED_17_8 0x17, 0x01, 0
194 #define SR_AACK_PROM_MODE 0x17, 0x02, 1
195 #define SR_AACK_ACK_TIME 0x17, 0x04, 2
196 #define SR_RESERVED_17_5 0x17, 0x08, 3
197 #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
198 #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
199 #define SR_CSMA_LBT_MODE 0x17, 0x40, 6
200 #define SR_RESERVED_17_1 0x17, 0x80, 7
201 #define RG_FTN_CTRL (0x18)
202 #define SR_RESERVED_18_2 0x18, 0x7f, 0
203 #define SR_FTN_START 0x18, 0x80, 7
204 #define RG_PLL_CF (0x1a)
205 #define SR_RESERVED_1a_2 0x1a, 0x7f, 0
206 #define SR_PLL_CF_START 0x1a, 0x80, 7
207 #define RG_PLL_DCU (0x1b)
208 #define SR_RESERVED_1b_3 0x1b, 0x3f, 0
209 #define SR_RESERVED_1b_2 0x1b, 0x40, 6
210 #define SR_PLL_DCU_START 0x1b, 0x80, 7
211 #define RG_PART_NUM (0x1c)
212 #define SR_PART_NUM 0x1c, 0xff, 0
213 #define RG_VERSION_NUM (0x1d)
214 #define SR_VERSION_NUM 0x1d, 0xff, 0
215 #define RG_MAN_ID_0 (0x1e)
216 #define SR_MAN_ID_0 0x1e, 0xff, 0
217 #define RG_MAN_ID_1 (0x1f)
218 #define SR_MAN_ID_1 0x1f, 0xff, 0
219 #define RG_SHORT_ADDR_0 (0x20)
220 #define SR_SHORT_ADDR_0 0x20, 0xff, 0
221 #define RG_SHORT_ADDR_1 (0x21)
222 #define SR_SHORT_ADDR_1 0x21, 0xff, 0
223 #define RG_PAN_ID_0 (0x22)
224 #define SR_PAN_ID_0 0x22, 0xff, 0
225 #define RG_PAN_ID_1 (0x23)
226 #define SR_PAN_ID_1 0x23, 0xff, 0
227 #define RG_IEEE_ADDR_0 (0x24)
228 #define SR_IEEE_ADDR_0 0x24, 0xff, 0
229 #define RG_IEEE_ADDR_1 (0x25)
230 #define SR_IEEE_ADDR_1 0x25, 0xff, 0
231 #define RG_IEEE_ADDR_2 (0x26)
232 #define SR_IEEE_ADDR_2 0x26, 0xff, 0
233 #define RG_IEEE_ADDR_3 (0x27)
234 #define SR_IEEE_ADDR_3 0x27, 0xff, 0
235 #define RG_IEEE_ADDR_4 (0x28)
236 #define SR_IEEE_ADDR_4 0x28, 0xff, 0
237 #define RG_IEEE_ADDR_5 (0x29)
238 #define SR_IEEE_ADDR_5 0x29, 0xff, 0
239 #define RG_IEEE_ADDR_6 (0x2a)
240 #define SR_IEEE_ADDR_6 0x2a, 0xff, 0
241 #define RG_IEEE_ADDR_7 (0x2b)
242 #define SR_IEEE_ADDR_7 0x2b, 0xff, 0
243 #define RG_XAH_CTRL_0 (0x2c)
244 #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0
245 #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
246 #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
247 #define RG_CSMA_SEED_0 (0x2d)
248 #define SR_CSMA_SEED_0 0x2d, 0xff, 0
249 #define RG_CSMA_SEED_1 (0x2e)
250 #define SR_CSMA_SEED_1 0x2e, 0x07, 0
251 #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3
252 #define SR_AACK_DIS_ACK 0x2e, 0x10, 4
253 #define SR_AACK_SET_PD 0x2e, 0x20, 5
254 #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6
255 #define RG_CSMA_BE (0x2f)
256 #define SR_MIN_BE 0x2f, 0x0f, 0
257 #define SR_MAX_BE 0x2f, 0xf0, 4
258
259 #define CMD_REG 0x80
260 #define CMD_REG_MASK 0x3f
261 #define CMD_WRITE 0x40
262 #define CMD_FB 0x20
263
264 #define IRQ_BAT_LOW (1 << 7)
265 #define IRQ_TRX_UR (1 << 6)
266 #define IRQ_AMI (1 << 5)
267 #define IRQ_CCA_ED (1 << 4)
268 #define IRQ_TRX_END (1 << 3)
269 #define IRQ_RX_START (1 << 2)
270 #define IRQ_PLL_UNL (1 << 1)
271 #define IRQ_PLL_LOCK (1 << 0)
272
273 #define IRQ_ACTIVE_HIGH 0
274 #define IRQ_ACTIVE_LOW 1
275
276 #define STATE_P_ON 0x00 /* BUSY */
277 #define STATE_BUSY_RX 0x01
278 #define STATE_BUSY_TX 0x02
279 #define STATE_FORCE_TRX_OFF 0x03
280 #define STATE_FORCE_TX_ON 0x04 /* IDLE */
281 /* 0x05 */ /* INVALID_PARAMETER */
282 #define STATE_RX_ON 0x06
283 /* 0x07 */ /* SUCCESS */
284 #define STATE_TRX_OFF 0x08
285 #define STATE_TX_ON 0x09
286 /* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */
287 #define STATE_SLEEP 0x0F
288 #define STATE_PREP_DEEP_SLEEP 0x10
289 #define STATE_BUSY_RX_AACK 0x11
290 #define STATE_BUSY_TX_ARET 0x12
291 #define STATE_RX_AACK_ON 0x16
292 #define STATE_TX_ARET_ON 0x19
293 #define STATE_RX_ON_NOCLK 0x1C
294 #define STATE_RX_AACK_ON_NOCLK 0x1D
295 #define STATE_BUSY_RX_AACK_NOCLK 0x1E
296 #define STATE_TRANSITION_IN_PROGRESS 0x1F
297
298 #define AT86RF2XX_NUMREGS 0x3F
299
300 static void
301 at86rf230_async_state_change(struct at86rf230_local *lp,
302 struct at86rf230_state_change *ctx,
303 const u8 state, void (*complete)(void *context),
304 const bool irq_enable);
305
306 static inline int
307 __at86rf230_write(struct at86rf230_local *lp,
308 unsigned int addr, unsigned int data)
309 {
310 return regmap_write(lp->regmap, addr, data);
311 }
312
313 static inline int
314 __at86rf230_read(struct at86rf230_local *lp,
315 unsigned int addr, unsigned int *data)
316 {
317 return regmap_read(lp->regmap, addr, data);
318 }
319
320 static inline int
321 at86rf230_read_subreg(struct at86rf230_local *lp,
322 unsigned int addr, unsigned int mask,
323 unsigned int shift, unsigned int *data)
324 {
325 int rc;
326
327 rc = __at86rf230_read(lp, addr, data);
328 if (rc > 0)
329 *data = (*data & mask) >> shift;
330
331 return rc;
332 }
333
334 static inline int
335 at86rf230_write_subreg(struct at86rf230_local *lp,
336 unsigned int addr, unsigned int mask,
337 unsigned int shift, unsigned int data)
338 {
339 return regmap_update_bits(lp->regmap, addr, mask, data << shift);
340 }
341
342 static bool
343 at86rf230_reg_writeable(struct device *dev, unsigned int reg)
344 {
345 switch (reg) {
346 case RG_TRX_STATE:
347 case RG_TRX_CTRL_0:
348 case RG_TRX_CTRL_1:
349 case RG_PHY_TX_PWR:
350 case RG_PHY_ED_LEVEL:
351 case RG_PHY_CC_CCA:
352 case RG_CCA_THRES:
353 case RG_RX_CTRL:
354 case RG_SFD_VALUE:
355 case RG_TRX_CTRL_2:
356 case RG_ANT_DIV:
357 case RG_IRQ_MASK:
358 case RG_VREG_CTRL:
359 case RG_BATMON:
360 case RG_XOSC_CTRL:
361 case RG_RX_SYN:
362 case RG_XAH_CTRL_1:
363 case RG_FTN_CTRL:
364 case RG_PLL_CF:
365 case RG_PLL_DCU:
366 case RG_SHORT_ADDR_0:
367 case RG_SHORT_ADDR_1:
368 case RG_PAN_ID_0:
369 case RG_PAN_ID_1:
370 case RG_IEEE_ADDR_0:
371 case RG_IEEE_ADDR_1:
372 case RG_IEEE_ADDR_2:
373 case RG_IEEE_ADDR_3:
374 case RG_IEEE_ADDR_4:
375 case RG_IEEE_ADDR_5:
376 case RG_IEEE_ADDR_6:
377 case RG_IEEE_ADDR_7:
378 case RG_XAH_CTRL_0:
379 case RG_CSMA_SEED_0:
380 case RG_CSMA_SEED_1:
381 case RG_CSMA_BE:
382 return true;
383 default:
384 return false;
385 }
386 }
387
388 static bool
389 at86rf230_reg_readable(struct device *dev, unsigned int reg)
390 {
391 bool rc;
392
393 /* all writeable are also readable */
394 rc = at86rf230_reg_writeable(dev, reg);
395 if (rc)
396 return rc;
397
398 /* readonly regs */
399 switch (reg) {
400 case RG_TRX_STATUS:
401 case RG_PHY_RSSI:
402 case RG_IRQ_STATUS:
403 case RG_PART_NUM:
404 case RG_VERSION_NUM:
405 case RG_MAN_ID_1:
406 case RG_MAN_ID_0:
407 return true;
408 default:
409 return false;
410 }
411 }
412
413 static bool
414 at86rf230_reg_volatile(struct device *dev, unsigned int reg)
415 {
416 /* can be changed during runtime */
417 switch (reg) {
418 case RG_TRX_STATUS:
419 case RG_TRX_STATE:
420 case RG_PHY_RSSI:
421 case RG_PHY_ED_LEVEL:
422 case RG_IRQ_STATUS:
423 case RG_VREG_CTRL:
424 case RG_PLL_CF:
425 case RG_PLL_DCU:
426 return true;
427 default:
428 return false;
429 }
430 }
431
432 static bool
433 at86rf230_reg_precious(struct device *dev, unsigned int reg)
434 {
435 /* don't clear irq line on read */
436 switch (reg) {
437 case RG_IRQ_STATUS:
438 return true;
439 default:
440 return false;
441 }
442 }
443
444 static const struct regmap_config at86rf230_regmap_spi_config = {
445 .reg_bits = 8,
446 .val_bits = 8,
447 .write_flag_mask = CMD_REG | CMD_WRITE,
448 .read_flag_mask = CMD_REG,
449 .cache_type = REGCACHE_RBTREE,
450 .max_register = AT86RF2XX_NUMREGS,
451 .writeable_reg = at86rf230_reg_writeable,
452 .readable_reg = at86rf230_reg_readable,
453 .volatile_reg = at86rf230_reg_volatile,
454 .precious_reg = at86rf230_reg_precious,
455 };
456
457 static void
458 at86rf230_async_error_recover(void *context)
459 {
460 struct at86rf230_state_change *ctx = context;
461 struct at86rf230_local *lp = ctx->lp;
462
463 at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON, NULL, false);
464 ieee802154_wake_queue(lp->hw);
465 }
466
467 static inline void
468 at86rf230_async_error(struct at86rf230_local *lp,
469 struct at86rf230_state_change *ctx, int rc)
470 {
471 dev_err(&lp->spi->dev, "spi_async error %d\n", rc);
472
473 at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF,
474 at86rf230_async_error_recover, false);
475 }
476
477 /* Generic function to get some register value in async mode */
478 static void
479 at86rf230_async_read_reg(struct at86rf230_local *lp, const u8 reg,
480 struct at86rf230_state_change *ctx,
481 void (*complete)(void *context),
482 const bool irq_enable)
483 {
484 int rc;
485
486 u8 *tx_buf = ctx->buf;
487
488 tx_buf[0] = (reg & CMD_REG_MASK) | CMD_REG;
489 ctx->msg.complete = complete;
490 ctx->irq_enable = irq_enable;
491 rc = spi_async(lp->spi, &ctx->msg);
492 if (rc) {
493 if (irq_enable)
494 enable_irq(ctx->irq);
495
496 at86rf230_async_error(lp, ctx, rc);
497 }
498 }
499
500 static inline u8 at86rf230_state_to_force(u8 state)
501 {
502 if (state == STATE_TX_ON)
503 return STATE_FORCE_TX_ON;
504 else
505 return STATE_FORCE_TRX_OFF;
506 }
507
508 static void
509 at86rf230_async_state_assert(void *context)
510 {
511 struct at86rf230_state_change *ctx = context;
512 struct at86rf230_local *lp = ctx->lp;
513 const u8 *buf = ctx->buf;
514 const u8 trx_state = buf[1] & 0x1f;
515
516 /* Assert state change */
517 if (trx_state != ctx->to_state) {
518 /* Special handling if transceiver state is in
519 * STATE_BUSY_RX_AACK and a SHR was detected.
520 */
521 if (trx_state == STATE_BUSY_RX_AACK) {
522 /* Undocumented race condition. If we send a state
523 * change to STATE_RX_AACK_ON the transceiver could
524 * change his state automatically to STATE_BUSY_RX_AACK
525 * if a SHR was detected. This is not an error, but we
526 * can't assert this.
527 */
528 if (ctx->to_state == STATE_RX_AACK_ON)
529 goto done;
530
531 /* If we change to STATE_TX_ON without forcing and
532 * transceiver state is STATE_BUSY_RX_AACK, we wait
533 * 'tFrame + tPAck' receiving time. In this time the
534 * PDU should be received. If the transceiver is still
535 * in STATE_BUSY_RX_AACK, we run a force state change
536 * to STATE_TX_ON. This is a timeout handling, if the
537 * transceiver stucks in STATE_BUSY_RX_AACK.
538 *
539 * Additional we do several retries to try to get into
540 * TX_ON state without forcing. If the retries are
541 * higher or equal than AT86RF2XX_MAX_TX_RETRIES we
542 * will do a force change.
543 */
544 if (ctx->to_state == STATE_TX_ON ||
545 ctx->to_state == STATE_TRX_OFF) {
546 u8 state = ctx->to_state;
547
548 if (lp->tx_retry >= AT86RF2XX_MAX_TX_RETRIES)
549 state = at86rf230_state_to_force(state);
550 lp->tx_retry++;
551
552 at86rf230_async_state_change(lp, ctx, state,
553 ctx->complete,
554 ctx->irq_enable);
555 return;
556 }
557 }
558
559 dev_warn(&lp->spi->dev, "unexcept state change from 0x%02x to 0x%02x. Actual state: 0x%02x\n",
560 ctx->from_state, ctx->to_state, trx_state);
561 }
562
563 done:
564 if (ctx->complete)
565 ctx->complete(context);
566 }
567
568 static enum hrtimer_restart at86rf230_async_state_timer(struct hrtimer *timer)
569 {
570 struct at86rf230_state_change *ctx =
571 container_of(timer, struct at86rf230_state_change, timer);
572 struct at86rf230_local *lp = ctx->lp;
573
574 at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
575 at86rf230_async_state_assert,
576 ctx->irq_enable);
577
578 return HRTIMER_NORESTART;
579 }
580
581 /* Do state change timing delay. */
582 static void
583 at86rf230_async_state_delay(void *context)
584 {
585 struct at86rf230_state_change *ctx = context;
586 struct at86rf230_local *lp = ctx->lp;
587 struct at86rf2xx_chip_data *c = lp->data;
588 bool force = false;
589 ktime_t tim;
590
591 /* The force state changes are will show as normal states in the
592 * state status subregister. We change the to_state to the
593 * corresponding one and remember if it was a force change, this
594 * differs if we do a state change from STATE_BUSY_RX_AACK.
595 */
596 switch (ctx->to_state) {
597 case STATE_FORCE_TX_ON:
598 ctx->to_state = STATE_TX_ON;
599 force = true;
600 break;
601 case STATE_FORCE_TRX_OFF:
602 ctx->to_state = STATE_TRX_OFF;
603 force = true;
604 break;
605 default:
606 break;
607 }
608
609 switch (ctx->from_state) {
610 case STATE_TRX_OFF:
611 switch (ctx->to_state) {
612 case STATE_RX_AACK_ON:
613 tim = ktime_set(0, c->t_off_to_aack * NSEC_PER_USEC);
614 goto change;
615 case STATE_TX_ON:
616 tim = ktime_set(0, c->t_off_to_tx_on * NSEC_PER_USEC);
617 /* state change from TRX_OFF to TX_ON to do a
618 * calibration, we need to reset the timeout for the
619 * next one.
620 */
621 lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
622 goto change;
623 default:
624 break;
625 }
626 break;
627 case STATE_BUSY_RX_AACK:
628 switch (ctx->to_state) {
629 case STATE_TRX_OFF:
630 case STATE_TX_ON:
631 /* Wait for worst case receiving time if we
632 * didn't make a force change from BUSY_RX_AACK
633 * to TX_ON or TRX_OFF.
634 */
635 if (!force) {
636 tim = ktime_set(0, (c->t_frame + c->t_p_ack) *
637 NSEC_PER_USEC);
638 goto change;
639 }
640 break;
641 default:
642 break;
643 }
644 break;
645 /* Default value, means RESET state */
646 case STATE_P_ON:
647 switch (ctx->to_state) {
648 case STATE_TRX_OFF:
649 tim = ktime_set(0, c->t_reset_to_off * NSEC_PER_USEC);
650 goto change;
651 default:
652 break;
653 }
654 break;
655 default:
656 break;
657 }
658
659 /* Default delay is 1us in the most cases */
660 tim = ktime_set(0, NSEC_PER_USEC);
661
662 change:
663 hrtimer_start(&ctx->timer, tim, HRTIMER_MODE_REL);
664 }
665
666 static void
667 at86rf230_async_state_change_start(void *context)
668 {
669 struct at86rf230_state_change *ctx = context;
670 struct at86rf230_local *lp = ctx->lp;
671 u8 *buf = ctx->buf;
672 const u8 trx_state = buf[1] & 0x1f;
673 int rc;
674
675 /* Check for "possible" STATE_TRANSITION_IN_PROGRESS */
676 if (trx_state == STATE_TRANSITION_IN_PROGRESS) {
677 udelay(1);
678 at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
679 at86rf230_async_state_change_start,
680 ctx->irq_enable);
681 return;
682 }
683
684 /* Check if we already are in the state which we change in */
685 if (trx_state == ctx->to_state) {
686 if (ctx->complete)
687 ctx->complete(context);
688 return;
689 }
690
691 /* Set current state to the context of state change */
692 ctx->from_state = trx_state;
693
694 /* Going into the next step for a state change which do a timing
695 * relevant delay.
696 */
697 buf[0] = (RG_TRX_STATE & CMD_REG_MASK) | CMD_REG | CMD_WRITE;
698 buf[1] = ctx->to_state;
699 ctx->msg.complete = at86rf230_async_state_delay;
700 rc = spi_async(lp->spi, &ctx->msg);
701 if (rc) {
702 if (ctx->irq_enable)
703 enable_irq(ctx->irq);
704
705 at86rf230_async_error(lp, ctx, rc);
706 }
707 }
708
709 static void
710 at86rf230_async_state_change(struct at86rf230_local *lp,
711 struct at86rf230_state_change *ctx,
712 const u8 state, void (*complete)(void *context),
713 const bool irq_enable)
714 {
715 /* Initialization for the state change context */
716 ctx->to_state = state;
717 ctx->complete = complete;
718 ctx->irq_enable = irq_enable;
719 at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
720 at86rf230_async_state_change_start,
721 irq_enable);
722 }
723
724 static void
725 at86rf230_sync_state_change_complete(void *context)
726 {
727 struct at86rf230_state_change *ctx = context;
728 struct at86rf230_local *lp = ctx->lp;
729
730 complete(&lp->state_complete);
731 }
732
733 /* This function do a sync framework above the async state change.
734 * Some callbacks of the IEEE 802.15.4 driver interface need to be
735 * handled synchronously.
736 */
737 static int
738 at86rf230_sync_state_change(struct at86rf230_local *lp, unsigned int state)
739 {
740 unsigned long rc;
741
742 at86rf230_async_state_change(lp, &lp->state, state,
743 at86rf230_sync_state_change_complete,
744 false);
745
746 rc = wait_for_completion_timeout(&lp->state_complete,
747 msecs_to_jiffies(100));
748 if (!rc) {
749 at86rf230_async_error(lp, &lp->state, -ETIMEDOUT);
750 return -ETIMEDOUT;
751 }
752
753 return 0;
754 }
755
756 static void
757 at86rf230_tx_complete(void *context)
758 {
759 struct at86rf230_state_change *ctx = context;
760 struct at86rf230_local *lp = ctx->lp;
761
762 enable_irq(ctx->irq);
763
764 ieee802154_xmit_complete(lp->hw, lp->tx_skb, !lp->tx_aret);
765 }
766
767 static void
768 at86rf230_tx_on(void *context)
769 {
770 struct at86rf230_state_change *ctx = context;
771 struct at86rf230_local *lp = ctx->lp;
772
773 at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON,
774 at86rf230_tx_complete, true);
775 }
776
777 static void
778 at86rf230_tx_trac_error(void *context)
779 {
780 struct at86rf230_state_change *ctx = context;
781 struct at86rf230_local *lp = ctx->lp;
782
783 at86rf230_async_state_change(lp, ctx, STATE_TX_ON,
784 at86rf230_tx_on, true);
785 }
786
787 static void
788 at86rf230_tx_trac_check(void *context)
789 {
790 struct at86rf230_state_change *ctx = context;
791 struct at86rf230_local *lp = ctx->lp;
792 const u8 *buf = ctx->buf;
793 const u8 trac = (buf[1] & 0xe0) >> 5;
794
795 /* If trac status is different than zero we need to do a state change
796 * to STATE_FORCE_TRX_OFF then STATE_TX_ON to recover the transceiver
797 * state to TX_ON.
798 */
799 if (trac)
800 at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF,
801 at86rf230_tx_trac_error, true);
802 else
803 at86rf230_tx_on(context);
804 }
805
806 static void
807 at86rf230_tx_trac_status(void *context)
808 {
809 struct at86rf230_state_change *ctx = context;
810 struct at86rf230_local *lp = ctx->lp;
811
812 at86rf230_async_read_reg(lp, RG_TRX_STATE, ctx,
813 at86rf230_tx_trac_check, true);
814 }
815
816 static void
817 at86rf230_rx_read_frame_complete(void *context)
818 {
819 struct at86rf230_state_change *ctx = context;
820 struct at86rf230_local *lp = ctx->lp;
821 u8 rx_local_buf[AT86RF2XX_MAX_BUF];
822 const u8 *buf = ctx->buf;
823 struct sk_buff *skb;
824 u8 len, lqi;
825
826 len = buf[1];
827 if (!ieee802154_is_valid_psdu_len(len)) {
828 dev_vdbg(&lp->spi->dev, "corrupted frame received\n");
829 len = IEEE802154_MTU;
830 }
831 lqi = buf[2 + len];
832
833 memcpy(rx_local_buf, buf + 2, len);
834 ctx->trx.len = 2;
835 enable_irq(ctx->irq);
836
837 skb = dev_alloc_skb(IEEE802154_MTU);
838 if (!skb) {
839 dev_vdbg(&lp->spi->dev, "failed to allocate sk_buff\n");
840 return;
841 }
842
843 memcpy(skb_put(skb, len), rx_local_buf, len);
844 ieee802154_rx_irqsafe(lp->hw, skb, lqi);
845 }
846
847 static void
848 at86rf230_rx_read_frame(void *context)
849 {
850 struct at86rf230_state_change *ctx = context;
851 struct at86rf230_local *lp = ctx->lp;
852 u8 *buf = ctx->buf;
853 int rc;
854
855 buf[0] = CMD_FB;
856 ctx->trx.len = AT86RF2XX_MAX_BUF;
857 ctx->msg.complete = at86rf230_rx_read_frame_complete;
858 rc = spi_async(lp->spi, &ctx->msg);
859 if (rc) {
860 ctx->trx.len = 2;
861 enable_irq(ctx->irq);
862 at86rf230_async_error(lp, ctx, rc);
863 }
864 }
865
866 static void
867 at86rf230_rx_trac_check(void *context)
868 {
869 /* Possible check on trac status here. This could be useful to make
870 * some stats why receive is failed. Not used at the moment, but it's
871 * maybe timing relevant. Datasheet doesn't say anything about this.
872 * The programming guide say do it so.
873 */
874
875 at86rf230_rx_read_frame(context);
876 }
877
878 static void
879 at86rf230_irq_trx_end(struct at86rf230_local *lp)
880 {
881 spin_lock(&lp->lock);
882 if (lp->is_tx) {
883 lp->is_tx = 0;
884 spin_unlock(&lp->lock);
885
886 if (lp->tx_aret)
887 at86rf230_async_state_change(lp, &lp->irq,
888 STATE_FORCE_TX_ON,
889 at86rf230_tx_trac_status,
890 true);
891 else
892 at86rf230_async_state_change(lp, &lp->irq,
893 STATE_RX_AACK_ON,
894 at86rf230_tx_complete,
895 true);
896 } else {
897 spin_unlock(&lp->lock);
898 at86rf230_async_read_reg(lp, RG_TRX_STATE, &lp->irq,
899 at86rf230_rx_trac_check, true);
900 }
901 }
902
903 static void
904 at86rf230_irq_status(void *context)
905 {
906 struct at86rf230_state_change *ctx = context;
907 struct at86rf230_local *lp = ctx->lp;
908 const u8 *buf = ctx->buf;
909 const u8 irq = buf[1];
910
911 if (irq & IRQ_TRX_END) {
912 at86rf230_irq_trx_end(lp);
913 } else {
914 enable_irq(ctx->irq);
915 dev_err(&lp->spi->dev, "not supported irq %02x received\n",
916 irq);
917 }
918 }
919
920 static irqreturn_t at86rf230_isr(int irq, void *data)
921 {
922 struct at86rf230_local *lp = data;
923 struct at86rf230_state_change *ctx = &lp->irq;
924 u8 *buf = ctx->buf;
925 int rc;
926
927 disable_irq_nosync(irq);
928
929 buf[0] = (RG_IRQ_STATUS & CMD_REG_MASK) | CMD_REG;
930 ctx->msg.complete = at86rf230_irq_status;
931 rc = spi_async(lp->spi, &ctx->msg);
932 if (rc) {
933 enable_irq(irq);
934 at86rf230_async_error(lp, ctx, rc);
935 return IRQ_NONE;
936 }
937
938 return IRQ_HANDLED;
939 }
940
941 static void
942 at86rf230_write_frame_complete(void *context)
943 {
944 struct at86rf230_state_change *ctx = context;
945 struct at86rf230_local *lp = ctx->lp;
946 u8 *buf = ctx->buf;
947 int rc;
948
949 buf[0] = (RG_TRX_STATE & CMD_REG_MASK) | CMD_REG | CMD_WRITE;
950 buf[1] = STATE_BUSY_TX;
951 ctx->trx.len = 2;
952 ctx->msg.complete = NULL;
953 rc = spi_async(lp->spi, &ctx->msg);
954 if (rc)
955 at86rf230_async_error(lp, ctx, rc);
956 }
957
958 static void
959 at86rf230_write_frame(void *context)
960 {
961 struct at86rf230_state_change *ctx = context;
962 struct at86rf230_local *lp = ctx->lp;
963 struct sk_buff *skb = lp->tx_skb;
964 u8 *buf = ctx->buf;
965 int rc;
966
967 spin_lock(&lp->lock);
968 lp->is_tx = 1;
969 spin_unlock(&lp->lock);
970
971 buf[0] = CMD_FB | CMD_WRITE;
972 buf[1] = skb->len + 2;
973 memcpy(buf + 2, skb->data, skb->len);
974 ctx->trx.len = skb->len + 2;
975 ctx->msg.complete = at86rf230_write_frame_complete;
976 rc = spi_async(lp->spi, &ctx->msg);
977 if (rc) {
978 ctx->trx.len = 2;
979 at86rf230_async_error(lp, ctx, rc);
980 }
981 }
982
983 static void
984 at86rf230_xmit_tx_on(void *context)
985 {
986 struct at86rf230_state_change *ctx = context;
987 struct at86rf230_local *lp = ctx->lp;
988
989 at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON,
990 at86rf230_write_frame, false);
991 }
992
993 static void
994 at86rf230_xmit_start(void *context)
995 {
996 struct at86rf230_state_change *ctx = context;
997 struct at86rf230_local *lp = ctx->lp;
998
999 /* In ARET mode we need to go into STATE_TX_ARET_ON after we
1000 * are in STATE_TX_ON. The pfad differs here, so we change
1001 * the complete handler.
1002 */
1003 if (lp->tx_aret)
1004 at86rf230_async_state_change(lp, ctx, STATE_TX_ON,
1005 at86rf230_xmit_tx_on, false);
1006 else
1007 at86rf230_async_state_change(lp, ctx, STATE_TX_ON,
1008 at86rf230_write_frame, false);
1009 }
1010
1011 static int
1012 at86rf230_xmit(struct ieee802154_hw *hw, struct sk_buff *skb)
1013 {
1014 struct at86rf230_local *lp = hw->priv;
1015 struct at86rf230_state_change *ctx = &lp->tx;
1016
1017 lp->tx_skb = skb;
1018 lp->tx_retry = 0;
1019
1020 /* After 5 minutes in PLL and the same frequency we run again the
1021 * calibration loops which is recommended by at86rf2xx datasheets.
1022 *
1023 * The calibration is initiate by a state change from TRX_OFF
1024 * to TX_ON, the lp->cal_timeout should be reinit by state_delay
1025 * function then to start in the next 5 minutes.
1026 */
1027 if (time_is_before_jiffies(lp->cal_timeout))
1028 at86rf230_async_state_change(lp, ctx, STATE_TRX_OFF,
1029 at86rf230_xmit_start, false);
1030 else
1031 at86rf230_xmit_start(ctx);
1032
1033 return 0;
1034 }
1035
1036 static int
1037 at86rf230_ed(struct ieee802154_hw *hw, u8 *level)
1038 {
1039 BUG_ON(!level);
1040 *level = 0xbe;
1041 return 0;
1042 }
1043
1044 static int
1045 at86rf230_start(struct ieee802154_hw *hw)
1046 {
1047 struct at86rf230_local *lp = hw->priv;
1048
1049 lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
1050 return at86rf230_sync_state_change(hw->priv, STATE_RX_AACK_ON);
1051 }
1052
1053 static void
1054 at86rf230_stop(struct ieee802154_hw *hw)
1055 {
1056 at86rf230_sync_state_change(hw->priv, STATE_FORCE_TRX_OFF);
1057 }
1058
1059 static int
1060 at86rf23x_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
1061 {
1062 return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
1063 }
1064
1065 static int
1066 at86rf212_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
1067 {
1068 int rc;
1069
1070 if (channel == 0)
1071 rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 0);
1072 else
1073 rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 1);
1074 if (rc < 0)
1075 return rc;
1076
1077 if (page == 0) {
1078 rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 0);
1079 lp->data->rssi_base_val = -100;
1080 } else {
1081 rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 1);
1082 lp->data->rssi_base_val = -98;
1083 }
1084 if (rc < 0)
1085 return rc;
1086
1087 /* This sets the symbol_duration according frequency on the 212.
1088 * TODO move this handling while set channel and page in cfg802154.
1089 * We can do that, this timings are according 802.15.4 standard.
1090 * If we do that in cfg802154, this is a more generic calculation.
1091 *
1092 * This should also protected from ifs_timer. Means cancel timer and
1093 * init with a new value. For now, this is okay.
1094 */
1095 if (channel == 0) {
1096 if (page == 0) {
1097 /* SUB:0 and BPSK:0 -> BPSK-20 */
1098 lp->hw->phy->symbol_duration = 50;
1099 } else {
1100 /* SUB:1 and BPSK:0 -> BPSK-40 */
1101 lp->hw->phy->symbol_duration = 25;
1102 }
1103 } else {
1104 if (page == 0)
1105 /* SUB:0 and BPSK:1 -> OQPSK-100/200/400 */
1106 lp->hw->phy->symbol_duration = 40;
1107 else
1108 /* SUB:1 and BPSK:1 -> OQPSK-250/500/1000 */
1109 lp->hw->phy->symbol_duration = 16;
1110 }
1111
1112 lp->hw->phy->lifs_period = IEEE802154_LIFS_PERIOD *
1113 lp->hw->phy->symbol_duration;
1114 lp->hw->phy->sifs_period = IEEE802154_SIFS_PERIOD *
1115 lp->hw->phy->symbol_duration;
1116
1117 return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
1118 }
1119
1120 static int
1121 at86rf230_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
1122 {
1123 struct at86rf230_local *lp = hw->priv;
1124 int rc;
1125
1126 rc = lp->data->set_channel(lp, page, channel);
1127 /* Wait for PLL */
1128 usleep_range(lp->data->t_channel_switch,
1129 lp->data->t_channel_switch + 10);
1130
1131 lp->cal_timeout = jiffies + AT86RF2XX_CAL_LOOP_TIMEOUT;
1132 return rc;
1133 }
1134
1135 static int
1136 at86rf230_set_hw_addr_filt(struct ieee802154_hw *hw,
1137 struct ieee802154_hw_addr_filt *filt,
1138 unsigned long changed)
1139 {
1140 struct at86rf230_local *lp = hw->priv;
1141
1142 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
1143 u16 addr = le16_to_cpu(filt->short_addr);
1144
1145 dev_vdbg(&lp->spi->dev,
1146 "at86rf230_set_hw_addr_filt called for saddr\n");
1147 __at86rf230_write(lp, RG_SHORT_ADDR_0, addr);
1148 __at86rf230_write(lp, RG_SHORT_ADDR_1, addr >> 8);
1149 }
1150
1151 if (changed & IEEE802154_AFILT_PANID_CHANGED) {
1152 u16 pan = le16_to_cpu(filt->pan_id);
1153
1154 dev_vdbg(&lp->spi->dev,
1155 "at86rf230_set_hw_addr_filt called for pan id\n");
1156 __at86rf230_write(lp, RG_PAN_ID_0, pan);
1157 __at86rf230_write(lp, RG_PAN_ID_1, pan >> 8);
1158 }
1159
1160 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
1161 u8 i, addr[8];
1162
1163 memcpy(addr, &filt->ieee_addr, 8);
1164 dev_vdbg(&lp->spi->dev,
1165 "at86rf230_set_hw_addr_filt called for IEEE addr\n");
1166 for (i = 0; i < 8; i++)
1167 __at86rf230_write(lp, RG_IEEE_ADDR_0 + i, addr[i]);
1168 }
1169
1170 if (changed & IEEE802154_AFILT_PANC_CHANGED) {
1171 dev_vdbg(&lp->spi->dev,
1172 "at86rf230_set_hw_addr_filt called for panc change\n");
1173 if (filt->pan_coord)
1174 at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 1);
1175 else
1176 at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 0);
1177 }
1178
1179 return 0;
1180 }
1181
1182 static int
1183 at86rf230_set_txpower(struct ieee802154_hw *hw, int db)
1184 {
1185 struct at86rf230_local *lp = hw->priv;
1186
1187 /* typical maximum output is 5dBm with RG_PHY_TX_PWR 0x60, lower five
1188 * bits decrease power in 1dB steps. 0x60 represents extra PA gain of
1189 * 0dB.
1190 * thus, supported values for db range from -26 to 5, for 31dB of
1191 * reduction to 0dB of reduction.
1192 */
1193 if (db > 5 || db < -26)
1194 return -EINVAL;
1195
1196 db = -(db - 5);
1197
1198 return __at86rf230_write(lp, RG_PHY_TX_PWR, 0x60 | db);
1199 }
1200
1201 static int
1202 at86rf230_set_lbt(struct ieee802154_hw *hw, bool on)
1203 {
1204 struct at86rf230_local *lp = hw->priv;
1205
1206 return at86rf230_write_subreg(lp, SR_CSMA_LBT_MODE, on);
1207 }
1208
1209 static int
1210 at86rf230_set_cca_mode(struct ieee802154_hw *hw,
1211 const struct wpan_phy_cca *cca)
1212 {
1213 struct at86rf230_local *lp = hw->priv;
1214 u8 val;
1215
1216 /* mapping 802.15.4 to driver spec */
1217 switch (cca->mode) {
1218 case NL802154_CCA_ENERGY:
1219 val = 1;
1220 break;
1221 case NL802154_CCA_CARRIER:
1222 val = 2;
1223 break;
1224 case NL802154_CCA_ENERGY_CARRIER:
1225 switch (cca->opt) {
1226 case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
1227 val = 3;
1228 break;
1229 case NL802154_CCA_OPT_ENERGY_CARRIER_OR:
1230 val = 0;
1231 break;
1232 default:
1233 return -EINVAL;
1234 }
1235 break;
1236 default:
1237 return -EINVAL;
1238 }
1239
1240 return at86rf230_write_subreg(lp, SR_CCA_MODE, val);
1241 }
1242
1243 static int
1244 at86rf212_get_desens_steps(struct at86rf230_local *lp, s32 level)
1245 {
1246 return (level - lp->data->rssi_base_val) * 100 / 207;
1247 }
1248
1249 static int
1250 at86rf23x_get_desens_steps(struct at86rf230_local *lp, s32 level)
1251 {
1252 return (level - lp->data->rssi_base_val) / 2;
1253 }
1254
1255 static int
1256 at86rf230_set_cca_ed_level(struct ieee802154_hw *hw, s32 level)
1257 {
1258 struct at86rf230_local *lp = hw->priv;
1259
1260 if (level < lp->data->rssi_base_val || level > 30)
1261 return -EINVAL;
1262
1263 return at86rf230_write_subreg(lp, SR_CCA_ED_THRES,
1264 lp->data->get_desense_steps(lp, level));
1265 }
1266
1267 static int
1268 at86rf230_set_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
1269 u8 retries)
1270 {
1271 struct at86rf230_local *lp = hw->priv;
1272 int rc;
1273
1274 rc = at86rf230_write_subreg(lp, SR_MIN_BE, min_be);
1275 if (rc)
1276 return rc;
1277
1278 rc = at86rf230_write_subreg(lp, SR_MAX_BE, max_be);
1279 if (rc)
1280 return rc;
1281
1282 return at86rf230_write_subreg(lp, SR_MAX_CSMA_RETRIES, retries);
1283 }
1284
1285 static int
1286 at86rf230_set_frame_retries(struct ieee802154_hw *hw, s8 retries)
1287 {
1288 struct at86rf230_local *lp = hw->priv;
1289 int rc = 0;
1290
1291 lp->tx_aret = retries >= 0;
1292 lp->max_frame_retries = retries;
1293
1294 if (retries >= 0)
1295 rc = at86rf230_write_subreg(lp, SR_MAX_FRAME_RETRIES, retries);
1296
1297 return rc;
1298 }
1299
1300 static int
1301 at86rf230_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on)
1302 {
1303 struct at86rf230_local *lp = hw->priv;
1304 int rc;
1305
1306 if (on) {
1307 rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 1);
1308 if (rc < 0)
1309 return rc;
1310
1311 rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 1);
1312 if (rc < 0)
1313 return rc;
1314 } else {
1315 rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 0);
1316 if (rc < 0)
1317 return rc;
1318
1319 rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 0);
1320 if (rc < 0)
1321 return rc;
1322 }
1323
1324 return 0;
1325 }
1326
1327 static const struct ieee802154_ops at86rf230_ops = {
1328 .owner = THIS_MODULE,
1329 .xmit_async = at86rf230_xmit,
1330 .ed = at86rf230_ed,
1331 .set_channel = at86rf230_channel,
1332 .start = at86rf230_start,
1333 .stop = at86rf230_stop,
1334 .set_hw_addr_filt = at86rf230_set_hw_addr_filt,
1335 .set_txpower = at86rf230_set_txpower,
1336 .set_lbt = at86rf230_set_lbt,
1337 .set_cca_mode = at86rf230_set_cca_mode,
1338 .set_cca_ed_level = at86rf230_set_cca_ed_level,
1339 .set_csma_params = at86rf230_set_csma_params,
1340 .set_frame_retries = at86rf230_set_frame_retries,
1341 .set_promiscuous_mode = at86rf230_set_promiscuous_mode,
1342 };
1343
1344 static struct at86rf2xx_chip_data at86rf233_data = {
1345 .t_sleep_cycle = 330,
1346 .t_channel_switch = 11,
1347 .t_reset_to_off = 26,
1348 .t_off_to_aack = 80,
1349 .t_off_to_tx_on = 80,
1350 .t_frame = 4096,
1351 .t_p_ack = 545,
1352 .rssi_base_val = -91,
1353 .set_channel = at86rf23x_set_channel,
1354 .get_desense_steps = at86rf23x_get_desens_steps
1355 };
1356
1357 static struct at86rf2xx_chip_data at86rf231_data = {
1358 .t_sleep_cycle = 330,
1359 .t_channel_switch = 24,
1360 .t_reset_to_off = 37,
1361 .t_off_to_aack = 110,
1362 .t_off_to_tx_on = 110,
1363 .t_frame = 4096,
1364 .t_p_ack = 545,
1365 .rssi_base_val = -91,
1366 .set_channel = at86rf23x_set_channel,
1367 .get_desense_steps = at86rf23x_get_desens_steps
1368 };
1369
1370 static struct at86rf2xx_chip_data at86rf212_data = {
1371 .t_sleep_cycle = 330,
1372 .t_channel_switch = 11,
1373 .t_reset_to_off = 26,
1374 .t_off_to_aack = 200,
1375 .t_off_to_tx_on = 200,
1376 .t_frame = 4096,
1377 .t_p_ack = 545,
1378 .rssi_base_val = -100,
1379 .set_channel = at86rf212_set_channel,
1380 .get_desense_steps = at86rf212_get_desens_steps
1381 };
1382
1383 static int at86rf230_hw_init(struct at86rf230_local *lp, u8 xtal_trim)
1384 {
1385 int rc, irq_type, irq_pol = IRQ_ACTIVE_HIGH;
1386 unsigned int dvdd;
1387 u8 csma_seed[2];
1388
1389 rc = at86rf230_sync_state_change(lp, STATE_FORCE_TRX_OFF);
1390 if (rc)
1391 return rc;
1392
1393 irq_type = irq_get_trigger_type(lp->spi->irq);
1394 if (irq_type == IRQ_TYPE_EDGE_RISING ||
1395 irq_type == IRQ_TYPE_EDGE_FALLING)
1396 dev_warn(&lp->spi->dev,
1397 "Using edge triggered irq's are not recommended!\n");
1398 if (irq_type == IRQ_TYPE_EDGE_FALLING ||
1399 irq_type == IRQ_TYPE_LEVEL_LOW)
1400 irq_pol = IRQ_ACTIVE_LOW;
1401
1402 rc = at86rf230_write_subreg(lp, SR_IRQ_POLARITY, irq_pol);
1403 if (rc)
1404 return rc;
1405
1406 rc = at86rf230_write_subreg(lp, SR_RX_SAFE_MODE, 1);
1407 if (rc)
1408 return rc;
1409
1410 rc = at86rf230_write_subreg(lp, SR_IRQ_MASK, IRQ_TRX_END);
1411 if (rc)
1412 return rc;
1413
1414 /* reset values differs in at86rf231 and at86rf233 */
1415 rc = at86rf230_write_subreg(lp, SR_IRQ_MASK_MODE, 0);
1416 if (rc)
1417 return rc;
1418
1419 get_random_bytes(csma_seed, ARRAY_SIZE(csma_seed));
1420 rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_0, csma_seed[0]);
1421 if (rc)
1422 return rc;
1423 rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_1, csma_seed[1]);
1424 if (rc)
1425 return rc;
1426
1427 /* CLKM changes are applied immediately */
1428 rc = at86rf230_write_subreg(lp, SR_CLKM_SHA_SEL, 0x00);
1429 if (rc)
1430 return rc;
1431
1432 /* Turn CLKM Off */
1433 rc = at86rf230_write_subreg(lp, SR_CLKM_CTRL, 0x00);
1434 if (rc)
1435 return rc;
1436 /* Wait the next SLEEP cycle */
1437 usleep_range(lp->data->t_sleep_cycle,
1438 lp->data->t_sleep_cycle + 100);
1439
1440 /* xtal_trim value is calculated by:
1441 * CL = 0.5 * (CX + CTRIM + CPAR)
1442 *
1443 * whereas:
1444 * CL = capacitor of used crystal
1445 * CX = connected capacitors at xtal pins
1446 * CPAR = in all at86rf2xx datasheets this is a constant value 3 pF,
1447 * but this is different on each board setup. You need to fine
1448 * tuning this value via CTRIM.
1449 * CTRIM = variable capacitor setting. Resolution is 0.3 pF range is
1450 * 0 pF upto 4.5 pF.
1451 *
1452 * Examples:
1453 * atben transceiver:
1454 *
1455 * CL = 8 pF
1456 * CX = 12 pF
1457 * CPAR = 3 pF (We assume the magic constant from datasheet)
1458 * CTRIM = 0.9 pF
1459 *
1460 * (12+0.9+3)/2 = 7.95 which is nearly at 8 pF
1461 *
1462 * xtal_trim = 0x3
1463 *
1464 * openlabs transceiver:
1465 *
1466 * CL = 16 pF
1467 * CX = 22 pF
1468 * CPAR = 3 pF (We assume the magic constant from datasheet)
1469 * CTRIM = 4.5 pF
1470 *
1471 * (22+4.5+3)/2 = 14.75 which is the nearest value to 16 pF
1472 *
1473 * xtal_trim = 0xf
1474 */
1475 rc = at86rf230_write_subreg(lp, SR_XTAL_TRIM, xtal_trim);
1476 if (rc)
1477 return rc;
1478
1479 rc = at86rf230_read_subreg(lp, SR_DVDD_OK, &dvdd);
1480 if (rc)
1481 return rc;
1482 if (!dvdd) {
1483 dev_err(&lp->spi->dev, "DVDD error\n");
1484 return -EINVAL;
1485 }
1486
1487 /* Force setting slotted operation bit to 0. Sometimes the atben
1488 * sets this bit and I don't know why. We set this always force
1489 * to zero while probing.
1490 */
1491 return at86rf230_write_subreg(lp, SR_SLOTTED_OPERATION, 0);
1492 }
1493
1494 static int
1495 at86rf230_get_pdata(struct spi_device *spi, int *rstn, int *slp_tr,
1496 u8 *xtal_trim)
1497 {
1498 struct at86rf230_platform_data *pdata = spi->dev.platform_data;
1499 int ret;
1500
1501 if (!IS_ENABLED(CONFIG_OF) || !spi->dev.of_node) {
1502 if (!pdata)
1503 return -ENOENT;
1504
1505 *rstn = pdata->rstn;
1506 *slp_tr = pdata->slp_tr;
1507 *xtal_trim = pdata->xtal_trim;
1508 return 0;
1509 }
1510
1511 *rstn = of_get_named_gpio(spi->dev.of_node, "reset-gpio", 0);
1512 *slp_tr = of_get_named_gpio(spi->dev.of_node, "sleep-gpio", 0);
1513 ret = of_property_read_u8(spi->dev.of_node, "xtal-trim", xtal_trim);
1514 if (ret < 0 && ret != -EINVAL)
1515 return ret;
1516
1517 return 0;
1518 }
1519
1520 static int
1521 at86rf230_detect_device(struct at86rf230_local *lp)
1522 {
1523 unsigned int part, version, val;
1524 u16 man_id = 0;
1525 const char *chip;
1526 int rc;
1527
1528 rc = __at86rf230_read(lp, RG_MAN_ID_0, &val);
1529 if (rc)
1530 return rc;
1531 man_id |= val;
1532
1533 rc = __at86rf230_read(lp, RG_MAN_ID_1, &val);
1534 if (rc)
1535 return rc;
1536 man_id |= (val << 8);
1537
1538 rc = __at86rf230_read(lp, RG_PART_NUM, &part);
1539 if (rc)
1540 return rc;
1541
1542 rc = __at86rf230_read(lp, RG_VERSION_NUM, &version);
1543 if (rc)
1544 return rc;
1545
1546 if (man_id != 0x001f) {
1547 dev_err(&lp->spi->dev, "Non-Atmel dev found (MAN_ID %02x %02x)\n",
1548 man_id >> 8, man_id & 0xFF);
1549 return -EINVAL;
1550 }
1551
1552 lp->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AACK |
1553 IEEE802154_HW_TXPOWER | IEEE802154_HW_ARET |
1554 IEEE802154_HW_AFILT | IEEE802154_HW_PROMISCUOUS;
1555
1556 lp->hw->phy->cca.mode = NL802154_CCA_ENERGY;
1557
1558 switch (part) {
1559 case 2:
1560 chip = "at86rf230";
1561 rc = -ENOTSUPP;
1562 break;
1563 case 3:
1564 chip = "at86rf231";
1565 lp->data = &at86rf231_data;
1566 lp->hw->phy->channels_supported[0] = 0x7FFF800;
1567 lp->hw->phy->current_channel = 11;
1568 lp->hw->phy->symbol_duration = 16;
1569 break;
1570 case 7:
1571 chip = "at86rf212";
1572 lp->data = &at86rf212_data;
1573 lp->hw->flags |= IEEE802154_HW_LBT;
1574 lp->hw->phy->channels_supported[0] = 0x00007FF;
1575 lp->hw->phy->channels_supported[2] = 0x00007FF;
1576 lp->hw->phy->current_channel = 5;
1577 lp->hw->phy->symbol_duration = 25;
1578 break;
1579 case 11:
1580 chip = "at86rf233";
1581 lp->data = &at86rf233_data;
1582 lp->hw->phy->channels_supported[0] = 0x7FFF800;
1583 lp->hw->phy->current_channel = 13;
1584 lp->hw->phy->symbol_duration = 16;
1585 break;
1586 default:
1587 chip = "unknown";
1588 rc = -ENOTSUPP;
1589 break;
1590 }
1591
1592 dev_info(&lp->spi->dev, "Detected %s chip version %d\n", chip, version);
1593
1594 return rc;
1595 }
1596
1597 static void
1598 at86rf230_setup_spi_messages(struct at86rf230_local *lp)
1599 {
1600 lp->state.lp = lp;
1601 lp->state.irq = lp->spi->irq;
1602 spi_message_init(&lp->state.msg);
1603 lp->state.msg.context = &lp->state;
1604 lp->state.trx.len = 2;
1605 lp->state.trx.tx_buf = lp->state.buf;
1606 lp->state.trx.rx_buf = lp->state.buf;
1607 spi_message_add_tail(&lp->state.trx, &lp->state.msg);
1608 hrtimer_init(&lp->state.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1609 lp->state.timer.function = at86rf230_async_state_timer;
1610
1611 lp->irq.lp = lp;
1612 lp->irq.irq = lp->spi->irq;
1613 spi_message_init(&lp->irq.msg);
1614 lp->irq.msg.context = &lp->irq;
1615 lp->irq.trx.len = 2;
1616 lp->irq.trx.tx_buf = lp->irq.buf;
1617 lp->irq.trx.rx_buf = lp->irq.buf;
1618 spi_message_add_tail(&lp->irq.trx, &lp->irq.msg);
1619 hrtimer_init(&lp->irq.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1620 lp->irq.timer.function = at86rf230_async_state_timer;
1621
1622 lp->tx.lp = lp;
1623 lp->tx.irq = lp->spi->irq;
1624 spi_message_init(&lp->tx.msg);
1625 lp->tx.msg.context = &lp->tx;
1626 lp->tx.trx.len = 2;
1627 lp->tx.trx.tx_buf = lp->tx.buf;
1628 lp->tx.trx.rx_buf = lp->tx.buf;
1629 spi_message_add_tail(&lp->tx.trx, &lp->tx.msg);
1630 hrtimer_init(&lp->tx.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1631 lp->tx.timer.function = at86rf230_async_state_timer;
1632 }
1633
1634 static int at86rf230_probe(struct spi_device *spi)
1635 {
1636 struct ieee802154_hw *hw;
1637 struct at86rf230_local *lp;
1638 unsigned int status;
1639 int rc, irq_type, rstn, slp_tr;
1640 u8 xtal_trim = 0;
1641
1642 if (!spi->irq) {
1643 dev_err(&spi->dev, "no IRQ specified\n");
1644 return -EINVAL;
1645 }
1646
1647 rc = at86rf230_get_pdata(spi, &rstn, &slp_tr, &xtal_trim);
1648 if (rc < 0) {
1649 dev_err(&spi->dev, "failed to parse platform_data: %d\n", rc);
1650 return rc;
1651 }
1652
1653 if (gpio_is_valid(rstn)) {
1654 rc = devm_gpio_request_one(&spi->dev, rstn,
1655 GPIOF_OUT_INIT_HIGH, "rstn");
1656 if (rc)
1657 return rc;
1658 }
1659
1660 if (gpio_is_valid(slp_tr)) {
1661 rc = devm_gpio_request_one(&spi->dev, slp_tr,
1662 GPIOF_OUT_INIT_LOW, "slp_tr");
1663 if (rc)
1664 return rc;
1665 }
1666
1667 /* Reset */
1668 if (gpio_is_valid(rstn)) {
1669 udelay(1);
1670 gpio_set_value(rstn, 0);
1671 udelay(1);
1672 gpio_set_value(rstn, 1);
1673 usleep_range(120, 240);
1674 }
1675
1676 hw = ieee802154_alloc_hw(sizeof(*lp), &at86rf230_ops);
1677 if (!hw)
1678 return -ENOMEM;
1679
1680 lp = hw->priv;
1681 lp->hw = hw;
1682 lp->spi = spi;
1683 hw->parent = &spi->dev;
1684 hw->vif_data_size = sizeof(*lp);
1685 ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
1686
1687 lp->regmap = devm_regmap_init_spi(spi, &at86rf230_regmap_spi_config);
1688 if (IS_ERR(lp->regmap)) {
1689 rc = PTR_ERR(lp->regmap);
1690 dev_err(&spi->dev, "Failed to allocate register map: %d\n",
1691 rc);
1692 goto free_dev;
1693 }
1694
1695 at86rf230_setup_spi_messages(lp);
1696
1697 rc = at86rf230_detect_device(lp);
1698 if (rc < 0)
1699 goto free_dev;
1700
1701 spin_lock_init(&lp->lock);
1702 init_completion(&lp->state_complete);
1703
1704 spi_set_drvdata(spi, lp);
1705
1706 rc = at86rf230_hw_init(lp, xtal_trim);
1707 if (rc)
1708 goto free_dev;
1709
1710 /* Read irq status register to reset irq line */
1711 rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &status);
1712 if (rc)
1713 goto free_dev;
1714
1715 irq_type = irq_get_trigger_type(spi->irq);
1716 if (!irq_type)
1717 irq_type = IRQF_TRIGGER_RISING;
1718
1719 rc = devm_request_irq(&spi->dev, spi->irq, at86rf230_isr,
1720 IRQF_SHARED | irq_type, dev_name(&spi->dev), lp);
1721 if (rc)
1722 goto free_dev;
1723
1724 rc = ieee802154_register_hw(lp->hw);
1725 if (rc)
1726 goto free_dev;
1727
1728 return rc;
1729
1730 free_dev:
1731 ieee802154_free_hw(lp->hw);
1732
1733 return rc;
1734 }
1735
1736 static int at86rf230_remove(struct spi_device *spi)
1737 {
1738 struct at86rf230_local *lp = spi_get_drvdata(spi);
1739
1740 /* mask all at86rf230 irq's */
1741 at86rf230_write_subreg(lp, SR_IRQ_MASK, 0);
1742 ieee802154_unregister_hw(lp->hw);
1743 ieee802154_free_hw(lp->hw);
1744 dev_dbg(&spi->dev, "unregistered at86rf230\n");
1745
1746 return 0;
1747 }
1748
1749 static const struct of_device_id at86rf230_of_match[] = {
1750 { .compatible = "atmel,at86rf230", },
1751 { .compatible = "atmel,at86rf231", },
1752 { .compatible = "atmel,at86rf233", },
1753 { .compatible = "atmel,at86rf212", },
1754 { },
1755 };
1756 MODULE_DEVICE_TABLE(of, at86rf230_of_match);
1757
1758 static const struct spi_device_id at86rf230_device_id[] = {
1759 { .name = "at86rf230", },
1760 { .name = "at86rf231", },
1761 { .name = "at86rf233", },
1762 { .name = "at86rf212", },
1763 { },
1764 };
1765 MODULE_DEVICE_TABLE(spi, at86rf230_device_id);
1766
1767 static struct spi_driver at86rf230_driver = {
1768 .id_table = at86rf230_device_id,
1769 .driver = {
1770 .of_match_table = of_match_ptr(at86rf230_of_match),
1771 .name = "at86rf230",
1772 .owner = THIS_MODULE,
1773 },
1774 .probe = at86rf230_probe,
1775 .remove = at86rf230_remove,
1776 };
1777
1778 module_spi_driver(at86rf230_driver);
1779
1780 MODULE_DESCRIPTION("AT86RF230 Transceiver Driver");
1781 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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