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at86rf230: replace state change sleeps with hrtimer
[deliverable/linux.git] / drivers / net / ieee802154 / at86rf230.c
1 /*
2 * AT86RF230/RF231 driver
3 *
4 * Copyright (C) 2009-2012 Siemens AG
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * Written by:
16 * Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
17 * Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
18 * Alexander Aring <aar@pengutronix.de>
19 */
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/hrtimer.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/gpio.h>
26 #include <linux/delay.h>
27 #include <linux/spinlock.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/at86rf230.h>
30 #include <linux/regmap.h>
31 #include <linux/skbuff.h>
32 #include <linux/of_gpio.h>
33 #include <linux/ieee802154.h>
34
35 #include <net/mac802154.h>
36 #include <net/cfg802154.h>
37
38 struct at86rf230_local;
39 /* at86rf2xx chip depend data.
40 * All timings are in us.
41 */
42 struct at86rf2xx_chip_data {
43 u16 t_sleep_cycle;
44 u16 t_channel_switch;
45 u16 t_reset_to_off;
46 u16 t_off_to_aack;
47 u16 t_off_to_tx_on;
48 u16 t_frame;
49 u16 t_p_ack;
50 int rssi_base_val;
51
52 int (*set_channel)(struct at86rf230_local *, u8, u8);
53 int (*get_desense_steps)(struct at86rf230_local *, s32);
54 };
55
56 #define AT86RF2XX_MAX_BUF (127 + 3)
57 /* tx retries to access the TX_ON state
58 * if it's above then force change will be started.
59 *
60 * We assume the max_frame_retries (7) value of 802.15.4 here.
61 */
62 #define AT86RF2XX_MAX_TX_RETRIES 7
63
64 struct at86rf230_state_change {
65 struct at86rf230_local *lp;
66 int irq;
67
68 struct hrtimer timer;
69 struct spi_message msg;
70 struct spi_transfer trx;
71 u8 buf[AT86RF2XX_MAX_BUF];
72
73 void (*complete)(void *context);
74 u8 from_state;
75 u8 to_state;
76
77 bool irq_enable;
78 };
79
80 struct at86rf230_local {
81 struct spi_device *spi;
82
83 struct ieee802154_hw *hw;
84 struct at86rf2xx_chip_data *data;
85 struct regmap *regmap;
86
87 struct completion state_complete;
88 struct at86rf230_state_change state;
89
90 struct at86rf230_state_change irq;
91
92 bool tx_aret;
93 s8 max_frame_retries;
94 bool is_tx;
95 /* spinlock for is_tx protection */
96 spinlock_t lock;
97 u8 tx_retry;
98 struct sk_buff *tx_skb;
99 struct at86rf230_state_change tx;
100 };
101
102 #define RG_TRX_STATUS (0x01)
103 #define SR_TRX_STATUS 0x01, 0x1f, 0
104 #define SR_RESERVED_01_3 0x01, 0x20, 5
105 #define SR_CCA_STATUS 0x01, 0x40, 6
106 #define SR_CCA_DONE 0x01, 0x80, 7
107 #define RG_TRX_STATE (0x02)
108 #define SR_TRX_CMD 0x02, 0x1f, 0
109 #define SR_TRAC_STATUS 0x02, 0xe0, 5
110 #define RG_TRX_CTRL_0 (0x03)
111 #define SR_CLKM_CTRL 0x03, 0x07, 0
112 #define SR_CLKM_SHA_SEL 0x03, 0x08, 3
113 #define SR_PAD_IO_CLKM 0x03, 0x30, 4
114 #define SR_PAD_IO 0x03, 0xc0, 6
115 #define RG_TRX_CTRL_1 (0x04)
116 #define SR_IRQ_POLARITY 0x04, 0x01, 0
117 #define SR_IRQ_MASK_MODE 0x04, 0x02, 1
118 #define SR_SPI_CMD_MODE 0x04, 0x0c, 2
119 #define SR_RX_BL_CTRL 0x04, 0x10, 4
120 #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
121 #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6
122 #define SR_PA_EXT_EN 0x04, 0x80, 7
123 #define RG_PHY_TX_PWR (0x05)
124 #define SR_TX_PWR 0x05, 0x0f, 0
125 #define SR_PA_LT 0x05, 0x30, 4
126 #define SR_PA_BUF_LT 0x05, 0xc0, 6
127 #define RG_PHY_RSSI (0x06)
128 #define SR_RSSI 0x06, 0x1f, 0
129 #define SR_RND_VALUE 0x06, 0x60, 5
130 #define SR_RX_CRC_VALID 0x06, 0x80, 7
131 #define RG_PHY_ED_LEVEL (0x07)
132 #define SR_ED_LEVEL 0x07, 0xff, 0
133 #define RG_PHY_CC_CCA (0x08)
134 #define SR_CHANNEL 0x08, 0x1f, 0
135 #define SR_CCA_MODE 0x08, 0x60, 5
136 #define SR_CCA_REQUEST 0x08, 0x80, 7
137 #define RG_CCA_THRES (0x09)
138 #define SR_CCA_ED_THRES 0x09, 0x0f, 0
139 #define SR_RESERVED_09_1 0x09, 0xf0, 4
140 #define RG_RX_CTRL (0x0a)
141 #define SR_PDT_THRES 0x0a, 0x0f, 0
142 #define SR_RESERVED_0a_1 0x0a, 0xf0, 4
143 #define RG_SFD_VALUE (0x0b)
144 #define SR_SFD_VALUE 0x0b, 0xff, 0
145 #define RG_TRX_CTRL_2 (0x0c)
146 #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
147 #define SR_SUB_MODE 0x0c, 0x04, 2
148 #define SR_BPSK_QPSK 0x0c, 0x08, 3
149 #define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4
150 #define SR_RESERVED_0c_5 0x0c, 0x60, 5
151 #define SR_RX_SAFE_MODE 0x0c, 0x80, 7
152 #define RG_ANT_DIV (0x0d)
153 #define SR_ANT_CTRL 0x0d, 0x03, 0
154 #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
155 #define SR_ANT_DIV_EN 0x0d, 0x08, 3
156 #define SR_RESERVED_0d_2 0x0d, 0x70, 4
157 #define SR_ANT_SEL 0x0d, 0x80, 7
158 #define RG_IRQ_MASK (0x0e)
159 #define SR_IRQ_MASK 0x0e, 0xff, 0
160 #define RG_IRQ_STATUS (0x0f)
161 #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
162 #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
163 #define SR_IRQ_2_RX_START 0x0f, 0x04, 2
164 #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
165 #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4
166 #define SR_IRQ_5_AMI 0x0f, 0x20, 5
167 #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
168 #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
169 #define RG_VREG_CTRL (0x10)
170 #define SR_RESERVED_10_6 0x10, 0x03, 0
171 #define SR_DVDD_OK 0x10, 0x04, 2
172 #define SR_DVREG_EXT 0x10, 0x08, 3
173 #define SR_RESERVED_10_3 0x10, 0x30, 4
174 #define SR_AVDD_OK 0x10, 0x40, 6
175 #define SR_AVREG_EXT 0x10, 0x80, 7
176 #define RG_BATMON (0x11)
177 #define SR_BATMON_VTH 0x11, 0x0f, 0
178 #define SR_BATMON_HR 0x11, 0x10, 4
179 #define SR_BATMON_OK 0x11, 0x20, 5
180 #define SR_RESERVED_11_1 0x11, 0xc0, 6
181 #define RG_XOSC_CTRL (0x12)
182 #define SR_XTAL_TRIM 0x12, 0x0f, 0
183 #define SR_XTAL_MODE 0x12, 0xf0, 4
184 #define RG_RX_SYN (0x15)
185 #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0
186 #define SR_RESERVED_15_2 0x15, 0x70, 4
187 #define SR_RX_PDT_DIS 0x15, 0x80, 7
188 #define RG_XAH_CTRL_1 (0x17)
189 #define SR_RESERVED_17_8 0x17, 0x01, 0
190 #define SR_AACK_PROM_MODE 0x17, 0x02, 1
191 #define SR_AACK_ACK_TIME 0x17, 0x04, 2
192 #define SR_RESERVED_17_5 0x17, 0x08, 3
193 #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
194 #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
195 #define SR_CSMA_LBT_MODE 0x17, 0x40, 6
196 #define SR_RESERVED_17_1 0x17, 0x80, 7
197 #define RG_FTN_CTRL (0x18)
198 #define SR_RESERVED_18_2 0x18, 0x7f, 0
199 #define SR_FTN_START 0x18, 0x80, 7
200 #define RG_PLL_CF (0x1a)
201 #define SR_RESERVED_1a_2 0x1a, 0x7f, 0
202 #define SR_PLL_CF_START 0x1a, 0x80, 7
203 #define RG_PLL_DCU (0x1b)
204 #define SR_RESERVED_1b_3 0x1b, 0x3f, 0
205 #define SR_RESERVED_1b_2 0x1b, 0x40, 6
206 #define SR_PLL_DCU_START 0x1b, 0x80, 7
207 #define RG_PART_NUM (0x1c)
208 #define SR_PART_NUM 0x1c, 0xff, 0
209 #define RG_VERSION_NUM (0x1d)
210 #define SR_VERSION_NUM 0x1d, 0xff, 0
211 #define RG_MAN_ID_0 (0x1e)
212 #define SR_MAN_ID_0 0x1e, 0xff, 0
213 #define RG_MAN_ID_1 (0x1f)
214 #define SR_MAN_ID_1 0x1f, 0xff, 0
215 #define RG_SHORT_ADDR_0 (0x20)
216 #define SR_SHORT_ADDR_0 0x20, 0xff, 0
217 #define RG_SHORT_ADDR_1 (0x21)
218 #define SR_SHORT_ADDR_1 0x21, 0xff, 0
219 #define RG_PAN_ID_0 (0x22)
220 #define SR_PAN_ID_0 0x22, 0xff, 0
221 #define RG_PAN_ID_1 (0x23)
222 #define SR_PAN_ID_1 0x23, 0xff, 0
223 #define RG_IEEE_ADDR_0 (0x24)
224 #define SR_IEEE_ADDR_0 0x24, 0xff, 0
225 #define RG_IEEE_ADDR_1 (0x25)
226 #define SR_IEEE_ADDR_1 0x25, 0xff, 0
227 #define RG_IEEE_ADDR_2 (0x26)
228 #define SR_IEEE_ADDR_2 0x26, 0xff, 0
229 #define RG_IEEE_ADDR_3 (0x27)
230 #define SR_IEEE_ADDR_3 0x27, 0xff, 0
231 #define RG_IEEE_ADDR_4 (0x28)
232 #define SR_IEEE_ADDR_4 0x28, 0xff, 0
233 #define RG_IEEE_ADDR_5 (0x29)
234 #define SR_IEEE_ADDR_5 0x29, 0xff, 0
235 #define RG_IEEE_ADDR_6 (0x2a)
236 #define SR_IEEE_ADDR_6 0x2a, 0xff, 0
237 #define RG_IEEE_ADDR_7 (0x2b)
238 #define SR_IEEE_ADDR_7 0x2b, 0xff, 0
239 #define RG_XAH_CTRL_0 (0x2c)
240 #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0
241 #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
242 #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
243 #define RG_CSMA_SEED_0 (0x2d)
244 #define SR_CSMA_SEED_0 0x2d, 0xff, 0
245 #define RG_CSMA_SEED_1 (0x2e)
246 #define SR_CSMA_SEED_1 0x2e, 0x07, 0
247 #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3
248 #define SR_AACK_DIS_ACK 0x2e, 0x10, 4
249 #define SR_AACK_SET_PD 0x2e, 0x20, 5
250 #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6
251 #define RG_CSMA_BE (0x2f)
252 #define SR_MIN_BE 0x2f, 0x0f, 0
253 #define SR_MAX_BE 0x2f, 0xf0, 4
254
255 #define CMD_REG 0x80
256 #define CMD_REG_MASK 0x3f
257 #define CMD_WRITE 0x40
258 #define CMD_FB 0x20
259
260 #define IRQ_BAT_LOW (1 << 7)
261 #define IRQ_TRX_UR (1 << 6)
262 #define IRQ_AMI (1 << 5)
263 #define IRQ_CCA_ED (1 << 4)
264 #define IRQ_TRX_END (1 << 3)
265 #define IRQ_RX_START (1 << 2)
266 #define IRQ_PLL_UNL (1 << 1)
267 #define IRQ_PLL_LOCK (1 << 0)
268
269 #define IRQ_ACTIVE_HIGH 0
270 #define IRQ_ACTIVE_LOW 1
271
272 #define STATE_P_ON 0x00 /* BUSY */
273 #define STATE_BUSY_RX 0x01
274 #define STATE_BUSY_TX 0x02
275 #define STATE_FORCE_TRX_OFF 0x03
276 #define STATE_FORCE_TX_ON 0x04 /* IDLE */
277 /* 0x05 */ /* INVALID_PARAMETER */
278 #define STATE_RX_ON 0x06
279 /* 0x07 */ /* SUCCESS */
280 #define STATE_TRX_OFF 0x08
281 #define STATE_TX_ON 0x09
282 /* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */
283 #define STATE_SLEEP 0x0F
284 #define STATE_PREP_DEEP_SLEEP 0x10
285 #define STATE_BUSY_RX_AACK 0x11
286 #define STATE_BUSY_TX_ARET 0x12
287 #define STATE_RX_AACK_ON 0x16
288 #define STATE_TX_ARET_ON 0x19
289 #define STATE_RX_ON_NOCLK 0x1C
290 #define STATE_RX_AACK_ON_NOCLK 0x1D
291 #define STATE_BUSY_RX_AACK_NOCLK 0x1E
292 #define STATE_TRANSITION_IN_PROGRESS 0x1F
293
294 #define AT86RF2XX_NUMREGS 0x3F
295
296 static void
297 at86rf230_async_state_change(struct at86rf230_local *lp,
298 struct at86rf230_state_change *ctx,
299 const u8 state, void (*complete)(void *context),
300 const bool irq_enable);
301
302 static inline int
303 __at86rf230_write(struct at86rf230_local *lp,
304 unsigned int addr, unsigned int data)
305 {
306 return regmap_write(lp->regmap, addr, data);
307 }
308
309 static inline int
310 __at86rf230_read(struct at86rf230_local *lp,
311 unsigned int addr, unsigned int *data)
312 {
313 return regmap_read(lp->regmap, addr, data);
314 }
315
316 static inline int
317 at86rf230_read_subreg(struct at86rf230_local *lp,
318 unsigned int addr, unsigned int mask,
319 unsigned int shift, unsigned int *data)
320 {
321 int rc;
322
323 rc = __at86rf230_read(lp, addr, data);
324 if (rc > 0)
325 *data = (*data & mask) >> shift;
326
327 return rc;
328 }
329
330 static inline int
331 at86rf230_write_subreg(struct at86rf230_local *lp,
332 unsigned int addr, unsigned int mask,
333 unsigned int shift, unsigned int data)
334 {
335 return regmap_update_bits(lp->regmap, addr, mask, data << shift);
336 }
337
338 static bool
339 at86rf230_reg_writeable(struct device *dev, unsigned int reg)
340 {
341 switch (reg) {
342 case RG_TRX_STATE:
343 case RG_TRX_CTRL_0:
344 case RG_TRX_CTRL_1:
345 case RG_PHY_TX_PWR:
346 case RG_PHY_ED_LEVEL:
347 case RG_PHY_CC_CCA:
348 case RG_CCA_THRES:
349 case RG_RX_CTRL:
350 case RG_SFD_VALUE:
351 case RG_TRX_CTRL_2:
352 case RG_ANT_DIV:
353 case RG_IRQ_MASK:
354 case RG_VREG_CTRL:
355 case RG_BATMON:
356 case RG_XOSC_CTRL:
357 case RG_RX_SYN:
358 case RG_XAH_CTRL_1:
359 case RG_FTN_CTRL:
360 case RG_PLL_CF:
361 case RG_PLL_DCU:
362 case RG_SHORT_ADDR_0:
363 case RG_SHORT_ADDR_1:
364 case RG_PAN_ID_0:
365 case RG_PAN_ID_1:
366 case RG_IEEE_ADDR_0:
367 case RG_IEEE_ADDR_1:
368 case RG_IEEE_ADDR_2:
369 case RG_IEEE_ADDR_3:
370 case RG_IEEE_ADDR_4:
371 case RG_IEEE_ADDR_5:
372 case RG_IEEE_ADDR_6:
373 case RG_IEEE_ADDR_7:
374 case RG_XAH_CTRL_0:
375 case RG_CSMA_SEED_0:
376 case RG_CSMA_SEED_1:
377 case RG_CSMA_BE:
378 return true;
379 default:
380 return false;
381 }
382 }
383
384 static bool
385 at86rf230_reg_readable(struct device *dev, unsigned int reg)
386 {
387 bool rc;
388
389 /* all writeable are also readable */
390 rc = at86rf230_reg_writeable(dev, reg);
391 if (rc)
392 return rc;
393
394 /* readonly regs */
395 switch (reg) {
396 case RG_TRX_STATUS:
397 case RG_PHY_RSSI:
398 case RG_IRQ_STATUS:
399 case RG_PART_NUM:
400 case RG_VERSION_NUM:
401 case RG_MAN_ID_1:
402 case RG_MAN_ID_0:
403 return true;
404 default:
405 return false;
406 }
407 }
408
409 static bool
410 at86rf230_reg_volatile(struct device *dev, unsigned int reg)
411 {
412 /* can be changed during runtime */
413 switch (reg) {
414 case RG_TRX_STATUS:
415 case RG_TRX_STATE:
416 case RG_PHY_RSSI:
417 case RG_PHY_ED_LEVEL:
418 case RG_IRQ_STATUS:
419 case RG_VREG_CTRL:
420 return true;
421 default:
422 return false;
423 }
424 }
425
426 static bool
427 at86rf230_reg_precious(struct device *dev, unsigned int reg)
428 {
429 /* don't clear irq line on read */
430 switch (reg) {
431 case RG_IRQ_STATUS:
432 return true;
433 default:
434 return false;
435 }
436 }
437
438 static const struct regmap_config at86rf230_regmap_spi_config = {
439 .reg_bits = 8,
440 .val_bits = 8,
441 .write_flag_mask = CMD_REG | CMD_WRITE,
442 .read_flag_mask = CMD_REG,
443 .cache_type = REGCACHE_RBTREE,
444 .max_register = AT86RF2XX_NUMREGS,
445 .writeable_reg = at86rf230_reg_writeable,
446 .readable_reg = at86rf230_reg_readable,
447 .volatile_reg = at86rf230_reg_volatile,
448 .precious_reg = at86rf230_reg_precious,
449 };
450
451 static void
452 at86rf230_async_error_recover(void *context)
453 {
454 struct at86rf230_state_change *ctx = context;
455 struct at86rf230_local *lp = ctx->lp;
456
457 at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON, NULL, false);
458 ieee802154_wake_queue(lp->hw);
459 }
460
461 static inline void
462 at86rf230_async_error(struct at86rf230_local *lp,
463 struct at86rf230_state_change *ctx, int rc)
464 {
465 dev_err(&lp->spi->dev, "spi_async error %d\n", rc);
466
467 at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF,
468 at86rf230_async_error_recover, false);
469 }
470
471 /* Generic function to get some register value in async mode */
472 static void
473 at86rf230_async_read_reg(struct at86rf230_local *lp, const u8 reg,
474 struct at86rf230_state_change *ctx,
475 void (*complete)(void *context),
476 const bool irq_enable)
477 {
478 int rc;
479
480 u8 *tx_buf = ctx->buf;
481
482 tx_buf[0] = (reg & CMD_REG_MASK) | CMD_REG;
483 ctx->msg.complete = complete;
484 ctx->irq_enable = irq_enable;
485 rc = spi_async(lp->spi, &ctx->msg);
486 if (rc) {
487 if (irq_enable)
488 enable_irq(ctx->irq);
489
490 at86rf230_async_error(lp, ctx, rc);
491 }
492 }
493
494 static void
495 at86rf230_async_state_assert(void *context)
496 {
497 struct at86rf230_state_change *ctx = context;
498 struct at86rf230_local *lp = ctx->lp;
499 const u8 *buf = ctx->buf;
500 const u8 trx_state = buf[1] & 0x1f;
501
502 /* Assert state change */
503 if (trx_state != ctx->to_state) {
504 /* Special handling if transceiver state is in
505 * STATE_BUSY_RX_AACK and a SHR was detected.
506 */
507 if (trx_state == STATE_BUSY_RX_AACK) {
508 /* Undocumented race condition. If we send a state
509 * change to STATE_RX_AACK_ON the transceiver could
510 * change his state automatically to STATE_BUSY_RX_AACK
511 * if a SHR was detected. This is not an error, but we
512 * can't assert this.
513 */
514 if (ctx->to_state == STATE_RX_AACK_ON)
515 goto done;
516
517 /* If we change to STATE_TX_ON without forcing and
518 * transceiver state is STATE_BUSY_RX_AACK, we wait
519 * 'tFrame + tPAck' receiving time. In this time the
520 * PDU should be received. If the transceiver is still
521 * in STATE_BUSY_RX_AACK, we run a force state change
522 * to STATE_TX_ON. This is a timeout handling, if the
523 * transceiver stucks in STATE_BUSY_RX_AACK.
524 *
525 * Additional we do several retries to try to get into
526 * TX_ON state without forcing. If the retries are
527 * higher or equal than AT86RF2XX_MAX_TX_RETRIES we
528 * will do a force change.
529 */
530 if (ctx->to_state == STATE_TX_ON) {
531 u8 state = STATE_TX_ON;
532
533 if (lp->tx_retry >= AT86RF2XX_MAX_TX_RETRIES)
534 state = STATE_FORCE_TX_ON;
535 lp->tx_retry++;
536
537 at86rf230_async_state_change(lp, ctx, state,
538 ctx->complete,
539 ctx->irq_enable);
540 return;
541 }
542 }
543
544 dev_warn(&lp->spi->dev, "unexcept state change from 0x%02x to 0x%02x. Actual state: 0x%02x\n",
545 ctx->from_state, ctx->to_state, trx_state);
546 }
547
548 done:
549 if (ctx->complete)
550 ctx->complete(context);
551 }
552
553 static enum hrtimer_restart at86rf230_async_state_timer(struct hrtimer *timer)
554 {
555 struct at86rf230_state_change *ctx =
556 container_of(timer, struct at86rf230_state_change, timer);
557 struct at86rf230_local *lp = ctx->lp;
558
559 at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
560 at86rf230_async_state_assert,
561 ctx->irq_enable);
562
563 return HRTIMER_NORESTART;
564 }
565
566 /* Do state change timing delay. */
567 static void
568 at86rf230_async_state_delay(void *context)
569 {
570 struct at86rf230_state_change *ctx = context;
571 struct at86rf230_local *lp = ctx->lp;
572 struct at86rf2xx_chip_data *c = lp->data;
573 bool force = false;
574 ktime_t tim;
575
576 /* The force state changes are will show as normal states in the
577 * state status subregister. We change the to_state to the
578 * corresponding one and remember if it was a force change, this
579 * differs if we do a state change from STATE_BUSY_RX_AACK.
580 */
581 switch (ctx->to_state) {
582 case STATE_FORCE_TX_ON:
583 ctx->to_state = STATE_TX_ON;
584 force = true;
585 break;
586 case STATE_FORCE_TRX_OFF:
587 ctx->to_state = STATE_TRX_OFF;
588 force = true;
589 break;
590 default:
591 break;
592 }
593
594 switch (ctx->from_state) {
595 case STATE_TRX_OFF:
596 switch (ctx->to_state) {
597 case STATE_RX_AACK_ON:
598 tim = ktime_set(0, c->t_off_to_aack * NSEC_PER_USEC);
599 goto change;
600 case STATE_TX_ON:
601 tim = ktime_set(0, c->t_off_to_tx_on * NSEC_PER_USEC);
602 goto change;
603 default:
604 break;
605 }
606 break;
607 case STATE_BUSY_RX_AACK:
608 switch (ctx->to_state) {
609 case STATE_TX_ON:
610 /* Wait for worst case receiving time if we
611 * didn't make a force change from BUSY_RX_AACK
612 * to TX_ON.
613 */
614 if (!force) {
615 tim = ktime_set(0, (c->t_frame + c->t_p_ack) *
616 NSEC_PER_USEC);
617 goto change;
618 }
619 break;
620 default:
621 break;
622 }
623 break;
624 /* Default value, means RESET state */
625 case STATE_P_ON:
626 switch (ctx->to_state) {
627 case STATE_TRX_OFF:
628 tim = ktime_set(0, c->t_reset_to_off * NSEC_PER_USEC);
629 goto change;
630 default:
631 break;
632 }
633 break;
634 default:
635 break;
636 }
637
638 /* Default delay is 1us in the most cases */
639 tim = ktime_set(0, NSEC_PER_USEC);
640
641 change:
642 hrtimer_start(&ctx->timer, tim, HRTIMER_MODE_REL);
643 }
644
645 static void
646 at86rf230_async_state_change_start(void *context)
647 {
648 struct at86rf230_state_change *ctx = context;
649 struct at86rf230_local *lp = ctx->lp;
650 u8 *buf = ctx->buf;
651 const u8 trx_state = buf[1] & 0x1f;
652 int rc;
653
654 /* Check for "possible" STATE_TRANSITION_IN_PROGRESS */
655 if (trx_state == STATE_TRANSITION_IN_PROGRESS) {
656 udelay(1);
657 at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
658 at86rf230_async_state_change_start,
659 ctx->irq_enable);
660 return;
661 }
662
663 /* Check if we already are in the state which we change in */
664 if (trx_state == ctx->to_state) {
665 if (ctx->complete)
666 ctx->complete(context);
667 return;
668 }
669
670 /* Set current state to the context of state change */
671 ctx->from_state = trx_state;
672
673 /* Going into the next step for a state change which do a timing
674 * relevant delay.
675 */
676 buf[0] = (RG_TRX_STATE & CMD_REG_MASK) | CMD_REG | CMD_WRITE;
677 buf[1] = ctx->to_state;
678 ctx->msg.complete = at86rf230_async_state_delay;
679 rc = spi_async(lp->spi, &ctx->msg);
680 if (rc) {
681 if (ctx->irq_enable)
682 enable_irq(ctx->irq);
683
684 at86rf230_async_error(lp, ctx, rc);
685 }
686 }
687
688 static void
689 at86rf230_async_state_change(struct at86rf230_local *lp,
690 struct at86rf230_state_change *ctx,
691 const u8 state, void (*complete)(void *context),
692 const bool irq_enable)
693 {
694 /* Initialization for the state change context */
695 ctx->to_state = state;
696 ctx->complete = complete;
697 ctx->irq_enable = irq_enable;
698 at86rf230_async_read_reg(lp, RG_TRX_STATUS, ctx,
699 at86rf230_async_state_change_start,
700 irq_enable);
701 }
702
703 static void
704 at86rf230_sync_state_change_complete(void *context)
705 {
706 struct at86rf230_state_change *ctx = context;
707 struct at86rf230_local *lp = ctx->lp;
708
709 complete(&lp->state_complete);
710 }
711
712 /* This function do a sync framework above the async state change.
713 * Some callbacks of the IEEE 802.15.4 driver interface need to be
714 * handled synchronously.
715 */
716 static int
717 at86rf230_sync_state_change(struct at86rf230_local *lp, unsigned int state)
718 {
719 unsigned long rc;
720
721 at86rf230_async_state_change(lp, &lp->state, state,
722 at86rf230_sync_state_change_complete,
723 false);
724
725 rc = wait_for_completion_timeout(&lp->state_complete,
726 msecs_to_jiffies(100));
727 if (!rc) {
728 at86rf230_async_error(lp, &lp->state, -ETIMEDOUT);
729 return -ETIMEDOUT;
730 }
731
732 return 0;
733 }
734
735 static void
736 at86rf230_tx_complete(void *context)
737 {
738 struct at86rf230_state_change *ctx = context;
739 struct at86rf230_local *lp = ctx->lp;
740
741 enable_irq(ctx->irq);
742
743 ieee802154_xmit_complete(lp->hw, lp->tx_skb, !lp->tx_aret);
744 }
745
746 static void
747 at86rf230_tx_on(void *context)
748 {
749 struct at86rf230_state_change *ctx = context;
750 struct at86rf230_local *lp = ctx->lp;
751
752 at86rf230_async_state_change(lp, ctx, STATE_RX_AACK_ON,
753 at86rf230_tx_complete, true);
754 }
755
756 static void
757 at86rf230_tx_trac_error(void *context)
758 {
759 struct at86rf230_state_change *ctx = context;
760 struct at86rf230_local *lp = ctx->lp;
761
762 at86rf230_async_state_change(lp, ctx, STATE_TX_ON,
763 at86rf230_tx_on, true);
764 }
765
766 static void
767 at86rf230_tx_trac_check(void *context)
768 {
769 struct at86rf230_state_change *ctx = context;
770 struct at86rf230_local *lp = ctx->lp;
771 const u8 *buf = ctx->buf;
772 const u8 trac = (buf[1] & 0xe0) >> 5;
773
774 /* If trac status is different than zero we need to do a state change
775 * to STATE_FORCE_TRX_OFF then STATE_TX_ON to recover the transceiver
776 * state to TX_ON.
777 */
778 if (trac)
779 at86rf230_async_state_change(lp, ctx, STATE_FORCE_TRX_OFF,
780 at86rf230_tx_trac_error, true);
781 else
782 at86rf230_tx_on(context);
783 }
784
785 static void
786 at86rf230_tx_trac_status(void *context)
787 {
788 struct at86rf230_state_change *ctx = context;
789 struct at86rf230_local *lp = ctx->lp;
790
791 at86rf230_async_read_reg(lp, RG_TRX_STATE, ctx,
792 at86rf230_tx_trac_check, true);
793 }
794
795 static void
796 at86rf230_rx_read_frame_complete(void *context)
797 {
798 struct at86rf230_state_change *ctx = context;
799 struct at86rf230_local *lp = ctx->lp;
800 u8 rx_local_buf[AT86RF2XX_MAX_BUF];
801 const u8 *buf = ctx->buf;
802 struct sk_buff *skb;
803 u8 len, lqi;
804
805 len = buf[1];
806 if (!ieee802154_is_valid_psdu_len(len)) {
807 dev_vdbg(&lp->spi->dev, "corrupted frame received\n");
808 len = IEEE802154_MTU;
809 }
810 lqi = buf[2 + len];
811
812 memcpy(rx_local_buf, buf + 2, len);
813 ctx->trx.len = 2;
814 enable_irq(ctx->irq);
815
816 skb = dev_alloc_skb(IEEE802154_MTU);
817 if (!skb) {
818 dev_vdbg(&lp->spi->dev, "failed to allocate sk_buff\n");
819 return;
820 }
821
822 memcpy(skb_put(skb, len), rx_local_buf, len);
823 ieee802154_rx_irqsafe(lp->hw, skb, lqi);
824 }
825
826 static void
827 at86rf230_rx_read_frame(void *context)
828 {
829 struct at86rf230_state_change *ctx = context;
830 struct at86rf230_local *lp = ctx->lp;
831 u8 *buf = ctx->buf;
832 int rc;
833
834 buf[0] = CMD_FB;
835 ctx->trx.len = AT86RF2XX_MAX_BUF;
836 ctx->msg.complete = at86rf230_rx_read_frame_complete;
837 rc = spi_async(lp->spi, &ctx->msg);
838 if (rc) {
839 ctx->trx.len = 2;
840 enable_irq(ctx->irq);
841 at86rf230_async_error(lp, ctx, rc);
842 }
843 }
844
845 static void
846 at86rf230_rx_trac_check(void *context)
847 {
848 /* Possible check on trac status here. This could be useful to make
849 * some stats why receive is failed. Not used at the moment, but it's
850 * maybe timing relevant. Datasheet doesn't say anything about this.
851 * The programming guide say do it so.
852 */
853
854 at86rf230_rx_read_frame(context);
855 }
856
857 static void
858 at86rf230_irq_trx_end(struct at86rf230_local *lp)
859 {
860 spin_lock(&lp->lock);
861 if (lp->is_tx) {
862 lp->is_tx = 0;
863 spin_unlock(&lp->lock);
864
865 if (lp->tx_aret)
866 at86rf230_async_state_change(lp, &lp->irq,
867 STATE_FORCE_TX_ON,
868 at86rf230_tx_trac_status,
869 true);
870 else
871 at86rf230_async_state_change(lp, &lp->irq,
872 STATE_RX_AACK_ON,
873 at86rf230_tx_complete,
874 true);
875 } else {
876 spin_unlock(&lp->lock);
877 at86rf230_async_read_reg(lp, RG_TRX_STATE, &lp->irq,
878 at86rf230_rx_trac_check, true);
879 }
880 }
881
882 static void
883 at86rf230_irq_status(void *context)
884 {
885 struct at86rf230_state_change *ctx = context;
886 struct at86rf230_local *lp = ctx->lp;
887 const u8 *buf = ctx->buf;
888 const u8 irq = buf[1];
889
890 if (irq & IRQ_TRX_END) {
891 at86rf230_irq_trx_end(lp);
892 } else {
893 enable_irq(ctx->irq);
894 dev_err(&lp->spi->dev, "not supported irq %02x received\n",
895 irq);
896 }
897 }
898
899 static irqreturn_t at86rf230_isr(int irq, void *data)
900 {
901 struct at86rf230_local *lp = data;
902 struct at86rf230_state_change *ctx = &lp->irq;
903 u8 *buf = ctx->buf;
904 int rc;
905
906 disable_irq_nosync(irq);
907
908 buf[0] = (RG_IRQ_STATUS & CMD_REG_MASK) | CMD_REG;
909 ctx->msg.complete = at86rf230_irq_status;
910 rc = spi_async(lp->spi, &ctx->msg);
911 if (rc) {
912 enable_irq(irq);
913 at86rf230_async_error(lp, ctx, rc);
914 return IRQ_NONE;
915 }
916
917 return IRQ_HANDLED;
918 }
919
920 static void
921 at86rf230_write_frame_complete(void *context)
922 {
923 struct at86rf230_state_change *ctx = context;
924 struct at86rf230_local *lp = ctx->lp;
925 u8 *buf = ctx->buf;
926 int rc;
927
928 buf[0] = (RG_TRX_STATE & CMD_REG_MASK) | CMD_REG | CMD_WRITE;
929 buf[1] = STATE_BUSY_TX;
930 ctx->trx.len = 2;
931 ctx->msg.complete = NULL;
932 rc = spi_async(lp->spi, &ctx->msg);
933 if (rc)
934 at86rf230_async_error(lp, ctx, rc);
935 }
936
937 static void
938 at86rf230_write_frame(void *context)
939 {
940 struct at86rf230_state_change *ctx = context;
941 struct at86rf230_local *lp = ctx->lp;
942 struct sk_buff *skb = lp->tx_skb;
943 u8 *buf = ctx->buf;
944 int rc;
945
946 spin_lock(&lp->lock);
947 lp->is_tx = 1;
948 spin_unlock(&lp->lock);
949
950 buf[0] = CMD_FB | CMD_WRITE;
951 buf[1] = skb->len + 2;
952 memcpy(buf + 2, skb->data, skb->len);
953 ctx->trx.len = skb->len + 2;
954 ctx->msg.complete = at86rf230_write_frame_complete;
955 rc = spi_async(lp->spi, &ctx->msg);
956 if (rc) {
957 ctx->trx.len = 2;
958 at86rf230_async_error(lp, ctx, rc);
959 }
960 }
961
962 static void
963 at86rf230_xmit_tx_on(void *context)
964 {
965 struct at86rf230_state_change *ctx = context;
966 struct at86rf230_local *lp = ctx->lp;
967
968 at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON,
969 at86rf230_write_frame, false);
970 }
971
972 static int
973 at86rf230_xmit(struct ieee802154_hw *hw, struct sk_buff *skb)
974 {
975 struct at86rf230_local *lp = hw->priv;
976 struct at86rf230_state_change *ctx = &lp->tx;
977
978 void (*tx_complete)(void *context) = at86rf230_write_frame;
979
980 lp->tx_skb = skb;
981
982 /* In ARET mode we need to go into STATE_TX_ARET_ON after we
983 * are in STATE_TX_ON. The pfad differs here, so we change
984 * the complete handler.
985 */
986 if (lp->tx_aret)
987 tx_complete = at86rf230_xmit_tx_on;
988
989 lp->tx_retry = 0;
990 at86rf230_async_state_change(lp, ctx, STATE_TX_ON, tx_complete, false);
991
992 return 0;
993 }
994
995 static int
996 at86rf230_ed(struct ieee802154_hw *hw, u8 *level)
997 {
998 BUG_ON(!level);
999 *level = 0xbe;
1000 return 0;
1001 }
1002
1003 static int
1004 at86rf230_start(struct ieee802154_hw *hw)
1005 {
1006 return at86rf230_sync_state_change(hw->priv, STATE_RX_AACK_ON);
1007 }
1008
1009 static void
1010 at86rf230_stop(struct ieee802154_hw *hw)
1011 {
1012 at86rf230_sync_state_change(hw->priv, STATE_FORCE_TRX_OFF);
1013 }
1014
1015 static int
1016 at86rf23x_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
1017 {
1018 return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
1019 }
1020
1021 static int
1022 at86rf212_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
1023 {
1024 int rc;
1025
1026 if (channel == 0)
1027 rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 0);
1028 else
1029 rc = at86rf230_write_subreg(lp, SR_SUB_MODE, 1);
1030 if (rc < 0)
1031 return rc;
1032
1033 if (page == 0) {
1034 rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 0);
1035 lp->data->rssi_base_val = -100;
1036 } else {
1037 rc = at86rf230_write_subreg(lp, SR_BPSK_QPSK, 1);
1038 lp->data->rssi_base_val = -98;
1039 }
1040 if (rc < 0)
1041 return rc;
1042
1043 /* This sets the symbol_duration according frequency on the 212.
1044 * TODO move this handling while set channel and page in cfg802154.
1045 * We can do that, this timings are according 802.15.4 standard.
1046 * If we do that in cfg802154, this is a more generic calculation.
1047 *
1048 * This should also protected from ifs_timer. Means cancel timer and
1049 * init with a new value. For now, this is okay.
1050 */
1051 if (channel == 0) {
1052 if (page == 0) {
1053 /* SUB:0 and BPSK:0 -> BPSK-20 */
1054 lp->hw->phy->symbol_duration = 50;
1055 } else {
1056 /* SUB:1 and BPSK:0 -> BPSK-40 */
1057 lp->hw->phy->symbol_duration = 25;
1058 }
1059 } else {
1060 if (page == 0)
1061 /* SUB:0 and BPSK:1 -> OQPSK-100/200/400 */
1062 lp->hw->phy->symbol_duration = 40;
1063 else
1064 /* SUB:1 and BPSK:1 -> OQPSK-250/500/1000 */
1065 lp->hw->phy->symbol_duration = 16;
1066 }
1067
1068 lp->hw->phy->lifs_period = IEEE802154_LIFS_PERIOD *
1069 lp->hw->phy->symbol_duration;
1070 lp->hw->phy->sifs_period = IEEE802154_SIFS_PERIOD *
1071 lp->hw->phy->symbol_duration;
1072
1073 return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
1074 }
1075
1076 static int
1077 at86rf230_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
1078 {
1079 struct at86rf230_local *lp = hw->priv;
1080 int rc;
1081
1082 rc = lp->data->set_channel(lp, page, channel);
1083 /* Wait for PLL */
1084 usleep_range(lp->data->t_channel_switch,
1085 lp->data->t_channel_switch + 10);
1086 return rc;
1087 }
1088
1089 static int
1090 at86rf230_set_hw_addr_filt(struct ieee802154_hw *hw,
1091 struct ieee802154_hw_addr_filt *filt,
1092 unsigned long changed)
1093 {
1094 struct at86rf230_local *lp = hw->priv;
1095
1096 if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
1097 u16 addr = le16_to_cpu(filt->short_addr);
1098
1099 dev_vdbg(&lp->spi->dev,
1100 "at86rf230_set_hw_addr_filt called for saddr\n");
1101 __at86rf230_write(lp, RG_SHORT_ADDR_0, addr);
1102 __at86rf230_write(lp, RG_SHORT_ADDR_1, addr >> 8);
1103 }
1104
1105 if (changed & IEEE802154_AFILT_PANID_CHANGED) {
1106 u16 pan = le16_to_cpu(filt->pan_id);
1107
1108 dev_vdbg(&lp->spi->dev,
1109 "at86rf230_set_hw_addr_filt called for pan id\n");
1110 __at86rf230_write(lp, RG_PAN_ID_0, pan);
1111 __at86rf230_write(lp, RG_PAN_ID_1, pan >> 8);
1112 }
1113
1114 if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
1115 u8 i, addr[8];
1116
1117 memcpy(addr, &filt->ieee_addr, 8);
1118 dev_vdbg(&lp->spi->dev,
1119 "at86rf230_set_hw_addr_filt called for IEEE addr\n");
1120 for (i = 0; i < 8; i++)
1121 __at86rf230_write(lp, RG_IEEE_ADDR_0 + i, addr[i]);
1122 }
1123
1124 if (changed & IEEE802154_AFILT_PANC_CHANGED) {
1125 dev_vdbg(&lp->spi->dev,
1126 "at86rf230_set_hw_addr_filt called for panc change\n");
1127 if (filt->pan_coord)
1128 at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 1);
1129 else
1130 at86rf230_write_subreg(lp, SR_AACK_I_AM_COORD, 0);
1131 }
1132
1133 return 0;
1134 }
1135
1136 static int
1137 at86rf230_set_txpower(struct ieee802154_hw *hw, int db)
1138 {
1139 struct at86rf230_local *lp = hw->priv;
1140
1141 /* typical maximum output is 5dBm with RG_PHY_TX_PWR 0x60, lower five
1142 * bits decrease power in 1dB steps. 0x60 represents extra PA gain of
1143 * 0dB.
1144 * thus, supported values for db range from -26 to 5, for 31dB of
1145 * reduction to 0dB of reduction.
1146 */
1147 if (db > 5 || db < -26)
1148 return -EINVAL;
1149
1150 db = -(db - 5);
1151
1152 return __at86rf230_write(lp, RG_PHY_TX_PWR, 0x60 | db);
1153 }
1154
1155 static int
1156 at86rf230_set_lbt(struct ieee802154_hw *hw, bool on)
1157 {
1158 struct at86rf230_local *lp = hw->priv;
1159
1160 return at86rf230_write_subreg(lp, SR_CSMA_LBT_MODE, on);
1161 }
1162
1163 static int
1164 at86rf230_set_cca_mode(struct ieee802154_hw *hw,
1165 const struct wpan_phy_cca *cca)
1166 {
1167 struct at86rf230_local *lp = hw->priv;
1168 u8 val;
1169
1170 /* mapping 802.15.4 to driver spec */
1171 switch (cca->mode) {
1172 case NL802154_CCA_ENERGY:
1173 val = 1;
1174 break;
1175 case NL802154_CCA_CARRIER:
1176 val = 2;
1177 break;
1178 case NL802154_CCA_ENERGY_CARRIER:
1179 switch (cca->opt) {
1180 case NL802154_CCA_OPT_ENERGY_CARRIER_AND:
1181 val = 3;
1182 break;
1183 case NL802154_CCA_OPT_ENERGY_CARRIER_OR:
1184 val = 0;
1185 break;
1186 default:
1187 return -EINVAL;
1188 }
1189 break;
1190 default:
1191 return -EINVAL;
1192 }
1193
1194 return at86rf230_write_subreg(lp, SR_CCA_MODE, val);
1195 }
1196
1197 static int
1198 at86rf212_get_desens_steps(struct at86rf230_local *lp, s32 level)
1199 {
1200 return (level - lp->data->rssi_base_val) * 100 / 207;
1201 }
1202
1203 static int
1204 at86rf23x_get_desens_steps(struct at86rf230_local *lp, s32 level)
1205 {
1206 return (level - lp->data->rssi_base_val) / 2;
1207 }
1208
1209 static int
1210 at86rf230_set_cca_ed_level(struct ieee802154_hw *hw, s32 level)
1211 {
1212 struct at86rf230_local *lp = hw->priv;
1213
1214 if (level < lp->data->rssi_base_val || level > 30)
1215 return -EINVAL;
1216
1217 return at86rf230_write_subreg(lp, SR_CCA_ED_THRES,
1218 lp->data->get_desense_steps(lp, level));
1219 }
1220
1221 static int
1222 at86rf230_set_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be,
1223 u8 retries)
1224 {
1225 struct at86rf230_local *lp = hw->priv;
1226 int rc;
1227
1228 rc = at86rf230_write_subreg(lp, SR_MIN_BE, min_be);
1229 if (rc)
1230 return rc;
1231
1232 rc = at86rf230_write_subreg(lp, SR_MAX_BE, max_be);
1233 if (rc)
1234 return rc;
1235
1236 return at86rf230_write_subreg(lp, SR_MAX_CSMA_RETRIES, retries);
1237 }
1238
1239 static int
1240 at86rf230_set_frame_retries(struct ieee802154_hw *hw, s8 retries)
1241 {
1242 struct at86rf230_local *lp = hw->priv;
1243 int rc = 0;
1244
1245 lp->tx_aret = retries >= 0;
1246 lp->max_frame_retries = retries;
1247
1248 if (retries >= 0)
1249 rc = at86rf230_write_subreg(lp, SR_MAX_FRAME_RETRIES, retries);
1250
1251 return rc;
1252 }
1253
1254 static int
1255 at86rf230_set_promiscuous_mode(struct ieee802154_hw *hw, const bool on)
1256 {
1257 struct at86rf230_local *lp = hw->priv;
1258 int rc;
1259
1260 if (on) {
1261 rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 1);
1262 if (rc < 0)
1263 return rc;
1264
1265 rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 1);
1266 if (rc < 0)
1267 return rc;
1268 } else {
1269 rc = at86rf230_write_subreg(lp, SR_AACK_PROM_MODE, 0);
1270 if (rc < 0)
1271 return rc;
1272
1273 rc = at86rf230_write_subreg(lp, SR_AACK_DIS_ACK, 0);
1274 if (rc < 0)
1275 return rc;
1276 }
1277
1278 return 0;
1279 }
1280
1281 static const struct ieee802154_ops at86rf230_ops = {
1282 .owner = THIS_MODULE,
1283 .xmit_async = at86rf230_xmit,
1284 .ed = at86rf230_ed,
1285 .set_channel = at86rf230_channel,
1286 .start = at86rf230_start,
1287 .stop = at86rf230_stop,
1288 .set_hw_addr_filt = at86rf230_set_hw_addr_filt,
1289 .set_txpower = at86rf230_set_txpower,
1290 .set_lbt = at86rf230_set_lbt,
1291 .set_cca_mode = at86rf230_set_cca_mode,
1292 .set_cca_ed_level = at86rf230_set_cca_ed_level,
1293 .set_csma_params = at86rf230_set_csma_params,
1294 .set_frame_retries = at86rf230_set_frame_retries,
1295 .set_promiscuous_mode = at86rf230_set_promiscuous_mode,
1296 };
1297
1298 static struct at86rf2xx_chip_data at86rf233_data = {
1299 .t_sleep_cycle = 330,
1300 .t_channel_switch = 11,
1301 .t_reset_to_off = 26,
1302 .t_off_to_aack = 80,
1303 .t_off_to_tx_on = 80,
1304 .t_frame = 4096,
1305 .t_p_ack = 545,
1306 .rssi_base_val = -91,
1307 .set_channel = at86rf23x_set_channel,
1308 .get_desense_steps = at86rf23x_get_desens_steps
1309 };
1310
1311 static struct at86rf2xx_chip_data at86rf231_data = {
1312 .t_sleep_cycle = 330,
1313 .t_channel_switch = 24,
1314 .t_reset_to_off = 37,
1315 .t_off_to_aack = 110,
1316 .t_off_to_tx_on = 110,
1317 .t_frame = 4096,
1318 .t_p_ack = 545,
1319 .rssi_base_val = -91,
1320 .set_channel = at86rf23x_set_channel,
1321 .get_desense_steps = at86rf23x_get_desens_steps
1322 };
1323
1324 static struct at86rf2xx_chip_data at86rf212_data = {
1325 .t_sleep_cycle = 330,
1326 .t_channel_switch = 11,
1327 .t_reset_to_off = 26,
1328 .t_off_to_aack = 200,
1329 .t_off_to_tx_on = 200,
1330 .t_frame = 4096,
1331 .t_p_ack = 545,
1332 .rssi_base_val = -100,
1333 .set_channel = at86rf212_set_channel,
1334 .get_desense_steps = at86rf212_get_desens_steps
1335 };
1336
1337 static int at86rf230_hw_init(struct at86rf230_local *lp, u8 xtal_trim)
1338 {
1339 int rc, irq_type, irq_pol = IRQ_ACTIVE_HIGH;
1340 unsigned int dvdd;
1341 u8 csma_seed[2];
1342
1343 rc = at86rf230_sync_state_change(lp, STATE_FORCE_TRX_OFF);
1344 if (rc)
1345 return rc;
1346
1347 irq_type = irq_get_trigger_type(lp->spi->irq);
1348 if (irq_type == IRQ_TYPE_EDGE_RISING ||
1349 irq_type == IRQ_TYPE_EDGE_FALLING)
1350 dev_warn(&lp->spi->dev,
1351 "Using edge triggered irq's are not recommended!\n");
1352 if (irq_type == IRQ_TYPE_EDGE_FALLING ||
1353 irq_type == IRQ_TYPE_LEVEL_LOW)
1354 irq_pol = IRQ_ACTIVE_LOW;
1355
1356 rc = at86rf230_write_subreg(lp, SR_IRQ_POLARITY, irq_pol);
1357 if (rc)
1358 return rc;
1359
1360 rc = at86rf230_write_subreg(lp, SR_RX_SAFE_MODE, 1);
1361 if (rc)
1362 return rc;
1363
1364 rc = at86rf230_write_subreg(lp, SR_IRQ_MASK, IRQ_TRX_END);
1365 if (rc)
1366 return rc;
1367
1368 /* reset values differs in at86rf231 and at86rf233 */
1369 rc = at86rf230_write_subreg(lp, SR_IRQ_MASK_MODE, 0);
1370 if (rc)
1371 return rc;
1372
1373 get_random_bytes(csma_seed, ARRAY_SIZE(csma_seed));
1374 rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_0, csma_seed[0]);
1375 if (rc)
1376 return rc;
1377 rc = at86rf230_write_subreg(lp, SR_CSMA_SEED_1, csma_seed[1]);
1378 if (rc)
1379 return rc;
1380
1381 /* CLKM changes are applied immediately */
1382 rc = at86rf230_write_subreg(lp, SR_CLKM_SHA_SEL, 0x00);
1383 if (rc)
1384 return rc;
1385
1386 /* Turn CLKM Off */
1387 rc = at86rf230_write_subreg(lp, SR_CLKM_CTRL, 0x00);
1388 if (rc)
1389 return rc;
1390 /* Wait the next SLEEP cycle */
1391 usleep_range(lp->data->t_sleep_cycle,
1392 lp->data->t_sleep_cycle + 100);
1393
1394 /* xtal_trim value is calculated by:
1395 * CL = 0.5 * (CX + CTRIM + CPAR)
1396 *
1397 * whereas:
1398 * CL = capacitor of used crystal
1399 * CX = connected capacitors at xtal pins
1400 * CPAR = in all at86rf2xx datasheets this is a constant value 3 pF,
1401 * but this is different on each board setup. You need to fine
1402 * tuning this value via CTRIM.
1403 * CTRIM = variable capacitor setting. Resolution is 0.3 pF range is
1404 * 0 pF upto 4.5 pF.
1405 *
1406 * Examples:
1407 * atben transceiver:
1408 *
1409 * CL = 8 pF
1410 * CX = 12 pF
1411 * CPAR = 3 pF (We assume the magic constant from datasheet)
1412 * CTRIM = 0.9 pF
1413 *
1414 * (12+0.9+3)/2 = 7.95 which is nearly at 8 pF
1415 *
1416 * xtal_trim = 0x3
1417 *
1418 * openlabs transceiver:
1419 *
1420 * CL = 16 pF
1421 * CX = 22 pF
1422 * CPAR = 3 pF (We assume the magic constant from datasheet)
1423 * CTRIM = 4.5 pF
1424 *
1425 * (22+4.5+3)/2 = 14.75 which is the nearest value to 16 pF
1426 *
1427 * xtal_trim = 0xf
1428 */
1429 rc = at86rf230_write_subreg(lp, SR_XTAL_TRIM, xtal_trim);
1430 if (rc)
1431 return rc;
1432
1433 rc = at86rf230_read_subreg(lp, SR_DVDD_OK, &dvdd);
1434 if (rc)
1435 return rc;
1436 if (!dvdd) {
1437 dev_err(&lp->spi->dev, "DVDD error\n");
1438 return -EINVAL;
1439 }
1440
1441 /* Force setting slotted operation bit to 0. Sometimes the atben
1442 * sets this bit and I don't know why. We set this always force
1443 * to zero while probing.
1444 */
1445 return at86rf230_write_subreg(lp, SR_SLOTTED_OPERATION, 0);
1446 }
1447
1448 static int
1449 at86rf230_get_pdata(struct spi_device *spi, int *rstn, int *slp_tr,
1450 u8 *xtal_trim)
1451 {
1452 struct at86rf230_platform_data *pdata = spi->dev.platform_data;
1453 int ret;
1454
1455 if (!IS_ENABLED(CONFIG_OF) || !spi->dev.of_node) {
1456 if (!pdata)
1457 return -ENOENT;
1458
1459 *rstn = pdata->rstn;
1460 *slp_tr = pdata->slp_tr;
1461 *xtal_trim = pdata->xtal_trim;
1462 return 0;
1463 }
1464
1465 *rstn = of_get_named_gpio(spi->dev.of_node, "reset-gpio", 0);
1466 *slp_tr = of_get_named_gpio(spi->dev.of_node, "sleep-gpio", 0);
1467 ret = of_property_read_u8(spi->dev.of_node, "xtal-trim", xtal_trim);
1468 if (ret < 0 && ret != -EINVAL)
1469 return ret;
1470
1471 return 0;
1472 }
1473
1474 static int
1475 at86rf230_detect_device(struct at86rf230_local *lp)
1476 {
1477 unsigned int part, version, val;
1478 u16 man_id = 0;
1479 const char *chip;
1480 int rc;
1481
1482 rc = __at86rf230_read(lp, RG_MAN_ID_0, &val);
1483 if (rc)
1484 return rc;
1485 man_id |= val;
1486
1487 rc = __at86rf230_read(lp, RG_MAN_ID_1, &val);
1488 if (rc)
1489 return rc;
1490 man_id |= (val << 8);
1491
1492 rc = __at86rf230_read(lp, RG_PART_NUM, &part);
1493 if (rc)
1494 return rc;
1495
1496 rc = __at86rf230_read(lp, RG_VERSION_NUM, &version);
1497 if (rc)
1498 return rc;
1499
1500 if (man_id != 0x001f) {
1501 dev_err(&lp->spi->dev, "Non-Atmel dev found (MAN_ID %02x %02x)\n",
1502 man_id >> 8, man_id & 0xFF);
1503 return -EINVAL;
1504 }
1505
1506 lp->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AACK |
1507 IEEE802154_HW_TXPOWER | IEEE802154_HW_ARET |
1508 IEEE802154_HW_AFILT | IEEE802154_HW_PROMISCUOUS;
1509
1510 lp->hw->phy->cca.mode = NL802154_CCA_ENERGY;
1511
1512 switch (part) {
1513 case 2:
1514 chip = "at86rf230";
1515 rc = -ENOTSUPP;
1516 break;
1517 case 3:
1518 chip = "at86rf231";
1519 lp->data = &at86rf231_data;
1520 lp->hw->phy->channels_supported[0] = 0x7FFF800;
1521 lp->hw->phy->current_channel = 11;
1522 lp->hw->phy->symbol_duration = 16;
1523 break;
1524 case 7:
1525 chip = "at86rf212";
1526 lp->data = &at86rf212_data;
1527 lp->hw->flags |= IEEE802154_HW_LBT;
1528 lp->hw->phy->channels_supported[0] = 0x00007FF;
1529 lp->hw->phy->channels_supported[2] = 0x00007FF;
1530 lp->hw->phy->current_channel = 5;
1531 lp->hw->phy->symbol_duration = 25;
1532 break;
1533 case 11:
1534 chip = "at86rf233";
1535 lp->data = &at86rf233_data;
1536 lp->hw->phy->channels_supported[0] = 0x7FFF800;
1537 lp->hw->phy->current_channel = 13;
1538 lp->hw->phy->symbol_duration = 16;
1539 break;
1540 default:
1541 chip = "unknown";
1542 rc = -ENOTSUPP;
1543 break;
1544 }
1545
1546 dev_info(&lp->spi->dev, "Detected %s chip version %d\n", chip, version);
1547
1548 return rc;
1549 }
1550
1551 static void
1552 at86rf230_setup_spi_messages(struct at86rf230_local *lp)
1553 {
1554 lp->state.lp = lp;
1555 lp->state.irq = lp->spi->irq;
1556 spi_message_init(&lp->state.msg);
1557 lp->state.msg.context = &lp->state;
1558 lp->state.trx.len = 2;
1559 lp->state.trx.tx_buf = lp->state.buf;
1560 lp->state.trx.rx_buf = lp->state.buf;
1561 spi_message_add_tail(&lp->state.trx, &lp->state.msg);
1562 hrtimer_init(&lp->state.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1563 lp->state.timer.function = at86rf230_async_state_timer;
1564
1565 lp->irq.lp = lp;
1566 lp->irq.irq = lp->spi->irq;
1567 spi_message_init(&lp->irq.msg);
1568 lp->irq.msg.context = &lp->irq;
1569 lp->irq.trx.len = 2;
1570 lp->irq.trx.tx_buf = lp->irq.buf;
1571 lp->irq.trx.rx_buf = lp->irq.buf;
1572 spi_message_add_tail(&lp->irq.trx, &lp->irq.msg);
1573 hrtimer_init(&lp->irq.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1574 lp->irq.timer.function = at86rf230_async_state_timer;
1575
1576 lp->tx.lp = lp;
1577 lp->tx.irq = lp->spi->irq;
1578 spi_message_init(&lp->tx.msg);
1579 lp->tx.msg.context = &lp->tx;
1580 lp->tx.trx.len = 2;
1581 lp->tx.trx.tx_buf = lp->tx.buf;
1582 lp->tx.trx.rx_buf = lp->tx.buf;
1583 spi_message_add_tail(&lp->tx.trx, &lp->tx.msg);
1584 hrtimer_init(&lp->tx.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1585 lp->tx.timer.function = at86rf230_async_state_timer;
1586 }
1587
1588 static int at86rf230_probe(struct spi_device *spi)
1589 {
1590 struct ieee802154_hw *hw;
1591 struct at86rf230_local *lp;
1592 unsigned int status;
1593 int rc, irq_type, rstn, slp_tr;
1594 u8 xtal_trim = 0;
1595
1596 if (!spi->irq) {
1597 dev_err(&spi->dev, "no IRQ specified\n");
1598 return -EINVAL;
1599 }
1600
1601 rc = at86rf230_get_pdata(spi, &rstn, &slp_tr, &xtal_trim);
1602 if (rc < 0) {
1603 dev_err(&spi->dev, "failed to parse platform_data: %d\n", rc);
1604 return rc;
1605 }
1606
1607 if (gpio_is_valid(rstn)) {
1608 rc = devm_gpio_request_one(&spi->dev, rstn,
1609 GPIOF_OUT_INIT_HIGH, "rstn");
1610 if (rc)
1611 return rc;
1612 }
1613
1614 if (gpio_is_valid(slp_tr)) {
1615 rc = devm_gpio_request_one(&spi->dev, slp_tr,
1616 GPIOF_OUT_INIT_LOW, "slp_tr");
1617 if (rc)
1618 return rc;
1619 }
1620
1621 /* Reset */
1622 if (gpio_is_valid(rstn)) {
1623 udelay(1);
1624 gpio_set_value(rstn, 0);
1625 udelay(1);
1626 gpio_set_value(rstn, 1);
1627 usleep_range(120, 240);
1628 }
1629
1630 hw = ieee802154_alloc_hw(sizeof(*lp), &at86rf230_ops);
1631 if (!hw)
1632 return -ENOMEM;
1633
1634 lp = hw->priv;
1635 lp->hw = hw;
1636 lp->spi = spi;
1637 hw->parent = &spi->dev;
1638 hw->vif_data_size = sizeof(*lp);
1639 ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
1640
1641 lp->regmap = devm_regmap_init_spi(spi, &at86rf230_regmap_spi_config);
1642 if (IS_ERR(lp->regmap)) {
1643 rc = PTR_ERR(lp->regmap);
1644 dev_err(&spi->dev, "Failed to allocate register map: %d\n",
1645 rc);
1646 goto free_dev;
1647 }
1648
1649 at86rf230_setup_spi_messages(lp);
1650
1651 rc = at86rf230_detect_device(lp);
1652 if (rc < 0)
1653 goto free_dev;
1654
1655 spin_lock_init(&lp->lock);
1656 init_completion(&lp->state_complete);
1657
1658 spi_set_drvdata(spi, lp);
1659
1660 rc = at86rf230_hw_init(lp, xtal_trim);
1661 if (rc)
1662 goto free_dev;
1663
1664 /* Read irq status register to reset irq line */
1665 rc = at86rf230_read_subreg(lp, RG_IRQ_STATUS, 0xff, 0, &status);
1666 if (rc)
1667 goto free_dev;
1668
1669 irq_type = irq_get_trigger_type(spi->irq);
1670 if (!irq_type)
1671 irq_type = IRQF_TRIGGER_RISING;
1672
1673 rc = devm_request_irq(&spi->dev, spi->irq, at86rf230_isr,
1674 IRQF_SHARED | irq_type, dev_name(&spi->dev), lp);
1675 if (rc)
1676 goto free_dev;
1677
1678 rc = ieee802154_register_hw(lp->hw);
1679 if (rc)
1680 goto free_dev;
1681
1682 return rc;
1683
1684 free_dev:
1685 ieee802154_free_hw(lp->hw);
1686
1687 return rc;
1688 }
1689
1690 static int at86rf230_remove(struct spi_device *spi)
1691 {
1692 struct at86rf230_local *lp = spi_get_drvdata(spi);
1693
1694 /* mask all at86rf230 irq's */
1695 at86rf230_write_subreg(lp, SR_IRQ_MASK, 0);
1696 ieee802154_unregister_hw(lp->hw);
1697 ieee802154_free_hw(lp->hw);
1698 dev_dbg(&spi->dev, "unregistered at86rf230\n");
1699
1700 return 0;
1701 }
1702
1703 static const struct of_device_id at86rf230_of_match[] = {
1704 { .compatible = "atmel,at86rf230", },
1705 { .compatible = "atmel,at86rf231", },
1706 { .compatible = "atmel,at86rf233", },
1707 { .compatible = "atmel,at86rf212", },
1708 { },
1709 };
1710 MODULE_DEVICE_TABLE(of, at86rf230_of_match);
1711
1712 static const struct spi_device_id at86rf230_device_id[] = {
1713 { .name = "at86rf230", },
1714 { .name = "at86rf231", },
1715 { .name = "at86rf233", },
1716 { .name = "at86rf212", },
1717 { },
1718 };
1719 MODULE_DEVICE_TABLE(spi, at86rf230_device_id);
1720
1721 static struct spi_driver at86rf230_driver = {
1722 .id_table = at86rf230_device_id,
1723 .driver = {
1724 .of_match_table = of_match_ptr(at86rf230_of_match),
1725 .name = "at86rf230",
1726 .owner = THIS_MODULE,
1727 },
1728 .probe = at86rf230_probe,
1729 .remove = at86rf230_remove,
1730 };
1731
1732 module_spi_driver(at86rf230_driver);
1733
1734 MODULE_DESCRIPTION("AT86RF230 Transceiver Driver");
1735 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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