1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/if_ether.h>
35 #include "e1000_mac.h"
36 #include "e1000_82575.h"
38 static s32
igb_get_invariants_82575(struct e1000_hw
*);
39 static s32
igb_acquire_phy_82575(struct e1000_hw
*);
40 static void igb_release_phy_82575(struct e1000_hw
*);
41 static s32
igb_acquire_nvm_82575(struct e1000_hw
*);
42 static void igb_release_nvm_82575(struct e1000_hw
*);
43 static s32
igb_check_for_link_82575(struct e1000_hw
*);
44 static s32
igb_get_cfg_done_82575(struct e1000_hw
*);
45 static s32
igb_init_hw_82575(struct e1000_hw
*);
46 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*);
47 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
*);
48 static s32
igb_read_phy_reg_82580(struct e1000_hw
*, u32
, u16
*);
49 static s32
igb_write_phy_reg_82580(struct e1000_hw
*, u32
, u16
);
50 static s32
igb_reset_hw_82575(struct e1000_hw
*);
51 static s32
igb_reset_hw_82580(struct e1000_hw
*);
52 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*, bool);
53 static s32
igb_setup_copper_link_82575(struct e1000_hw
*);
54 static s32
igb_setup_serdes_link_82575(struct e1000_hw
*);
55 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
);
56 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*);
57 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*, u16
);
58 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*, u16
*,
60 static s32
igb_get_phy_id_82575(struct e1000_hw
*);
61 static void igb_release_swfw_sync_82575(struct e1000_hw
*, u16
);
62 static bool igb_sgmii_active_82575(struct e1000_hw
*);
63 static s32
igb_reset_init_script_82575(struct e1000_hw
*);
64 static s32
igb_read_mac_addr_82575(struct e1000_hw
*);
65 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
);
67 static const u16 e1000_82580_rxpbs_table
[] =
68 { 36, 72, 144, 1, 2, 4, 8, 16,
70 #define E1000_82580_RXPBS_TABLE_SIZE \
71 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
73 static s32
igb_get_invariants_82575(struct e1000_hw
*hw
)
75 struct e1000_phy_info
*phy
= &hw
->phy
;
76 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
77 struct e1000_mac_info
*mac
= &hw
->mac
;
78 struct e1000_dev_spec_82575
* dev_spec
= &hw
->dev_spec
._82575
;
84 switch (hw
->device_id
) {
85 case E1000_DEV_ID_82575EB_COPPER
:
86 case E1000_DEV_ID_82575EB_FIBER_SERDES
:
87 case E1000_DEV_ID_82575GB_QUAD_COPPER
:
88 mac
->type
= e1000_82575
;
90 case E1000_DEV_ID_82576
:
91 case E1000_DEV_ID_82576_NS
:
92 case E1000_DEV_ID_82576_NS_SERDES
:
93 case E1000_DEV_ID_82576_FIBER
:
94 case E1000_DEV_ID_82576_SERDES
:
95 case E1000_DEV_ID_82576_QUAD_COPPER
:
96 case E1000_DEV_ID_82576_QUAD_COPPER_ET2
:
97 case E1000_DEV_ID_82576_SERDES_QUAD
:
98 mac
->type
= e1000_82576
;
100 case E1000_DEV_ID_82580_COPPER
:
101 case E1000_DEV_ID_82580_FIBER
:
102 case E1000_DEV_ID_82580_SERDES
:
103 case E1000_DEV_ID_82580_SGMII
:
104 case E1000_DEV_ID_82580_COPPER_DUAL
:
105 mac
->type
= e1000_82580
;
107 case E1000_DEV_ID_I350_COPPER
:
108 case E1000_DEV_ID_I350_FIBER
:
109 case E1000_DEV_ID_I350_SERDES
:
110 case E1000_DEV_ID_I350_SGMII
:
111 mac
->type
= e1000_i350
;
114 return -E1000_ERR_MAC_INIT
;
120 * The 82575 uses bits 22:23 for link mode. The mode can be changed
121 * based on the EEPROM. We cannot rely upon device ID. There
122 * is no distinguishable difference between fiber and internal
123 * SerDes mode on the 82575. There can be an external PHY attached
124 * on the SGMII interface. For this, we'll set sgmii_active to true.
126 phy
->media_type
= e1000_media_type_copper
;
127 dev_spec
->sgmii_active
= false;
129 ctrl_ext
= rd32(E1000_CTRL_EXT
);
130 switch (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) {
131 case E1000_CTRL_EXT_LINK_MODE_SGMII
:
132 dev_spec
->sgmii_active
= true;
133 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
135 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
:
136 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES
:
137 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
138 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
141 ctrl_ext
&= ~E1000_CTRL_I2C_ENA
;
145 wr32(E1000_CTRL_EXT
, ctrl_ext
);
148 * if using i2c make certain the MDICNFG register is cleared to prevent
149 * communications from being misrouted to the mdic registers
151 if ((ctrl_ext
& E1000_CTRL_I2C_ENA
) && (hw
->mac
.type
== e1000_82580
))
152 wr32(E1000_MDICNFG
, 0);
154 /* Set mta register count */
155 mac
->mta_reg_count
= 128;
156 /* Set rar entry count */
157 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82575
;
158 if (mac
->type
== e1000_82576
)
159 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82576
;
160 if (mac
->type
== e1000_82580
)
161 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82580
;
162 if (mac
->type
== e1000_i350
)
163 mac
->rar_entry_count
= E1000_RAR_ENTRIES_I350
;
165 if (mac
->type
>= e1000_82580
)
166 mac
->ops
.reset_hw
= igb_reset_hw_82580
;
168 mac
->ops
.reset_hw
= igb_reset_hw_82575
;
169 /* Set if part includes ASF firmware */
170 mac
->asf_firmware_present
= true;
171 /* Set if manageability features are enabled. */
172 mac
->arc_subsystem_valid
=
173 (rd32(E1000_FWSM
) & E1000_FWSM_MODE_MASK
)
176 /* physical interface link setup */
177 mac
->ops
.setup_physical_interface
=
178 (hw
->phy
.media_type
== e1000_media_type_copper
)
179 ? igb_setup_copper_link_82575
180 : igb_setup_serdes_link_82575
;
182 /* NVM initialization */
183 eecd
= rd32(E1000_EECD
);
185 nvm
->opcode_bits
= 8;
187 switch (nvm
->override
) {
188 case e1000_nvm_override_spi_large
:
190 nvm
->address_bits
= 16;
192 case e1000_nvm_override_spi_small
:
194 nvm
->address_bits
= 8;
197 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
198 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
? 16 : 8;
202 nvm
->type
= e1000_nvm_eeprom_spi
;
204 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
205 E1000_EECD_SIZE_EX_SHIFT
);
208 * Added to a constant, "size" becomes the left-shift value
209 * for setting word_size.
211 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
213 /* EEPROM access above 16k is unsupported */
216 nvm
->word_size
= 1 << size
;
218 /* if 82576 then initialize mailbox parameters */
219 if (mac
->type
== e1000_82576
)
220 igb_init_mbx_params_pf(hw
);
222 /* setup PHY parameters */
223 if (phy
->media_type
!= e1000_media_type_copper
) {
224 phy
->type
= e1000_phy_none
;
228 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
229 phy
->reset_delay_us
= 100;
231 /* PHY function pointers */
232 if (igb_sgmii_active_82575(hw
)) {
233 phy
->ops
.reset
= igb_phy_hw_reset_sgmii_82575
;
234 phy
->ops
.read_reg
= igb_read_phy_reg_sgmii_82575
;
235 phy
->ops
.write_reg
= igb_write_phy_reg_sgmii_82575
;
236 } else if (hw
->mac
.type
>= e1000_82580
) {
237 phy
->ops
.reset
= igb_phy_hw_reset
;
238 phy
->ops
.read_reg
= igb_read_phy_reg_82580
;
239 phy
->ops
.write_reg
= igb_write_phy_reg_82580
;
241 phy
->ops
.reset
= igb_phy_hw_reset
;
242 phy
->ops
.read_reg
= igb_read_phy_reg_igp
;
243 phy
->ops
.write_reg
= igb_write_phy_reg_igp
;
247 hw
->bus
.func
= (rd32(E1000_STATUS
) & E1000_STATUS_FUNC_MASK
) >>
248 E1000_STATUS_FUNC_SHIFT
;
250 /* Set phy->phy_addr and phy->id. */
251 ret_val
= igb_get_phy_id_82575(hw
);
255 /* Verify phy id and set remaining function pointers */
257 case M88E1111_I_PHY_ID
:
258 phy
->type
= e1000_phy_m88
;
259 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
260 phy
->ops
.get_cable_length
= igb_get_cable_length_m88
;
261 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
263 case IGP03E1000_E_PHY_ID
:
264 phy
->type
= e1000_phy_igp_3
;
265 phy
->ops
.get_phy_info
= igb_get_phy_info_igp
;
266 phy
->ops
.get_cable_length
= igb_get_cable_length_igp_2
;
267 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_igp
;
268 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82575
;
269 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state
;
271 case I82580_I_PHY_ID
:
273 phy
->type
= e1000_phy_82580
;
274 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_82580
;
275 phy
->ops
.get_cable_length
= igb_get_cable_length_82580
;
276 phy
->ops
.get_phy_info
= igb_get_phy_info_82580
;
279 return -E1000_ERR_PHY
;
286 * igb_acquire_phy_82575 - Acquire rights to access PHY
287 * @hw: pointer to the HW structure
289 * Acquire access rights to the correct PHY. This is a
290 * function pointer entry point called by the api module.
292 static s32
igb_acquire_phy_82575(struct e1000_hw
*hw
)
294 u16 mask
= E1000_SWFW_PHY0_SM
;
296 if (hw
->bus
.func
== E1000_FUNC_1
)
297 mask
= E1000_SWFW_PHY1_SM
;
298 else if (hw
->bus
.func
== E1000_FUNC_2
)
299 mask
= E1000_SWFW_PHY2_SM
;
300 else if (hw
->bus
.func
== E1000_FUNC_3
)
301 mask
= E1000_SWFW_PHY3_SM
;
303 return igb_acquire_swfw_sync_82575(hw
, mask
);
307 * igb_release_phy_82575 - Release rights to access PHY
308 * @hw: pointer to the HW structure
310 * A wrapper to release access rights to the correct PHY. This is a
311 * function pointer entry point called by the api module.
313 static void igb_release_phy_82575(struct e1000_hw
*hw
)
315 u16 mask
= E1000_SWFW_PHY0_SM
;
317 if (hw
->bus
.func
== E1000_FUNC_1
)
318 mask
= E1000_SWFW_PHY1_SM
;
319 else if (hw
->bus
.func
== E1000_FUNC_2
)
320 mask
= E1000_SWFW_PHY2_SM
;
321 else if (hw
->bus
.func
== E1000_FUNC_3
)
322 mask
= E1000_SWFW_PHY3_SM
;
324 igb_release_swfw_sync_82575(hw
, mask
);
328 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
329 * @hw: pointer to the HW structure
330 * @offset: register offset to be read
331 * @data: pointer to the read data
333 * Reads the PHY register at offset using the serial gigabit media independent
334 * interface and stores the retrieved information in data.
336 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
339 s32 ret_val
= -E1000_ERR_PARAM
;
341 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
342 hw_dbg("PHY Address %u is out of range\n", offset
);
346 ret_val
= hw
->phy
.ops
.acquire(hw
);
350 ret_val
= igb_read_phy_reg_i2c(hw
, offset
, data
);
352 hw
->phy
.ops
.release(hw
);
359 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
360 * @hw: pointer to the HW structure
361 * @offset: register offset to write to
362 * @data: data to write at register offset
364 * Writes the data to PHY register at the offset using the serial gigabit
365 * media independent interface.
367 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
370 s32 ret_val
= -E1000_ERR_PARAM
;
373 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
374 hw_dbg("PHY Address %d is out of range\n", offset
);
378 ret_val
= hw
->phy
.ops
.acquire(hw
);
382 ret_val
= igb_write_phy_reg_i2c(hw
, offset
, data
);
384 hw
->phy
.ops
.release(hw
);
391 * igb_get_phy_id_82575 - Retrieve PHY addr and id
392 * @hw: pointer to the HW structure
394 * Retrieves the PHY address and ID for both PHY's which do and do not use
397 static s32
igb_get_phy_id_82575(struct e1000_hw
*hw
)
399 struct e1000_phy_info
*phy
= &hw
->phy
;
405 * For SGMII PHYs, we try the list of possible addresses until
406 * we find one that works. For non-SGMII PHYs
407 * (e.g. integrated copper PHYs), an address of 1 should
408 * work. The result of this function should mean phy->phy_addr
409 * and phy->id are set correctly.
411 if (!(igb_sgmii_active_82575(hw
))) {
413 ret_val
= igb_get_phy_id(hw
);
417 /* Power on sgmii phy if it is disabled */
418 ctrl_ext
= rd32(E1000_CTRL_EXT
);
419 wr32(E1000_CTRL_EXT
, ctrl_ext
& ~E1000_CTRL_EXT_SDP3_DATA
);
424 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
425 * Therefore, we need to test 1-7
427 for (phy
->addr
= 1; phy
->addr
< 8; phy
->addr
++) {
428 ret_val
= igb_read_phy_reg_sgmii_82575(hw
, PHY_ID1
, &phy_id
);
430 hw_dbg("Vendor ID 0x%08X read at address %u\n",
433 * At the time of this writing, The M88 part is
434 * the only supported SGMII PHY product.
436 if (phy_id
== M88_VENDOR
)
439 hw_dbg("PHY address %u was unreadable\n", phy
->addr
);
443 /* A valid PHY type couldn't be found. */
444 if (phy
->addr
== 8) {
446 ret_val
= -E1000_ERR_PHY
;
449 ret_val
= igb_get_phy_id(hw
);
452 /* restore previous sfp cage power state */
453 wr32(E1000_CTRL_EXT
, ctrl_ext
);
460 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
461 * @hw: pointer to the HW structure
463 * Resets the PHY using the serial gigabit media independent interface.
465 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*hw
)
470 * This isn't a true "hard" reset, but is the only reset
471 * available to us at this time.
474 hw_dbg("Soft resetting SGMII attached PHY...\n");
477 * SFP documentation requires the following to configure the SPF module
478 * to work on SGMII. No further documentation is given.
480 ret_val
= hw
->phy
.ops
.write_reg(hw
, 0x1B, 0x8084);
484 ret_val
= igb_phy_sw_reset(hw
);
491 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
492 * @hw: pointer to the HW structure
493 * @active: true to enable LPLU, false to disable
495 * Sets the LPLU D0 state according to the active flag. When
496 * activating LPLU this function also disables smart speed
497 * and vice versa. LPLU will not be activated unless the
498 * device autonegotiation advertisement meets standards of
499 * either 10 or 10/100 or 10/100/1000 at all duplexes.
500 * This is a function pointer entry point only called by
501 * PHY setup routines.
503 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*hw
, bool active
)
505 struct e1000_phy_info
*phy
= &hw
->phy
;
509 ret_val
= phy
->ops
.read_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
514 data
|= IGP02E1000_PM_D0_LPLU
;
515 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
520 /* When LPLU is enabled, we should disable SmartSpeed */
521 ret_val
= phy
->ops
.read_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
523 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
524 ret_val
= phy
->ops
.write_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
529 data
&= ~IGP02E1000_PM_D0_LPLU
;
530 ret_val
= phy
->ops
.write_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
533 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
534 * during Dx states where the power conservation is most
535 * important. During driver activity we should enable
536 * SmartSpeed, so performance is maintained.
538 if (phy
->smart_speed
== e1000_smart_speed_on
) {
539 ret_val
= phy
->ops
.read_reg(hw
,
540 IGP01E1000_PHY_PORT_CONFIG
, &data
);
544 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
545 ret_val
= phy
->ops
.write_reg(hw
,
546 IGP01E1000_PHY_PORT_CONFIG
, data
);
549 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
550 ret_val
= phy
->ops
.read_reg(hw
,
551 IGP01E1000_PHY_PORT_CONFIG
, &data
);
555 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
556 ret_val
= phy
->ops
.write_reg(hw
,
557 IGP01E1000_PHY_PORT_CONFIG
, data
);
568 * igb_acquire_nvm_82575 - Request for access to EEPROM
569 * @hw: pointer to the HW structure
571 * Acquire the necessary semaphores for exclusive access to the EEPROM.
572 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
573 * Return successful if access grant bit set, else clear the request for
574 * EEPROM access and return -E1000_ERR_NVM (-1).
576 static s32
igb_acquire_nvm_82575(struct e1000_hw
*hw
)
580 ret_val
= igb_acquire_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
584 ret_val
= igb_acquire_nvm(hw
);
587 igb_release_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
594 * igb_release_nvm_82575 - Release exclusive access to EEPROM
595 * @hw: pointer to the HW structure
597 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
598 * then release the semaphores acquired.
600 static void igb_release_nvm_82575(struct e1000_hw
*hw
)
603 igb_release_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
607 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
608 * @hw: pointer to the HW structure
609 * @mask: specifies which semaphore to acquire
611 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
612 * will also specify which port we're acquiring the lock for.
614 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
618 u32 fwmask
= mask
<< 16;
620 s32 i
= 0, timeout
= 200; /* FIXME: find real value to use here */
622 while (i
< timeout
) {
623 if (igb_get_hw_semaphore(hw
)) {
624 ret_val
= -E1000_ERR_SWFW_SYNC
;
628 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
629 if (!(swfw_sync
& (fwmask
| swmask
)))
633 * Firmware currently using resource (fwmask)
634 * or other software thread using resource (swmask)
636 igb_put_hw_semaphore(hw
);
642 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
643 ret_val
= -E1000_ERR_SWFW_SYNC
;
648 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
650 igb_put_hw_semaphore(hw
);
657 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
658 * @hw: pointer to the HW structure
659 * @mask: specifies which semaphore to acquire
661 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
662 * will also specify which port we're releasing the lock for.
664 static void igb_release_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
668 while (igb_get_hw_semaphore(hw
) != 0);
671 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
673 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
675 igb_put_hw_semaphore(hw
);
679 * igb_get_cfg_done_82575 - Read config done bit
680 * @hw: pointer to the HW structure
682 * Read the management control register for the config done bit for
683 * completion status. NOTE: silicon which is EEPROM-less will fail trying
684 * to read the config done bit, so an error is *ONLY* logged and returns
685 * 0. If we were to return with error, EEPROM-less silicon
686 * would not be able to be reset or change link.
688 static s32
igb_get_cfg_done_82575(struct e1000_hw
*hw
)
690 s32 timeout
= PHY_CFG_TIMEOUT
;
692 u32 mask
= E1000_NVM_CFG_DONE_PORT_0
;
694 if (hw
->bus
.func
== 1)
695 mask
= E1000_NVM_CFG_DONE_PORT_1
;
696 else if (hw
->bus
.func
== E1000_FUNC_2
)
697 mask
= E1000_NVM_CFG_DONE_PORT_2
;
698 else if (hw
->bus
.func
== E1000_FUNC_3
)
699 mask
= E1000_NVM_CFG_DONE_PORT_3
;
702 if (rd32(E1000_EEMNGCTL
) & mask
)
708 hw_dbg("MNG configuration cycle has not completed.\n");
710 /* If EEPROM is not marked present, init the PHY manually */
711 if (((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0) &&
712 (hw
->phy
.type
== e1000_phy_igp_3
))
713 igb_phy_init_script_igp3(hw
);
719 * igb_check_for_link_82575 - Check for link
720 * @hw: pointer to the HW structure
722 * If sgmii is enabled, then use the pcs register to determine link, otherwise
723 * use the generic interface for determining link.
725 static s32
igb_check_for_link_82575(struct e1000_hw
*hw
)
730 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
731 ret_val
= igb_get_pcs_speed_and_duplex_82575(hw
, &speed
,
734 * Use this flag to determine if link needs to be checked or
735 * not. If we have link clear the flag so that we do not
736 * continue to check for link.
738 hw
->mac
.get_link_status
= !hw
->mac
.serdes_has_link
;
740 ret_val
= igb_check_for_copper_link(hw
);
747 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
748 * @hw: pointer to the HW structure
750 void igb_power_up_serdes_link_82575(struct e1000_hw
*hw
)
755 if ((hw
->phy
.media_type
!= e1000_media_type_internal_serdes
) &&
756 !igb_sgmii_active_82575(hw
))
759 /* Enable PCS to turn on link */
760 reg
= rd32(E1000_PCS_CFG0
);
761 reg
|= E1000_PCS_CFG_PCS_EN
;
762 wr32(E1000_PCS_CFG0
, reg
);
764 /* Power up the laser */
765 reg
= rd32(E1000_CTRL_EXT
);
766 reg
&= ~E1000_CTRL_EXT_SDP3_DATA
;
767 wr32(E1000_CTRL_EXT
, reg
);
769 /* flush the write to verify completion */
775 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
776 * @hw: pointer to the HW structure
777 * @speed: stores the current speed
778 * @duplex: stores the current duplex
780 * Using the physical coding sub-layer (PCS), retrieve the current speed and
781 * duplex, then store the values in the pointers provided.
783 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*hw
, u16
*speed
,
786 struct e1000_mac_info
*mac
= &hw
->mac
;
789 /* Set up defaults for the return values of this function */
790 mac
->serdes_has_link
= false;
795 * Read the PCS Status register for link state. For non-copper mode,
796 * the status register is not accurate. The PCS status register is
799 pcs
= rd32(E1000_PCS_LSTAT
);
802 * The link up bit determines when link is up on autoneg. The sync ok
803 * gets set once both sides sync up and agree upon link. Stable link
804 * can be determined by checking for both link up and link sync ok
806 if ((pcs
& E1000_PCS_LSTS_LINK_OK
) && (pcs
& E1000_PCS_LSTS_SYNK_OK
)) {
807 mac
->serdes_has_link
= true;
809 /* Detect and store PCS speed */
810 if (pcs
& E1000_PCS_LSTS_SPEED_1000
) {
812 } else if (pcs
& E1000_PCS_LSTS_SPEED_100
) {
818 /* Detect and store PCS duplex */
819 if (pcs
& E1000_PCS_LSTS_DUPLEX_FULL
) {
820 *duplex
= FULL_DUPLEX
;
822 *duplex
= HALF_DUPLEX
;
830 * igb_shutdown_serdes_link_82575 - Remove link during power down
831 * @hw: pointer to the HW structure
833 * In the case of fiber serdes, shut down optics and PCS on driver unload
834 * when management pass thru is not enabled.
836 void igb_shutdown_serdes_link_82575(struct e1000_hw
*hw
)
840 if (hw
->phy
.media_type
!= e1000_media_type_internal_serdes
&&
841 igb_sgmii_active_82575(hw
))
844 if (!igb_enable_mng_pass_thru(hw
)) {
845 /* Disable PCS to turn off link */
846 reg
= rd32(E1000_PCS_CFG0
);
847 reg
&= ~E1000_PCS_CFG_PCS_EN
;
848 wr32(E1000_PCS_CFG0
, reg
);
850 /* shutdown the laser */
851 reg
= rd32(E1000_CTRL_EXT
);
852 reg
|= E1000_CTRL_EXT_SDP3_DATA
;
853 wr32(E1000_CTRL_EXT
, reg
);
855 /* flush the write to verify completion */
862 * igb_reset_hw_82575 - Reset hardware
863 * @hw: pointer to the HW structure
865 * This resets the hardware into a known state. This is a
866 * function pointer entry point called by the api module.
868 static s32
igb_reset_hw_82575(struct e1000_hw
*hw
)
874 * Prevent the PCI-E bus from sticking if there is no TLP connection
875 * on the last TLP read/write transaction when MAC is reset.
877 ret_val
= igb_disable_pcie_master(hw
);
879 hw_dbg("PCI-E Master disable polling has failed.\n");
881 /* set the completion timeout for interface */
882 ret_val
= igb_set_pcie_completion_timeout(hw
);
884 hw_dbg("PCI-E Set completion timeout has failed.\n");
887 hw_dbg("Masking off all interrupts\n");
888 wr32(E1000_IMC
, 0xffffffff);
891 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
896 ctrl
= rd32(E1000_CTRL
);
898 hw_dbg("Issuing a global reset to MAC\n");
899 wr32(E1000_CTRL
, ctrl
| E1000_CTRL_RST
);
901 ret_val
= igb_get_auto_rd_done(hw
);
904 * When auto config read does not complete, do not
905 * return with an error. This can happen in situations
906 * where there is no eeprom and prevents getting link.
908 hw_dbg("Auto Read Done did not complete\n");
911 /* If EEPROM is not present, run manual init scripts */
912 if ((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0)
913 igb_reset_init_script_82575(hw
);
915 /* Clear any pending interrupt events. */
916 wr32(E1000_IMC
, 0xffffffff);
917 icr
= rd32(E1000_ICR
);
919 /* Install any alternate MAC address into RAR0 */
920 ret_val
= igb_check_alt_mac_addr(hw
);
926 * igb_init_hw_82575 - Initialize hardware
927 * @hw: pointer to the HW structure
929 * This inits the hardware readying it for operation.
931 static s32
igb_init_hw_82575(struct e1000_hw
*hw
)
933 struct e1000_mac_info
*mac
= &hw
->mac
;
935 u16 i
, rar_count
= mac
->rar_entry_count
;
937 /* Initialize identification LED */
938 ret_val
= igb_id_led_init(hw
);
940 hw_dbg("Error initializing identification LED\n");
941 /* This is not fatal and we should not stop init due to this */
944 /* Disabling VLAN filtering */
945 hw_dbg("Initializing the IEEE VLAN\n");
948 /* Setup the receive address */
949 igb_init_rx_addrs(hw
, rar_count
);
951 /* Zero out the Multicast HASH table */
952 hw_dbg("Zeroing the MTA\n");
953 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
954 array_wr32(E1000_MTA
, i
, 0);
956 /* Zero out the Unicast HASH table */
957 hw_dbg("Zeroing the UTA\n");
958 for (i
= 0; i
< mac
->uta_reg_count
; i
++)
959 array_wr32(E1000_UTA
, i
, 0);
961 /* Setup link and flow control */
962 ret_val
= igb_setup_link(hw
);
965 * Clear all of the statistics registers (clear on read). It is
966 * important that we do this after we have tried to establish link
967 * because the symbol error count will increment wildly if there
970 igb_clear_hw_cntrs_82575(hw
);
976 * igb_setup_copper_link_82575 - Configure copper link settings
977 * @hw: pointer to the HW structure
979 * Configures the link for auto-neg or forced speed and duplex. Then we check
980 * for link, once link is established calls to configure collision distance
981 * and flow control are called.
983 static s32
igb_setup_copper_link_82575(struct e1000_hw
*hw
)
988 ctrl
= rd32(E1000_CTRL
);
989 ctrl
|= E1000_CTRL_SLU
;
990 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
991 wr32(E1000_CTRL
, ctrl
);
993 ret_val
= igb_setup_serdes_link_82575(hw
);
997 if (igb_sgmii_active_82575(hw
) && !hw
->phy
.reset_disable
) {
998 /* allow time for SFP cage time to power up phy */
1001 ret_val
= hw
->phy
.ops
.reset(hw
);
1003 hw_dbg("Error resetting the PHY.\n");
1007 switch (hw
->phy
.type
) {
1009 ret_val
= igb_copper_link_setup_m88(hw
);
1011 case e1000_phy_igp_3
:
1012 ret_val
= igb_copper_link_setup_igp(hw
);
1014 case e1000_phy_82580
:
1015 ret_val
= igb_copper_link_setup_82580(hw
);
1018 ret_val
= -E1000_ERR_PHY
;
1025 ret_val
= igb_setup_copper_link(hw
);
1031 * igb_setup_serdes_link_82575 - Setup link for serdes
1032 * @hw: pointer to the HW structure
1034 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1035 * used on copper connections where the serialized gigabit media independent
1036 * interface (sgmii), or serdes fiber is being used. Configures the link
1037 * for auto-negotiation or forces speed/duplex.
1039 static s32
igb_setup_serdes_link_82575(struct e1000_hw
*hw
)
1041 u32 ctrl_ext
, ctrl_reg
, reg
;
1044 if ((hw
->phy
.media_type
!= e1000_media_type_internal_serdes
) &&
1045 !igb_sgmii_active_82575(hw
))
1049 * On the 82575, SerDes loopback mode persists until it is
1050 * explicitly turned off or a power cycle is performed. A read to
1051 * the register does not indicate its status. Therefore, we ensure
1052 * loopback mode is disabled during initialization.
1054 wr32(E1000_SCTL
, E1000_SCTL_DISABLE_SERDES_LOOPBACK
);
1056 /* power on the sfp cage if present */
1057 ctrl_ext
= rd32(E1000_CTRL_EXT
);
1058 ctrl_ext
&= ~E1000_CTRL_EXT_SDP3_DATA
;
1059 wr32(E1000_CTRL_EXT
, ctrl_ext
);
1061 ctrl_reg
= rd32(E1000_CTRL
);
1062 ctrl_reg
|= E1000_CTRL_SLU
;
1064 if (hw
->mac
.type
== e1000_82575
|| hw
->mac
.type
== e1000_82576
) {
1065 /* set both sw defined pins */
1066 ctrl_reg
|= E1000_CTRL_SWDPIN0
| E1000_CTRL_SWDPIN1
;
1068 /* Set switch control to serdes energy detect */
1069 reg
= rd32(E1000_CONNSW
);
1070 reg
|= E1000_CONNSW_ENRGSRC
;
1071 wr32(E1000_CONNSW
, reg
);
1074 reg
= rd32(E1000_PCS_LCTL
);
1076 /* default pcs_autoneg to the same setting as mac autoneg */
1077 pcs_autoneg
= hw
->mac
.autoneg
;
1079 switch (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) {
1080 case E1000_CTRL_EXT_LINK_MODE_SGMII
:
1081 /* sgmii mode lets the phy handle forcing speed/duplex */
1083 /* autoneg time out should be disabled for SGMII mode */
1084 reg
&= ~(E1000_PCS_LCTL_AN_TIMEOUT
);
1086 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX
:
1087 /* disable PCS autoneg and support parallel detect only */
1088 pcs_autoneg
= false;
1091 * non-SGMII modes only supports a speed of 1000/Full for the
1092 * link so it is best to just force the MAC and let the pcs
1093 * link either autoneg or be forced to 1000/Full
1095 ctrl_reg
|= E1000_CTRL_SPD_1000
| E1000_CTRL_FRCSPD
|
1096 E1000_CTRL_FD
| E1000_CTRL_FRCDPX
;
1098 /* set speed of 1000/Full if speed/duplex is forced */
1099 reg
|= E1000_PCS_LCTL_FSV_1000
| E1000_PCS_LCTL_FDV_FULL
;
1103 wr32(E1000_CTRL
, ctrl_reg
);
1106 * New SerDes mode allows for forcing speed or autonegotiating speed
1107 * at 1gb. Autoneg should be default set by most drivers. This is the
1108 * mode that will be compatible with older link partners and switches.
1109 * However, both are supported by the hardware and some drivers/tools.
1111 reg
&= ~(E1000_PCS_LCTL_AN_ENABLE
| E1000_PCS_LCTL_FLV_LINK_UP
|
1112 E1000_PCS_LCTL_FSD
| E1000_PCS_LCTL_FORCE_LINK
);
1115 * We force flow control to prevent the CTRL register values from being
1116 * overwritten by the autonegotiated flow control values
1118 reg
|= E1000_PCS_LCTL_FORCE_FCTRL
;
1121 /* Set PCS register for autoneg */
1122 reg
|= E1000_PCS_LCTL_AN_ENABLE
| /* Enable Autoneg */
1123 E1000_PCS_LCTL_AN_RESTART
; /* Restart autoneg */
1124 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg
);
1126 /* Set PCS register for forced link */
1127 reg
|= E1000_PCS_LCTL_FSD
; /* Force Speed */
1129 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg
);
1132 wr32(E1000_PCS_LCTL
, reg
);
1134 if (!igb_sgmii_active_82575(hw
))
1135 igb_force_mac_fc(hw
);
1141 * igb_sgmii_active_82575 - Return sgmii state
1142 * @hw: pointer to the HW structure
1144 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1145 * which can be enabled for use in the embedded applications. Simply
1146 * return the current state of the sgmii interface.
1148 static bool igb_sgmii_active_82575(struct e1000_hw
*hw
)
1150 struct e1000_dev_spec_82575
*dev_spec
= &hw
->dev_spec
._82575
;
1151 return dev_spec
->sgmii_active
;
1155 * igb_reset_init_script_82575 - Inits HW defaults after reset
1156 * @hw: pointer to the HW structure
1158 * Inits recommended HW defaults after a reset when there is no EEPROM
1159 * detected. This is only for the 82575.
1161 static s32
igb_reset_init_script_82575(struct e1000_hw
*hw
)
1163 if (hw
->mac
.type
== e1000_82575
) {
1164 hw_dbg("Running reset init script for 82575\n");
1165 /* SerDes configuration via SERDESCTRL */
1166 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x00, 0x0C);
1167 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x01, 0x78);
1168 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x1B, 0x23);
1169 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x23, 0x15);
1171 /* CCM configuration via CCMCTL register */
1172 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x14, 0x00);
1173 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x10, 0x00);
1175 /* PCIe lanes configuration */
1176 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x00, 0xEC);
1177 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x61, 0xDF);
1178 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x34, 0x05);
1179 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x2F, 0x81);
1181 /* PCIe PLL Configuration */
1182 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x02, 0x47);
1183 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x14, 0x00);
1184 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x10, 0x00);
1191 * igb_read_mac_addr_82575 - Read device MAC address
1192 * @hw: pointer to the HW structure
1194 static s32
igb_read_mac_addr_82575(struct e1000_hw
*hw
)
1199 * If there's an alternate MAC address place it in RAR0
1200 * so that it will override the Si installed default perm
1203 ret_val
= igb_check_alt_mac_addr(hw
);
1207 ret_val
= igb_read_mac_addr(hw
);
1214 * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1215 * @hw: pointer to the HW structure
1217 * In the case of a PHY power down to save power, or to turn off link during a
1218 * driver unload, or wake on lan is not enabled, remove the link.
1220 void igb_power_down_phy_copper_82575(struct e1000_hw
*hw
)
1222 /* If the management interface is not enabled, then power down */
1223 if (!(igb_enable_mng_pass_thru(hw
) || igb_check_reset_block(hw
)))
1224 igb_power_down_phy_copper(hw
);
1228 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1229 * @hw: pointer to the HW structure
1231 * Clears the hardware counters by reading the counter registers.
1233 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*hw
)
1235 igb_clear_hw_cntrs_base(hw
);
1241 rd32(E1000_PRC1023
);
1242 rd32(E1000_PRC1522
);
1247 rd32(E1000_PTC1023
);
1248 rd32(E1000_PTC1522
);
1250 rd32(E1000_ALGNERRC
);
1253 rd32(E1000_CEXTERR
);
1264 rd32(E1000_ICRXPTC
);
1265 rd32(E1000_ICRXATC
);
1266 rd32(E1000_ICTXPTC
);
1267 rd32(E1000_ICTXATC
);
1268 rd32(E1000_ICTXQEC
);
1269 rd32(E1000_ICTXQMTC
);
1270 rd32(E1000_ICRXDMTC
);
1277 rd32(E1000_HTCBDPC
);
1282 rd32(E1000_LENERRS
);
1284 /* This register should not be read in copper configurations */
1285 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
||
1286 igb_sgmii_active_82575(hw
))
1291 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1292 * @hw: pointer to the HW structure
1294 * After rx enable if managability is enabled then there is likely some
1295 * bad data at the start of the fifo and possibly in the DMA fifo. This
1296 * function clears the fifos and flushes any packets that came in as rx was
1299 void igb_rx_fifo_flush_82575(struct e1000_hw
*hw
)
1301 u32 rctl
, rlpml
, rxdctl
[4], rfctl
, temp_rctl
, rx_enabled
;
1304 if (hw
->mac
.type
!= e1000_82575
||
1305 !(rd32(E1000_MANC
) & E1000_MANC_RCV_TCO_EN
))
1308 /* Disable all RX queues */
1309 for (i
= 0; i
< 4; i
++) {
1310 rxdctl
[i
] = rd32(E1000_RXDCTL(i
));
1311 wr32(E1000_RXDCTL(i
),
1312 rxdctl
[i
] & ~E1000_RXDCTL_QUEUE_ENABLE
);
1314 /* Poll all queues to verify they have shut down */
1315 for (ms_wait
= 0; ms_wait
< 10; ms_wait
++) {
1318 for (i
= 0; i
< 4; i
++)
1319 rx_enabled
|= rd32(E1000_RXDCTL(i
));
1320 if (!(rx_enabled
& E1000_RXDCTL_QUEUE_ENABLE
))
1325 hw_dbg("Queue disable timed out after 10ms\n");
1327 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1328 * incoming packets are rejected. Set enable and wait 2ms so that
1329 * any packet that was coming in as RCTL.EN was set is flushed
1331 rfctl
= rd32(E1000_RFCTL
);
1332 wr32(E1000_RFCTL
, rfctl
& ~E1000_RFCTL_LEF
);
1334 rlpml
= rd32(E1000_RLPML
);
1335 wr32(E1000_RLPML
, 0);
1337 rctl
= rd32(E1000_RCTL
);
1338 temp_rctl
= rctl
& ~(E1000_RCTL_EN
| E1000_RCTL_SBP
);
1339 temp_rctl
|= E1000_RCTL_LPE
;
1341 wr32(E1000_RCTL
, temp_rctl
);
1342 wr32(E1000_RCTL
, temp_rctl
| E1000_RCTL_EN
);
1346 /* Enable RX queues that were previously enabled and restore our
1349 for (i
= 0; i
< 4; i
++)
1350 wr32(E1000_RXDCTL(i
), rxdctl
[i
]);
1351 wr32(E1000_RCTL
, rctl
);
1354 wr32(E1000_RLPML
, rlpml
);
1355 wr32(E1000_RFCTL
, rfctl
);
1357 /* Flush receive errors generated by workaround */
1364 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1365 * @hw: pointer to the HW structure
1367 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1368 * however the hardware default for these parts is 500us to 1ms which is less
1369 * than the 10ms recommended by the pci-e spec. To address this we need to
1370 * increase the value to either 10ms to 200ms for capability version 1 config,
1371 * or 16ms to 55ms for version 2.
1373 static s32
igb_set_pcie_completion_timeout(struct e1000_hw
*hw
)
1375 u32 gcr
= rd32(E1000_GCR
);
1379 /* only take action if timeout value is defaulted to 0 */
1380 if (gcr
& E1000_GCR_CMPL_TMOUT_MASK
)
1384 * if capababilities version is type 1 we can write the
1385 * timeout of 10ms to 200ms through the GCR register
1387 if (!(gcr
& E1000_GCR_CAP_VER2
)) {
1388 gcr
|= E1000_GCR_CMPL_TMOUT_10ms
;
1393 * for version 2 capabilities we need to write the config space
1394 * directly in order to set the completion timeout value for
1397 ret_val
= igb_read_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1402 pcie_devctl2
|= PCIE_DEVICE_CONTROL2_16ms
;
1404 ret_val
= igb_write_pcie_cap_reg(hw
, PCIE_DEVICE_CONTROL2
,
1407 /* disable completion timeout resend */
1408 gcr
&= ~E1000_GCR_CMPL_TMOUT_RESEND
;
1410 wr32(E1000_GCR
, gcr
);
1415 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1416 * @hw: pointer to the hardware struct
1417 * @enable: state to enter, either enabled or disabled
1419 * enables/disables L2 switch loopback functionality.
1421 void igb_vmdq_set_loopback_pf(struct e1000_hw
*hw
, bool enable
)
1423 u32 dtxswc
= rd32(E1000_DTXSWC
);
1426 dtxswc
|= E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1428 dtxswc
&= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN
;
1430 wr32(E1000_DTXSWC
, dtxswc
);
1434 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1435 * @hw: pointer to the hardware struct
1436 * @enable: state to enter, either enabled or disabled
1438 * enables/disables replication of packets across multiple pools.
1440 void igb_vmdq_set_replication_pf(struct e1000_hw
*hw
, bool enable
)
1442 u32 vt_ctl
= rd32(E1000_VT_CTL
);
1445 vt_ctl
|= E1000_VT_CTL_VM_REPL_EN
;
1447 vt_ctl
&= ~E1000_VT_CTL_VM_REPL_EN
;
1449 wr32(E1000_VT_CTL
, vt_ctl
);
1453 * igb_read_phy_reg_82580 - Read 82580 MDI control register
1454 * @hw: pointer to the HW structure
1455 * @offset: register offset to be read
1456 * @data: pointer to the read data
1458 * Reads the MDI control register in the PHY at offset and stores the
1459 * information read to data.
1461 static s32
igb_read_phy_reg_82580(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
1466 ret_val
= hw
->phy
.ops
.acquire(hw
);
1470 ret_val
= igb_read_phy_reg_mdic(hw
, offset
, data
);
1472 hw
->phy
.ops
.release(hw
);
1479 * igb_write_phy_reg_82580 - Write 82580 MDI control register
1480 * @hw: pointer to the HW structure
1481 * @offset: register offset to write to
1482 * @data: data to write to register at offset
1484 * Writes data to MDI control register in the PHY at offset.
1486 static s32
igb_write_phy_reg_82580(struct e1000_hw
*hw
, u32 offset
, u16 data
)
1491 ret_val
= hw
->phy
.ops
.acquire(hw
);
1495 ret_val
= igb_write_phy_reg_mdic(hw
, offset
, data
);
1497 hw
->phy
.ops
.release(hw
);
1504 * igb_reset_hw_82580 - Reset hardware
1505 * @hw: pointer to the HW structure
1507 * This resets function or entire device (all ports, etc.)
1510 static s32
igb_reset_hw_82580(struct e1000_hw
*hw
)
1513 /* BH SW mailbox bit in SW_FW_SYNC */
1514 u16 swmbsw_mask
= E1000_SW_SYNCH_MB
;
1516 bool global_device_reset
= hw
->dev_spec
._82575
.global_device_reset
;
1519 hw
->dev_spec
._82575
.global_device_reset
= false;
1521 /* Get current control state. */
1522 ctrl
= rd32(E1000_CTRL
);
1525 * Prevent the PCI-E bus from sticking if there is no TLP connection
1526 * on the last TLP read/write transaction when MAC is reset.
1528 ret_val
= igb_disable_pcie_master(hw
);
1530 hw_dbg("PCI-E Master disable polling has failed.\n");
1532 hw_dbg("Masking off all interrupts\n");
1533 wr32(E1000_IMC
, 0xffffffff);
1534 wr32(E1000_RCTL
, 0);
1535 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
1540 /* Determine whether or not a global dev reset is requested */
1541 if (global_device_reset
&&
1542 igb_acquire_swfw_sync_82575(hw
, swmbsw_mask
))
1543 global_device_reset
= false;
1545 if (global_device_reset
&&
1546 !(rd32(E1000_STATUS
) & E1000_STAT_DEV_RST_SET
))
1547 ctrl
|= E1000_CTRL_DEV_RST
;
1549 ctrl
|= E1000_CTRL_RST
;
1551 wr32(E1000_CTRL
, ctrl
);
1553 /* Add delay to insure DEV_RST has time to complete */
1554 if (global_device_reset
)
1557 ret_val
= igb_get_auto_rd_done(hw
);
1560 * When auto config read does not complete, do not
1561 * return with an error. This can happen in situations
1562 * where there is no eeprom and prevents getting link.
1564 hw_dbg("Auto Read Done did not complete\n");
1567 /* If EEPROM is not present, run manual init scripts */
1568 if ((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0)
1569 igb_reset_init_script_82575(hw
);
1571 /* clear global device reset status bit */
1572 wr32(E1000_STATUS
, E1000_STAT_DEV_RST_SET
);
1574 /* Clear any pending interrupt events. */
1575 wr32(E1000_IMC
, 0xffffffff);
1576 icr
= rd32(E1000_ICR
);
1578 /* Install any alternate MAC address into RAR0 */
1579 ret_val
= igb_check_alt_mac_addr(hw
);
1581 /* Release semaphore */
1582 if (global_device_reset
)
1583 igb_release_swfw_sync_82575(hw
, swmbsw_mask
);
1589 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1590 * @data: data received by reading RXPBS register
1592 * The 82580 uses a table based approach for packet buffer allocation sizes.
1593 * This function converts the retrieved value into the correct table value
1594 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1595 * 0x0 36 72 144 1 2 4 8 16
1596 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1598 u16
igb_rxpbs_adjust_82580(u32 data
)
1602 if (data
< E1000_82580_RXPBS_TABLE_SIZE
)
1603 ret_val
= e1000_82580_rxpbs_table
[data
];
1608 static struct e1000_mac_operations e1000_mac_ops_82575
= {
1609 .init_hw
= igb_init_hw_82575
,
1610 .check_for_link
= igb_check_for_link_82575
,
1611 .rar_set
= igb_rar_set
,
1612 .read_mac_addr
= igb_read_mac_addr_82575
,
1613 .get_speed_and_duplex
= igb_get_speed_and_duplex_copper
,
1616 static struct e1000_phy_operations e1000_phy_ops_82575
= {
1617 .acquire
= igb_acquire_phy_82575
,
1618 .get_cfg_done
= igb_get_cfg_done_82575
,
1619 .release
= igb_release_phy_82575
,
1622 static struct e1000_nvm_operations e1000_nvm_ops_82575
= {
1623 .acquire
= igb_acquire_nvm_82575
,
1624 .read
= igb_read_nvm_eerd
,
1625 .release
= igb_release_nvm_82575
,
1626 .write
= igb_write_nvm_spi
,
1629 const struct e1000_info e1000_82575_info
= {
1630 .get_invariants
= igb_get_invariants_82575
,
1631 .mac_ops
= &e1000_mac_ops_82575
,
1632 .phy_ops
= &e1000_phy_ops_82575
,
1633 .nvm_ops
= &e1000_nvm_ops_82575
,