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igb: make use of the uta to allow for promiscous mode filter
[deliverable/linux.git] / drivers / net / igb / e1000_82575.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* e1000_82575
29 * e1000_82576
30 */
31
32 #include <linux/types.h>
33 #include <linux/slab.h>
34 #include <linux/if_ether.h>
35
36 #include "e1000_mac.h"
37 #include "e1000_82575.h"
38
39 static s32 igb_get_invariants_82575(struct e1000_hw *);
40 static s32 igb_acquire_phy_82575(struct e1000_hw *);
41 static void igb_release_phy_82575(struct e1000_hw *);
42 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
43 static void igb_release_nvm_82575(struct e1000_hw *);
44 static s32 igb_check_for_link_82575(struct e1000_hw *);
45 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
46 static s32 igb_init_hw_82575(struct e1000_hw *);
47 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
48 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
49 static s32 igb_reset_hw_82575(struct e1000_hw *);
50 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
51 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
52 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
53 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
54 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
55 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
56 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
57 u16 *);
58 static s32 igb_get_phy_id_82575(struct e1000_hw *);
59 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
60 static bool igb_sgmii_active_82575(struct e1000_hw *);
61 static s32 igb_reset_init_script_82575(struct e1000_hw *);
62 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
63 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
64
65 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
66 {
67 struct e1000_phy_info *phy = &hw->phy;
68 struct e1000_nvm_info *nvm = &hw->nvm;
69 struct e1000_mac_info *mac = &hw->mac;
70 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
71 u32 eecd;
72 s32 ret_val;
73 u16 size;
74 u32 ctrl_ext = 0;
75
76 switch (hw->device_id) {
77 case E1000_DEV_ID_82575EB_COPPER:
78 case E1000_DEV_ID_82575EB_FIBER_SERDES:
79 case E1000_DEV_ID_82575GB_QUAD_COPPER:
80 mac->type = e1000_82575;
81 break;
82 case E1000_DEV_ID_82576:
83 case E1000_DEV_ID_82576_NS:
84 case E1000_DEV_ID_82576_FIBER:
85 case E1000_DEV_ID_82576_SERDES:
86 case E1000_DEV_ID_82576_QUAD_COPPER:
87 case E1000_DEV_ID_82576_SERDES_QUAD:
88 mac->type = e1000_82576;
89 break;
90 default:
91 return -E1000_ERR_MAC_INIT;
92 break;
93 }
94
95 /* Set media type */
96 /*
97 * The 82575 uses bits 22:23 for link mode. The mode can be changed
98 * based on the EEPROM. We cannot rely upon device ID. There
99 * is no distinguishable difference between fiber and internal
100 * SerDes mode on the 82575. There can be an external PHY attached
101 * on the SGMII interface. For this, we'll set sgmii_active to true.
102 */
103 phy->media_type = e1000_media_type_copper;
104 dev_spec->sgmii_active = false;
105
106 ctrl_ext = rd32(E1000_CTRL_EXT);
107 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
108 case E1000_CTRL_EXT_LINK_MODE_SGMII:
109 dev_spec->sgmii_active = true;
110 ctrl_ext |= E1000_CTRL_I2C_ENA;
111 break;
112 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
113 hw->phy.media_type = e1000_media_type_internal_serdes;
114 ctrl_ext |= E1000_CTRL_I2C_ENA;
115 break;
116 default:
117 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
118 break;
119 }
120
121 wr32(E1000_CTRL_EXT, ctrl_ext);
122
123 /* Set mta register count */
124 mac->mta_reg_count = 128;
125 /* Set rar entry count */
126 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
127 if (mac->type == e1000_82576)
128 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
129 /* Set if part includes ASF firmware */
130 mac->asf_firmware_present = true;
131 /* Set if manageability features are enabled. */
132 mac->arc_subsystem_valid =
133 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
134 ? true : false;
135
136 /* physical interface link setup */
137 mac->ops.setup_physical_interface =
138 (hw->phy.media_type == e1000_media_type_copper)
139 ? igb_setup_copper_link_82575
140 : igb_setup_serdes_link_82575;
141
142 /* NVM initialization */
143 eecd = rd32(E1000_EECD);
144
145 nvm->opcode_bits = 8;
146 nvm->delay_usec = 1;
147 switch (nvm->override) {
148 case e1000_nvm_override_spi_large:
149 nvm->page_size = 32;
150 nvm->address_bits = 16;
151 break;
152 case e1000_nvm_override_spi_small:
153 nvm->page_size = 8;
154 nvm->address_bits = 8;
155 break;
156 default:
157 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
158 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
159 break;
160 }
161
162 nvm->type = e1000_nvm_eeprom_spi;
163
164 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
165 E1000_EECD_SIZE_EX_SHIFT);
166
167 /*
168 * Added to a constant, "size" becomes the left-shift value
169 * for setting word_size.
170 */
171 size += NVM_WORD_SIZE_BASE_SHIFT;
172
173 /* EEPROM access above 16k is unsupported */
174 if (size > 14)
175 size = 14;
176 nvm->word_size = 1 << size;
177
178 /* if 82576 then initialize mailbox parameters */
179 if (mac->type == e1000_82576)
180 igb_init_mbx_params_pf(hw);
181
182 /* setup PHY parameters */
183 if (phy->media_type != e1000_media_type_copper) {
184 phy->type = e1000_phy_none;
185 return 0;
186 }
187
188 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
189 phy->reset_delay_us = 100;
190
191 /* PHY function pointers */
192 if (igb_sgmii_active_82575(hw)) {
193 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
194 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
195 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
196 } else {
197 phy->ops.reset = igb_phy_hw_reset;
198 phy->ops.read_reg = igb_read_phy_reg_igp;
199 phy->ops.write_reg = igb_write_phy_reg_igp;
200 }
201
202 /* set lan id */
203 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
204 E1000_STATUS_FUNC_SHIFT;
205
206 /* Set phy->phy_addr and phy->id. */
207 ret_val = igb_get_phy_id_82575(hw);
208 if (ret_val)
209 return ret_val;
210
211 /* Verify phy id and set remaining function pointers */
212 switch (phy->id) {
213 case M88E1111_I_PHY_ID:
214 phy->type = e1000_phy_m88;
215 phy->ops.get_phy_info = igb_get_phy_info_m88;
216 phy->ops.get_cable_length = igb_get_cable_length_m88;
217 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
218 break;
219 case IGP03E1000_E_PHY_ID:
220 phy->type = e1000_phy_igp_3;
221 phy->ops.get_phy_info = igb_get_phy_info_igp;
222 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
223 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
224 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
225 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
226 break;
227 default:
228 return -E1000_ERR_PHY;
229 }
230
231 return 0;
232 }
233
234 /**
235 * igb_acquire_phy_82575 - Acquire rights to access PHY
236 * @hw: pointer to the HW structure
237 *
238 * Acquire access rights to the correct PHY. This is a
239 * function pointer entry point called by the api module.
240 **/
241 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
242 {
243 u16 mask = E1000_SWFW_PHY0_SM;
244
245 if (hw->bus.func == E1000_FUNC_1)
246 mask = E1000_SWFW_PHY1_SM;
247
248 return igb_acquire_swfw_sync_82575(hw, mask);
249 }
250
251 /**
252 * igb_release_phy_82575 - Release rights to access PHY
253 * @hw: pointer to the HW structure
254 *
255 * A wrapper to release access rights to the correct PHY. This is a
256 * function pointer entry point called by the api module.
257 **/
258 static void igb_release_phy_82575(struct e1000_hw *hw)
259 {
260 u16 mask = E1000_SWFW_PHY0_SM;
261
262 if (hw->bus.func == E1000_FUNC_1)
263 mask = E1000_SWFW_PHY1_SM;
264
265 igb_release_swfw_sync_82575(hw, mask);
266 }
267
268 /**
269 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
270 * @hw: pointer to the HW structure
271 * @offset: register offset to be read
272 * @data: pointer to the read data
273 *
274 * Reads the PHY register at offset using the serial gigabit media independent
275 * interface and stores the retrieved information in data.
276 **/
277 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
278 u16 *data)
279 {
280 s32 ret_val = -E1000_ERR_PARAM;
281
282 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
283 hw_dbg("PHY Address %u is out of range\n", offset);
284 goto out;
285 }
286
287 ret_val = hw->phy.ops.acquire(hw);
288 if (ret_val)
289 goto out;
290
291 ret_val = igb_read_phy_reg_i2c(hw, offset, data);
292
293 hw->phy.ops.release(hw);
294
295 out:
296 return ret_val;
297 }
298
299 /**
300 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
301 * @hw: pointer to the HW structure
302 * @offset: register offset to write to
303 * @data: data to write at register offset
304 *
305 * Writes the data to PHY register at the offset using the serial gigabit
306 * media independent interface.
307 **/
308 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
309 u16 data)
310 {
311 s32 ret_val = -E1000_ERR_PARAM;
312
313
314 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
315 hw_dbg("PHY Address %d is out of range\n", offset);
316 goto out;
317 }
318
319 ret_val = hw->phy.ops.acquire(hw);
320 if (ret_val)
321 goto out;
322
323 ret_val = igb_write_phy_reg_i2c(hw, offset, data);
324
325 hw->phy.ops.release(hw);
326
327 out:
328 return ret_val;
329 }
330
331 /**
332 * igb_get_phy_id_82575 - Retrieve PHY addr and id
333 * @hw: pointer to the HW structure
334 *
335 * Retrieves the PHY address and ID for both PHY's which do and do not use
336 * sgmi interface.
337 **/
338 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
339 {
340 struct e1000_phy_info *phy = &hw->phy;
341 s32 ret_val = 0;
342 u16 phy_id;
343 u32 ctrl_ext;
344
345 /*
346 * For SGMII PHYs, we try the list of possible addresses until
347 * we find one that works. For non-SGMII PHYs
348 * (e.g. integrated copper PHYs), an address of 1 should
349 * work. The result of this function should mean phy->phy_addr
350 * and phy->id are set correctly.
351 */
352 if (!(igb_sgmii_active_82575(hw))) {
353 phy->addr = 1;
354 ret_val = igb_get_phy_id(hw);
355 goto out;
356 }
357
358 /* Power on sgmii phy if it is disabled */
359 ctrl_ext = rd32(E1000_CTRL_EXT);
360 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
361 wrfl();
362 msleep(300);
363
364 /*
365 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
366 * Therefore, we need to test 1-7
367 */
368 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
369 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
370 if (ret_val == 0) {
371 hw_dbg("Vendor ID 0x%08X read at address %u\n",
372 phy_id, phy->addr);
373 /*
374 * At the time of this writing, The M88 part is
375 * the only supported SGMII PHY product.
376 */
377 if (phy_id == M88_VENDOR)
378 break;
379 } else {
380 hw_dbg("PHY address %u was unreadable\n", phy->addr);
381 }
382 }
383
384 /* A valid PHY type couldn't be found. */
385 if (phy->addr == 8) {
386 phy->addr = 0;
387 ret_val = -E1000_ERR_PHY;
388 goto out;
389 } else {
390 ret_val = igb_get_phy_id(hw);
391 }
392
393 /* restore previous sfp cage power state */
394 wr32(E1000_CTRL_EXT, ctrl_ext);
395
396 out:
397 return ret_val;
398 }
399
400 /**
401 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
402 * @hw: pointer to the HW structure
403 *
404 * Resets the PHY using the serial gigabit media independent interface.
405 **/
406 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
407 {
408 s32 ret_val;
409
410 /*
411 * This isn't a true "hard" reset, but is the only reset
412 * available to us at this time.
413 */
414
415 hw_dbg("Soft resetting SGMII attached PHY...\n");
416
417 /*
418 * SFP documentation requires the following to configure the SPF module
419 * to work on SGMII. No further documentation is given.
420 */
421 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
422 if (ret_val)
423 goto out;
424
425 ret_val = igb_phy_sw_reset(hw);
426
427 out:
428 return ret_val;
429 }
430
431 /**
432 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
433 * @hw: pointer to the HW structure
434 * @active: true to enable LPLU, false to disable
435 *
436 * Sets the LPLU D0 state according to the active flag. When
437 * activating LPLU this function also disables smart speed
438 * and vice versa. LPLU will not be activated unless the
439 * device autonegotiation advertisement meets standards of
440 * either 10 or 10/100 or 10/100/1000 at all duplexes.
441 * This is a function pointer entry point only called by
442 * PHY setup routines.
443 **/
444 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
445 {
446 struct e1000_phy_info *phy = &hw->phy;
447 s32 ret_val;
448 u16 data;
449
450 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
451 if (ret_val)
452 goto out;
453
454 if (active) {
455 data |= IGP02E1000_PM_D0_LPLU;
456 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
457 data);
458 if (ret_val)
459 goto out;
460
461 /* When LPLU is enabled, we should disable SmartSpeed */
462 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
463 &data);
464 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
465 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
466 data);
467 if (ret_val)
468 goto out;
469 } else {
470 data &= ~IGP02E1000_PM_D0_LPLU;
471 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
472 data);
473 /*
474 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
475 * during Dx states where the power conservation is most
476 * important. During driver activity we should enable
477 * SmartSpeed, so performance is maintained.
478 */
479 if (phy->smart_speed == e1000_smart_speed_on) {
480 ret_val = phy->ops.read_reg(hw,
481 IGP01E1000_PHY_PORT_CONFIG, &data);
482 if (ret_val)
483 goto out;
484
485 data |= IGP01E1000_PSCFR_SMART_SPEED;
486 ret_val = phy->ops.write_reg(hw,
487 IGP01E1000_PHY_PORT_CONFIG, data);
488 if (ret_val)
489 goto out;
490 } else if (phy->smart_speed == e1000_smart_speed_off) {
491 ret_val = phy->ops.read_reg(hw,
492 IGP01E1000_PHY_PORT_CONFIG, &data);
493 if (ret_val)
494 goto out;
495
496 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
497 ret_val = phy->ops.write_reg(hw,
498 IGP01E1000_PHY_PORT_CONFIG, data);
499 if (ret_val)
500 goto out;
501 }
502 }
503
504 out:
505 return ret_val;
506 }
507
508 /**
509 * igb_acquire_nvm_82575 - Request for access to EEPROM
510 * @hw: pointer to the HW structure
511 *
512 * Acquire the necessary semaphores for exclusive access to the EEPROM.
513 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
514 * Return successful if access grant bit set, else clear the request for
515 * EEPROM access and return -E1000_ERR_NVM (-1).
516 **/
517 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
518 {
519 s32 ret_val;
520
521 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
522 if (ret_val)
523 goto out;
524
525 ret_val = igb_acquire_nvm(hw);
526
527 if (ret_val)
528 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
529
530 out:
531 return ret_val;
532 }
533
534 /**
535 * igb_release_nvm_82575 - Release exclusive access to EEPROM
536 * @hw: pointer to the HW structure
537 *
538 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
539 * then release the semaphores acquired.
540 **/
541 static void igb_release_nvm_82575(struct e1000_hw *hw)
542 {
543 igb_release_nvm(hw);
544 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
545 }
546
547 /**
548 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
549 * @hw: pointer to the HW structure
550 * @mask: specifies which semaphore to acquire
551 *
552 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
553 * will also specify which port we're acquiring the lock for.
554 **/
555 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
556 {
557 u32 swfw_sync;
558 u32 swmask = mask;
559 u32 fwmask = mask << 16;
560 s32 ret_val = 0;
561 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
562
563 while (i < timeout) {
564 if (igb_get_hw_semaphore(hw)) {
565 ret_val = -E1000_ERR_SWFW_SYNC;
566 goto out;
567 }
568
569 swfw_sync = rd32(E1000_SW_FW_SYNC);
570 if (!(swfw_sync & (fwmask | swmask)))
571 break;
572
573 /*
574 * Firmware currently using resource (fwmask)
575 * or other software thread using resource (swmask)
576 */
577 igb_put_hw_semaphore(hw);
578 mdelay(5);
579 i++;
580 }
581
582 if (i == timeout) {
583 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
584 ret_val = -E1000_ERR_SWFW_SYNC;
585 goto out;
586 }
587
588 swfw_sync |= swmask;
589 wr32(E1000_SW_FW_SYNC, swfw_sync);
590
591 igb_put_hw_semaphore(hw);
592
593 out:
594 return ret_val;
595 }
596
597 /**
598 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
599 * @hw: pointer to the HW structure
600 * @mask: specifies which semaphore to acquire
601 *
602 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
603 * will also specify which port we're releasing the lock for.
604 **/
605 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
606 {
607 u32 swfw_sync;
608
609 while (igb_get_hw_semaphore(hw) != 0);
610 /* Empty */
611
612 swfw_sync = rd32(E1000_SW_FW_SYNC);
613 swfw_sync &= ~mask;
614 wr32(E1000_SW_FW_SYNC, swfw_sync);
615
616 igb_put_hw_semaphore(hw);
617 }
618
619 /**
620 * igb_get_cfg_done_82575 - Read config done bit
621 * @hw: pointer to the HW structure
622 *
623 * Read the management control register for the config done bit for
624 * completion status. NOTE: silicon which is EEPROM-less will fail trying
625 * to read the config done bit, so an error is *ONLY* logged and returns
626 * 0. If we were to return with error, EEPROM-less silicon
627 * would not be able to be reset or change link.
628 **/
629 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
630 {
631 s32 timeout = PHY_CFG_TIMEOUT;
632 s32 ret_val = 0;
633 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
634
635 if (hw->bus.func == 1)
636 mask = E1000_NVM_CFG_DONE_PORT_1;
637
638 while (timeout) {
639 if (rd32(E1000_EEMNGCTL) & mask)
640 break;
641 msleep(1);
642 timeout--;
643 }
644 if (!timeout)
645 hw_dbg("MNG configuration cycle has not completed.\n");
646
647 /* If EEPROM is not marked present, init the PHY manually */
648 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
649 (hw->phy.type == e1000_phy_igp_3))
650 igb_phy_init_script_igp3(hw);
651
652 return ret_val;
653 }
654
655 /**
656 * igb_check_for_link_82575 - Check for link
657 * @hw: pointer to the HW structure
658 *
659 * If sgmii is enabled, then use the pcs register to determine link, otherwise
660 * use the generic interface for determining link.
661 **/
662 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
663 {
664 s32 ret_val;
665 u16 speed, duplex;
666
667 if (hw->phy.media_type != e1000_media_type_copper) {
668 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
669 &duplex);
670 /*
671 * Use this flag to determine if link needs to be checked or
672 * not. If we have link clear the flag so that we do not
673 * continue to check for link.
674 */
675 hw->mac.get_link_status = !hw->mac.serdes_has_link;
676 } else {
677 ret_val = igb_check_for_copper_link(hw);
678 }
679
680 return ret_val;
681 }
682
683 /**
684 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
685 * @hw: pointer to the HW structure
686 * @speed: stores the current speed
687 * @duplex: stores the current duplex
688 *
689 * Using the physical coding sub-layer (PCS), retrieve the current speed and
690 * duplex, then store the values in the pointers provided.
691 **/
692 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
693 u16 *duplex)
694 {
695 struct e1000_mac_info *mac = &hw->mac;
696 u32 pcs;
697
698 /* Set up defaults for the return values of this function */
699 mac->serdes_has_link = false;
700 *speed = 0;
701 *duplex = 0;
702
703 /*
704 * Read the PCS Status register for link state. For non-copper mode,
705 * the status register is not accurate. The PCS status register is
706 * used instead.
707 */
708 pcs = rd32(E1000_PCS_LSTAT);
709
710 /*
711 * The link up bit determines when link is up on autoneg. The sync ok
712 * gets set once both sides sync up and agree upon link. Stable link
713 * can be determined by checking for both link up and link sync ok
714 */
715 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
716 mac->serdes_has_link = true;
717
718 /* Detect and store PCS speed */
719 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
720 *speed = SPEED_1000;
721 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
722 *speed = SPEED_100;
723 } else {
724 *speed = SPEED_10;
725 }
726
727 /* Detect and store PCS duplex */
728 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
729 *duplex = FULL_DUPLEX;
730 } else {
731 *duplex = HALF_DUPLEX;
732 }
733 }
734
735 return 0;
736 }
737
738 /**
739 * igb_shutdown_serdes_link_82575 - Remove link during power down
740 * @hw: pointer to the HW structure
741 *
742 * In the case of fiber serdes, shut down optics and PCS on driver unload
743 * when management pass thru is not enabled.
744 **/
745 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
746 {
747 u32 reg;
748 u16 eeprom_data = 0;
749
750 if (hw->phy.media_type != e1000_media_type_internal_serdes ||
751 igb_sgmii_active_82575(hw))
752 return;
753
754 if (hw->bus.func == E1000_FUNC_0)
755 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
756 else if (hw->bus.func == E1000_FUNC_1)
757 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
758
759 /*
760 * If APM is not enabled in the EEPROM and management interface is
761 * not enabled, then power down.
762 */
763 if (!(eeprom_data & E1000_NVM_APME_82575) &&
764 !igb_enable_mng_pass_thru(hw)) {
765 /* Disable PCS to turn off link */
766 reg = rd32(E1000_PCS_CFG0);
767 reg &= ~E1000_PCS_CFG_PCS_EN;
768 wr32(E1000_PCS_CFG0, reg);
769
770 /* shutdown the laser */
771 reg = rd32(E1000_CTRL_EXT);
772 reg |= E1000_CTRL_EXT_SDP3_DATA;
773 wr32(E1000_CTRL_EXT, reg);
774
775 /* flush the write to verify completion */
776 wrfl();
777 msleep(1);
778 }
779
780 return;
781 }
782
783 /**
784 * igb_reset_hw_82575 - Reset hardware
785 * @hw: pointer to the HW structure
786 *
787 * This resets the hardware into a known state. This is a
788 * function pointer entry point called by the api module.
789 **/
790 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
791 {
792 u32 ctrl, icr;
793 s32 ret_val;
794
795 /*
796 * Prevent the PCI-E bus from sticking if there is no TLP connection
797 * on the last TLP read/write transaction when MAC is reset.
798 */
799 ret_val = igb_disable_pcie_master(hw);
800 if (ret_val)
801 hw_dbg("PCI-E Master disable polling has failed.\n");
802
803 /* set the completion timeout for interface */
804 ret_val = igb_set_pcie_completion_timeout(hw);
805 if (ret_val) {
806 hw_dbg("PCI-E Set completion timeout has failed.\n");
807 }
808
809 hw_dbg("Masking off all interrupts\n");
810 wr32(E1000_IMC, 0xffffffff);
811
812 wr32(E1000_RCTL, 0);
813 wr32(E1000_TCTL, E1000_TCTL_PSP);
814 wrfl();
815
816 msleep(10);
817
818 ctrl = rd32(E1000_CTRL);
819
820 hw_dbg("Issuing a global reset to MAC\n");
821 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
822
823 ret_val = igb_get_auto_rd_done(hw);
824 if (ret_val) {
825 /*
826 * When auto config read does not complete, do not
827 * return with an error. This can happen in situations
828 * where there is no eeprom and prevents getting link.
829 */
830 hw_dbg("Auto Read Done did not complete\n");
831 }
832
833 /* If EEPROM is not present, run manual init scripts */
834 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
835 igb_reset_init_script_82575(hw);
836
837 /* Clear any pending interrupt events. */
838 wr32(E1000_IMC, 0xffffffff);
839 icr = rd32(E1000_ICR);
840
841 /* Install any alternate MAC address into RAR0 */
842 ret_val = igb_check_alt_mac_addr(hw);
843
844 return ret_val;
845 }
846
847 /**
848 * igb_init_hw_82575 - Initialize hardware
849 * @hw: pointer to the HW structure
850 *
851 * This inits the hardware readying it for operation.
852 **/
853 static s32 igb_init_hw_82575(struct e1000_hw *hw)
854 {
855 struct e1000_mac_info *mac = &hw->mac;
856 s32 ret_val;
857 u16 i, rar_count = mac->rar_entry_count;
858
859 /* Initialize identification LED */
860 ret_val = igb_id_led_init(hw);
861 if (ret_val) {
862 hw_dbg("Error initializing identification LED\n");
863 /* This is not fatal and we should not stop init due to this */
864 }
865
866 /* Disabling VLAN filtering */
867 hw_dbg("Initializing the IEEE VLAN\n");
868 igb_clear_vfta(hw);
869
870 /* Setup the receive address */
871 igb_init_rx_addrs(hw, rar_count);
872
873 /* Zero out the Multicast HASH table */
874 hw_dbg("Zeroing the MTA\n");
875 for (i = 0; i < mac->mta_reg_count; i++)
876 array_wr32(E1000_MTA, i, 0);
877
878 /* Zero out the Unicast HASH table */
879 hw_dbg("Zeroing the UTA\n");
880 for (i = 0; i < mac->uta_reg_count; i++)
881 array_wr32(E1000_UTA, i, 0);
882
883 /* Setup link and flow control */
884 ret_val = igb_setup_link(hw);
885
886 /*
887 * Clear all of the statistics registers (clear on read). It is
888 * important that we do this after we have tried to establish link
889 * because the symbol error count will increment wildly if there
890 * is no link.
891 */
892 igb_clear_hw_cntrs_82575(hw);
893
894 return ret_val;
895 }
896
897 /**
898 * igb_setup_copper_link_82575 - Configure copper link settings
899 * @hw: pointer to the HW structure
900 *
901 * Configures the link for auto-neg or forced speed and duplex. Then we check
902 * for link, once link is established calls to configure collision distance
903 * and flow control are called.
904 **/
905 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
906 {
907 u32 ctrl;
908 s32 ret_val;
909 bool link;
910
911 ctrl = rd32(E1000_CTRL);
912 ctrl |= E1000_CTRL_SLU;
913 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
914 wr32(E1000_CTRL, ctrl);
915
916 ret_val = igb_setup_serdes_link_82575(hw);
917 if (ret_val)
918 goto out;
919
920 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
921 ret_val = hw->phy.ops.reset(hw);
922 if (ret_val) {
923 hw_dbg("Error resetting the PHY.\n");
924 goto out;
925 }
926 }
927 switch (hw->phy.type) {
928 case e1000_phy_m88:
929 ret_val = igb_copper_link_setup_m88(hw);
930 break;
931 case e1000_phy_igp_3:
932 ret_val = igb_copper_link_setup_igp(hw);
933 break;
934 default:
935 ret_val = -E1000_ERR_PHY;
936 break;
937 }
938
939 if (ret_val)
940 goto out;
941
942 if (hw->mac.autoneg) {
943 /*
944 * Setup autoneg and flow control advertisement
945 * and perform autonegotiation.
946 */
947 ret_val = igb_copper_link_autoneg(hw);
948 if (ret_val)
949 goto out;
950 } else {
951 /*
952 * PHY will be set to 10H, 10F, 100H or 100F
953 * depending on user settings.
954 */
955 hw_dbg("Forcing Speed and Duplex\n");
956 ret_val = hw->phy.ops.force_speed_duplex(hw);
957 if (ret_val) {
958 hw_dbg("Error Forcing Speed and Duplex\n");
959 goto out;
960 }
961 }
962
963 /*
964 * Check link status. Wait up to 100 microseconds for link to become
965 * valid.
966 */
967 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
968 if (ret_val)
969 goto out;
970
971 if (link) {
972 hw_dbg("Valid link established!!!\n");
973 /* Config the MAC and PHY after link is up */
974 igb_config_collision_dist(hw);
975 ret_val = igb_config_fc_after_link_up(hw);
976 } else {
977 hw_dbg("Unable to establish link!!!\n");
978 }
979
980 out:
981 return ret_val;
982 }
983
984 /**
985 * igb_setup_serdes_link_82575 - Setup link for serdes
986 * @hw: pointer to the HW structure
987 *
988 * Configure the physical coding sub-layer (PCS) link. The PCS link is
989 * used on copper connections where the serialized gigabit media independent
990 * interface (sgmii), or serdes fiber is being used. Configures the link
991 * for auto-negotiation or forces speed/duplex.
992 **/
993 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
994 {
995 u32 ctrl_reg, reg;
996
997 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
998 !igb_sgmii_active_82575(hw))
999 return 0;
1000
1001 /*
1002 * On the 82575, SerDes loopback mode persists until it is
1003 * explicitly turned off or a power cycle is performed. A read to
1004 * the register does not indicate its status. Therefore, we ensure
1005 * loopback mode is disabled during initialization.
1006 */
1007 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1008
1009 /* power on the sfp cage if present */
1010 reg = rd32(E1000_CTRL_EXT);
1011 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1012 wr32(E1000_CTRL_EXT, reg);
1013
1014 ctrl_reg = rd32(E1000_CTRL);
1015 ctrl_reg |= E1000_CTRL_SLU;
1016
1017 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1018 /* set both sw defined pins */
1019 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1020
1021 /* Set switch control to serdes energy detect */
1022 reg = rd32(E1000_CONNSW);
1023 reg |= E1000_CONNSW_ENRGSRC;
1024 wr32(E1000_CONNSW, reg);
1025 }
1026
1027 reg = rd32(E1000_PCS_LCTL);
1028
1029 if (igb_sgmii_active_82575(hw)) {
1030 /* allow time for SFP cage to power up phy */
1031 msleep(300);
1032
1033 /* AN time out should be disabled for SGMII mode */
1034 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1035 } else {
1036 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1037 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1038 }
1039
1040 wr32(E1000_CTRL, ctrl_reg);
1041
1042 /*
1043 * New SerDes mode allows for forcing speed or autonegotiating speed
1044 * at 1gb. Autoneg should be default set by most drivers. This is the
1045 * mode that will be compatible with older link partners and switches.
1046 * However, both are supported by the hardware and some drivers/tools.
1047 */
1048
1049 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1050 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1051
1052 /*
1053 * We force flow control to prevent the CTRL register values from being
1054 * overwritten by the autonegotiated flow control values
1055 */
1056 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1057
1058 /*
1059 * we always set sgmii to autoneg since it is the phy that will be
1060 * forcing the link and the serdes is just a go-between
1061 */
1062 if (hw->mac.autoneg || igb_sgmii_active_82575(hw)) {
1063 /* Set PCS register for autoneg */
1064 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1065 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full dplx */
1066 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1067 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1068 hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1069 } else {
1070 /* Check for duplex first */
1071 if (hw->mac.forced_speed_duplex & E1000_ALL_FULL_DUPLEX)
1072 reg |= E1000_PCS_LCTL_FDV_FULL;
1073
1074 /* No need to check for 1000/full since the spec states that
1075 * it requires autoneg to be enabled */
1076 /* Now set speed */
1077 if (hw->mac.forced_speed_duplex & E1000_ALL_100_SPEED)
1078 reg |= E1000_PCS_LCTL_FSV_100;
1079
1080 /* Force speed and force link */
1081 reg |= E1000_PCS_LCTL_FSD |
1082 E1000_PCS_LCTL_FORCE_LINK |
1083 E1000_PCS_LCTL_FLV_LINK_UP;
1084
1085 hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
1086 }
1087
1088 wr32(E1000_PCS_LCTL, reg);
1089
1090 if (!igb_sgmii_active_82575(hw))
1091 igb_force_mac_fc(hw);
1092
1093 return 0;
1094 }
1095
1096 /**
1097 * igb_sgmii_active_82575 - Return sgmii state
1098 * @hw: pointer to the HW structure
1099 *
1100 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1101 * which can be enabled for use in the embedded applications. Simply
1102 * return the current state of the sgmii interface.
1103 **/
1104 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1105 {
1106 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1107 return dev_spec->sgmii_active;
1108 }
1109
1110 /**
1111 * igb_reset_init_script_82575 - Inits HW defaults after reset
1112 * @hw: pointer to the HW structure
1113 *
1114 * Inits recommended HW defaults after a reset when there is no EEPROM
1115 * detected. This is only for the 82575.
1116 **/
1117 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1118 {
1119 if (hw->mac.type == e1000_82575) {
1120 hw_dbg("Running reset init script for 82575\n");
1121 /* SerDes configuration via SERDESCTRL */
1122 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1123 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1124 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1125 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1126
1127 /* CCM configuration via CCMCTL register */
1128 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1129 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1130
1131 /* PCIe lanes configuration */
1132 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1133 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1134 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1135 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1136
1137 /* PCIe PLL Configuration */
1138 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1139 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1140 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1141 }
1142
1143 return 0;
1144 }
1145
1146 /**
1147 * igb_read_mac_addr_82575 - Read device MAC address
1148 * @hw: pointer to the HW structure
1149 **/
1150 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1151 {
1152 s32 ret_val = 0;
1153
1154 if (igb_check_alt_mac_addr(hw))
1155 ret_val = igb_read_mac_addr(hw);
1156
1157 return ret_val;
1158 }
1159
1160 /**
1161 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1162 * @hw: pointer to the HW structure
1163 *
1164 * Clears the hardware counters by reading the counter registers.
1165 **/
1166 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1167 {
1168 igb_clear_hw_cntrs_base(hw);
1169
1170 rd32(E1000_PRC64);
1171 rd32(E1000_PRC127);
1172 rd32(E1000_PRC255);
1173 rd32(E1000_PRC511);
1174 rd32(E1000_PRC1023);
1175 rd32(E1000_PRC1522);
1176 rd32(E1000_PTC64);
1177 rd32(E1000_PTC127);
1178 rd32(E1000_PTC255);
1179 rd32(E1000_PTC511);
1180 rd32(E1000_PTC1023);
1181 rd32(E1000_PTC1522);
1182
1183 rd32(E1000_ALGNERRC);
1184 rd32(E1000_RXERRC);
1185 rd32(E1000_TNCRS);
1186 rd32(E1000_CEXTERR);
1187 rd32(E1000_TSCTC);
1188 rd32(E1000_TSCTFC);
1189
1190 rd32(E1000_MGTPRC);
1191 rd32(E1000_MGTPDC);
1192 rd32(E1000_MGTPTC);
1193
1194 rd32(E1000_IAC);
1195 rd32(E1000_ICRXOC);
1196
1197 rd32(E1000_ICRXPTC);
1198 rd32(E1000_ICRXATC);
1199 rd32(E1000_ICTXPTC);
1200 rd32(E1000_ICTXATC);
1201 rd32(E1000_ICTXQEC);
1202 rd32(E1000_ICTXQMTC);
1203 rd32(E1000_ICRXDMTC);
1204
1205 rd32(E1000_CBTMPC);
1206 rd32(E1000_HTDPMC);
1207 rd32(E1000_CBRMPC);
1208 rd32(E1000_RPTHC);
1209 rd32(E1000_HGPTC);
1210 rd32(E1000_HTCBDPC);
1211 rd32(E1000_HGORCL);
1212 rd32(E1000_HGORCH);
1213 rd32(E1000_HGOTCL);
1214 rd32(E1000_HGOTCH);
1215 rd32(E1000_LENERRS);
1216
1217 /* This register should not be read in copper configurations */
1218 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1219 igb_sgmii_active_82575(hw))
1220 rd32(E1000_SCVPC);
1221 }
1222
1223 /**
1224 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1225 * @hw: pointer to the HW structure
1226 *
1227 * After rx enable if managability is enabled then there is likely some
1228 * bad data at the start of the fifo and possibly in the DMA fifo. This
1229 * function clears the fifos and flushes any packets that came in as rx was
1230 * being enabled.
1231 **/
1232 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1233 {
1234 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1235 int i, ms_wait;
1236
1237 if (hw->mac.type != e1000_82575 ||
1238 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1239 return;
1240
1241 /* Disable all RX queues */
1242 for (i = 0; i < 4; i++) {
1243 rxdctl[i] = rd32(E1000_RXDCTL(i));
1244 wr32(E1000_RXDCTL(i),
1245 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1246 }
1247 /* Poll all queues to verify they have shut down */
1248 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1249 msleep(1);
1250 rx_enabled = 0;
1251 for (i = 0; i < 4; i++)
1252 rx_enabled |= rd32(E1000_RXDCTL(i));
1253 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1254 break;
1255 }
1256
1257 if (ms_wait == 10)
1258 hw_dbg("Queue disable timed out after 10ms\n");
1259
1260 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1261 * incoming packets are rejected. Set enable and wait 2ms so that
1262 * any packet that was coming in as RCTL.EN was set is flushed
1263 */
1264 rfctl = rd32(E1000_RFCTL);
1265 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1266
1267 rlpml = rd32(E1000_RLPML);
1268 wr32(E1000_RLPML, 0);
1269
1270 rctl = rd32(E1000_RCTL);
1271 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1272 temp_rctl |= E1000_RCTL_LPE;
1273
1274 wr32(E1000_RCTL, temp_rctl);
1275 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1276 wrfl();
1277 msleep(2);
1278
1279 /* Enable RX queues that were previously enabled and restore our
1280 * previous state
1281 */
1282 for (i = 0; i < 4; i++)
1283 wr32(E1000_RXDCTL(i), rxdctl[i]);
1284 wr32(E1000_RCTL, rctl);
1285 wrfl();
1286
1287 wr32(E1000_RLPML, rlpml);
1288 wr32(E1000_RFCTL, rfctl);
1289
1290 /* Flush receive errors generated by workaround */
1291 rd32(E1000_ROC);
1292 rd32(E1000_RNBC);
1293 rd32(E1000_MPC);
1294 }
1295
1296 /**
1297 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1298 * @hw: pointer to the HW structure
1299 *
1300 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1301 * however the hardware default for these parts is 500us to 1ms which is less
1302 * than the 10ms recommended by the pci-e spec. To address this we need to
1303 * increase the value to either 10ms to 200ms for capability version 1 config,
1304 * or 16ms to 55ms for version 2.
1305 **/
1306 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1307 {
1308 u32 gcr = rd32(E1000_GCR);
1309 s32 ret_val = 0;
1310 u16 pcie_devctl2;
1311
1312 /* only take action if timeout value is defaulted to 0 */
1313 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1314 goto out;
1315
1316 /*
1317 * if capababilities version is type 1 we can write the
1318 * timeout of 10ms to 200ms through the GCR register
1319 */
1320 if (!(gcr & E1000_GCR_CAP_VER2)) {
1321 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1322 goto out;
1323 }
1324
1325 /*
1326 * for version 2 capabilities we need to write the config space
1327 * directly in order to set the completion timeout value for
1328 * 16ms to 55ms
1329 */
1330 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1331 &pcie_devctl2);
1332 if (ret_val)
1333 goto out;
1334
1335 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1336
1337 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1338 &pcie_devctl2);
1339 out:
1340 /* disable completion timeout resend */
1341 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1342
1343 wr32(E1000_GCR, gcr);
1344 return ret_val;
1345 }
1346
1347 /**
1348 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1349 * @hw: pointer to the hardware struct
1350 * @enable: state to enter, either enabled or disabled
1351 *
1352 * enables/disables L2 switch loopback functionality.
1353 **/
1354 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1355 {
1356 u32 dtxswc = rd32(E1000_DTXSWC);
1357
1358 if (enable)
1359 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1360 else
1361 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1362
1363 wr32(E1000_DTXSWC, dtxswc);
1364 }
1365
1366 /**
1367 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1368 * @hw: pointer to the hardware struct
1369 * @enable: state to enter, either enabled or disabled
1370 *
1371 * enables/disables replication of packets across multiple pools.
1372 **/
1373 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1374 {
1375 u32 vt_ctl = rd32(E1000_VT_CTL);
1376
1377 if (enable)
1378 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1379 else
1380 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1381
1382 wr32(E1000_VT_CTL, vt_ctl);
1383 }
1384
1385 static struct e1000_mac_operations e1000_mac_ops_82575 = {
1386 .reset_hw = igb_reset_hw_82575,
1387 .init_hw = igb_init_hw_82575,
1388 .check_for_link = igb_check_for_link_82575,
1389 .rar_set = igb_rar_set,
1390 .read_mac_addr = igb_read_mac_addr_82575,
1391 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1392 };
1393
1394 static struct e1000_phy_operations e1000_phy_ops_82575 = {
1395 .acquire = igb_acquire_phy_82575,
1396 .get_cfg_done = igb_get_cfg_done_82575,
1397 .release = igb_release_phy_82575,
1398 };
1399
1400 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
1401 .acquire = igb_acquire_nvm_82575,
1402 .read = igb_read_nvm_eerd,
1403 .release = igb_release_nvm_82575,
1404 .write = igb_write_nvm_spi,
1405 };
1406
1407 const struct e1000_info e1000_82575_info = {
1408 .get_invariants = igb_get_invariants_82575,
1409 .mac_ops = &e1000_mac_ops_82575,
1410 .phy_ops = &e1000_phy_ops_82575,
1411 .nvm_ops = &e1000_nvm_ops_82575,
1412 };
1413
Linux kernel - Deliverables
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