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igb: update the approach taken to acquiring and releasing the phy lock
[deliverable/linux.git] / drivers / net / igb / e1000_82575.c
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 /* e1000_82575
29 * e1000_82576
30 */
31
32 #include <linux/types.h>
33 #include <linux/slab.h>
34 #include <linux/if_ether.h>
35
36 #include "e1000_mac.h"
37 #include "e1000_82575.h"
38
39 static s32 igb_get_invariants_82575(struct e1000_hw *);
40 static s32 igb_acquire_phy_82575(struct e1000_hw *);
41 static void igb_release_phy_82575(struct e1000_hw *);
42 static s32 igb_acquire_nvm_82575(struct e1000_hw *);
43 static void igb_release_nvm_82575(struct e1000_hw *);
44 static s32 igb_check_for_link_82575(struct e1000_hw *);
45 static s32 igb_get_cfg_done_82575(struct e1000_hw *);
46 static s32 igb_init_hw_82575(struct e1000_hw *);
47 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
48 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
49 static s32 igb_reset_hw_82575(struct e1000_hw *);
50 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
51 static s32 igb_setup_copper_link_82575(struct e1000_hw *);
52 static s32 igb_setup_serdes_link_82575(struct e1000_hw *);
53 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
54 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
55 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
56 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
57 u16 *);
58 static s32 igb_get_phy_id_82575(struct e1000_hw *);
59 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
60 static bool igb_sgmii_active_82575(struct e1000_hw *);
61 static s32 igb_reset_init_script_82575(struct e1000_hw *);
62 static s32 igb_read_mac_addr_82575(struct e1000_hw *);
63 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
64
65 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
66 {
67 struct e1000_phy_info *phy = &hw->phy;
68 struct e1000_nvm_info *nvm = &hw->nvm;
69 struct e1000_mac_info *mac = &hw->mac;
70 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
71 u32 eecd;
72 s32 ret_val;
73 u16 size;
74 u32 ctrl_ext = 0;
75
76 switch (hw->device_id) {
77 case E1000_DEV_ID_82575EB_COPPER:
78 case E1000_DEV_ID_82575EB_FIBER_SERDES:
79 case E1000_DEV_ID_82575GB_QUAD_COPPER:
80 mac->type = e1000_82575;
81 break;
82 case E1000_DEV_ID_82576:
83 case E1000_DEV_ID_82576_NS:
84 case E1000_DEV_ID_82576_FIBER:
85 case E1000_DEV_ID_82576_SERDES:
86 case E1000_DEV_ID_82576_QUAD_COPPER:
87 case E1000_DEV_ID_82576_SERDES_QUAD:
88 mac->type = e1000_82576;
89 break;
90 default:
91 return -E1000_ERR_MAC_INIT;
92 break;
93 }
94
95 /* Set media type */
96 /*
97 * The 82575 uses bits 22:23 for link mode. The mode can be changed
98 * based on the EEPROM. We cannot rely upon device ID. There
99 * is no distinguishable difference between fiber and internal
100 * SerDes mode on the 82575. There can be an external PHY attached
101 * on the SGMII interface. For this, we'll set sgmii_active to true.
102 */
103 phy->media_type = e1000_media_type_copper;
104 dev_spec->sgmii_active = false;
105
106 ctrl_ext = rd32(E1000_CTRL_EXT);
107 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
108 case E1000_CTRL_EXT_LINK_MODE_SGMII:
109 dev_spec->sgmii_active = true;
110 ctrl_ext |= E1000_CTRL_I2C_ENA;
111 break;
112 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
113 hw->phy.media_type = e1000_media_type_internal_serdes;
114 ctrl_ext |= E1000_CTRL_I2C_ENA;
115 break;
116 default:
117 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
118 break;
119 }
120
121 wr32(E1000_CTRL_EXT, ctrl_ext);
122
123 /* Set mta register count */
124 mac->mta_reg_count = 128;
125 /* Set rar entry count */
126 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
127 if (mac->type == e1000_82576)
128 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
129 /* Set if part includes ASF firmware */
130 mac->asf_firmware_present = true;
131 /* Set if manageability features are enabled. */
132 mac->arc_subsystem_valid =
133 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
134 ? true : false;
135
136 /* physical interface link setup */
137 mac->ops.setup_physical_interface =
138 (hw->phy.media_type == e1000_media_type_copper)
139 ? igb_setup_copper_link_82575
140 : igb_setup_serdes_link_82575;
141
142 /* NVM initialization */
143 eecd = rd32(E1000_EECD);
144
145 nvm->opcode_bits = 8;
146 nvm->delay_usec = 1;
147 switch (nvm->override) {
148 case e1000_nvm_override_spi_large:
149 nvm->page_size = 32;
150 nvm->address_bits = 16;
151 break;
152 case e1000_nvm_override_spi_small:
153 nvm->page_size = 8;
154 nvm->address_bits = 8;
155 break;
156 default:
157 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
158 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
159 break;
160 }
161
162 nvm->type = e1000_nvm_eeprom_spi;
163
164 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
165 E1000_EECD_SIZE_EX_SHIFT);
166
167 /*
168 * Added to a constant, "size" becomes the left-shift value
169 * for setting word_size.
170 */
171 size += NVM_WORD_SIZE_BASE_SHIFT;
172
173 /* EEPROM access above 16k is unsupported */
174 if (size > 14)
175 size = 14;
176 nvm->word_size = 1 << size;
177
178 /* if 82576 then initialize mailbox parameters */
179 if (mac->type == e1000_82576)
180 igb_init_mbx_params_pf(hw);
181
182 /* setup PHY parameters */
183 if (phy->media_type != e1000_media_type_copper) {
184 phy->type = e1000_phy_none;
185 return 0;
186 }
187
188 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
189 phy->reset_delay_us = 100;
190
191 /* PHY function pointers */
192 if (igb_sgmii_active_82575(hw)) {
193 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
194 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
195 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
196 } else {
197 phy->ops.reset = igb_phy_hw_reset;
198 phy->ops.read_reg = igb_read_phy_reg_igp;
199 phy->ops.write_reg = igb_write_phy_reg_igp;
200 }
201
202 /* set lan id */
203 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
204 E1000_STATUS_FUNC_SHIFT;
205
206 /* Set phy->phy_addr and phy->id. */
207 ret_val = igb_get_phy_id_82575(hw);
208 if (ret_val)
209 return ret_val;
210
211 /* Verify phy id and set remaining function pointers */
212 switch (phy->id) {
213 case M88E1111_I_PHY_ID:
214 phy->type = e1000_phy_m88;
215 phy->ops.get_phy_info = igb_get_phy_info_m88;
216 phy->ops.get_cable_length = igb_get_cable_length_m88;
217 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
218 break;
219 case IGP03E1000_E_PHY_ID:
220 phy->type = e1000_phy_igp_3;
221 phy->ops.get_phy_info = igb_get_phy_info_igp;
222 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
223 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
224 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
225 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
226 break;
227 default:
228 return -E1000_ERR_PHY;
229 }
230
231 return 0;
232 }
233
234 /**
235 * igb_acquire_phy_82575 - Acquire rights to access PHY
236 * @hw: pointer to the HW structure
237 *
238 * Acquire access rights to the correct PHY. This is a
239 * function pointer entry point called by the api module.
240 **/
241 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
242 {
243 u16 mask = E1000_SWFW_PHY0_SM;
244
245 if (hw->bus.func == E1000_FUNC_1)
246 mask = E1000_SWFW_PHY1_SM;
247
248 return igb_acquire_swfw_sync_82575(hw, mask);
249 }
250
251 /**
252 * igb_release_phy_82575 - Release rights to access PHY
253 * @hw: pointer to the HW structure
254 *
255 * A wrapper to release access rights to the correct PHY. This is a
256 * function pointer entry point called by the api module.
257 **/
258 static void igb_release_phy_82575(struct e1000_hw *hw)
259 {
260 u16 mask = E1000_SWFW_PHY0_SM;
261
262 if (hw->bus.func == E1000_FUNC_1)
263 mask = E1000_SWFW_PHY1_SM;
264
265 igb_release_swfw_sync_82575(hw, mask);
266 }
267
268 /**
269 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
270 * @hw: pointer to the HW structure
271 * @offset: register offset to be read
272 * @data: pointer to the read data
273 *
274 * Reads the PHY register at offset using the serial gigabit media independent
275 * interface and stores the retrieved information in data.
276 **/
277 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
278 u16 *data)
279 {
280 struct e1000_phy_info *phy = &hw->phy;
281 u32 i, i2ccmd = 0;
282
283 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
284 hw_dbg("PHY Address %u is out of range\n", offset);
285 return -E1000_ERR_PARAM;
286 }
287
288 /*
289 * Set up Op-code, Phy Address, and register address in the I2CCMD
290 * register. The MAC will take care of interfacing with the
291 * PHY to retrieve the desired data.
292 */
293 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
294 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
295 (E1000_I2CCMD_OPCODE_READ));
296
297 wr32(E1000_I2CCMD, i2ccmd);
298
299 /* Poll the ready bit to see if the I2C read completed */
300 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
301 udelay(50);
302 i2ccmd = rd32(E1000_I2CCMD);
303 if (i2ccmd & E1000_I2CCMD_READY)
304 break;
305 }
306 if (!(i2ccmd & E1000_I2CCMD_READY)) {
307 hw_dbg("I2CCMD Read did not complete\n");
308 return -E1000_ERR_PHY;
309 }
310 if (i2ccmd & E1000_I2CCMD_ERROR) {
311 hw_dbg("I2CCMD Error bit set\n");
312 return -E1000_ERR_PHY;
313 }
314
315 /* Need to byte-swap the 16-bit value. */
316 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
317
318 return 0;
319 }
320
321 /**
322 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
323 * @hw: pointer to the HW structure
324 * @offset: register offset to write to
325 * @data: data to write at register offset
326 *
327 * Writes the data to PHY register at the offset using the serial gigabit
328 * media independent interface.
329 **/
330 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
331 u16 data)
332 {
333 struct e1000_phy_info *phy = &hw->phy;
334 u32 i, i2ccmd = 0;
335 u16 phy_data_swapped;
336
337 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
338 hw_dbg("PHY Address %d is out of range\n", offset);
339 return -E1000_ERR_PARAM;
340 }
341
342 /* Swap the data bytes for the I2C interface */
343 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
344
345 /*
346 * Set up Op-code, Phy Address, and register address in the I2CCMD
347 * register. The MAC will take care of interfacing with the
348 * PHY to retrieve the desired data.
349 */
350 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
351 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
352 E1000_I2CCMD_OPCODE_WRITE |
353 phy_data_swapped);
354
355 wr32(E1000_I2CCMD, i2ccmd);
356
357 /* Poll the ready bit to see if the I2C read completed */
358 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
359 udelay(50);
360 i2ccmd = rd32(E1000_I2CCMD);
361 if (i2ccmd & E1000_I2CCMD_READY)
362 break;
363 }
364 if (!(i2ccmd & E1000_I2CCMD_READY)) {
365 hw_dbg("I2CCMD Write did not complete\n");
366 return -E1000_ERR_PHY;
367 }
368 if (i2ccmd & E1000_I2CCMD_ERROR) {
369 hw_dbg("I2CCMD Error bit set\n");
370 return -E1000_ERR_PHY;
371 }
372
373 return 0;
374 }
375
376 /**
377 * igb_get_phy_id_82575 - Retrieve PHY addr and id
378 * @hw: pointer to the HW structure
379 *
380 * Retrieves the PHY address and ID for both PHY's which do and do not use
381 * sgmi interface.
382 **/
383 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
384 {
385 struct e1000_phy_info *phy = &hw->phy;
386 s32 ret_val = 0;
387 u16 phy_id;
388 u32 ctrl_ext;
389
390 /*
391 * For SGMII PHYs, we try the list of possible addresses until
392 * we find one that works. For non-SGMII PHYs
393 * (e.g. integrated copper PHYs), an address of 1 should
394 * work. The result of this function should mean phy->phy_addr
395 * and phy->id are set correctly.
396 */
397 if (!(igb_sgmii_active_82575(hw))) {
398 phy->addr = 1;
399 ret_val = igb_get_phy_id(hw);
400 goto out;
401 }
402
403 /* Power on sgmii phy if it is disabled */
404 ctrl_ext = rd32(E1000_CTRL_EXT);
405 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
406 wrfl();
407 msleep(300);
408
409 /*
410 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
411 * Therefore, we need to test 1-7
412 */
413 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
414 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
415 if (ret_val == 0) {
416 hw_dbg("Vendor ID 0x%08X read at address %u\n",
417 phy_id, phy->addr);
418 /*
419 * At the time of this writing, The M88 part is
420 * the only supported SGMII PHY product.
421 */
422 if (phy_id == M88_VENDOR)
423 break;
424 } else {
425 hw_dbg("PHY address %u was unreadable\n", phy->addr);
426 }
427 }
428
429 /* A valid PHY type couldn't be found. */
430 if (phy->addr == 8) {
431 phy->addr = 0;
432 ret_val = -E1000_ERR_PHY;
433 goto out;
434 } else {
435 ret_val = igb_get_phy_id(hw);
436 }
437
438 /* restore previous sfp cage power state */
439 wr32(E1000_CTRL_EXT, ctrl_ext);
440
441 out:
442 return ret_val;
443 }
444
445 /**
446 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
447 * @hw: pointer to the HW structure
448 *
449 * Resets the PHY using the serial gigabit media independent interface.
450 **/
451 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
452 {
453 s32 ret_val;
454
455 /*
456 * This isn't a true "hard" reset, but is the only reset
457 * available to us at this time.
458 */
459
460 hw_dbg("Soft resetting SGMII attached PHY...\n");
461
462 /*
463 * SFP documentation requires the following to configure the SPF module
464 * to work on SGMII. No further documentation is given.
465 */
466 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
467 if (ret_val)
468 goto out;
469
470 ret_val = igb_phy_sw_reset(hw);
471
472 out:
473 return ret_val;
474 }
475
476 /**
477 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
478 * @hw: pointer to the HW structure
479 * @active: true to enable LPLU, false to disable
480 *
481 * Sets the LPLU D0 state according to the active flag. When
482 * activating LPLU this function also disables smart speed
483 * and vice versa. LPLU will not be activated unless the
484 * device autonegotiation advertisement meets standards of
485 * either 10 or 10/100 or 10/100/1000 at all duplexes.
486 * This is a function pointer entry point only called by
487 * PHY setup routines.
488 **/
489 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
490 {
491 struct e1000_phy_info *phy = &hw->phy;
492 s32 ret_val;
493 u16 data;
494
495 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
496 if (ret_val)
497 goto out;
498
499 if (active) {
500 data |= IGP02E1000_PM_D0_LPLU;
501 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
502 data);
503 if (ret_val)
504 goto out;
505
506 /* When LPLU is enabled, we should disable SmartSpeed */
507 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
508 &data);
509 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
510 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
511 data);
512 if (ret_val)
513 goto out;
514 } else {
515 data &= ~IGP02E1000_PM_D0_LPLU;
516 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
517 data);
518 /*
519 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
520 * during Dx states where the power conservation is most
521 * important. During driver activity we should enable
522 * SmartSpeed, so performance is maintained.
523 */
524 if (phy->smart_speed == e1000_smart_speed_on) {
525 ret_val = phy->ops.read_reg(hw,
526 IGP01E1000_PHY_PORT_CONFIG, &data);
527 if (ret_val)
528 goto out;
529
530 data |= IGP01E1000_PSCFR_SMART_SPEED;
531 ret_val = phy->ops.write_reg(hw,
532 IGP01E1000_PHY_PORT_CONFIG, data);
533 if (ret_val)
534 goto out;
535 } else if (phy->smart_speed == e1000_smart_speed_off) {
536 ret_val = phy->ops.read_reg(hw,
537 IGP01E1000_PHY_PORT_CONFIG, &data);
538 if (ret_val)
539 goto out;
540
541 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
542 ret_val = phy->ops.write_reg(hw,
543 IGP01E1000_PHY_PORT_CONFIG, data);
544 if (ret_val)
545 goto out;
546 }
547 }
548
549 out:
550 return ret_val;
551 }
552
553 /**
554 * igb_acquire_nvm_82575 - Request for access to EEPROM
555 * @hw: pointer to the HW structure
556 *
557 * Acquire the necessary semaphores for exclusive access to the EEPROM.
558 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
559 * Return successful if access grant bit set, else clear the request for
560 * EEPROM access and return -E1000_ERR_NVM (-1).
561 **/
562 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
563 {
564 s32 ret_val;
565
566 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
567 if (ret_val)
568 goto out;
569
570 ret_val = igb_acquire_nvm(hw);
571
572 if (ret_val)
573 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
574
575 out:
576 return ret_val;
577 }
578
579 /**
580 * igb_release_nvm_82575 - Release exclusive access to EEPROM
581 * @hw: pointer to the HW structure
582 *
583 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
584 * then release the semaphores acquired.
585 **/
586 static void igb_release_nvm_82575(struct e1000_hw *hw)
587 {
588 igb_release_nvm(hw);
589 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
590 }
591
592 /**
593 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
594 * @hw: pointer to the HW structure
595 * @mask: specifies which semaphore to acquire
596 *
597 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
598 * will also specify which port we're acquiring the lock for.
599 **/
600 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
601 {
602 u32 swfw_sync;
603 u32 swmask = mask;
604 u32 fwmask = mask << 16;
605 s32 ret_val = 0;
606 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
607
608 while (i < timeout) {
609 if (igb_get_hw_semaphore(hw)) {
610 ret_val = -E1000_ERR_SWFW_SYNC;
611 goto out;
612 }
613
614 swfw_sync = rd32(E1000_SW_FW_SYNC);
615 if (!(swfw_sync & (fwmask | swmask)))
616 break;
617
618 /*
619 * Firmware currently using resource (fwmask)
620 * or other software thread using resource (swmask)
621 */
622 igb_put_hw_semaphore(hw);
623 mdelay(5);
624 i++;
625 }
626
627 if (i == timeout) {
628 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
629 ret_val = -E1000_ERR_SWFW_SYNC;
630 goto out;
631 }
632
633 swfw_sync |= swmask;
634 wr32(E1000_SW_FW_SYNC, swfw_sync);
635
636 igb_put_hw_semaphore(hw);
637
638 out:
639 return ret_val;
640 }
641
642 /**
643 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
644 * @hw: pointer to the HW structure
645 * @mask: specifies which semaphore to acquire
646 *
647 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
648 * will also specify which port we're releasing the lock for.
649 **/
650 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
651 {
652 u32 swfw_sync;
653
654 while (igb_get_hw_semaphore(hw) != 0);
655 /* Empty */
656
657 swfw_sync = rd32(E1000_SW_FW_SYNC);
658 swfw_sync &= ~mask;
659 wr32(E1000_SW_FW_SYNC, swfw_sync);
660
661 igb_put_hw_semaphore(hw);
662 }
663
664 /**
665 * igb_get_cfg_done_82575 - Read config done bit
666 * @hw: pointer to the HW structure
667 *
668 * Read the management control register for the config done bit for
669 * completion status. NOTE: silicon which is EEPROM-less will fail trying
670 * to read the config done bit, so an error is *ONLY* logged and returns
671 * 0. If we were to return with error, EEPROM-less silicon
672 * would not be able to be reset or change link.
673 **/
674 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
675 {
676 s32 timeout = PHY_CFG_TIMEOUT;
677 s32 ret_val = 0;
678 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
679
680 if (hw->bus.func == 1)
681 mask = E1000_NVM_CFG_DONE_PORT_1;
682
683 while (timeout) {
684 if (rd32(E1000_EEMNGCTL) & mask)
685 break;
686 msleep(1);
687 timeout--;
688 }
689 if (!timeout)
690 hw_dbg("MNG configuration cycle has not completed.\n");
691
692 /* If EEPROM is not marked present, init the PHY manually */
693 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
694 (hw->phy.type == e1000_phy_igp_3))
695 igb_phy_init_script_igp3(hw);
696
697 return ret_val;
698 }
699
700 /**
701 * igb_check_for_link_82575 - Check for link
702 * @hw: pointer to the HW structure
703 *
704 * If sgmii is enabled, then use the pcs register to determine link, otherwise
705 * use the generic interface for determining link.
706 **/
707 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
708 {
709 s32 ret_val;
710 u16 speed, duplex;
711
712 if (hw->phy.media_type != e1000_media_type_copper) {
713 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
714 &duplex);
715 /*
716 * Use this flag to determine if link needs to be checked or
717 * not. If we have link clear the flag so that we do not
718 * continue to check for link.
719 */
720 hw->mac.get_link_status = !hw->mac.serdes_has_link;
721 } else {
722 ret_val = igb_check_for_copper_link(hw);
723 }
724
725 return ret_val;
726 }
727
728 /**
729 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
730 * @hw: pointer to the HW structure
731 * @speed: stores the current speed
732 * @duplex: stores the current duplex
733 *
734 * Using the physical coding sub-layer (PCS), retrieve the current speed and
735 * duplex, then store the values in the pointers provided.
736 **/
737 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
738 u16 *duplex)
739 {
740 struct e1000_mac_info *mac = &hw->mac;
741 u32 pcs;
742
743 /* Set up defaults for the return values of this function */
744 mac->serdes_has_link = false;
745 *speed = 0;
746 *duplex = 0;
747
748 /*
749 * Read the PCS Status register for link state. For non-copper mode,
750 * the status register is not accurate. The PCS status register is
751 * used instead.
752 */
753 pcs = rd32(E1000_PCS_LSTAT);
754
755 /*
756 * The link up bit determines when link is up on autoneg. The sync ok
757 * gets set once both sides sync up and agree upon link. Stable link
758 * can be determined by checking for both link up and link sync ok
759 */
760 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
761 mac->serdes_has_link = true;
762
763 /* Detect and store PCS speed */
764 if (pcs & E1000_PCS_LSTS_SPEED_1000) {
765 *speed = SPEED_1000;
766 } else if (pcs & E1000_PCS_LSTS_SPEED_100) {
767 *speed = SPEED_100;
768 } else {
769 *speed = SPEED_10;
770 }
771
772 /* Detect and store PCS duplex */
773 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) {
774 *duplex = FULL_DUPLEX;
775 } else {
776 *duplex = HALF_DUPLEX;
777 }
778 }
779
780 return 0;
781 }
782
783 /**
784 * igb_shutdown_serdes_link_82575 - Remove link during power down
785 * @hw: pointer to the HW structure
786 *
787 * In the case of fiber serdes, shut down optics and PCS on driver unload
788 * when management pass thru is not enabled.
789 **/
790 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
791 {
792 u32 reg;
793 u16 eeprom_data = 0;
794
795 if (hw->phy.media_type != e1000_media_type_internal_serdes ||
796 igb_sgmii_active_82575(hw))
797 return;
798
799 if (hw->bus.func == E1000_FUNC_0)
800 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
801 else if (hw->bus.func == E1000_FUNC_1)
802 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
803
804 /*
805 * If APM is not enabled in the EEPROM and management interface is
806 * not enabled, then power down.
807 */
808 if (!(eeprom_data & E1000_NVM_APME_82575) &&
809 !igb_enable_mng_pass_thru(hw)) {
810 /* Disable PCS to turn off link */
811 reg = rd32(E1000_PCS_CFG0);
812 reg &= ~E1000_PCS_CFG_PCS_EN;
813 wr32(E1000_PCS_CFG0, reg);
814
815 /* shutdown the laser */
816 reg = rd32(E1000_CTRL_EXT);
817 reg |= E1000_CTRL_EXT_SDP3_DATA;
818 wr32(E1000_CTRL_EXT, reg);
819
820 /* flush the write to verify completion */
821 wrfl();
822 msleep(1);
823 }
824
825 return;
826 }
827
828 /**
829 * igb_reset_hw_82575 - Reset hardware
830 * @hw: pointer to the HW structure
831 *
832 * This resets the hardware into a known state. This is a
833 * function pointer entry point called by the api module.
834 **/
835 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
836 {
837 u32 ctrl, icr;
838 s32 ret_val;
839
840 /*
841 * Prevent the PCI-E bus from sticking if there is no TLP connection
842 * on the last TLP read/write transaction when MAC is reset.
843 */
844 ret_val = igb_disable_pcie_master(hw);
845 if (ret_val)
846 hw_dbg("PCI-E Master disable polling has failed.\n");
847
848 /* set the completion timeout for interface */
849 ret_val = igb_set_pcie_completion_timeout(hw);
850 if (ret_val) {
851 hw_dbg("PCI-E Set completion timeout has failed.\n");
852 }
853
854 hw_dbg("Masking off all interrupts\n");
855 wr32(E1000_IMC, 0xffffffff);
856
857 wr32(E1000_RCTL, 0);
858 wr32(E1000_TCTL, E1000_TCTL_PSP);
859 wrfl();
860
861 msleep(10);
862
863 ctrl = rd32(E1000_CTRL);
864
865 hw_dbg("Issuing a global reset to MAC\n");
866 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
867
868 ret_val = igb_get_auto_rd_done(hw);
869 if (ret_val) {
870 /*
871 * When auto config read does not complete, do not
872 * return with an error. This can happen in situations
873 * where there is no eeprom and prevents getting link.
874 */
875 hw_dbg("Auto Read Done did not complete\n");
876 }
877
878 /* If EEPROM is not present, run manual init scripts */
879 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
880 igb_reset_init_script_82575(hw);
881
882 /* Clear any pending interrupt events. */
883 wr32(E1000_IMC, 0xffffffff);
884 icr = rd32(E1000_ICR);
885
886 /* Install any alternate MAC address into RAR0 */
887 ret_val = igb_check_alt_mac_addr(hw);
888
889 return ret_val;
890 }
891
892 /**
893 * igb_init_hw_82575 - Initialize hardware
894 * @hw: pointer to the HW structure
895 *
896 * This inits the hardware readying it for operation.
897 **/
898 static s32 igb_init_hw_82575(struct e1000_hw *hw)
899 {
900 struct e1000_mac_info *mac = &hw->mac;
901 s32 ret_val;
902 u16 i, rar_count = mac->rar_entry_count;
903
904 /* Initialize identification LED */
905 ret_val = igb_id_led_init(hw);
906 if (ret_val) {
907 hw_dbg("Error initializing identification LED\n");
908 /* This is not fatal and we should not stop init due to this */
909 }
910
911 /* Disabling VLAN filtering */
912 hw_dbg("Initializing the IEEE VLAN\n");
913 igb_clear_vfta(hw);
914
915 /* Setup the receive address */
916 igb_init_rx_addrs(hw, rar_count);
917
918 /* Zero out the Multicast HASH table */
919 hw_dbg("Zeroing the MTA\n");
920 for (i = 0; i < mac->mta_reg_count; i++)
921 array_wr32(E1000_MTA, i, 0);
922
923 /* Setup link and flow control */
924 ret_val = igb_setup_link(hw);
925
926 /*
927 * Clear all of the statistics registers (clear on read). It is
928 * important that we do this after we have tried to establish link
929 * because the symbol error count will increment wildly if there
930 * is no link.
931 */
932 igb_clear_hw_cntrs_82575(hw);
933
934 return ret_val;
935 }
936
937 /**
938 * igb_setup_copper_link_82575 - Configure copper link settings
939 * @hw: pointer to the HW structure
940 *
941 * Configures the link for auto-neg or forced speed and duplex. Then we check
942 * for link, once link is established calls to configure collision distance
943 * and flow control are called.
944 **/
945 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
946 {
947 u32 ctrl;
948 s32 ret_val;
949 bool link;
950
951 ctrl = rd32(E1000_CTRL);
952 ctrl |= E1000_CTRL_SLU;
953 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
954 wr32(E1000_CTRL, ctrl);
955
956 ret_val = igb_setup_serdes_link_82575(hw);
957 if (ret_val)
958 goto out;
959
960 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
961 ret_val = hw->phy.ops.reset(hw);
962 if (ret_val) {
963 hw_dbg("Error resetting the PHY.\n");
964 goto out;
965 }
966 }
967 switch (hw->phy.type) {
968 case e1000_phy_m88:
969 ret_val = igb_copper_link_setup_m88(hw);
970 break;
971 case e1000_phy_igp_3:
972 ret_val = igb_copper_link_setup_igp(hw);
973 break;
974 default:
975 ret_val = -E1000_ERR_PHY;
976 break;
977 }
978
979 if (ret_val)
980 goto out;
981
982 if (hw->mac.autoneg) {
983 /*
984 * Setup autoneg and flow control advertisement
985 * and perform autonegotiation.
986 */
987 ret_val = igb_copper_link_autoneg(hw);
988 if (ret_val)
989 goto out;
990 } else {
991 /*
992 * PHY will be set to 10H, 10F, 100H or 100F
993 * depending on user settings.
994 */
995 hw_dbg("Forcing Speed and Duplex\n");
996 ret_val = hw->phy.ops.force_speed_duplex(hw);
997 if (ret_val) {
998 hw_dbg("Error Forcing Speed and Duplex\n");
999 goto out;
1000 }
1001 }
1002
1003 /*
1004 * Check link status. Wait up to 100 microseconds for link to become
1005 * valid.
1006 */
1007 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
1008 if (ret_val)
1009 goto out;
1010
1011 if (link) {
1012 hw_dbg("Valid link established!!!\n");
1013 /* Config the MAC and PHY after link is up */
1014 igb_config_collision_dist(hw);
1015 ret_val = igb_config_fc_after_link_up(hw);
1016 } else {
1017 hw_dbg("Unable to establish link!!!\n");
1018 }
1019
1020 out:
1021 return ret_val;
1022 }
1023
1024 /**
1025 * igb_setup_serdes_link_82575 - Setup link for serdes
1026 * @hw: pointer to the HW structure
1027 *
1028 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1029 * used on copper connections where the serialized gigabit media independent
1030 * interface (sgmii), or serdes fiber is being used. Configures the link
1031 * for auto-negotiation or forces speed/duplex.
1032 **/
1033 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1034 {
1035 u32 ctrl_reg, reg;
1036
1037 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1038 !igb_sgmii_active_82575(hw))
1039 return 0;
1040
1041 /*
1042 * On the 82575, SerDes loopback mode persists until it is
1043 * explicitly turned off or a power cycle is performed. A read to
1044 * the register does not indicate its status. Therefore, we ensure
1045 * loopback mode is disabled during initialization.
1046 */
1047 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1048
1049 /* power on the sfp cage if present */
1050 reg = rd32(E1000_CTRL_EXT);
1051 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1052 wr32(E1000_CTRL_EXT, reg);
1053
1054 ctrl_reg = rd32(E1000_CTRL);
1055 ctrl_reg |= E1000_CTRL_SLU;
1056
1057 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1058 /* set both sw defined pins */
1059 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1060
1061 /* Set switch control to serdes energy detect */
1062 reg = rd32(E1000_CONNSW);
1063 reg |= E1000_CONNSW_ENRGSRC;
1064 wr32(E1000_CONNSW, reg);
1065 }
1066
1067 reg = rd32(E1000_PCS_LCTL);
1068
1069 if (igb_sgmii_active_82575(hw)) {
1070 /* allow time for SFP cage to power up phy */
1071 msleep(300);
1072
1073 /* AN time out should be disabled for SGMII mode */
1074 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1075 } else {
1076 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1077 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1078 }
1079
1080 wr32(E1000_CTRL, ctrl_reg);
1081
1082 /*
1083 * New SerDes mode allows for forcing speed or autonegotiating speed
1084 * at 1gb. Autoneg should be default set by most drivers. This is the
1085 * mode that will be compatible with older link partners and switches.
1086 * However, both are supported by the hardware and some drivers/tools.
1087 */
1088
1089 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1090 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1091
1092 /*
1093 * We force flow control to prevent the CTRL register values from being
1094 * overwritten by the autonegotiated flow control values
1095 */
1096 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1097
1098 /*
1099 * we always set sgmii to autoneg since it is the phy that will be
1100 * forcing the link and the serdes is just a go-between
1101 */
1102 if (hw->mac.autoneg || igb_sgmii_active_82575(hw)) {
1103 /* Set PCS register for autoneg */
1104 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1105 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full dplx */
1106 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1107 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1108 hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1109 } else {
1110 /* Check for duplex first */
1111 if (hw->mac.forced_speed_duplex & E1000_ALL_FULL_DUPLEX)
1112 reg |= E1000_PCS_LCTL_FDV_FULL;
1113
1114 /* No need to check for 1000/full since the spec states that
1115 * it requires autoneg to be enabled */
1116 /* Now set speed */
1117 if (hw->mac.forced_speed_duplex & E1000_ALL_100_SPEED)
1118 reg |= E1000_PCS_LCTL_FSV_100;
1119
1120 /* Force speed and force link */
1121 reg |= E1000_PCS_LCTL_FSD |
1122 E1000_PCS_LCTL_FORCE_LINK |
1123 E1000_PCS_LCTL_FLV_LINK_UP;
1124
1125 hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
1126 }
1127
1128 wr32(E1000_PCS_LCTL, reg);
1129
1130 if (!igb_sgmii_active_82575(hw))
1131 igb_force_mac_fc(hw);
1132
1133 return 0;
1134 }
1135
1136 /**
1137 * igb_sgmii_active_82575 - Return sgmii state
1138 * @hw: pointer to the HW structure
1139 *
1140 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1141 * which can be enabled for use in the embedded applications. Simply
1142 * return the current state of the sgmii interface.
1143 **/
1144 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1145 {
1146 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1147 return dev_spec->sgmii_active;
1148 }
1149
1150 /**
1151 * igb_reset_init_script_82575 - Inits HW defaults after reset
1152 * @hw: pointer to the HW structure
1153 *
1154 * Inits recommended HW defaults after a reset when there is no EEPROM
1155 * detected. This is only for the 82575.
1156 **/
1157 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1158 {
1159 if (hw->mac.type == e1000_82575) {
1160 hw_dbg("Running reset init script for 82575\n");
1161 /* SerDes configuration via SERDESCTRL */
1162 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1163 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1164 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1165 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1166
1167 /* CCM configuration via CCMCTL register */
1168 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1169 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1170
1171 /* PCIe lanes configuration */
1172 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1173 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1174 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1175 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1176
1177 /* PCIe PLL Configuration */
1178 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1179 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1180 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1181 }
1182
1183 return 0;
1184 }
1185
1186 /**
1187 * igb_read_mac_addr_82575 - Read device MAC address
1188 * @hw: pointer to the HW structure
1189 **/
1190 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1191 {
1192 s32 ret_val = 0;
1193
1194 if (igb_check_alt_mac_addr(hw))
1195 ret_val = igb_read_mac_addr(hw);
1196
1197 return ret_val;
1198 }
1199
1200 /**
1201 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1202 * @hw: pointer to the HW structure
1203 *
1204 * Clears the hardware counters by reading the counter registers.
1205 **/
1206 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1207 {
1208 igb_clear_hw_cntrs_base(hw);
1209
1210 rd32(E1000_PRC64);
1211 rd32(E1000_PRC127);
1212 rd32(E1000_PRC255);
1213 rd32(E1000_PRC511);
1214 rd32(E1000_PRC1023);
1215 rd32(E1000_PRC1522);
1216 rd32(E1000_PTC64);
1217 rd32(E1000_PTC127);
1218 rd32(E1000_PTC255);
1219 rd32(E1000_PTC511);
1220 rd32(E1000_PTC1023);
1221 rd32(E1000_PTC1522);
1222
1223 rd32(E1000_ALGNERRC);
1224 rd32(E1000_RXERRC);
1225 rd32(E1000_TNCRS);
1226 rd32(E1000_CEXTERR);
1227 rd32(E1000_TSCTC);
1228 rd32(E1000_TSCTFC);
1229
1230 rd32(E1000_MGTPRC);
1231 rd32(E1000_MGTPDC);
1232 rd32(E1000_MGTPTC);
1233
1234 rd32(E1000_IAC);
1235 rd32(E1000_ICRXOC);
1236
1237 rd32(E1000_ICRXPTC);
1238 rd32(E1000_ICRXATC);
1239 rd32(E1000_ICTXPTC);
1240 rd32(E1000_ICTXATC);
1241 rd32(E1000_ICTXQEC);
1242 rd32(E1000_ICTXQMTC);
1243 rd32(E1000_ICRXDMTC);
1244
1245 rd32(E1000_CBTMPC);
1246 rd32(E1000_HTDPMC);
1247 rd32(E1000_CBRMPC);
1248 rd32(E1000_RPTHC);
1249 rd32(E1000_HGPTC);
1250 rd32(E1000_HTCBDPC);
1251 rd32(E1000_HGORCL);
1252 rd32(E1000_HGORCH);
1253 rd32(E1000_HGOTCL);
1254 rd32(E1000_HGOTCH);
1255 rd32(E1000_LENERRS);
1256
1257 /* This register should not be read in copper configurations */
1258 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1259 igb_sgmii_active_82575(hw))
1260 rd32(E1000_SCVPC);
1261 }
1262
1263 /**
1264 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1265 * @hw: pointer to the HW structure
1266 *
1267 * After rx enable if managability is enabled then there is likely some
1268 * bad data at the start of the fifo and possibly in the DMA fifo. This
1269 * function clears the fifos and flushes any packets that came in as rx was
1270 * being enabled.
1271 **/
1272 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1273 {
1274 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1275 int i, ms_wait;
1276
1277 if (hw->mac.type != e1000_82575 ||
1278 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1279 return;
1280
1281 /* Disable all RX queues */
1282 for (i = 0; i < 4; i++) {
1283 rxdctl[i] = rd32(E1000_RXDCTL(i));
1284 wr32(E1000_RXDCTL(i),
1285 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1286 }
1287 /* Poll all queues to verify they have shut down */
1288 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1289 msleep(1);
1290 rx_enabled = 0;
1291 for (i = 0; i < 4; i++)
1292 rx_enabled |= rd32(E1000_RXDCTL(i));
1293 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1294 break;
1295 }
1296
1297 if (ms_wait == 10)
1298 hw_dbg("Queue disable timed out after 10ms\n");
1299
1300 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1301 * incoming packets are rejected. Set enable and wait 2ms so that
1302 * any packet that was coming in as RCTL.EN was set is flushed
1303 */
1304 rfctl = rd32(E1000_RFCTL);
1305 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1306
1307 rlpml = rd32(E1000_RLPML);
1308 wr32(E1000_RLPML, 0);
1309
1310 rctl = rd32(E1000_RCTL);
1311 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1312 temp_rctl |= E1000_RCTL_LPE;
1313
1314 wr32(E1000_RCTL, temp_rctl);
1315 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1316 wrfl();
1317 msleep(2);
1318
1319 /* Enable RX queues that were previously enabled and restore our
1320 * previous state
1321 */
1322 for (i = 0; i < 4; i++)
1323 wr32(E1000_RXDCTL(i), rxdctl[i]);
1324 wr32(E1000_RCTL, rctl);
1325 wrfl();
1326
1327 wr32(E1000_RLPML, rlpml);
1328 wr32(E1000_RFCTL, rfctl);
1329
1330 /* Flush receive errors generated by workaround */
1331 rd32(E1000_ROC);
1332 rd32(E1000_RNBC);
1333 rd32(E1000_MPC);
1334 }
1335
1336 /**
1337 * igb_set_pcie_completion_timeout - set pci-e completion timeout
1338 * @hw: pointer to the HW structure
1339 *
1340 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1341 * however the hardware default for these parts is 500us to 1ms which is less
1342 * than the 10ms recommended by the pci-e spec. To address this we need to
1343 * increase the value to either 10ms to 200ms for capability version 1 config,
1344 * or 16ms to 55ms for version 2.
1345 **/
1346 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1347 {
1348 u32 gcr = rd32(E1000_GCR);
1349 s32 ret_val = 0;
1350 u16 pcie_devctl2;
1351
1352 /* only take action if timeout value is defaulted to 0 */
1353 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1354 goto out;
1355
1356 /*
1357 * if capababilities version is type 1 we can write the
1358 * timeout of 10ms to 200ms through the GCR register
1359 */
1360 if (!(gcr & E1000_GCR_CAP_VER2)) {
1361 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1362 goto out;
1363 }
1364
1365 /*
1366 * for version 2 capabilities we need to write the config space
1367 * directly in order to set the completion timeout value for
1368 * 16ms to 55ms
1369 */
1370 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1371 &pcie_devctl2);
1372 if (ret_val)
1373 goto out;
1374
1375 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1376
1377 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1378 &pcie_devctl2);
1379 out:
1380 /* disable completion timeout resend */
1381 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1382
1383 wr32(E1000_GCR, gcr);
1384 return ret_val;
1385 }
1386
1387 /**
1388 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1389 * @hw: pointer to the hardware struct
1390 * @enable: state to enter, either enabled or disabled
1391 *
1392 * enables/disables L2 switch loopback functionality.
1393 **/
1394 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1395 {
1396 u32 dtxswc = rd32(E1000_DTXSWC);
1397
1398 if (enable)
1399 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1400 else
1401 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1402
1403 wr32(E1000_DTXSWC, dtxswc);
1404 }
1405
1406 /**
1407 * igb_vmdq_set_replication_pf - enable or disable vmdq replication
1408 * @hw: pointer to the hardware struct
1409 * @enable: state to enter, either enabled or disabled
1410 *
1411 * enables/disables replication of packets across multiple pools.
1412 **/
1413 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1414 {
1415 u32 vt_ctl = rd32(E1000_VT_CTL);
1416
1417 if (enable)
1418 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1419 else
1420 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1421
1422 wr32(E1000_VT_CTL, vt_ctl);
1423 }
1424
1425 static struct e1000_mac_operations e1000_mac_ops_82575 = {
1426 .reset_hw = igb_reset_hw_82575,
1427 .init_hw = igb_init_hw_82575,
1428 .check_for_link = igb_check_for_link_82575,
1429 .rar_set = igb_rar_set,
1430 .read_mac_addr = igb_read_mac_addr_82575,
1431 .get_speed_and_duplex = igb_get_speed_and_duplex_copper,
1432 };
1433
1434 static struct e1000_phy_operations e1000_phy_ops_82575 = {
1435 .acquire = igb_acquire_phy_82575,
1436 .get_cfg_done = igb_get_cfg_done_82575,
1437 .release = igb_release_phy_82575,
1438 };
1439
1440 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
1441 .acquire = igb_acquire_nvm_82575,
1442 .read = igb_read_nvm_eerd,
1443 .release = igb_release_nvm_82575,
1444 .write = igb_write_nvm_spi,
1445 };
1446
1447 const struct e1000_info e1000_82575_info = {
1448 .get_invariants = igb_get_invariants_82575,
1449 .mac_ops = &e1000_mac_ops_82575,
1450 .phy_ops = &e1000_phy_ops_82575,
1451 .nvm_ops = &e1000_nvm_ops_82575,
1452 };
1453
Linux kernel - Deliverables
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