1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
32 #include <linux/types.h>
33 #include <linux/slab.h>
34 #include <linux/if_ether.h>
36 #include "e1000_mac.h"
37 #include "e1000_82575.h"
39 static s32
igb_get_invariants_82575(struct e1000_hw
*);
40 static s32
igb_acquire_phy_82575(struct e1000_hw
*);
41 static void igb_release_phy_82575(struct e1000_hw
*);
42 static s32
igb_acquire_nvm_82575(struct e1000_hw
*);
43 static void igb_release_nvm_82575(struct e1000_hw
*);
44 static s32
igb_check_for_link_82575(struct e1000_hw
*);
45 static s32
igb_get_cfg_done_82575(struct e1000_hw
*);
46 static s32
igb_init_hw_82575(struct e1000_hw
*);
47 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*);
48 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
*);
49 static s32
igb_reset_hw_82575(struct e1000_hw
*);
50 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*, bool);
51 static s32
igb_setup_copper_link_82575(struct e1000_hw
*);
52 static s32
igb_setup_fiber_serdes_link_82575(struct e1000_hw
*);
53 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*, u32
, u16
);
54 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*);
55 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*, u16
);
56 static s32
igb_configure_pcs_link_82575(struct e1000_hw
*);
57 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*, u16
*,
59 static s32
igb_get_phy_id_82575(struct e1000_hw
*);
60 static void igb_release_swfw_sync_82575(struct e1000_hw
*, u16
);
61 static bool igb_sgmii_active_82575(struct e1000_hw
*);
62 static s32
igb_reset_init_script_82575(struct e1000_hw
*);
63 static s32
igb_read_mac_addr_82575(struct e1000_hw
*);
66 struct e1000_dev_spec_82575
{
70 static s32
igb_get_invariants_82575(struct e1000_hw
*hw
)
72 struct e1000_phy_info
*phy
= &hw
->phy
;
73 struct e1000_nvm_info
*nvm
= &hw
->nvm
;
74 struct e1000_mac_info
*mac
= &hw
->mac
;
75 struct e1000_dev_spec_82575
*dev_spec
;
81 switch (hw
->device_id
) {
82 case E1000_DEV_ID_82575EB_COPPER
:
83 case E1000_DEV_ID_82575EB_FIBER_SERDES
:
84 case E1000_DEV_ID_82575GB_QUAD_COPPER
:
85 mac
->type
= e1000_82575
;
87 case E1000_DEV_ID_82576
:
88 case E1000_DEV_ID_82576_FIBER
:
89 case E1000_DEV_ID_82576_SERDES
:
90 case E1000_DEV_ID_82576_QUAD_COPPER
:
91 mac
->type
= e1000_82576
;
94 return -E1000_ERR_MAC_INIT
;
98 /* MAC initialization */
99 hw
->dev_spec_size
= sizeof(struct e1000_dev_spec_82575
);
101 /* Device-specific structure allocation */
102 hw
->dev_spec
= kzalloc(hw
->dev_spec_size
, GFP_KERNEL
);
107 dev_spec
= (struct e1000_dev_spec_82575
*)hw
->dev_spec
;
111 * The 82575 uses bits 22:23 for link mode. The mode can be changed
112 * based on the EEPROM. We cannot rely upon device ID. There
113 * is no distinguishable difference between fiber and internal
114 * SerDes mode on the 82575. There can be an external PHY attached
115 * on the SGMII interface. For this, we'll set sgmii_active to true.
117 phy
->media_type
= e1000_media_type_copper
;
118 dev_spec
->sgmii_active
= false;
120 ctrl_ext
= rd32(E1000_CTRL_EXT
);
121 if ((ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_MASK
) ==
122 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES
) {
123 hw
->phy
.media_type
= e1000_media_type_internal_serdes
;
124 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
125 } else if (ctrl_ext
& E1000_CTRL_EXT_LINK_MODE_SGMII
) {
126 dev_spec
->sgmii_active
= true;
127 ctrl_ext
|= E1000_CTRL_I2C_ENA
;
129 ctrl_ext
&= ~E1000_CTRL_I2C_ENA
;
131 wr32(E1000_CTRL_EXT
, ctrl_ext
);
133 /* Set mta register count */
134 mac
->mta_reg_count
= 128;
135 /* Set rar entry count */
136 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82575
;
137 if (mac
->type
== e1000_82576
)
138 mac
->rar_entry_count
= E1000_RAR_ENTRIES_82576
;
139 /* Set if part includes ASF firmware */
140 mac
->asf_firmware_present
= true;
141 /* Set if manageability features are enabled. */
142 mac
->arc_subsystem_valid
=
143 (rd32(E1000_FWSM
) & E1000_FWSM_MODE_MASK
)
146 /* physical interface link setup */
147 mac
->ops
.setup_physical_interface
=
148 (hw
->phy
.media_type
== e1000_media_type_copper
)
149 ? igb_setup_copper_link_82575
150 : igb_setup_fiber_serdes_link_82575
;
152 /* NVM initialization */
153 eecd
= rd32(E1000_EECD
);
155 nvm
->opcode_bits
= 8;
157 switch (nvm
->override
) {
158 case e1000_nvm_override_spi_large
:
160 nvm
->address_bits
= 16;
162 case e1000_nvm_override_spi_small
:
164 nvm
->address_bits
= 8;
167 nvm
->page_size
= eecd
& E1000_EECD_ADDR_BITS
? 32 : 8;
168 nvm
->address_bits
= eecd
& E1000_EECD_ADDR_BITS
? 16 : 8;
172 nvm
->type
= e1000_nvm_eeprom_spi
;
174 size
= (u16
)((eecd
& E1000_EECD_SIZE_EX_MASK
) >>
175 E1000_EECD_SIZE_EX_SHIFT
);
178 * Added to a constant, "size" becomes the left-shift value
179 * for setting word_size.
181 size
+= NVM_WORD_SIZE_BASE_SHIFT
;
183 /* EEPROM access above 16k is unsupported */
186 nvm
->word_size
= 1 << size
;
188 /* setup PHY parameters */
189 if (phy
->media_type
!= e1000_media_type_copper
) {
190 phy
->type
= e1000_phy_none
;
194 phy
->autoneg_mask
= AUTONEG_ADVERTISE_SPEED_DEFAULT
;
195 phy
->reset_delay_us
= 100;
197 /* PHY function pointers */
198 if (igb_sgmii_active_82575(hw
)) {
199 phy
->ops
.reset_phy
= igb_phy_hw_reset_sgmii_82575
;
200 phy
->ops
.read_phy_reg
= igb_read_phy_reg_sgmii_82575
;
201 phy
->ops
.write_phy_reg
= igb_write_phy_reg_sgmii_82575
;
203 phy
->ops
.reset_phy
= igb_phy_hw_reset
;
204 phy
->ops
.read_phy_reg
= igb_read_phy_reg_igp
;
205 phy
->ops
.write_phy_reg
= igb_write_phy_reg_igp
;
208 /* Set phy->phy_addr and phy->id. */
209 ret_val
= igb_get_phy_id_82575(hw
);
213 /* Verify phy id and set remaining function pointers */
215 case M88E1111_I_PHY_ID
:
216 phy
->type
= e1000_phy_m88
;
217 phy
->ops
.get_phy_info
= igb_get_phy_info_m88
;
218 phy
->ops
.get_cable_length
= igb_get_cable_length_m88
;
219 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_m88
;
221 case IGP03E1000_E_PHY_ID
:
222 phy
->type
= e1000_phy_igp_3
;
223 phy
->ops
.get_phy_info
= igb_get_phy_info_igp
;
224 phy
->ops
.get_cable_length
= igb_get_cable_length_igp_2
;
225 phy
->ops
.force_speed_duplex
= igb_phy_force_speed_duplex_igp
;
226 phy
->ops
.set_d0_lplu_state
= igb_set_d0_lplu_state_82575
;
227 phy
->ops
.set_d3_lplu_state
= igb_set_d3_lplu_state
;
230 return -E1000_ERR_PHY
;
237 * igb_acquire_phy_82575 - Acquire rights to access PHY
238 * @hw: pointer to the HW structure
240 * Acquire access rights to the correct PHY. This is a
241 * function pointer entry point called by the api module.
243 static s32
igb_acquire_phy_82575(struct e1000_hw
*hw
)
247 mask
= hw
->bus
.func
? E1000_SWFW_PHY1_SM
: E1000_SWFW_PHY0_SM
;
249 return igb_acquire_swfw_sync_82575(hw
, mask
);
253 * igb_release_phy_82575 - Release rights to access PHY
254 * @hw: pointer to the HW structure
256 * A wrapper to release access rights to the correct PHY. This is a
257 * function pointer entry point called by the api module.
259 static void igb_release_phy_82575(struct e1000_hw
*hw
)
263 mask
= hw
->bus
.func
? E1000_SWFW_PHY1_SM
: E1000_SWFW_PHY0_SM
;
264 igb_release_swfw_sync_82575(hw
, mask
);
268 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
269 * @hw: pointer to the HW structure
270 * @offset: register offset to be read
271 * @data: pointer to the read data
273 * Reads the PHY register at offset using the serial gigabit media independent
274 * interface and stores the retrieved information in data.
276 static s32
igb_read_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
279 struct e1000_phy_info
*phy
= &hw
->phy
;
282 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
283 hw_dbg("PHY Address %u is out of range\n", offset
);
284 return -E1000_ERR_PARAM
;
288 * Set up Op-code, Phy Address, and register address in the I2CCMD
289 * register. The MAC will take care of interfacing with the
290 * PHY to retrieve the desired data.
292 i2ccmd
= ((offset
<< E1000_I2CCMD_REG_ADDR_SHIFT
) |
293 (phy
->addr
<< E1000_I2CCMD_PHY_ADDR_SHIFT
) |
294 (E1000_I2CCMD_OPCODE_READ
));
296 wr32(E1000_I2CCMD
, i2ccmd
);
298 /* Poll the ready bit to see if the I2C read completed */
299 for (i
= 0; i
< E1000_I2CCMD_PHY_TIMEOUT
; i
++) {
301 i2ccmd
= rd32(E1000_I2CCMD
);
302 if (i2ccmd
& E1000_I2CCMD_READY
)
305 if (!(i2ccmd
& E1000_I2CCMD_READY
)) {
306 hw_dbg("I2CCMD Read did not complete\n");
307 return -E1000_ERR_PHY
;
309 if (i2ccmd
& E1000_I2CCMD_ERROR
) {
310 hw_dbg("I2CCMD Error bit set\n");
311 return -E1000_ERR_PHY
;
314 /* Need to byte-swap the 16-bit value. */
315 *data
= ((i2ccmd
>> 8) & 0x00FF) | ((i2ccmd
<< 8) & 0xFF00);
321 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
322 * @hw: pointer to the HW structure
323 * @offset: register offset to write to
324 * @data: data to write at register offset
326 * Writes the data to PHY register at the offset using the serial gigabit
327 * media independent interface.
329 static s32
igb_write_phy_reg_sgmii_82575(struct e1000_hw
*hw
, u32 offset
,
332 struct e1000_phy_info
*phy
= &hw
->phy
;
334 u16 phy_data_swapped
;
336 if (offset
> E1000_MAX_SGMII_PHY_REG_ADDR
) {
337 hw_dbg("PHY Address %d is out of range\n", offset
);
338 return -E1000_ERR_PARAM
;
341 /* Swap the data bytes for the I2C interface */
342 phy_data_swapped
= ((data
>> 8) & 0x00FF) | ((data
<< 8) & 0xFF00);
345 * Set up Op-code, Phy Address, and register address in the I2CCMD
346 * register. The MAC will take care of interfacing with the
347 * PHY to retrieve the desired data.
349 i2ccmd
= ((offset
<< E1000_I2CCMD_REG_ADDR_SHIFT
) |
350 (phy
->addr
<< E1000_I2CCMD_PHY_ADDR_SHIFT
) |
351 E1000_I2CCMD_OPCODE_WRITE
|
354 wr32(E1000_I2CCMD
, i2ccmd
);
356 /* Poll the ready bit to see if the I2C read completed */
357 for (i
= 0; i
< E1000_I2CCMD_PHY_TIMEOUT
; i
++) {
359 i2ccmd
= rd32(E1000_I2CCMD
);
360 if (i2ccmd
& E1000_I2CCMD_READY
)
363 if (!(i2ccmd
& E1000_I2CCMD_READY
)) {
364 hw_dbg("I2CCMD Write did not complete\n");
365 return -E1000_ERR_PHY
;
367 if (i2ccmd
& E1000_I2CCMD_ERROR
) {
368 hw_dbg("I2CCMD Error bit set\n");
369 return -E1000_ERR_PHY
;
376 * igb_get_phy_id_82575 - Retrieve PHY addr and id
377 * @hw: pointer to the HW structure
379 * Retrieves the PHY address and ID for both PHY's which do and do not use
382 static s32
igb_get_phy_id_82575(struct e1000_hw
*hw
)
384 struct e1000_phy_info
*phy
= &hw
->phy
;
389 * For SGMII PHYs, we try the list of possible addresses until
390 * we find one that works. For non-SGMII PHYs
391 * (e.g. integrated copper PHYs), an address of 1 should
392 * work. The result of this function should mean phy->phy_addr
393 * and phy->id are set correctly.
395 if (!(igb_sgmii_active_82575(hw
))) {
397 ret_val
= igb_get_phy_id(hw
);
402 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
403 * Therefore, we need to test 1-7
405 for (phy
->addr
= 1; phy
->addr
< 8; phy
->addr
++) {
406 ret_val
= igb_read_phy_reg_sgmii_82575(hw
, PHY_ID1
, &phy_id
);
408 hw_dbg("Vendor ID 0x%08X read at address %u\n",
411 * At the time of this writing, The M88 part is
412 * the only supported SGMII PHY product.
414 if (phy_id
== M88_VENDOR
)
417 hw_dbg("PHY address %u was unreadable\n", phy
->addr
);
421 /* A valid PHY type couldn't be found. */
422 if (phy
->addr
== 8) {
424 ret_val
= -E1000_ERR_PHY
;
428 ret_val
= igb_get_phy_id(hw
);
435 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
436 * @hw: pointer to the HW structure
438 * Resets the PHY using the serial gigabit media independent interface.
440 static s32
igb_phy_hw_reset_sgmii_82575(struct e1000_hw
*hw
)
445 * This isn't a true "hard" reset, but is the only reset
446 * available to us at this time.
449 hw_dbg("Soft resetting SGMII attached PHY...\n");
452 * SFP documentation requires the following to configure the SPF module
453 * to work on SGMII. No further documentation is given.
455 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, 0x1B, 0x8084);
459 ret_val
= igb_phy_sw_reset(hw
);
466 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
467 * @hw: pointer to the HW structure
468 * @active: true to enable LPLU, false to disable
470 * Sets the LPLU D0 state according to the active flag. When
471 * activating LPLU this function also disables smart speed
472 * and vice versa. LPLU will not be activated unless the
473 * device autonegotiation advertisement meets standards of
474 * either 10 or 10/100 or 10/100/1000 at all duplexes.
475 * This is a function pointer entry point only called by
476 * PHY setup routines.
478 static s32
igb_set_d0_lplu_state_82575(struct e1000_hw
*hw
, bool active
)
480 struct e1000_phy_info
*phy
= &hw
->phy
;
484 ret_val
= phy
->ops
.read_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
489 data
|= IGP02E1000_PM_D0_LPLU
;
490 ret_val
= phy
->ops
.write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
495 /* When LPLU is enabled, we should disable SmartSpeed */
496 ret_val
= phy
->ops
.read_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
498 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
499 ret_val
= phy
->ops
.write_phy_reg(hw
, IGP01E1000_PHY_PORT_CONFIG
,
504 data
&= ~IGP02E1000_PM_D0_LPLU
;
505 ret_val
= phy
->ops
.write_phy_reg(hw
, IGP02E1000_PHY_POWER_MGMT
,
508 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
509 * during Dx states where the power conservation is most
510 * important. During driver activity we should enable
511 * SmartSpeed, so performance is maintained.
513 if (phy
->smart_speed
== e1000_smart_speed_on
) {
514 ret_val
= phy
->ops
.read_phy_reg(hw
,
515 IGP01E1000_PHY_PORT_CONFIG
, &data
);
519 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
520 ret_val
= phy
->ops
.write_phy_reg(hw
,
521 IGP01E1000_PHY_PORT_CONFIG
, data
);
524 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
525 ret_val
= phy
->ops
.read_phy_reg(hw
,
526 IGP01E1000_PHY_PORT_CONFIG
, &data
);
530 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
531 ret_val
= phy
->ops
.write_phy_reg(hw
,
532 IGP01E1000_PHY_PORT_CONFIG
, data
);
543 * igb_acquire_nvm_82575 - Request for access to EEPROM
544 * @hw: pointer to the HW structure
546 * Acquire the necessary semaphores for exclusive access to the EEPROM.
547 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
548 * Return successful if access grant bit set, else clear the request for
549 * EEPROM access and return -E1000_ERR_NVM (-1).
551 static s32
igb_acquire_nvm_82575(struct e1000_hw
*hw
)
555 ret_val
= igb_acquire_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
559 ret_val
= igb_acquire_nvm(hw
);
562 igb_release_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
569 * igb_release_nvm_82575 - Release exclusive access to EEPROM
570 * @hw: pointer to the HW structure
572 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
573 * then release the semaphores acquired.
575 static void igb_release_nvm_82575(struct e1000_hw
*hw
)
578 igb_release_swfw_sync_82575(hw
, E1000_SWFW_EEP_SM
);
582 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
583 * @hw: pointer to the HW structure
584 * @mask: specifies which semaphore to acquire
586 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
587 * will also specify which port we're acquiring the lock for.
589 static s32
igb_acquire_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
593 u32 fwmask
= mask
<< 16;
595 s32 i
= 0, timeout
= 200; /* FIXME: find real value to use here */
597 while (i
< timeout
) {
598 if (igb_get_hw_semaphore(hw
)) {
599 ret_val
= -E1000_ERR_SWFW_SYNC
;
603 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
604 if (!(swfw_sync
& (fwmask
| swmask
)))
608 * Firmware currently using resource (fwmask)
609 * or other software thread using resource (swmask)
611 igb_put_hw_semaphore(hw
);
617 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
618 ret_val
= -E1000_ERR_SWFW_SYNC
;
623 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
625 igb_put_hw_semaphore(hw
);
632 * igb_release_swfw_sync_82575 - Release SW/FW semaphore
633 * @hw: pointer to the HW structure
634 * @mask: specifies which semaphore to acquire
636 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
637 * will also specify which port we're releasing the lock for.
639 static void igb_release_swfw_sync_82575(struct e1000_hw
*hw
, u16 mask
)
643 while (igb_get_hw_semaphore(hw
) != 0);
646 swfw_sync
= rd32(E1000_SW_FW_SYNC
);
648 wr32(E1000_SW_FW_SYNC
, swfw_sync
);
650 igb_put_hw_semaphore(hw
);
654 * igb_get_cfg_done_82575 - Read config done bit
655 * @hw: pointer to the HW structure
657 * Read the management control register for the config done bit for
658 * completion status. NOTE: silicon which is EEPROM-less will fail trying
659 * to read the config done bit, so an error is *ONLY* logged and returns
660 * 0. If we were to return with error, EEPROM-less silicon
661 * would not be able to be reset or change link.
663 static s32
igb_get_cfg_done_82575(struct e1000_hw
*hw
)
665 s32 timeout
= PHY_CFG_TIMEOUT
;
667 u32 mask
= E1000_NVM_CFG_DONE_PORT_0
;
669 if (hw
->bus
.func
== 1)
670 mask
= E1000_NVM_CFG_DONE_PORT_1
;
673 if (rd32(E1000_EEMNGCTL
) & mask
)
679 hw_dbg("MNG configuration cycle has not completed.\n");
681 /* If EEPROM is not marked present, init the PHY manually */
682 if (((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0) &&
683 (hw
->phy
.type
== e1000_phy_igp_3
))
684 igb_phy_init_script_igp3(hw
);
690 * igb_check_for_link_82575 - Check for link
691 * @hw: pointer to the HW structure
693 * If sgmii is enabled, then use the pcs register to determine link, otherwise
694 * use the generic interface for determining link.
696 static s32
igb_check_for_link_82575(struct e1000_hw
*hw
)
701 /* SGMII link check is done through the PCS register. */
702 if ((hw
->phy
.media_type
!= e1000_media_type_copper
) ||
703 (igb_sgmii_active_82575(hw
)))
704 ret_val
= igb_get_pcs_speed_and_duplex_82575(hw
, &speed
,
707 ret_val
= igb_check_for_copper_link(hw
);
712 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
713 * @hw: pointer to the HW structure
714 * @speed: stores the current speed
715 * @duplex: stores the current duplex
717 * Using the physical coding sub-layer (PCS), retrieve the current speed and
718 * duplex, then store the values in the pointers provided.
720 static s32
igb_get_pcs_speed_and_duplex_82575(struct e1000_hw
*hw
, u16
*speed
,
723 struct e1000_mac_info
*mac
= &hw
->mac
;
726 /* Set up defaults for the return values of this function */
727 mac
->serdes_has_link
= false;
732 * Read the PCS Status register for link state. For non-copper mode,
733 * the status register is not accurate. The PCS status register is
736 pcs
= rd32(E1000_PCS_LSTAT
);
739 * The link up bit determines when link is up on autoneg. The sync ok
740 * gets set once both sides sync up and agree upon link. Stable link
741 * can be determined by checking for both link up and link sync ok
743 if ((pcs
& E1000_PCS_LSTS_LINK_OK
) && (pcs
& E1000_PCS_LSTS_SYNK_OK
)) {
744 mac
->serdes_has_link
= true;
746 /* Detect and store PCS speed */
747 if (pcs
& E1000_PCS_LSTS_SPEED_1000
) {
749 } else if (pcs
& E1000_PCS_LSTS_SPEED_100
) {
755 /* Detect and store PCS duplex */
756 if (pcs
& E1000_PCS_LSTS_DUPLEX_FULL
) {
757 *duplex
= FULL_DUPLEX
;
759 *duplex
= HALF_DUPLEX
;
767 * igb_init_rx_addrs_82575 - Initialize receive address's
768 * @hw: pointer to the HW structure
769 * @rar_count: receive address registers
771 * Setups the receive address registers by setting the base receive address
772 * register to the devices MAC address and clearing all the other receive
773 * address registers to 0.
775 static void igb_init_rx_addrs_82575(struct e1000_hw
*hw
, u16 rar_count
)
778 u8 addr
[6] = {0,0,0,0,0,0};
780 * This function is essentially the same as that of
781 * e1000_init_rx_addrs_generic. However it also takes care
782 * of the special case where the register offset of the
783 * second set of RARs begins elsewhere. This is implicitly taken care by
784 * function e1000_rar_set_generic.
787 hw_dbg("e1000_init_rx_addrs_82575");
789 /* Setup the receive address */
790 hw_dbg("Programming MAC Address into RAR[0]\n");
791 hw
->mac
.ops
.rar_set(hw
, hw
->mac
.addr
, 0);
793 /* Zero out the other (rar_entry_count - 1) receive addresses */
794 hw_dbg("Clearing RAR[1-%u]\n", rar_count
-1);
795 for (i
= 1; i
< rar_count
; i
++)
796 hw
->mac
.ops
.rar_set(hw
, addr
, i
);
800 * igb_update_mc_addr_list_82575 - Update Multicast addresses
801 * @hw: pointer to the HW structure
802 * @mc_addr_list: array of multicast addresses to program
803 * @mc_addr_count: number of multicast addresses to program
804 * @rar_used_count: the first RAR register free to program
805 * @rar_count: total number of supported Receive Address Registers
807 * Updates the Receive Address Registers and Multicast Table Array.
808 * The caller must have a packed mc_addr_list of multicast addresses.
809 * The parameter rar_count will usually be hw->mac.rar_entry_count
810 * unless there are workarounds that change this.
812 void igb_update_mc_addr_list_82575(struct e1000_hw
*hw
,
813 u8
*mc_addr_list
, u32 mc_addr_count
,
814 u32 rar_used_count
, u32 rar_count
)
818 u8 addr
[6] = {0,0,0,0,0,0};
820 * This function is essentially the same as that of
821 * igb_update_mc_addr_list_generic. However it also takes care
822 * of the special case where the register offset of the
823 * second set of RARs begins elsewhere. This is implicitly taken care by
824 * function e1000_rar_set_generic.
828 * Load the first set of multicast addresses into the exact
829 * filters (RAR). If there are not enough to fill the RAR
830 * array, clear the filters.
832 for (i
= rar_used_count
; i
< rar_count
; i
++) {
834 igb_rar_set(hw
, mc_addr_list
, i
);
836 mc_addr_list
+= ETH_ALEN
;
838 igb_rar_set(hw
, addr
, i
);
842 /* Clear the old settings from the MTA */
843 hw_dbg("Clearing MTA\n");
844 for (i
= 0; i
< hw
->mac
.mta_reg_count
; i
++) {
845 array_wr32(E1000_MTA
, i
, 0);
849 /* Load any remaining multicast addresses into the hash table. */
850 for (; mc_addr_count
> 0; mc_addr_count
--) {
851 hash_value
= igb_hash_mc_addr(hw
, mc_addr_list
);
852 hw_dbg("Hash value = 0x%03X\n", hash_value
);
853 hw
->mac
.ops
.mta_set(hw
, hash_value
);
854 mc_addr_list
+= ETH_ALEN
;
859 * igb_shutdown_fiber_serdes_link_82575 - Remove link during power down
860 * @hw: pointer to the HW structure
862 * In the case of fiber serdes, shut down optics and PCS on driver unload
863 * when management pass thru is not enabled.
865 void igb_shutdown_fiber_serdes_link_82575(struct e1000_hw
*hw
)
869 if (hw
->mac
.type
!= e1000_82576
||
870 (hw
->phy
.media_type
!= e1000_media_type_fiber
&&
871 hw
->phy
.media_type
!= e1000_media_type_internal_serdes
))
874 /* if the management interface is not enabled, then power down */
875 if (!igb_enable_mng_pass_thru(hw
)) {
876 /* Disable PCS to turn off link */
877 reg
= rd32(E1000_PCS_CFG0
);
878 reg
&= ~E1000_PCS_CFG_PCS_EN
;
879 wr32(E1000_PCS_CFG0
, reg
);
881 /* shutdown the laser */
882 reg
= rd32(E1000_CTRL_EXT
);
883 reg
|= E1000_CTRL_EXT_SDP7_DATA
;
884 wr32(E1000_CTRL_EXT
, reg
);
886 /* flush the write to verify completion */
895 * igb_reset_hw_82575 - Reset hardware
896 * @hw: pointer to the HW structure
898 * This resets the hardware into a known state. This is a
899 * function pointer entry point called by the api module.
901 static s32
igb_reset_hw_82575(struct e1000_hw
*hw
)
907 * Prevent the PCI-E bus from sticking if there is no TLP connection
908 * on the last TLP read/write transaction when MAC is reset.
910 ret_val
= igb_disable_pcie_master(hw
);
912 hw_dbg("PCI-E Master disable polling has failed.\n");
914 hw_dbg("Masking off all interrupts\n");
915 wr32(E1000_IMC
, 0xffffffff);
918 wr32(E1000_TCTL
, E1000_TCTL_PSP
);
923 ctrl
= rd32(E1000_CTRL
);
925 hw_dbg("Issuing a global reset to MAC\n");
926 wr32(E1000_CTRL
, ctrl
| E1000_CTRL_RST
);
928 ret_val
= igb_get_auto_rd_done(hw
);
931 * When auto config read does not complete, do not
932 * return with an error. This can happen in situations
933 * where there is no eeprom and prevents getting link.
935 hw_dbg("Auto Read Done did not complete\n");
938 /* If EEPROM is not present, run manual init scripts */
939 if ((rd32(E1000_EECD
) & E1000_EECD_PRES
) == 0)
940 igb_reset_init_script_82575(hw
);
942 /* Clear any pending interrupt events. */
943 wr32(E1000_IMC
, 0xffffffff);
944 icr
= rd32(E1000_ICR
);
946 igb_check_alt_mac_addr(hw
);
952 * igb_init_hw_82575 - Initialize hardware
953 * @hw: pointer to the HW structure
955 * This inits the hardware readying it for operation.
957 static s32
igb_init_hw_82575(struct e1000_hw
*hw
)
959 struct e1000_mac_info
*mac
= &hw
->mac
;
961 u16 i
, rar_count
= mac
->rar_entry_count
;
963 /* Initialize identification LED */
964 ret_val
= igb_id_led_init(hw
);
966 hw_dbg("Error initializing identification LED\n");
967 /* This is not fatal and we should not stop init due to this */
970 /* Disabling VLAN filtering */
971 hw_dbg("Initializing the IEEE VLAN\n");
974 /* Setup the receive address */
975 igb_init_rx_addrs_82575(hw
, rar_count
);
976 /* Zero out the Multicast HASH table */
977 hw_dbg("Zeroing the MTA\n");
978 for (i
= 0; i
< mac
->mta_reg_count
; i
++)
979 array_wr32(E1000_MTA
, i
, 0);
981 /* Setup link and flow control */
982 ret_val
= igb_setup_link(hw
);
985 * Clear all of the statistics registers (clear on read). It is
986 * important that we do this after we have tried to establish link
987 * because the symbol error count will increment wildly if there
990 igb_clear_hw_cntrs_82575(hw
);
996 * igb_setup_copper_link_82575 - Configure copper link settings
997 * @hw: pointer to the HW structure
999 * Configures the link for auto-neg or forced speed and duplex. Then we check
1000 * for link, once link is established calls to configure collision distance
1001 * and flow control are called.
1003 static s32
igb_setup_copper_link_82575(struct e1000_hw
*hw
)
1009 ctrl
= rd32(E1000_CTRL
);
1010 ctrl
|= E1000_CTRL_SLU
;
1011 ctrl
&= ~(E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1012 wr32(E1000_CTRL
, ctrl
);
1014 switch (hw
->phy
.type
) {
1016 ret_val
= igb_copper_link_setup_m88(hw
);
1018 case e1000_phy_igp_3
:
1019 ret_val
= igb_copper_link_setup_igp(hw
);
1020 /* Setup activity LED */
1021 led_ctrl
= rd32(E1000_LEDCTL
);
1022 led_ctrl
&= IGP_ACTIVITY_LED_MASK
;
1023 led_ctrl
|= (IGP_ACTIVITY_LED_ENABLE
| IGP_LED3_MODE
);
1024 wr32(E1000_LEDCTL
, led_ctrl
);
1027 ret_val
= -E1000_ERR_PHY
;
1034 if (hw
->mac
.autoneg
) {
1036 * Setup autoneg and flow control advertisement
1037 * and perform autonegotiation.
1039 ret_val
= igb_copper_link_autoneg(hw
);
1044 * PHY will be set to 10H, 10F, 100H or 100F
1045 * depending on user settings.
1047 hw_dbg("Forcing Speed and Duplex\n");
1048 ret_val
= igb_phy_force_speed_duplex(hw
);
1050 hw_dbg("Error Forcing Speed and Duplex\n");
1055 ret_val
= igb_configure_pcs_link_82575(hw
);
1060 * Check link status. Wait up to 100 microseconds for link to become
1063 ret_val
= igb_phy_has_link(hw
, COPPER_LINK_UP_LIMIT
, 10, &link
);
1068 hw_dbg("Valid link established!!!\n");
1069 /* Config the MAC and PHY after link is up */
1070 igb_config_collision_dist(hw
);
1071 ret_val
= igb_config_fc_after_link_up(hw
);
1073 hw_dbg("Unable to establish link!!!\n");
1081 * igb_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
1082 * @hw: pointer to the HW structure
1084 * Configures speed and duplex for fiber and serdes links.
1086 static s32
igb_setup_fiber_serdes_link_82575(struct e1000_hw
*hw
)
1091 * On the 82575, SerDes loopback mode persists until it is
1092 * explicitly turned off or a power cycle is performed. A read to
1093 * the register does not indicate its status. Therefore, we ensure
1094 * loopback mode is disabled during initialization.
1096 wr32(E1000_SCTL
, E1000_SCTL_DISABLE_SERDES_LOOPBACK
);
1098 /* Force link up, set 1gb, set both sw defined pins */
1099 reg
= rd32(E1000_CTRL
);
1100 reg
|= E1000_CTRL_SLU
|
1101 E1000_CTRL_SPD_1000
|
1103 E1000_CTRL_SWDPIN0
|
1105 wr32(E1000_CTRL
, reg
);
1107 /* Set switch control to serdes energy detect */
1108 reg
= rd32(E1000_CONNSW
);
1109 reg
|= E1000_CONNSW_ENRGSRC
;
1110 wr32(E1000_CONNSW
, reg
);
1113 * New SerDes mode allows for forcing speed or autonegotiating speed
1114 * at 1gb. Autoneg should be default set by most drivers. This is the
1115 * mode that will be compatible with older link partners and switches.
1116 * However, both are supported by the hardware and some drivers/tools.
1118 reg
= rd32(E1000_PCS_LCTL
);
1120 reg
&= ~(E1000_PCS_LCTL_AN_ENABLE
| E1000_PCS_LCTL_FLV_LINK_UP
|
1121 E1000_PCS_LCTL_FSD
| E1000_PCS_LCTL_FORCE_LINK
);
1123 if (hw
->mac
.autoneg
) {
1124 /* Set PCS register for autoneg */
1125 reg
|= E1000_PCS_LCTL_FSV_1000
| /* Force 1000 */
1126 E1000_PCS_LCTL_FDV_FULL
| /* SerDes Full duplex */
1127 E1000_PCS_LCTL_AN_ENABLE
| /* Enable Autoneg */
1128 E1000_PCS_LCTL_AN_RESTART
; /* Restart autoneg */
1129 hw_dbg("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg
);
1131 /* Set PCS register for forced speed */
1132 reg
|= E1000_PCS_LCTL_FLV_LINK_UP
| /* Force link up */
1133 E1000_PCS_LCTL_FSV_1000
| /* Force 1000 */
1134 E1000_PCS_LCTL_FDV_FULL
| /* SerDes Full duplex */
1135 E1000_PCS_LCTL_FSD
| /* Force Speed */
1136 E1000_PCS_LCTL_FORCE_LINK
; /* Force Link */
1137 hw_dbg("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg
);
1139 wr32(E1000_PCS_LCTL
, reg
);
1145 * igb_configure_pcs_link_82575 - Configure PCS link
1146 * @hw: pointer to the HW structure
1148 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1149 * only used on copper connections where the serialized gigabit media
1150 * independent interface (sgmii) is being used. Configures the link
1151 * for auto-negotiation or forces speed/duplex.
1153 static s32
igb_configure_pcs_link_82575(struct e1000_hw
*hw
)
1155 struct e1000_mac_info
*mac
= &hw
->mac
;
1158 if (hw
->phy
.media_type
!= e1000_media_type_copper
||
1159 !(igb_sgmii_active_82575(hw
)))
1162 /* For SGMII, we need to issue a PCS autoneg restart */
1163 reg
= rd32(E1000_PCS_LCTL
);
1165 /* AN time out should be disabled for SGMII mode */
1166 reg
&= ~(E1000_PCS_LCTL_AN_TIMEOUT
);
1169 /* Make sure forced speed and force link are not set */
1170 reg
&= ~(E1000_PCS_LCTL_FSD
| E1000_PCS_LCTL_FORCE_LINK
);
1173 * The PHY should be setup prior to calling this function.
1174 * All we need to do is restart autoneg and enable autoneg.
1176 reg
|= E1000_PCS_LCTL_AN_RESTART
| E1000_PCS_LCTL_AN_ENABLE
;
1178 /* Set PCS register for forced speed */
1180 /* Turn off bits for full duplex, speed, and autoneg */
1181 reg
&= ~(E1000_PCS_LCTL_FSV_1000
|
1182 E1000_PCS_LCTL_FSV_100
|
1183 E1000_PCS_LCTL_FDV_FULL
|
1184 E1000_PCS_LCTL_AN_ENABLE
);
1186 /* Check for duplex first */
1187 if (mac
->forced_speed_duplex
& E1000_ALL_FULL_DUPLEX
)
1188 reg
|= E1000_PCS_LCTL_FDV_FULL
;
1191 if (mac
->forced_speed_duplex
& E1000_ALL_100_SPEED
)
1192 reg
|= E1000_PCS_LCTL_FSV_100
;
1194 /* Force speed and force link */
1195 reg
|= E1000_PCS_LCTL_FSD
|
1196 E1000_PCS_LCTL_FORCE_LINK
|
1197 E1000_PCS_LCTL_FLV_LINK_UP
;
1199 hw_dbg("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
1202 wr32(E1000_PCS_LCTL
, reg
);
1209 * igb_sgmii_active_82575 - Return sgmii state
1210 * @hw: pointer to the HW structure
1212 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1213 * which can be enabled for use in the embedded applications. Simply
1214 * return the current state of the sgmii interface.
1216 static bool igb_sgmii_active_82575(struct e1000_hw
*hw
)
1218 struct e1000_dev_spec_82575
*dev_spec
;
1221 if (hw
->mac
.type
!= e1000_82575
) {
1226 dev_spec
= (struct e1000_dev_spec_82575
*)hw
->dev_spec
;
1228 ret_val
= dev_spec
->sgmii_active
;
1235 * igb_translate_register_82576 - Translate the proper register offset
1236 * @reg: e1000 register to be read
1238 * Registers in 82576 are located in different offsets than other adapters
1239 * even though they function in the same manner. This function takes in
1240 * the name of the register to read and returns the correct offset for
1243 u32
igb_translate_register_82576(u32 reg
)
1246 * Some of the Kawela registers are located at different
1247 * offsets than they are in older adapters.
1248 * Despite the difference in location, the registers
1249 * function in the same manner.
1252 case E1000_TDBAL(0):
1255 case E1000_TDBAH(0):
1258 case E1000_TDLEN(0):
1267 case E1000_TXDCTL(0):
1270 case E1000_RDBAL(0):
1273 case E1000_RDBAH(0):
1276 case E1000_RDLEN(0):
1285 case E1000_RXDCTL(0):
1288 case E1000_SRRCTL(0):
1299 * igb_reset_init_script_82575 - Inits HW defaults after reset
1300 * @hw: pointer to the HW structure
1302 * Inits recommended HW defaults after a reset when there is no EEPROM
1303 * detected. This is only for the 82575.
1305 static s32
igb_reset_init_script_82575(struct e1000_hw
*hw
)
1307 if (hw
->mac
.type
== e1000_82575
) {
1308 hw_dbg("Running reset init script for 82575\n");
1309 /* SerDes configuration via SERDESCTRL */
1310 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x00, 0x0C);
1311 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x01, 0x78);
1312 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x1B, 0x23);
1313 igb_write_8bit_ctrl_reg(hw
, E1000_SCTL
, 0x23, 0x15);
1315 /* CCM configuration via CCMCTL register */
1316 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x14, 0x00);
1317 igb_write_8bit_ctrl_reg(hw
, E1000_CCMCTL
, 0x10, 0x00);
1319 /* PCIe lanes configuration */
1320 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x00, 0xEC);
1321 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x61, 0xDF);
1322 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x34, 0x05);
1323 igb_write_8bit_ctrl_reg(hw
, E1000_GIOCTL
, 0x2F, 0x81);
1325 /* PCIe PLL Configuration */
1326 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x02, 0x47);
1327 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x14, 0x00);
1328 igb_write_8bit_ctrl_reg(hw
, E1000_SCCTL
, 0x10, 0x00);
1335 * igb_read_mac_addr_82575 - Read device MAC address
1336 * @hw: pointer to the HW structure
1338 static s32
igb_read_mac_addr_82575(struct e1000_hw
*hw
)
1342 if (igb_check_alt_mac_addr(hw
))
1343 ret_val
= igb_read_mac_addr(hw
);
1349 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1350 * @hw: pointer to the HW structure
1352 * Clears the hardware counters by reading the counter registers.
1354 static void igb_clear_hw_cntrs_82575(struct e1000_hw
*hw
)
1358 igb_clear_hw_cntrs_base(hw
);
1360 temp
= rd32(E1000_PRC64
);
1361 temp
= rd32(E1000_PRC127
);
1362 temp
= rd32(E1000_PRC255
);
1363 temp
= rd32(E1000_PRC511
);
1364 temp
= rd32(E1000_PRC1023
);
1365 temp
= rd32(E1000_PRC1522
);
1366 temp
= rd32(E1000_PTC64
);
1367 temp
= rd32(E1000_PTC127
);
1368 temp
= rd32(E1000_PTC255
);
1369 temp
= rd32(E1000_PTC511
);
1370 temp
= rd32(E1000_PTC1023
);
1371 temp
= rd32(E1000_PTC1522
);
1373 temp
= rd32(E1000_ALGNERRC
);
1374 temp
= rd32(E1000_RXERRC
);
1375 temp
= rd32(E1000_TNCRS
);
1376 temp
= rd32(E1000_CEXTERR
);
1377 temp
= rd32(E1000_TSCTC
);
1378 temp
= rd32(E1000_TSCTFC
);
1380 temp
= rd32(E1000_MGTPRC
);
1381 temp
= rd32(E1000_MGTPDC
);
1382 temp
= rd32(E1000_MGTPTC
);
1384 temp
= rd32(E1000_IAC
);
1385 temp
= rd32(E1000_ICRXOC
);
1387 temp
= rd32(E1000_ICRXPTC
);
1388 temp
= rd32(E1000_ICRXATC
);
1389 temp
= rd32(E1000_ICTXPTC
);
1390 temp
= rd32(E1000_ICTXATC
);
1391 temp
= rd32(E1000_ICTXQEC
);
1392 temp
= rd32(E1000_ICTXQMTC
);
1393 temp
= rd32(E1000_ICRXDMTC
);
1395 temp
= rd32(E1000_CBTMPC
);
1396 temp
= rd32(E1000_HTDPMC
);
1397 temp
= rd32(E1000_CBRMPC
);
1398 temp
= rd32(E1000_RPTHC
);
1399 temp
= rd32(E1000_HGPTC
);
1400 temp
= rd32(E1000_HTCBDPC
);
1401 temp
= rd32(E1000_HGORCL
);
1402 temp
= rd32(E1000_HGORCH
);
1403 temp
= rd32(E1000_HGOTCL
);
1404 temp
= rd32(E1000_HGOTCH
);
1405 temp
= rd32(E1000_LENERRS
);
1407 /* This register should not be read in copper configurations */
1408 if (hw
->phy
.media_type
== e1000_media_type_internal_serdes
)
1409 temp
= rd32(E1000_SCVPC
);
1413 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1414 * @hw: pointer to the HW structure
1416 * After rx enable if managability is enabled then there is likely some
1417 * bad data at the start of the fifo and possibly in the DMA fifo. This
1418 * function clears the fifos and flushes any packets that came in as rx was
1421 void igb_rx_fifo_flush_82575(struct e1000_hw
*hw
)
1423 u32 rctl
, rlpml
, rxdctl
[4], rfctl
, temp_rctl
, rx_enabled
;
1426 if (hw
->mac
.type
!= e1000_82575
||
1427 !(rd32(E1000_MANC
) & E1000_MANC_RCV_TCO_EN
))
1430 /* Disable all RX queues */
1431 for (i
= 0; i
< 4; i
++) {
1432 rxdctl
[i
] = rd32(E1000_RXDCTL(i
));
1433 wr32(E1000_RXDCTL(i
),
1434 rxdctl
[i
] & ~E1000_RXDCTL_QUEUE_ENABLE
);
1436 /* Poll all queues to verify they have shut down */
1437 for (ms_wait
= 0; ms_wait
< 10; ms_wait
++) {
1440 for (i
= 0; i
< 4; i
++)
1441 rx_enabled
|= rd32(E1000_RXDCTL(i
));
1442 if (!(rx_enabled
& E1000_RXDCTL_QUEUE_ENABLE
))
1447 hw_dbg("Queue disable timed out after 10ms\n");
1449 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1450 * incoming packets are rejected. Set enable and wait 2ms so that
1451 * any packet that was coming in as RCTL.EN was set is flushed
1453 rfctl
= rd32(E1000_RFCTL
);
1454 wr32(E1000_RFCTL
, rfctl
& ~E1000_RFCTL_LEF
);
1456 rlpml
= rd32(E1000_RLPML
);
1457 wr32(E1000_RLPML
, 0);
1459 rctl
= rd32(E1000_RCTL
);
1460 temp_rctl
= rctl
& ~(E1000_RCTL_EN
| E1000_RCTL_SBP
);
1461 temp_rctl
|= E1000_RCTL_LPE
;
1463 wr32(E1000_RCTL
, temp_rctl
);
1464 wr32(E1000_RCTL
, temp_rctl
| E1000_RCTL_EN
);
1468 /* Enable RX queues that were previously enabled and restore our
1471 for (i
= 0; i
< 4; i
++)
1472 wr32(E1000_RXDCTL(i
), rxdctl
[i
]);
1473 wr32(E1000_RCTL
, rctl
);
1476 wr32(E1000_RLPML
, rlpml
);
1477 wr32(E1000_RFCTL
, rfctl
);
1479 /* Flush receive errors generated by workaround */
1485 static struct e1000_mac_operations e1000_mac_ops_82575
= {
1486 .reset_hw
= igb_reset_hw_82575
,
1487 .init_hw
= igb_init_hw_82575
,
1488 .check_for_link
= igb_check_for_link_82575
,
1489 .rar_set
= igb_rar_set
,
1490 .read_mac_addr
= igb_read_mac_addr_82575
,
1491 .get_speed_and_duplex
= igb_get_speed_and_duplex_copper
,
1494 static struct e1000_phy_operations e1000_phy_ops_82575
= {
1495 .acquire_phy
= igb_acquire_phy_82575
,
1496 .get_cfg_done
= igb_get_cfg_done_82575
,
1497 .release_phy
= igb_release_phy_82575
,
1500 static struct e1000_nvm_operations e1000_nvm_ops_82575
= {
1501 .acquire_nvm
= igb_acquire_nvm_82575
,
1502 .read_nvm
= igb_read_nvm_eerd
,
1503 .release_nvm
= igb_release_nvm_82575
,
1504 .write_nvm
= igb_write_nvm_spi
,
1507 const struct e1000_info e1000_82575_info
= {
1508 .get_invariants
= igb_get_invariants_82575
,
1509 .mac_ops
= &e1000_mac_ops_82575
,
1510 .phy_ops
= &e1000_phy_ops_82575
,
1511 .nvm_ops
= &e1000_nvm_ops_82575
,